Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * P5 specific Machine Check Exception Reporting | |
87c6fe26 | 3 | * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 | 4 | */ |
1da177e4 | 5 | #include <linux/interrupt.h> |
ed8bc7ed IM |
6 | #include <linux/kernel.h> |
7 | #include <linux/types.h> | |
8 | #include <linux/init.h> | |
1da177e4 LT |
9 | #include <linux/smp.h> |
10 | ||
15777205 | 11 | #include <asm/processor.h> |
1da177e4 | 12 | #include <asm/system.h> |
9e55e44e | 13 | #include <asm/mce.h> |
1da177e4 LT |
14 | #include <asm/msr.h> |
15 | ||
4efc0670 | 16 | /* By default disabled */ |
c6978369 | 17 | int mce_p5_enabled __read_mostly; |
4efc0670 | 18 | |
ed8bc7ed | 19 | /* Machine check handler for Pentium class Intel CPUs: */ |
15777205 | 20 | static void pentium_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
21 | { |
22 | u32 loaddr, hi, lotype; | |
ed8bc7ed | 23 | |
1da177e4 LT |
24 | rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); |
25 | rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); | |
ed8bc7ed IM |
26 | |
27 | printk(KERN_EMERG | |
28 | "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", | |
29 | smp_processor_id(), loaddr, lotype); | |
30 | ||
31 | if (lotype & (1<<5)) { | |
32 | printk(KERN_EMERG | |
33 | "CPU#%d: Possible thermal failure (CPU on fire ?).\n", | |
34 | smp_processor_id()); | |
35 | } | |
36 | ||
1da177e4 LT |
37 | add_taint(TAINT_MACHINE_CHECK); |
38 | } | |
39 | ||
ed8bc7ed | 40 | /* Set up machine check reporting for processors with Intel style MCE: */ |
31ab269a | 41 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
42 | { |
43 | u32 l, h; | |
15777205 | 44 | |
c6978369 HS |
45 | /* Default P5 to off as its often misconnected: */ |
46 | if (!mce_p5_enabled) | |
15777205 | 47 | return; |
1da177e4 | 48 | |
c6978369 HS |
49 | /* Check for MCE support: */ |
50 | if (!cpu_has(c, X86_FEATURE_MCE)) | |
1da177e4 | 51 | return; |
ed8bc7ed | 52 | |
1da177e4 | 53 | machine_check_vector = pentium_machine_check; |
ed8bc7ed | 54 | /* Make sure the vector pointer is visible before we enable MCEs: */ |
1da177e4 LT |
55 | wmb(); |
56 | ||
ed8bc7ed | 57 | /* Read registers before enabling: */ |
1da177e4 LT |
58 | rdmsr(MSR_IA32_P5_MC_ADDR, l, h); |
59 | rdmsr(MSR_IA32_P5_MC_TYPE, l, h); | |
ed8bc7ed IM |
60 | printk(KERN_INFO |
61 | "Intel old style machine check architecture supported.\n"); | |
1da177e4 | 62 | |
ed8bc7ed | 63 | /* Enable MCE: */ |
1da177e4 | 64 | set_in_cr4(X86_CR4_MCE); |
ed8bc7ed IM |
65 | printk(KERN_INFO |
66 | "Intel old style machine check reporting enabled on CPU#%d.\n", | |
67 | smp_processor_id()); | |
1da177e4 | 68 | } |