Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
87a6d409 | 23 | #include <linux/string.h> |
1cb2a8e1 | 24 | |
019f34fc | 25 | #include <asm/amd_nb.h> |
89b831ef JS |
26 | #include <asm/apic.h> |
27 | #include <asm/mce.h> | |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
262e6811 BP |
31 | #include "mce-internal.h" |
32 | ||
60f116fc | 33 | #define NR_BLOCKS 5 |
2903ee85 JS |
34 | #define THRESHOLD_MAX 0xFFF |
35 | #define INT_TYPE_APIC 0x00020000 | |
36 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
37 | #define MASK_CNTP_HI 0x40000000 |
38 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
39 | #define MASK_LVTOFF_HI 0x00F00000 |
40 | #define MASK_COUNT_EN_HI 0x00080000 | |
41 | #define MASK_INT_TYPE_HI 0x00060000 | |
42 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 43 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
44 | #define MASK_BLKPTR_LO 0xFF000000 |
45 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 46 | |
24fd78a8 AG |
47 | /* Deferred error settings */ |
48 | #define MSR_CU_DEF_ERR 0xC0000410 | |
49 | #define MASK_DEF_LVTOFF 0x000000F0 | |
50 | #define MASK_DEF_INT_TYPE 0x00000006 | |
51 | #define DEF_LVT_OFF 0x2 | |
52 | #define DEF_INT_TYPE_APIC 0x2 | |
53 | ||
f57a1f3c AG |
54 | /* Scalable MCA: */ |
55 | ||
56 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
57 | #define SMCA_THR_LVT_OFF 0xF000 | |
58 | ||
4d7b02d5 SAS |
59 | static bool thresholding_en; |
60 | ||
336d335a BP |
61 | static const char * const th_names[] = { |
62 | "load_store", | |
63 | "insn_fetch", | |
64 | "combined_unit", | |
29f72ce3 | 65 | "decode_unit", |
336d335a BP |
66 | "northbridge", |
67 | "execution_unit", | |
68 | }; | |
69 | ||
87a6d409 YG |
70 | static const char * const smca_umc_block_names[] = { |
71 | "dram_ecc", | |
72 | "misc_umc" | |
73 | }; | |
74 | ||
c09a8c40 BP |
75 | struct smca_bank_name { |
76 | const char *name; /* Short name for sysfs */ | |
77 | const char *long_name; /* Long name for pretty-printing */ | |
78 | }; | |
79 | ||
80 | static struct smca_bank_name smca_names[] = { | |
5896820e YG |
81 | [SMCA_LS] = { "load_store", "Load Store Unit" }, |
82 | [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" }, | |
83 | [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" }, | |
84 | [SMCA_DE] = { "decode_unit", "Decode Unit" }, | |
68627a69 | 85 | [SMCA_RESERVED] = { "reserved", "Reserved" }, |
5896820e YG |
86 | [SMCA_EX] = { "execution_unit", "Execution Unit" }, |
87 | [SMCA_FP] = { "floating_point", "Floating Point Unit" }, | |
88 | [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" }, | |
89 | [SMCA_CS] = { "coherent_slave", "Coherent Slave" }, | |
90 | [SMCA_PIE] = { "pie", "Power, Interrupts, etc." }, | |
91 | [SMCA_UMC] = { "umc", "Unified Memory Controller" }, | |
92 | [SMCA_PB] = { "param_block", "Parameter Block" }, | |
93 | [SMCA_PSP] = { "psp", "Platform Security Processor" }, | |
94 | [SMCA_SMU] = { "smu", "System Management Unit" }, | |
be0aec23 | 95 | }; |
c09a8c40 | 96 | |
78ce2410 BP |
97 | static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init = |
98 | { | |
99 | [0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 } | |
100 | }; | |
101 | ||
c09a8c40 BP |
102 | const char *smca_get_name(enum smca_bank_types t) |
103 | { | |
104 | if (t >= N_SMCA_BANK_TYPES) | |
105 | return NULL; | |
106 | ||
107 | return smca_names[t].name; | |
108 | } | |
109 | ||
110 | const char *smca_get_long_name(enum smca_bank_types t) | |
111 | { | |
112 | if (t >= N_SMCA_BANK_TYPES) | |
113 | return NULL; | |
114 | ||
115 | return smca_names[t].long_name; | |
116 | } | |
117 | EXPORT_SYMBOL_GPL(smca_get_long_name); | |
5896820e | 118 | |
e5d6a126 | 119 | static enum smca_bank_types smca_get_bank_type(unsigned int bank) |
11cf8877 YG |
120 | { |
121 | struct smca_bank *b; | |
122 | ||
e5d6a126 | 123 | if (bank >= MAX_NR_BANKS) |
11cf8877 YG |
124 | return N_SMCA_BANK_TYPES; |
125 | ||
e5d6a126 | 126 | b = &smca_banks[bank]; |
11cf8877 YG |
127 | if (!b->hwid) |
128 | return N_SMCA_BANK_TYPES; | |
129 | ||
130 | return b->hwid->bank_type; | |
131 | } | |
132 | ||
1ce9cd7f | 133 | static struct smca_hwid smca_hwid_mcatypes[] = { |
5896820e YG |
134 | /* { bank_type, hwid_mcatype, xec_bitmap } */ |
135 | ||
68627a69 YG |
136 | /* Reserved type */ |
137 | { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 }, | |
138 | ||
5896820e YG |
139 | /* ZN Core (HWID=0xB0) MCA types */ |
140 | { SMCA_LS, HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF }, | |
141 | { SMCA_IF, HWID_MCATYPE(0xB0, 0x1), 0x3FFF }, | |
142 | { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF }, | |
143 | { SMCA_DE, HWID_MCATYPE(0xB0, 0x3), 0x1FF }, | |
144 | /* HWID 0xB0 MCATYPE 0x4 is Reserved */ | |
145 | { SMCA_EX, HWID_MCATYPE(0xB0, 0x5), 0x7FF }, | |
146 | { SMCA_FP, HWID_MCATYPE(0xB0, 0x6), 0x7F }, | |
147 | { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF }, | |
148 | ||
149 | /* Data Fabric MCA types */ | |
150 | { SMCA_CS, HWID_MCATYPE(0x2E, 0x0), 0x1FF }, | |
151 | { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1), 0xF }, | |
152 | ||
153 | /* Unified Memory Controller MCA type */ | |
154 | { SMCA_UMC, HWID_MCATYPE(0x96, 0x0), 0x3F }, | |
155 | ||
156 | /* Parameter Block MCA type */ | |
157 | { SMCA_PB, HWID_MCATYPE(0x05, 0x0), 0x1 }, | |
be0aec23 | 158 | |
5896820e YG |
159 | /* Platform Security Processor MCA type */ |
160 | { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0), 0x1 }, | |
161 | ||
162 | /* System Management Unit MCA type */ | |
163 | { SMCA_SMU, HWID_MCATYPE(0x01, 0x0), 0x1 }, | |
be0aec23 | 164 | }; |
5896820e | 165 | |
79349f52 | 166 | struct smca_bank smca_banks[MAX_NR_BANKS]; |
5896820e | 167 | EXPORT_SYMBOL_GPL(smca_banks); |
be0aec23 | 168 | |
87a6d409 YG |
169 | /* |
170 | * In SMCA enabled processors, we can have multiple banks for a given IP type. | |
171 | * So to define a unique name for each bank, we use a temp c-string to append | |
172 | * the MCA_IPID[InstanceId] to type's name in get_name(). | |
173 | * | |
174 | * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN | |
175 | * is greater than 8 plus 1 (for underscore) plus length of longest type name. | |
176 | */ | |
177 | #define MAX_MCATYPE_NAME_LEN 30 | |
178 | static char buf_mcatype[MAX_MCATYPE_NAME_LEN]; | |
179 | ||
bafcdd3b | 180 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
955d1427 | 181 | static DEFINE_PER_CPU(unsigned int, bank_map); /* see which banks are on */ |
89b831ef | 182 | |
b2762686 | 183 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
184 | static void amd_deferred_error_interrupt(void); |
185 | ||
186 | static void default_deferred_error_interrupt(void) | |
187 | { | |
188 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
189 | } | |
190 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 191 | |
84bcc1d5 | 192 | static void smca_configure(unsigned int bank, unsigned int cpu) |
5896820e | 193 | { |
84bcc1d5 | 194 | unsigned int i, hwid_mcatype; |
1ce9cd7f | 195 | struct smca_hwid *s_hwid; |
84bcc1d5 YG |
196 | u32 high, low; |
197 | u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); | |
198 | ||
199 | /* Set appropriate bits in MCA_CONFIG */ | |
200 | if (!rdmsr_safe(smca_config, &low, &high)) { | |
201 | /* | |
202 | * OS is required to set the MCAX bit to acknowledge that it is | |
203 | * now using the new MSR ranges and new registers under each | |
204 | * bank. It also means that the OS will configure deferred | |
205 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
206 | * uncorrectable errors will cause a system panic. | |
207 | * | |
208 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
209 | */ | |
210 | high |= BIT(0); | |
211 | ||
212 | /* | |
213 | * SMCA sets the Deferred Error Interrupt type per bank. | |
214 | * | |
215 | * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us | |
216 | * if the DeferredIntType bit field is available. | |
217 | * | |
218 | * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the | |
219 | * high portion of the MSR). OS should set this to 0x1 to enable | |
220 | * APIC based interrupt. First, check that no interrupt has been | |
221 | * set. | |
222 | */ | |
223 | if ((low & BIT(5)) && !((high >> 5) & 0x3)) | |
224 | high |= BIT(5); | |
225 | ||
226 | wrmsr(smca_config, low, high); | |
227 | } | |
5896820e | 228 | |
9662d43f YG |
229 | /* Return early if this bank was already initialized. */ |
230 | if (smca_banks[bank].hwid) | |
5896820e YG |
231 | return; |
232 | ||
84bcc1d5 | 233 | if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { |
5896820e YG |
234 | pr_warn("Failed to read MCA_IPID for bank %d\n", bank); |
235 | return; | |
236 | } | |
237 | ||
1ce9cd7f BP |
238 | hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, |
239 | (high & MCI_IPID_MCATYPE) >> 16); | |
5896820e YG |
240 | |
241 | for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { | |
1ce9cd7f BP |
242 | s_hwid = &smca_hwid_mcatypes[i]; |
243 | if (hwid_mcatype == s_hwid->hwid_mcatype) { | |
244 | smca_banks[bank].hwid = s_hwid; | |
84bcc1d5 | 245 | smca_banks[bank].id = low; |
0b737a9c | 246 | smca_banks[bank].sysfs_id = s_hwid->count++; |
5896820e YG |
247 | break; |
248 | } | |
249 | } | |
250 | } | |
251 | ||
4cd4601d | 252 | struct thresh_restart { |
1cb2a8e1 IM |
253 | struct threshold_block *b; |
254 | int reset; | |
9c37c9d8 RR |
255 | int set_lvt_off; |
256 | int lvt_off; | |
1cb2a8e1 | 257 | u16 old_limit; |
4cd4601d MT |
258 | }; |
259 | ||
c76e8164 BO |
260 | static inline bool is_shared_bank(int bank) |
261 | { | |
284b965c AG |
262 | /* |
263 | * Scalable MCA provides for only one core to have access to the MSRs of | |
264 | * a shared bank. | |
265 | */ | |
266 | if (mce_flags.smca) | |
267 | return false; | |
268 | ||
c76e8164 BO |
269 | /* Bank 4 is for northbridge reporting and is thus shared */ |
270 | return (bank == 4); | |
271 | } | |
272 | ||
2cd4c303 | 273 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
274 | { |
275 | switch (b->address) { | |
276 | /* MSR4_MISC0 */ | |
277 | case 0x00000413: | |
278 | return "dram"; | |
279 | ||
280 | case 0xc0000408: | |
281 | return "ht_links"; | |
282 | ||
283 | case 0xc0000409: | |
284 | return "l3_cache"; | |
285 | ||
286 | default: | |
287 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
288 | return ""; | |
289 | } | |
290 | }; | |
291 | ||
292 | ||
f227d430 BP |
293 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
294 | { | |
295 | /* | |
296 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
297 | */ | |
298 | if (bank == 4) | |
299 | return true; | |
300 | ||
301 | /* | |
302 | * IntP: interrupt present; if this bit is set, the thresholding | |
303 | * bank can generate APIC LVT interrupts | |
304 | */ | |
305 | return msr_high_bits & BIT(28); | |
306 | } | |
307 | ||
bbaff08d RR |
308 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
309 | { | |
310 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
311 | ||
312 | if (apic < 0) { | |
313 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
314 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
315 | b->bank, b->block, b->address, hi, lo); | |
316 | return 0; | |
317 | } | |
318 | ||
319 | if (apic != msr) { | |
f57a1f3c AG |
320 | /* |
321 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
322 | * the BIOS provides the value. The original field where LVT offset | |
323 | * was set is reserved. Return early here: | |
324 | */ | |
325 | if (mce_flags.smca) | |
326 | return 0; | |
327 | ||
bbaff08d RR |
328 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
329 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
330 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
331 | return 0; | |
332 | } | |
333 | ||
334 | return 1; | |
335 | }; | |
336 | ||
ea2ca36b | 337 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 338 | static void threshold_restart_bank(void *_tr) |
89b831ef | 339 | { |
4cd4601d | 340 | struct thresh_restart *tr = _tr; |
7203a049 | 341 | u32 hi, lo; |
89b831ef | 342 | |
7203a049 | 343 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 344 | |
7203a049 | 345 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 346 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 347 | |
4cd4601d | 348 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
349 | hi = |
350 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
351 | (THRESHOLD_MAX - tr->b->threshold_limit); |
352 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 353 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 354 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 355 | |
7203a049 | 356 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
357 | (new_count & THRESHOLD_MAX); |
358 | } | |
359 | ||
f227d430 BP |
360 | /* clear IntType */ |
361 | hi &= ~MASK_INT_TYPE_HI; | |
362 | ||
363 | if (!tr->b->interrupt_capable) | |
364 | goto done; | |
365 | ||
9c37c9d8 | 366 | if (tr->set_lvt_off) { |
bbaff08d RR |
367 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
368 | /* set new lvt offset */ | |
369 | hi &= ~MASK_LVTOFF_HI; | |
370 | hi |= tr->lvt_off << 20; | |
371 | } | |
9c37c9d8 RR |
372 | } |
373 | ||
f227d430 BP |
374 | if (tr->b->interrupt_enable) |
375 | hi |= INT_TYPE_APIC; | |
376 | ||
377 | done: | |
89b831ef | 378 | |
7203a049 RR |
379 | hi |= MASK_COUNT_EN_HI; |
380 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
381 | } |
382 | ||
9c37c9d8 RR |
383 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
384 | { | |
385 | struct thresh_restart tr = { | |
386 | .b = b, | |
387 | .set_lvt_off = 1, | |
388 | .lvt_off = offset, | |
389 | }; | |
390 | ||
391 | b->threshold_limit = THRESHOLD_MAX; | |
392 | threshold_restart_bank(&tr); | |
393 | }; | |
394 | ||
868c00bb | 395 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
396 | { |
397 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
398 | APIC_EILVT_MSG_FIX, 0)) | |
399 | return new; | |
400 | ||
401 | return reserved; | |
402 | } | |
403 | ||
24fd78a8 AG |
404 | static int setup_APIC_deferred_error(int reserved, int new) |
405 | { | |
406 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
407 | APIC_EILVT_MSG_FIX, 0)) | |
408 | return new; | |
409 | ||
410 | return reserved; | |
411 | } | |
412 | ||
413 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
414 | { | |
415 | u32 low = 0, high = 0; | |
416 | int def_offset = -1, def_new; | |
417 | ||
418 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
419 | return; | |
420 | ||
421 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
422 | if (!(low & MASK_DEF_LVTOFF)) { | |
423 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
424 | def_new = DEF_LVT_OFF; | |
425 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
426 | } | |
427 | ||
428 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
429 | if ((def_offset == def_new) && | |
430 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
431 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
432 | ||
c8a4364c YG |
433 | if (!mce_flags.smca) |
434 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
435 | ||
24fd78a8 AG |
436 | wrmsr(MSR_CU_DEF_ERR, low, high); |
437 | } | |
438 | ||
fbf96cf9 | 439 | static u32 smca_get_block_address(unsigned int bank, unsigned int block) |
8a331f4a YG |
440 | { |
441 | u32 low, high; | |
442 | u32 addr = 0; | |
443 | ||
444 | if (smca_get_bank_type(bank) == SMCA_RESERVED) | |
445 | return addr; | |
446 | ||
447 | if (!block) | |
448 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
449 | ||
78ce2410 BP |
450 | /* Check our cache first: */ |
451 | if (smca_bank_addrs[bank][block] != -1) | |
452 | return smca_bank_addrs[bank][block]; | |
453 | ||
8a331f4a YG |
454 | /* |
455 | * For SMCA enabled processors, BLKPTR field of the first MISC register | |
456 | * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4). | |
457 | */ | |
fbf96cf9 | 458 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) |
78ce2410 | 459 | goto out; |
8a331f4a YG |
460 | |
461 | if (!(low & MCI_CONFIG_MCAX)) | |
78ce2410 | 462 | goto out; |
8a331f4a | 463 | |
fbf96cf9 | 464 | if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && |
8a331f4a | 465 | (low & MASK_BLKPTR_LO)) |
78ce2410 | 466 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); |
8a331f4a | 467 | |
78ce2410 BP |
468 | out: |
469 | smca_bank_addrs[bank][block] = addr; | |
8a331f4a YG |
470 | return addr; |
471 | } | |
472 | ||
fbf96cf9 | 473 | static u32 get_block_address(u32 current_addr, u32 low, u32 high, |
8dd1e17a AG |
474 | unsigned int bank, unsigned int block) |
475 | { | |
476 | u32 addr = 0, offset = 0; | |
477 | ||
27bd5950 YG |
478 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
479 | return addr; | |
480 | ||
8a331f4a | 481 | if (mce_flags.smca) |
fbf96cf9 | 482 | return smca_get_block_address(bank, block); |
8dd1e17a AG |
483 | |
484 | /* Fall back to method we used for older processors: */ | |
485 | switch (block) { | |
486 | case 0: | |
d9d73fcc | 487 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
488 | break; |
489 | case 1: | |
490 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
491 | if (offset) | |
492 | addr = MCG_XBLK_ADDR + offset; | |
493 | break; | |
494 | default: | |
495 | addr = ++current_addr; | |
496 | } | |
497 | return addr; | |
498 | } | |
499 | ||
429893b1 BP |
500 | static int |
501 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
502 | int offset, u32 misc_high) | |
503 | { | |
504 | unsigned int cpu = smp_processor_id(); | |
84bcc1d5 | 505 | u32 smca_low, smca_high; |
429893b1 BP |
506 | struct threshold_block b; |
507 | int new; | |
508 | ||
509 | if (!block) | |
510 | per_cpu(bank_map, cpu) |= (1 << bank); | |
511 | ||
512 | memset(&b, 0, sizeof(b)); | |
513 | b.cpu = cpu; | |
514 | b.bank = bank; | |
515 | b.block = block; | |
516 | b.address = addr; | |
517 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
518 | ||
519 | if (!b.interrupt_capable) | |
520 | goto done; | |
521 | ||
522 | b.interrupt_enable = 1; | |
523 | ||
e128b4f4 BP |
524 | if (!mce_flags.smca) { |
525 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
526 | goto set_offset; | |
527 | } | |
32544f06 | 528 | |
e128b4f4 BP |
529 | /* Gather LVT offset for thresholding: */ |
530 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
531 | goto out; | |
532 | ||
533 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
534 | ||
535 | set_offset: | |
429893b1 BP |
536 | offset = setup_APIC_mce_threshold(offset, new); |
537 | ||
538 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
539 | mce_threshold_vector = amd_threshold_interrupt; | |
540 | ||
541 | done: | |
542 | mce_threshold_block_init(&b, offset); | |
543 | ||
544 | out: | |
545 | return offset; | |
546 | } | |
547 | ||
95268664 | 548 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 549 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 550 | { |
95268664 | 551 | u32 low = 0, high = 0, address = 0; |
cfee4f6f | 552 | unsigned int bank, block, cpu = smp_processor_id(); |
429893b1 | 553 | int offset = -1; |
89b831ef | 554 | |
bafcdd3b | 555 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5896820e | 556 | if (mce_flags.smca) |
84bcc1d5 | 557 | smca_configure(bank, cpu); |
5896820e | 558 | |
95268664 | 559 | for (block = 0; block < NR_BLOCKS; ++block) { |
fbf96cf9 | 560 | address = get_block_address(address, low, high, bank, block); |
8dd1e17a AG |
561 | if (!address) |
562 | break; | |
95268664 JS |
563 | |
564 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 565 | break; |
95268664 | 566 | |
6dcbfe4f BP |
567 | if (!(high & MASK_VALID_HI)) |
568 | continue; | |
95268664 | 569 | |
24ce0e96 JB |
570 | if (!(high & MASK_CNTP_HI) || |
571 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
572 | continue; |
573 | ||
429893b1 | 574 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 575 | } |
89b831ef | 576 | } |
24fd78a8 AG |
577 | |
578 | if (mce_flags.succor) | |
579 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
580 | } |
581 | ||
f5382de9 YG |
582 | int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) |
583 | { | |
584 | u64 dram_base_addr, dram_limit_addr, dram_hole_base; | |
585 | /* We start from the normalized address */ | |
586 | u64 ret_addr = norm_addr; | |
587 | ||
588 | u32 tmp; | |
589 | ||
590 | u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask; | |
591 | u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets; | |
592 | u8 intlv_addr_sel, intlv_addr_bit; | |
593 | u8 num_intlv_bits, hashed_bit; | |
594 | u8 lgcy_mmio_hole_en, base = 0; | |
595 | u8 cs_mask, cs_id = 0; | |
596 | bool hash_enabled = false; | |
597 | ||
598 | /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ | |
599 | if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) | |
600 | goto out_err; | |
601 | ||
602 | /* Remove HiAddrOffset from normalized address, if enabled: */ | |
603 | if (tmp & BIT(0)) { | |
604 | u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8; | |
605 | ||
606 | if (norm_addr >= hi_addr_offset) { | |
607 | ret_addr -= hi_addr_offset; | |
608 | base = 1; | |
609 | } | |
610 | } | |
611 | ||
612 | /* Read D18F0x110 (DramBaseAddress). */ | |
613 | if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) | |
614 | goto out_err; | |
615 | ||
616 | /* Check if address range is valid. */ | |
617 | if (!(tmp & BIT(0))) { | |
618 | pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n", | |
619 | __func__, tmp); | |
620 | goto out_err; | |
621 | } | |
622 | ||
623 | lgcy_mmio_hole_en = tmp & BIT(1); | |
624 | intlv_num_chan = (tmp >> 4) & 0xF; | |
625 | intlv_addr_sel = (tmp >> 8) & 0x7; | |
626 | dram_base_addr = (tmp & GENMASK_ULL(31, 12)) << 16; | |
627 | ||
628 | /* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */ | |
629 | if (intlv_addr_sel > 3) { | |
630 | pr_err("%s: Invalid interleave address select %d.\n", | |
631 | __func__, intlv_addr_sel); | |
632 | goto out_err; | |
633 | } | |
634 | ||
635 | /* Read D18F0x114 (DramLimitAddress). */ | |
636 | if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) | |
637 | goto out_err; | |
638 | ||
639 | intlv_num_sockets = (tmp >> 8) & 0x1; | |
640 | intlv_num_dies = (tmp >> 10) & 0x3; | |
641 | dram_limit_addr = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0); | |
642 | ||
643 | intlv_addr_bit = intlv_addr_sel + 8; | |
644 | ||
645 | /* Re-use intlv_num_chan by setting it equal to log2(#channels) */ | |
646 | switch (intlv_num_chan) { | |
647 | case 0: intlv_num_chan = 0; break; | |
648 | case 1: intlv_num_chan = 1; break; | |
649 | case 3: intlv_num_chan = 2; break; | |
650 | case 5: intlv_num_chan = 3; break; | |
651 | case 7: intlv_num_chan = 4; break; | |
652 | ||
653 | case 8: intlv_num_chan = 1; | |
654 | hash_enabled = true; | |
655 | break; | |
656 | default: | |
657 | pr_err("%s: Invalid number of interleaved channels %d.\n", | |
658 | __func__, intlv_num_chan); | |
659 | goto out_err; | |
660 | } | |
661 | ||
662 | num_intlv_bits = intlv_num_chan; | |
663 | ||
664 | if (intlv_num_dies > 2) { | |
665 | pr_err("%s: Invalid number of interleaved nodes/dies %d.\n", | |
666 | __func__, intlv_num_dies); | |
667 | goto out_err; | |
668 | } | |
669 | ||
670 | num_intlv_bits += intlv_num_dies; | |
671 | ||
672 | /* Add a bit if sockets are interleaved. */ | |
673 | num_intlv_bits += intlv_num_sockets; | |
674 | ||
675 | /* Assert num_intlv_bits <= 4 */ | |
676 | if (num_intlv_bits > 4) { | |
677 | pr_err("%s: Invalid interleave bits %d.\n", | |
678 | __func__, num_intlv_bits); | |
679 | goto out_err; | |
680 | } | |
681 | ||
682 | if (num_intlv_bits > 0) { | |
683 | u64 temp_addr_x, temp_addr_i, temp_addr_y; | |
684 | u8 die_id_bit, sock_id_bit, cs_fabric_id; | |
685 | ||
686 | /* | |
687 | * Read FabricBlockInstanceInformation3_CS[BlockFabricID]. | |
688 | * This is the fabric id for this coherent slave. Use | |
689 | * umc/channel# as instance id of the coherent slave | |
690 | * for FICAA. | |
691 | */ | |
692 | if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) | |
693 | goto out_err; | |
694 | ||
695 | cs_fabric_id = (tmp >> 8) & 0xFF; | |
696 | die_id_bit = 0; | |
697 | ||
698 | /* If interleaved over more than 1 channel: */ | |
699 | if (intlv_num_chan) { | |
700 | die_id_bit = intlv_num_chan; | |
701 | cs_mask = (1 << die_id_bit) - 1; | |
702 | cs_id = cs_fabric_id & cs_mask; | |
703 | } | |
704 | ||
705 | sock_id_bit = die_id_bit; | |
706 | ||
707 | /* Read D18F1x208 (SystemFabricIdMask). */ | |
708 | if (intlv_num_dies || intlv_num_sockets) | |
709 | if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) | |
710 | goto out_err; | |
711 | ||
712 | /* If interleaved over more than 1 die. */ | |
713 | if (intlv_num_dies) { | |
714 | sock_id_bit = die_id_bit + intlv_num_dies; | |
715 | die_id_shift = (tmp >> 24) & 0xF; | |
716 | die_id_mask = (tmp >> 8) & 0xFF; | |
717 | ||
718 | cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit; | |
719 | } | |
720 | ||
721 | /* If interleaved over more than 1 socket. */ | |
722 | if (intlv_num_sockets) { | |
723 | socket_id_shift = (tmp >> 28) & 0xF; | |
724 | socket_id_mask = (tmp >> 16) & 0xFF; | |
725 | ||
726 | cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit; | |
727 | } | |
728 | ||
729 | /* | |
730 | * The pre-interleaved address consists of XXXXXXIIIYYYYY | |
731 | * where III is the ID for this CS, and XXXXXXYYYYY are the | |
732 | * address bits from the post-interleaved address. | |
733 | * "num_intlv_bits" has been calculated to tell us how many "I" | |
734 | * bits there are. "intlv_addr_bit" tells us how many "Y" bits | |
735 | * there are (where "I" starts). | |
736 | */ | |
737 | temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0); | |
738 | temp_addr_i = (cs_id << intlv_addr_bit); | |
739 | temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits; | |
740 | ret_addr = temp_addr_x | temp_addr_i | temp_addr_y; | |
741 | } | |
742 | ||
743 | /* Add dram base address */ | |
744 | ret_addr += dram_base_addr; | |
745 | ||
746 | /* If legacy MMIO hole enabled */ | |
747 | if (lgcy_mmio_hole_en) { | |
748 | if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) | |
749 | goto out_err; | |
750 | ||
751 | dram_hole_base = tmp & GENMASK(31, 24); | |
752 | if (ret_addr >= dram_hole_base) | |
753 | ret_addr += (BIT_ULL(32) - dram_hole_base); | |
754 | } | |
755 | ||
756 | if (hash_enabled) { | |
757 | /* Save some parentheses and grab ls-bit at the end. */ | |
758 | hashed_bit = (ret_addr >> 12) ^ | |
759 | (ret_addr >> 18) ^ | |
760 | (ret_addr >> 21) ^ | |
761 | (ret_addr >> 30) ^ | |
762 | cs_id; | |
763 | ||
764 | hashed_bit &= BIT(0); | |
765 | ||
766 | if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) | |
767 | ret_addr ^= BIT(intlv_addr_bit); | |
768 | } | |
769 | ||
770 | /* Is calculated system address is above DRAM limit address? */ | |
771 | if (ret_addr > dram_limit_addr) | |
772 | goto out_err; | |
773 | ||
774 | *sys_addr = ret_addr; | |
775 | return 0; | |
776 | ||
777 | out_err: | |
778 | return -EINVAL; | |
779 | } | |
780 | EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); | |
781 | ||
c6708d50 YG |
782 | bool amd_mce_is_memory_error(struct mce *m) |
783 | { | |
784 | /* ErrCodeExt[20:16] */ | |
785 | u8 xec = (m->status >> 16) & 0x1f; | |
786 | ||
787 | if (mce_flags.smca) | |
e5d6a126 | 788 | return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0; |
c6708d50 YG |
789 | |
790 | return m->bank == 4 && xec == 0x8; | |
791 | } | |
792 | ||
37d43acf | 793 | static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) |
afdf344e AG |
794 | { |
795 | struct mce m; | |
afdf344e AG |
796 | |
797 | mce_setup(&m); | |
798 | ||
799 | m.status = status; | |
37d43acf | 800 | m.misc = misc; |
669c00f0 BP |
801 | m.bank = bank; |
802 | m.tsc = rdtsc(); | |
6e6e746e | 803 | |
4f29b73b | 804 | if (m.status & MCI_STATUS_ADDRV) { |
37d43acf | 805 | m.addr = addr; |
afdf344e | 806 | |
4f29b73b YG |
807 | /* |
808 | * Extract [55:<lsb>] where lsb is the least significant | |
809 | * *valid* bit of the address bits. | |
810 | */ | |
811 | if (mce_flags.smca) { | |
812 | u8 lsb = (m.addr >> 56) & 0x3f; | |
813 | ||
814 | m.addr &= GENMASK_ULL(55, lsb); | |
815 | } | |
816 | } | |
817 | ||
5828c46f YG |
818 | if (mce_flags.smca) { |
819 | rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid); | |
820 | ||
821 | if (m.status & MCI_STATUS_SYNDV) | |
822 | rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd); | |
823 | } | |
db819d60 | 824 | |
6e6e746e | 825 | mce_log(&m); |
afdf344e AG |
826 | } |
827 | ||
c4158ff5 | 828 | asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void) |
24fd78a8 AG |
829 | { |
830 | entering_irq(); | |
831 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
0f42ae28 TG |
832 | inc_irq_stat(irq_deferred_error_count); |
833 | deferred_error_int_vector(); | |
24fd78a8 AG |
834 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); |
835 | exiting_ack_irq(); | |
836 | } | |
837 | ||
37d43acf YG |
838 | /* |
839 | * Returns true if the logged error is deferred. False, otherwise. | |
840 | */ | |
841 | static inline bool | |
842 | _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) | |
24fd78a8 | 843 | { |
37d43acf | 844 | u64 status, addr = 0; |
24fd78a8 | 845 | |
37d43acf YG |
846 | rdmsrl(msr_stat, status); |
847 | if (!(status & MCI_STATUS_VAL)) | |
848 | return false; | |
34102009 | 849 | |
37d43acf YG |
850 | if (status & MCI_STATUS_ADDRV) |
851 | rdmsrl(msr_addr, addr); | |
24fd78a8 | 852 | |
37d43acf | 853 | __log_error(bank, status, addr, misc); |
24fd78a8 | 854 | |
a24b8c34 | 855 | wrmsrl(msr_stat, 0); |
37d43acf YG |
856 | |
857 | return status & MCI_STATUS_DEFERRED; | |
24fd78a8 AG |
858 | } |
859 | ||
89b831ef | 860 | /* |
37d43acf YG |
861 | * We have three scenarios for checking for Deferred errors: |
862 | * | |
863 | * 1) Non-SMCA systems check MCA_STATUS and log error if found. | |
864 | * 2) SMCA systems check MCA_STATUS. If error is found then log it and also | |
865 | * clear MCA_DESTAT. | |
866 | * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and | |
867 | * log it. | |
89b831ef | 868 | */ |
37d43acf YG |
869 | static void log_error_deferred(unsigned int bank) |
870 | { | |
871 | bool defrd; | |
872 | ||
873 | defrd = _log_error_bank(bank, msr_ops.status(bank), | |
874 | msr_ops.addr(bank), 0); | |
875 | ||
876 | if (!mce_flags.smca) | |
877 | return; | |
878 | ||
879 | /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ | |
880 | if (defrd) { | |
881 | wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); | |
882 | return; | |
883 | } | |
884 | ||
885 | /* | |
886 | * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check | |
887 | * for a valid error. | |
888 | */ | |
889 | _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), | |
890 | MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); | |
891 | } | |
892 | ||
893 | /* APIC interrupt handler for deferred errors */ | |
894 | static void amd_deferred_error_interrupt(void) | |
895 | { | |
896 | unsigned int bank; | |
897 | ||
898 | for (bank = 0; bank < mca_cfg.banks; ++bank) | |
899 | log_error_deferred(bank); | |
900 | } | |
901 | ||
902 | static void log_error_thresholding(unsigned int bank, u64 misc) | |
903 | { | |
904 | _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); | |
905 | } | |
89b831ef | 906 | |
17ef4af0 YG |
907 | static void log_and_reset_block(struct threshold_block *block) |
908 | { | |
909 | struct thresh_restart tr; | |
910 | u32 low = 0, high = 0; | |
911 | ||
912 | if (!block) | |
913 | return; | |
914 | ||
915 | if (rdmsr_safe(block->address, &low, &high)) | |
916 | return; | |
917 | ||
918 | if (!(high & MASK_OVERFLOW_HI)) | |
919 | return; | |
920 | ||
921 | /* Log the MCE which caused the threshold event. */ | |
922 | log_error_thresholding(block->bank, ((u64)high << 32) | low); | |
923 | ||
924 | /* Reset threshold block after logging error. */ | |
925 | memset(&tr, 0, sizeof(tr)); | |
926 | tr.b = block; | |
927 | threshold_restart_bank(&tr); | |
928 | } | |
929 | ||
89b831ef | 930 | /* |
37d43acf YG |
931 | * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt |
932 | * goes off when error_count reaches threshold_limit. | |
89b831ef | 933 | */ |
b2762686 | 934 | static void amd_threshold_interrupt(void) |
89b831ef | 935 | { |
17ef4af0 YG |
936 | struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; |
937 | unsigned int bank, cpu = smp_processor_id(); | |
89b831ef | 938 | |
bafcdd3b | 939 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 940 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 941 | continue; |
44612a3a | 942 | |
17ef4af0 YG |
943 | first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; |
944 | if (!first_block) | |
945 | continue; | |
18807ddb | 946 | |
17ef4af0 YG |
947 | /* |
948 | * The first block is also the head of the list. Check it first | |
949 | * before iterating over the rest. | |
950 | */ | |
951 | log_and_reset_block(first_block); | |
952 | list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) | |
953 | log_and_reset_block(block); | |
37d43acf | 954 | } |
89b831ef JS |
955 | } |
956 | ||
957 | /* | |
958 | * Sysfs Interface | |
959 | */ | |
960 | ||
89b831ef | 961 | struct threshold_attr { |
2903ee85 | 962 | struct attribute attr; |
1cb2a8e1 IM |
963 | ssize_t (*show) (struct threshold_block *, char *); |
964 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
965 | }; |
966 | ||
1cb2a8e1 IM |
967 | #define SHOW_FIELDS(name) \ |
968 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
969 | { \ | |
18c20f37 | 970 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 971 | } |
89b831ef JS |
972 | SHOW_FIELDS(interrupt_enable) |
973 | SHOW_FIELDS(threshold_limit) | |
974 | ||
1cb2a8e1 | 975 | static ssize_t |
9319cec8 | 976 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 977 | { |
4cd4601d | 978 | struct thresh_restart tr; |
1cb2a8e1 | 979 | unsigned long new; |
1cb2a8e1 | 980 | |
f227d430 BP |
981 | if (!b->interrupt_capable) |
982 | return -EINVAL; | |
983 | ||
164109e3 | 984 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 985 | return -EINVAL; |
1cb2a8e1 | 986 | |
89b831ef JS |
987 | b->interrupt_enable = !!new; |
988 | ||
9c37c9d8 | 989 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 990 | tr.b = b; |
1cb2a8e1 | 991 | |
a6b6a14e | 992 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 993 | |
9319cec8 | 994 | return size; |
89b831ef JS |
995 | } |
996 | ||
1cb2a8e1 | 997 | static ssize_t |
9319cec8 | 998 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 999 | { |
4cd4601d | 1000 | struct thresh_restart tr; |
1cb2a8e1 | 1001 | unsigned long new; |
1cb2a8e1 | 1002 | |
164109e3 | 1003 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 1004 | return -EINVAL; |
1cb2a8e1 | 1005 | |
89b831ef JS |
1006 | if (new > THRESHOLD_MAX) |
1007 | new = THRESHOLD_MAX; | |
1008 | if (new < 1) | |
1009 | new = 1; | |
1cb2a8e1 | 1010 | |
9c37c9d8 | 1011 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 1012 | tr.old_limit = b->threshold_limit; |
89b831ef | 1013 | b->threshold_limit = new; |
4cd4601d | 1014 | tr.b = b; |
89b831ef | 1015 | |
a6b6a14e | 1016 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 1017 | |
9319cec8 | 1018 | return size; |
89b831ef JS |
1019 | } |
1020 | ||
4cd4601d MT |
1021 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
1022 | { | |
2c9c42fa BP |
1023 | u32 lo, hi; |
1024 | ||
1025 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 1026 | |
2c9c42fa BP |
1027 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
1028 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
1029 | } |
1030 | ||
6e927361 BP |
1031 | static struct threshold_attr error_count = { |
1032 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
1033 | .show = show_error_count, | |
1034 | }; | |
89b831ef | 1035 | |
34fa1967 HS |
1036 | #define RW_ATTR(val) \ |
1037 | static struct threshold_attr val = { \ | |
1038 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
1039 | .show = show_## val, \ | |
1040 | .store = store_## val, \ | |
89b831ef JS |
1041 | }; |
1042 | ||
2903ee85 JS |
1043 | RW_ATTR(interrupt_enable); |
1044 | RW_ATTR(threshold_limit); | |
89b831ef JS |
1045 | |
1046 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
1047 | &threshold_limit.attr, |
1048 | &error_count.attr, | |
d26ecc48 BP |
1049 | NULL, /* possibly interrupt_enable if supported, see below */ |
1050 | NULL, | |
89b831ef JS |
1051 | }; |
1052 | ||
1cb2a8e1 IM |
1053 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
1054 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
1055 | |
1056 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
1057 | { | |
95268664 | 1058 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1059 | struct threshold_attr *a = to_attr(attr); |
1060 | ssize_t ret; | |
1cb2a8e1 | 1061 | |
89b831ef | 1062 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 1063 | |
89b831ef JS |
1064 | return ret; |
1065 | } | |
1066 | ||
1067 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
1068 | const char *buf, size_t count) | |
1069 | { | |
95268664 | 1070 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
1071 | struct threshold_attr *a = to_attr(attr); |
1072 | ssize_t ret; | |
1cb2a8e1 | 1073 | |
89b831ef | 1074 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 1075 | |
89b831ef JS |
1076 | return ret; |
1077 | } | |
1078 | ||
52cf25d0 | 1079 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
1080 | .show = show, |
1081 | .store = store, | |
89b831ef JS |
1082 | }; |
1083 | ||
1084 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
1085 | .sysfs_ops = &threshold_ops, |
1086 | .default_attrs = default_attrs, | |
89b831ef JS |
1087 | }; |
1088 | ||
87a6d409 YG |
1089 | static const char *get_name(unsigned int bank, struct threshold_block *b) |
1090 | { | |
e5d6a126 | 1091 | enum smca_bank_types bank_type; |
87a6d409 YG |
1092 | |
1093 | if (!mce_flags.smca) { | |
1094 | if (b && bank == 4) | |
1095 | return bank4_names(b); | |
1096 | ||
1097 | return th_names[bank]; | |
1098 | } | |
1099 | ||
e5d6a126 YG |
1100 | bank_type = smca_get_bank_type(bank); |
1101 | if (bank_type >= N_SMCA_BANK_TYPES) | |
87a6d409 YG |
1102 | return NULL; |
1103 | ||
87a6d409 YG |
1104 | if (b && bank_type == SMCA_UMC) { |
1105 | if (b->block < ARRAY_SIZE(smca_umc_block_names)) | |
1106 | return smca_umc_block_names[b->block]; | |
1107 | return NULL; | |
1108 | } | |
1109 | ||
0b737a9c YG |
1110 | if (smca_banks[bank].hwid->count == 1) |
1111 | return smca_get_name(bank_type); | |
1112 | ||
87a6d409 | 1113 | snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, |
c09a8c40 | 1114 | "%s_%x", smca_get_name(bank_type), |
0b737a9c | 1115 | smca_banks[bank].sysfs_id); |
87a6d409 YG |
1116 | return buf_mcatype; |
1117 | } | |
1118 | ||
148f9bb8 PG |
1119 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
1120 | unsigned int block, u32 address) | |
95268664 | 1121 | { |
95268664 | 1122 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
1123 | u32 low, high; |
1124 | int err; | |
95268664 | 1125 | |
bafcdd3b | 1126 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
1127 | return 0; |
1128 | ||
a6b6a14e | 1129 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 1130 | return 0; |
95268664 JS |
1131 | |
1132 | if (!(high & MASK_VALID_HI)) { | |
1133 | if (block) | |
1134 | goto recurse; | |
1135 | else | |
1136 | return 0; | |
1137 | } | |
1138 | ||
24ce0e96 JB |
1139 | if (!(high & MASK_CNTP_HI) || |
1140 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
1141 | goto recurse; |
1142 | ||
1143 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
1144 | if (!b) | |
1145 | return -ENOMEM; | |
95268664 | 1146 | |
1cb2a8e1 IM |
1147 | b->block = block; |
1148 | b->bank = bank; | |
1149 | b->cpu = cpu; | |
1150 | b->address = address; | |
1151 | b->interrupt_enable = 0; | |
f227d430 | 1152 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 1153 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 1154 | |
d79f931f | 1155 | if (b->interrupt_capable) { |
d26ecc48 | 1156 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
1157 | b->interrupt_enable = 1; |
1158 | } else { | |
d26ecc48 | 1159 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 1160 | } |
d26ecc48 | 1161 | |
95268664 JS |
1162 | INIT_LIST_HEAD(&b->miscj); |
1163 | ||
1cb2a8e1 | 1164 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
1165 | list_add(&b->miscj, |
1166 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 1167 | } else { |
95268664 | 1168 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 1169 | } |
95268664 | 1170 | |
542eb75a GKH |
1171 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
1172 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
87a6d409 | 1173 | get_name(bank, b)); |
95268664 JS |
1174 | if (err) |
1175 | goto out_free; | |
1176 | recurse: | |
fbf96cf9 | 1177 | address = get_block_address(address, low, high, bank, ++block); |
8dd1e17a AG |
1178 | if (!address) |
1179 | return 0; | |
95268664 | 1180 | |
8dd1e17a | 1181 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
1182 | if (err) |
1183 | goto out_free; | |
1184 | ||
213eca7f GK |
1185 | if (b) |
1186 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 1187 | |
95268664 JS |
1188 | return err; |
1189 | ||
1190 | out_free: | |
1191 | if (b) { | |
38a382ae | 1192 | kobject_put(&b->kobj); |
d9a5ac9e | 1193 | list_del(&b->miscj); |
95268664 JS |
1194 | kfree(b); |
1195 | } | |
1196 | return err; | |
1197 | } | |
1198 | ||
148f9bb8 | 1199 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
1200 | { |
1201 | struct list_head *head = &b->blocks->miscj; | |
1202 | struct threshold_block *pos = NULL; | |
1203 | struct threshold_block *tmp = NULL; | |
1204 | int err = 0; | |
1205 | ||
1206 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
1207 | if (err) | |
1208 | return err; | |
1209 | ||
1210 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
1211 | ||
1212 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
1213 | if (err) { | |
1214 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
1215 | kobject_del(&pos->kobj); | |
1216 | ||
1217 | return err; | |
1218 | } | |
1219 | } | |
1220 | return err; | |
1221 | } | |
1222 | ||
148f9bb8 | 1223 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 1224 | { |
d6126ef5 | 1225 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 1226 | struct amd_northbridge *nb = NULL; |
92e26e2a | 1227 | struct threshold_bank *b = NULL; |
87a6d409 | 1228 | const char *name = get_name(bank, NULL); |
92e26e2a | 1229 | int err = 0; |
95268664 | 1230 | |
0dad3a30 TG |
1231 | if (!dev) |
1232 | return -ENODEV; | |
1233 | ||
c76e8164 | 1234 | if (is_shared_bank(bank)) { |
019f34fc | 1235 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
1236 | |
1237 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 1238 | if (nb && nb->bank4) { |
019f34fc BP |
1239 | /* yes, use it */ |
1240 | b = nb->bank4; | |
1241 | err = kobject_add(b->kobj, &dev->kobj, name); | |
1242 | if (err) | |
1243 | goto out; | |
1244 | ||
1245 | per_cpu(threshold_banks, cpu)[bank] = b; | |
473e90b2 | 1246 | refcount_inc(&b->cpus); |
019f34fc BP |
1247 | |
1248 | err = __threshold_add_blocks(b); | |
1249 | ||
1250 | goto out; | |
1251 | } | |
1252 | } | |
1253 | ||
95268664 | 1254 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
1255 | if (!b) { |
1256 | err = -ENOMEM; | |
1257 | goto out; | |
1258 | } | |
89b831ef | 1259 | |
e032d807 | 1260 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
1261 | if (!b->kobj) { |
1262 | err = -EINVAL; | |
a521cf20 | 1263 | goto out_free; |
92e26e2a | 1264 | } |
95268664 | 1265 | |
89b831ef | 1266 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 1267 | |
c76e8164 | 1268 | if (is_shared_bank(bank)) { |
473e90b2 | 1269 | refcount_set(&b->cpus, 1); |
019f34fc BP |
1270 | |
1271 | /* nb is already initialized, see above */ | |
21c5e50e DB |
1272 | if (nb) { |
1273 | WARN_ON(nb->bank4); | |
1274 | nb->bank4 = b; | |
1275 | } | |
019f34fc BP |
1276 | } |
1277 | ||
74ab0e7a | 1278 | err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank)); |
92e26e2a BP |
1279 | if (!err) |
1280 | goto out; | |
95268664 | 1281 | |
019f34fc | 1282 | out_free: |
95268664 | 1283 | kfree(b); |
019f34fc BP |
1284 | |
1285 | out: | |
89b831ef JS |
1286 | return err; |
1287 | } | |
1288 | ||
be6b5a35 | 1289 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
1290 | unsigned int bank) |
1291 | { | |
1292 | struct threshold_block *pos = NULL; | |
1293 | struct threshold_block *tmp = NULL; | |
1294 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
1295 | ||
1296 | if (!head) | |
1297 | return; | |
1298 | ||
1299 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 1300 | kobject_put(&pos->kobj); |
95268664 JS |
1301 | list_del(&pos->miscj); |
1302 | kfree(pos); | |
1303 | } | |
1304 | ||
1305 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
1306 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
1307 | } | |
1308 | ||
019f34fc BP |
1309 | static void __threshold_remove_blocks(struct threshold_bank *b) |
1310 | { | |
1311 | struct threshold_block *pos = NULL; | |
1312 | struct threshold_block *tmp = NULL; | |
1313 | ||
1314 | kobject_del(b->kobj); | |
1315 | ||
1316 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
1317 | kobject_del(&pos->kobj); | |
1318 | } | |
1319 | ||
be6b5a35 | 1320 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 1321 | { |
019f34fc | 1322 | struct amd_northbridge *nb; |
89b831ef | 1323 | struct threshold_bank *b; |
89b831ef JS |
1324 | |
1325 | b = per_cpu(threshold_banks, cpu)[bank]; | |
1326 | if (!b) | |
1327 | return; | |
019f34fc | 1328 | |
95268664 JS |
1329 | if (!b->blocks) |
1330 | goto free_out; | |
1331 | ||
c76e8164 | 1332 | if (is_shared_bank(bank)) { |
473e90b2 | 1333 | if (!refcount_dec_and_test(&b->cpus)) { |
019f34fc BP |
1334 | __threshold_remove_blocks(b); |
1335 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
1336 | return; | |
1337 | } else { | |
1338 | /* | |
1339 | * the last CPU on this node using the shared bank is | |
1340 | * going away, remove that bank now. | |
1341 | */ | |
1342 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
1343 | nb->bank4 = NULL; | |
1344 | } | |
1345 | } | |
1346 | ||
95268664 JS |
1347 | deallocate_threshold_block(cpu, bank); |
1348 | ||
1349 | free_out: | |
8735728e | 1350 | kobject_del(b->kobj); |
38a382ae | 1351 | kobject_put(b->kobj); |
95268664 JS |
1352 | kfree(b); |
1353 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
1354 | } |
1355 | ||
4d7b02d5 | 1356 | int mce_threshold_remove_device(unsigned int cpu) |
89b831ef | 1357 | { |
2903ee85 | 1358 | unsigned int bank; |
89b831ef | 1359 | |
4d7b02d5 SAS |
1360 | if (!thresholding_en) |
1361 | return 0; | |
1362 | ||
bafcdd3b | 1363 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 1364 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
1365 | continue; |
1366 | threshold_remove_bank(cpu, bank); | |
1367 | } | |
bafcdd3b | 1368 | kfree(per_cpu(threshold_banks, cpu)); |
ec553abb | 1369 | per_cpu(threshold_banks, cpu) = NULL; |
4d7b02d5 | 1370 | return 0; |
89b831ef JS |
1371 | } |
1372 | ||
09436372 | 1373 | /* create dir/files for all valid threshold banks */ |
4d7b02d5 | 1374 | int mce_threshold_create_device(unsigned int cpu) |
89b831ef | 1375 | { |
09436372 SAS |
1376 | unsigned int bank; |
1377 | struct threshold_bank **bp; | |
1378 | int err = 0; | |
1379 | ||
4d7b02d5 SAS |
1380 | if (!thresholding_en) |
1381 | return 0; | |
1382 | ||
7f34b935 SAS |
1383 | bp = per_cpu(threshold_banks, cpu); |
1384 | if (bp) | |
1385 | return 0; | |
1386 | ||
09436372 SAS |
1387 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
1388 | GFP_KERNEL); | |
1389 | if (!bp) | |
1390 | return -ENOMEM; | |
1391 | ||
1392 | per_cpu(threshold_banks, cpu) = bp; | |
1393 | ||
1394 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
1395 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) | |
1396 | continue; | |
1397 | err = threshold_create_bank(cpu, bank); | |
1398 | if (err) | |
ec553abb | 1399 | goto err; |
89b831ef | 1400 | } |
ec553abb SAS |
1401 | return err; |
1402 | err: | |
4d7b02d5 | 1403 | mce_threshold_remove_device(cpu); |
09436372 | 1404 | return err; |
89b831ef JS |
1405 | } |
1406 | ||
89b831ef JS |
1407 | static __init int threshold_init_device(void) |
1408 | { | |
2903ee85 | 1409 | unsigned lcpu = 0; |
89b831ef | 1410 | |
254fe9c7 BP |
1411 | if (mce_threshold_vector == amd_threshold_interrupt) |
1412 | thresholding_en = true; | |
1413 | ||
89b831ef JS |
1414 | /* to hit CPUs online before the notifier is up */ |
1415 | for_each_online_cpu(lcpu) { | |
4d7b02d5 | 1416 | int err = mce_threshold_create_device(lcpu); |
1cb2a8e1 | 1417 | |
89b831ef | 1418 | if (err) |
fff2e89f | 1419 | return err; |
89b831ef | 1420 | } |
1cb2a8e1 | 1421 | |
fff2e89f | 1422 | return 0; |
89b831ef | 1423 | } |
a8fccdb0 LJ |
1424 | /* |
1425 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1426 | * 1. xen_late_init_mcelog | |
1427 | * 2. mcheck_init_device | |
1428 | * 3. threshold_init_device | |
1429 | * | |
1430 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1431 | * native mce_chrdev_device registration if running under xen platform; | |
1432 | * | |
1433 | * mcheck_init_device should be inited before threshold_init_device to | |
1434 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1435 | * | |
1436 | * so we use following _initcalls | |
1437 | * 1. device_initcall(xen_late_init_mcelog); | |
1438 | * 2. device_initcall_sync(mcheck_init_device); | |
1439 | * 3. late_initcall(threshold_init_device); | |
1440 | * | |
1441 | * when running under xen, the initcall order is 1,2,3; | |
1442 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1443 | */ | |
1444 | late_initcall(threshold_init_device); |