Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
60f116fc | 31 | #define NR_BLOCKS 5 |
2903ee85 JS |
32 | #define THRESHOLD_MAX 0xFFF |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
f57a1f3c AG |
52 | /* Scalable MCA: */ |
53 | ||
54 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
55 | #define SMCA_THR_LVT_OFF 0xF000 | |
56 | ||
336d335a BP |
57 | static const char * const th_names[] = { |
58 | "load_store", | |
59 | "insn_fetch", | |
60 | "combined_unit", | |
61 | "", | |
62 | "northbridge", | |
63 | "execution_unit", | |
64 | }; | |
65 | ||
be0aec23 AG |
66 | /* Define HWID to IP type mappings for Scalable MCA */ |
67 | struct amd_hwid amd_hwids[] = { | |
68 | [SMCA_F17H_CORE] = { "f17h_core", 0xB0 }, | |
69 | [SMCA_DF] = { "data_fabric", 0x2E }, | |
70 | [SMCA_UMC] = { "umc", 0x96 }, | |
71 | [SMCA_PB] = { "param_block", 0x5 }, | |
72 | [SMCA_PSP] = { "psp", 0xFF }, | |
73 | [SMCA_SMU] = { "smu", 0x1 }, | |
74 | }; | |
75 | EXPORT_SYMBOL_GPL(amd_hwids); | |
76 | ||
77 | const char * const amd_core_mcablock_names[] = { | |
78 | [SMCA_LS] = "load_store", | |
79 | [SMCA_IF] = "insn_fetch", | |
80 | [SMCA_L2_CACHE] = "l2_cache", | |
81 | [SMCA_DE] = "decode_unit", | |
82 | [RES] = "", | |
83 | [SMCA_EX] = "execution_unit", | |
84 | [SMCA_FP] = "floating_point", | |
85 | [SMCA_L3_CACHE] = "l3_cache", | |
86 | }; | |
87 | EXPORT_SYMBOL_GPL(amd_core_mcablock_names); | |
88 | ||
89 | const char * const amd_df_mcablock_names[] = { | |
90 | [SMCA_CS] = "coherent_slave", | |
91 | [SMCA_PIE] = "pie", | |
92 | }; | |
93 | EXPORT_SYMBOL_GPL(amd_df_mcablock_names); | |
94 | ||
bafcdd3b | 95 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
96 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
97 | ||
b2762686 | 98 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
99 | static void amd_deferred_error_interrupt(void); |
100 | ||
101 | static void default_deferred_error_interrupt(void) | |
102 | { | |
103 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
104 | } | |
105 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 106 | |
89b831ef JS |
107 | /* |
108 | * CPU Initialization | |
109 | */ | |
110 | ||
4cd4601d | 111 | struct thresh_restart { |
1cb2a8e1 IM |
112 | struct threshold_block *b; |
113 | int reset; | |
9c37c9d8 RR |
114 | int set_lvt_off; |
115 | int lvt_off; | |
1cb2a8e1 | 116 | u16 old_limit; |
4cd4601d MT |
117 | }; |
118 | ||
c76e8164 BO |
119 | static inline bool is_shared_bank(int bank) |
120 | { | |
284b965c AG |
121 | /* |
122 | * Scalable MCA provides for only one core to have access to the MSRs of | |
123 | * a shared bank. | |
124 | */ | |
125 | if (mce_flags.smca) | |
126 | return false; | |
127 | ||
c76e8164 BO |
128 | /* Bank 4 is for northbridge reporting and is thus shared */ |
129 | return (bank == 4); | |
130 | } | |
131 | ||
2cd4c303 | 132 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
133 | { |
134 | switch (b->address) { | |
135 | /* MSR4_MISC0 */ | |
136 | case 0x00000413: | |
137 | return "dram"; | |
138 | ||
139 | case 0xc0000408: | |
140 | return "ht_links"; | |
141 | ||
142 | case 0xc0000409: | |
143 | return "l3_cache"; | |
144 | ||
145 | default: | |
146 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
147 | return ""; | |
148 | } | |
149 | }; | |
150 | ||
151 | ||
f227d430 BP |
152 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
153 | { | |
154 | /* | |
155 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
156 | */ | |
157 | if (bank == 4) | |
158 | return true; | |
159 | ||
160 | /* | |
161 | * IntP: interrupt present; if this bit is set, the thresholding | |
162 | * bank can generate APIC LVT interrupts | |
163 | */ | |
164 | return msr_high_bits & BIT(28); | |
165 | } | |
166 | ||
bbaff08d RR |
167 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
168 | { | |
169 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
170 | ||
171 | if (apic < 0) { | |
172 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
173 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
174 | b->bank, b->block, b->address, hi, lo); | |
175 | return 0; | |
176 | } | |
177 | ||
178 | if (apic != msr) { | |
f57a1f3c AG |
179 | /* |
180 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
181 | * the BIOS provides the value. The original field where LVT offset | |
182 | * was set is reserved. Return early here: | |
183 | */ | |
184 | if (mce_flags.smca) | |
185 | return 0; | |
186 | ||
bbaff08d RR |
187 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
188 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
189 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
190 | return 0; | |
191 | } | |
192 | ||
193 | return 1; | |
194 | }; | |
195 | ||
ea2ca36b | 196 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 197 | static void threshold_restart_bank(void *_tr) |
89b831ef | 198 | { |
4cd4601d | 199 | struct thresh_restart *tr = _tr; |
7203a049 | 200 | u32 hi, lo; |
89b831ef | 201 | |
7203a049 | 202 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 203 | |
7203a049 | 204 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 205 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 206 | |
4cd4601d | 207 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
208 | hi = |
209 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
210 | (THRESHOLD_MAX - tr->b->threshold_limit); |
211 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 212 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 213 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 214 | |
7203a049 | 215 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
216 | (new_count & THRESHOLD_MAX); |
217 | } | |
218 | ||
f227d430 BP |
219 | /* clear IntType */ |
220 | hi &= ~MASK_INT_TYPE_HI; | |
221 | ||
222 | if (!tr->b->interrupt_capable) | |
223 | goto done; | |
224 | ||
9c37c9d8 | 225 | if (tr->set_lvt_off) { |
bbaff08d RR |
226 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
227 | /* set new lvt offset */ | |
228 | hi &= ~MASK_LVTOFF_HI; | |
229 | hi |= tr->lvt_off << 20; | |
230 | } | |
9c37c9d8 RR |
231 | } |
232 | ||
f227d430 BP |
233 | if (tr->b->interrupt_enable) |
234 | hi |= INT_TYPE_APIC; | |
235 | ||
236 | done: | |
89b831ef | 237 | |
7203a049 RR |
238 | hi |= MASK_COUNT_EN_HI; |
239 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
240 | } |
241 | ||
9c37c9d8 RR |
242 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
243 | { | |
244 | struct thresh_restart tr = { | |
245 | .b = b, | |
246 | .set_lvt_off = 1, | |
247 | .lvt_off = offset, | |
248 | }; | |
249 | ||
250 | b->threshold_limit = THRESHOLD_MAX; | |
251 | threshold_restart_bank(&tr); | |
252 | }; | |
253 | ||
868c00bb | 254 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
255 | { |
256 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
257 | APIC_EILVT_MSG_FIX, 0)) | |
258 | return new; | |
259 | ||
260 | return reserved; | |
261 | } | |
262 | ||
24fd78a8 AG |
263 | static int setup_APIC_deferred_error(int reserved, int new) |
264 | { | |
265 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
266 | APIC_EILVT_MSG_FIX, 0)) | |
267 | return new; | |
268 | ||
269 | return reserved; | |
270 | } | |
271 | ||
272 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
273 | { | |
274 | u32 low = 0, high = 0; | |
275 | int def_offset = -1, def_new; | |
276 | ||
277 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
278 | return; | |
279 | ||
280 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
281 | if (!(low & MASK_DEF_LVTOFF)) { | |
282 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
283 | def_new = DEF_LVT_OFF; | |
284 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
285 | } | |
286 | ||
287 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
288 | if ((def_offset == def_new) && | |
289 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
290 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
291 | ||
292 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
293 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
294 | } | |
295 | ||
8dd1e17a AG |
296 | static u32 get_block_address(u32 current_addr, u32 low, u32 high, |
297 | unsigned int bank, unsigned int block) | |
298 | { | |
299 | u32 addr = 0, offset = 0; | |
300 | ||
301 | if (mce_flags.smca) { | |
302 | if (!block) { | |
303 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
304 | } else { | |
305 | /* | |
306 | * For SMCA enabled processors, BLKPTR field of the | |
307 | * first MISC register (MCx_MISC0) indicates presence of | |
308 | * additional MISC register set (MISC1-4). | |
309 | */ | |
310 | u32 low, high; | |
311 | ||
312 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) | |
313 | return addr; | |
314 | ||
315 | if (!(low & MCI_CONFIG_MCAX)) | |
316 | return addr; | |
317 | ||
318 | if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && | |
319 | (low & MASK_BLKPTR_LO)) | |
320 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
321 | } | |
322 | return addr; | |
323 | } | |
324 | ||
325 | /* Fall back to method we used for older processors: */ | |
326 | switch (block) { | |
327 | case 0: | |
d9d73fcc | 328 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
329 | break; |
330 | case 1: | |
331 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
332 | if (offset) | |
333 | addr = MCG_XBLK_ADDR + offset; | |
334 | break; | |
335 | default: | |
336 | addr = ++current_addr; | |
337 | } | |
338 | return addr; | |
339 | } | |
340 | ||
429893b1 BP |
341 | static int |
342 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
343 | int offset, u32 misc_high) | |
344 | { | |
345 | unsigned int cpu = smp_processor_id(); | |
e128b4f4 | 346 | u32 smca_low, smca_high, smca_addr; |
429893b1 BP |
347 | struct threshold_block b; |
348 | int new; | |
349 | ||
350 | if (!block) | |
351 | per_cpu(bank_map, cpu) |= (1 << bank); | |
352 | ||
353 | memset(&b, 0, sizeof(b)); | |
354 | b.cpu = cpu; | |
355 | b.bank = bank; | |
356 | b.block = block; | |
357 | b.address = addr; | |
358 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
359 | ||
360 | if (!b.interrupt_capable) | |
361 | goto done; | |
362 | ||
363 | b.interrupt_enable = 1; | |
364 | ||
e128b4f4 BP |
365 | if (!mce_flags.smca) { |
366 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
367 | goto set_offset; | |
368 | } | |
32544f06 | 369 | |
e128b4f4 | 370 | smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
32544f06 | 371 | |
e128b4f4 BP |
372 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { |
373 | /* | |
374 | * OS is required to set the MCAX bit to acknowledge that it is | |
375 | * now using the new MSR ranges and new registers under each | |
376 | * bank. It also means that the OS will configure deferred | |
377 | * errors in the new MCx_CONFIG register. If the bit is not set, | |
378 | * uncorrectable errors will cause a system panic. | |
379 | * | |
380 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) | |
381 | */ | |
382 | smca_high |= BIT(0); | |
429893b1 | 383 | |
e128b4f4 BP |
384 | /* |
385 | * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} | |
386 | * registers with the option of additionally logging to | |
387 | * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. | |
388 | * | |
389 | * This bit is usually set by BIOS to retain the old behavior | |
390 | * for OSes that don't use the new registers. Linux supports the | |
391 | * new registers so let's disable that additional logging here. | |
392 | * | |
393 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high | |
394 | * portion of the MSR). | |
395 | */ | |
396 | smca_high &= ~BIT(2); | |
429893b1 | 397 | |
e128b4f4 | 398 | wrmsr(smca_addr, smca_low, smca_high); |
429893b1 BP |
399 | } |
400 | ||
e128b4f4 BP |
401 | /* Gather LVT offset for thresholding: */ |
402 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
403 | goto out; | |
404 | ||
405 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
406 | ||
407 | set_offset: | |
429893b1 BP |
408 | offset = setup_APIC_mce_threshold(offset, new); |
409 | ||
410 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
411 | mce_threshold_vector = amd_threshold_interrupt; | |
412 | ||
413 | done: | |
414 | mce_threshold_block_init(&b, offset); | |
415 | ||
416 | out: | |
417 | return offset; | |
418 | } | |
419 | ||
95268664 | 420 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 421 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 422 | { |
95268664 | 423 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 424 | unsigned int bank, block; |
429893b1 | 425 | int offset = -1; |
89b831ef | 426 | |
bafcdd3b | 427 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 | 428 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
429 | address = get_block_address(address, low, high, bank, block); |
430 | if (!address) | |
431 | break; | |
95268664 JS |
432 | |
433 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 434 | break; |
95268664 | 435 | |
6dcbfe4f BP |
436 | if (!(high & MASK_VALID_HI)) |
437 | continue; | |
95268664 | 438 | |
24ce0e96 JB |
439 | if (!(high & MASK_CNTP_HI) || |
440 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
441 | continue; |
442 | ||
429893b1 | 443 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 444 | } |
89b831ef | 445 | } |
24fd78a8 AG |
446 | |
447 | if (mce_flags.succor) | |
448 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
449 | } |
450 | ||
34102009 YG |
451 | static void |
452 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) | |
afdf344e | 453 | { |
34102009 YG |
454 | u32 msr_status = msr_ops.status(bank); |
455 | u32 msr_addr = msr_ops.addr(bank); | |
afdf344e AG |
456 | struct mce m; |
457 | u64 status; | |
458 | ||
34102009 YG |
459 | WARN_ON_ONCE(deferred_err && threshold_err); |
460 | ||
461 | if (deferred_err && mce_flags.smca) { | |
462 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); | |
463 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); | |
464 | } | |
465 | ||
466 | rdmsrl(msr_status, status); | |
467 | ||
afdf344e AG |
468 | if (!(status & MCI_STATUS_VAL)) |
469 | return; | |
470 | ||
471 | mce_setup(&m); | |
472 | ||
473 | m.status = status; | |
474 | m.bank = bank; | |
6e6e746e | 475 | |
afdf344e AG |
476 | if (threshold_err) |
477 | m.misc = misc; | |
478 | ||
6e6e746e | 479 | if (m.status & MCI_STATUS_ADDRV) |
34102009 | 480 | rdmsrl(msr_addr, m.addr); |
afdf344e | 481 | |
6e6e746e | 482 | mce_log(&m); |
34102009 YG |
483 | |
484 | wrmsrl(msr_status, 0); | |
afdf344e AG |
485 | } |
486 | ||
24fd78a8 AG |
487 | static inline void __smp_deferred_error_interrupt(void) |
488 | { | |
489 | inc_irq_stat(irq_deferred_error_count); | |
490 | deferred_error_int_vector(); | |
491 | } | |
492 | ||
493 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
494 | { | |
495 | entering_irq(); | |
496 | __smp_deferred_error_interrupt(); | |
497 | exiting_ack_irq(); | |
498 | } | |
499 | ||
500 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
501 | { | |
502 | entering_irq(); | |
503 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
504 | __smp_deferred_error_interrupt(); | |
505 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
506 | exiting_ack_irq(); | |
507 | } | |
508 | ||
509 | /* APIC interrupt handler for deferred errors */ | |
510 | static void amd_deferred_error_interrupt(void) | |
511 | { | |
24fd78a8 | 512 | unsigned int bank; |
34102009 YG |
513 | u32 msr_status; |
514 | u64 status; | |
24fd78a8 AG |
515 | |
516 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
34102009 YG |
517 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
518 | : msr_ops.status(bank); | |
519 | ||
520 | rdmsrl(msr_status, status); | |
24fd78a8 AG |
521 | |
522 | if (!(status & MCI_STATUS_VAL) || | |
523 | !(status & MCI_STATUS_DEFERRED)) | |
524 | continue; | |
525 | ||
34102009 | 526 | __log_error(bank, true, false, 0); |
24fd78a8 AG |
527 | break; |
528 | } | |
529 | } | |
530 | ||
89b831ef JS |
531 | /* |
532 | * APIC Interrupt Handler | |
533 | */ | |
534 | ||
535 | /* | |
536 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
537 | * the interrupt goes off when error_count reaches threshold_limit. | |
538 | * the handler will simply log mcelog w/ software defined bank number. | |
539 | */ | |
afdf344e | 540 | |
b2762686 | 541 | static void amd_threshold_interrupt(void) |
89b831ef | 542 | { |
1cb2a8e1 | 543 | u32 low = 0, high = 0, address = 0; |
44612a3a | 544 | int cpu = smp_processor_id(); |
95268664 | 545 | unsigned int bank, block; |
89b831ef | 546 | |
89b831ef | 547 | /* assume first bank caused it */ |
bafcdd3b | 548 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 549 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 550 | continue; |
95268664 | 551 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
552 | address = get_block_address(address, low, high, bank, block); |
553 | if (!address) | |
554 | break; | |
95268664 JS |
555 | |
556 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 557 | break; |
95268664 JS |
558 | |
559 | if (!(high & MASK_VALID_HI)) { | |
560 | if (block) | |
561 | continue; | |
562 | else | |
563 | break; | |
564 | } | |
565 | ||
24ce0e96 JB |
566 | if (!(high & MASK_CNTP_HI) || |
567 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
568 | continue; |
569 | ||
1cb2a8e1 IM |
570 | /* |
571 | * Log the machine check that caused the threshold | |
572 | * event. | |
573 | */ | |
44612a3a CY |
574 | if (high & MASK_OVERFLOW_HI) |
575 | goto log; | |
89b831ef JS |
576 | } |
577 | } | |
44612a3a CY |
578 | return; |
579 | ||
580 | log: | |
34102009 | 581 | __log_error(bank, false, true, ((u64)high << 32) | low); |
89b831ef JS |
582 | } |
583 | ||
584 | /* | |
585 | * Sysfs Interface | |
586 | */ | |
587 | ||
89b831ef | 588 | struct threshold_attr { |
2903ee85 | 589 | struct attribute attr; |
1cb2a8e1 IM |
590 | ssize_t (*show) (struct threshold_block *, char *); |
591 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
592 | }; |
593 | ||
1cb2a8e1 IM |
594 | #define SHOW_FIELDS(name) \ |
595 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
596 | { \ | |
18c20f37 | 597 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 598 | } |
89b831ef JS |
599 | SHOW_FIELDS(interrupt_enable) |
600 | SHOW_FIELDS(threshold_limit) | |
601 | ||
1cb2a8e1 | 602 | static ssize_t |
9319cec8 | 603 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 604 | { |
4cd4601d | 605 | struct thresh_restart tr; |
1cb2a8e1 | 606 | unsigned long new; |
1cb2a8e1 | 607 | |
f227d430 BP |
608 | if (!b->interrupt_capable) |
609 | return -EINVAL; | |
610 | ||
164109e3 | 611 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 612 | return -EINVAL; |
1cb2a8e1 | 613 | |
89b831ef JS |
614 | b->interrupt_enable = !!new; |
615 | ||
9c37c9d8 | 616 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 617 | tr.b = b; |
1cb2a8e1 | 618 | |
a6b6a14e | 619 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 620 | |
9319cec8 | 621 | return size; |
89b831ef JS |
622 | } |
623 | ||
1cb2a8e1 | 624 | static ssize_t |
9319cec8 | 625 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 626 | { |
4cd4601d | 627 | struct thresh_restart tr; |
1cb2a8e1 | 628 | unsigned long new; |
1cb2a8e1 | 629 | |
164109e3 | 630 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 631 | return -EINVAL; |
1cb2a8e1 | 632 | |
89b831ef JS |
633 | if (new > THRESHOLD_MAX) |
634 | new = THRESHOLD_MAX; | |
635 | if (new < 1) | |
636 | new = 1; | |
1cb2a8e1 | 637 | |
9c37c9d8 | 638 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 639 | tr.old_limit = b->threshold_limit; |
89b831ef | 640 | b->threshold_limit = new; |
4cd4601d | 641 | tr.b = b; |
89b831ef | 642 | |
a6b6a14e | 643 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 644 | |
9319cec8 | 645 | return size; |
89b831ef JS |
646 | } |
647 | ||
4cd4601d MT |
648 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
649 | { | |
2c9c42fa BP |
650 | u32 lo, hi; |
651 | ||
652 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 653 | |
2c9c42fa BP |
654 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
655 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
656 | } |
657 | ||
6e927361 BP |
658 | static struct threshold_attr error_count = { |
659 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
660 | .show = show_error_count, | |
661 | }; | |
89b831ef | 662 | |
34fa1967 HS |
663 | #define RW_ATTR(val) \ |
664 | static struct threshold_attr val = { \ | |
665 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
666 | .show = show_## val, \ | |
667 | .store = store_## val, \ | |
89b831ef JS |
668 | }; |
669 | ||
2903ee85 JS |
670 | RW_ATTR(interrupt_enable); |
671 | RW_ATTR(threshold_limit); | |
89b831ef JS |
672 | |
673 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
674 | &threshold_limit.attr, |
675 | &error_count.attr, | |
d26ecc48 BP |
676 | NULL, /* possibly interrupt_enable if supported, see below */ |
677 | NULL, | |
89b831ef JS |
678 | }; |
679 | ||
1cb2a8e1 IM |
680 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
681 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
682 | |
683 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
684 | { | |
95268664 | 685 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
686 | struct threshold_attr *a = to_attr(attr); |
687 | ssize_t ret; | |
1cb2a8e1 | 688 | |
89b831ef | 689 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 690 | |
89b831ef JS |
691 | return ret; |
692 | } | |
693 | ||
694 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
695 | const char *buf, size_t count) | |
696 | { | |
95268664 | 697 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
698 | struct threshold_attr *a = to_attr(attr); |
699 | ssize_t ret; | |
1cb2a8e1 | 700 | |
89b831ef | 701 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 702 | |
89b831ef JS |
703 | return ret; |
704 | } | |
705 | ||
52cf25d0 | 706 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
707 | .show = show, |
708 | .store = store, | |
89b831ef JS |
709 | }; |
710 | ||
711 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
712 | .sysfs_ops = &threshold_ops, |
713 | .default_attrs = default_attrs, | |
89b831ef JS |
714 | }; |
715 | ||
148f9bb8 PG |
716 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
717 | unsigned int block, u32 address) | |
95268664 | 718 | { |
95268664 | 719 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
720 | u32 low, high; |
721 | int err; | |
95268664 | 722 | |
bafcdd3b | 723 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
724 | return 0; |
725 | ||
a6b6a14e | 726 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 727 | return 0; |
95268664 JS |
728 | |
729 | if (!(high & MASK_VALID_HI)) { | |
730 | if (block) | |
731 | goto recurse; | |
732 | else | |
733 | return 0; | |
734 | } | |
735 | ||
24ce0e96 JB |
736 | if (!(high & MASK_CNTP_HI) || |
737 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
738 | goto recurse; |
739 | ||
740 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
741 | if (!b) | |
742 | return -ENOMEM; | |
95268664 | 743 | |
1cb2a8e1 IM |
744 | b->block = block; |
745 | b->bank = bank; | |
746 | b->cpu = cpu; | |
747 | b->address = address; | |
748 | b->interrupt_enable = 0; | |
f227d430 | 749 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 750 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 751 | |
d79f931f | 752 | if (b->interrupt_capable) { |
d26ecc48 | 753 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
754 | b->interrupt_enable = 1; |
755 | } else { | |
d26ecc48 | 756 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 757 | } |
d26ecc48 | 758 | |
95268664 JS |
759 | INIT_LIST_HEAD(&b->miscj); |
760 | ||
1cb2a8e1 | 761 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
762 | list_add(&b->miscj, |
763 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 764 | } else { |
95268664 | 765 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 766 | } |
95268664 | 767 | |
542eb75a GKH |
768 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
769 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 770 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
771 | if (err) |
772 | goto out_free; | |
773 | recurse: | |
8dd1e17a AG |
774 | address = get_block_address(address, low, high, bank, ++block); |
775 | if (!address) | |
776 | return 0; | |
95268664 | 777 | |
8dd1e17a | 778 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
779 | if (err) |
780 | goto out_free; | |
781 | ||
213eca7f GK |
782 | if (b) |
783 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 784 | |
95268664 JS |
785 | return err; |
786 | ||
787 | out_free: | |
788 | if (b) { | |
38a382ae | 789 | kobject_put(&b->kobj); |
d9a5ac9e | 790 | list_del(&b->miscj); |
95268664 JS |
791 | kfree(b); |
792 | } | |
793 | return err; | |
794 | } | |
795 | ||
148f9bb8 | 796 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
797 | { |
798 | struct list_head *head = &b->blocks->miscj; | |
799 | struct threshold_block *pos = NULL; | |
800 | struct threshold_block *tmp = NULL; | |
801 | int err = 0; | |
802 | ||
803 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
804 | if (err) | |
805 | return err; | |
806 | ||
807 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
808 | ||
809 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
810 | if (err) { | |
811 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
812 | kobject_del(&pos->kobj); | |
813 | ||
814 | return err; | |
815 | } | |
816 | } | |
817 | return err; | |
818 | } | |
819 | ||
148f9bb8 | 820 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 821 | { |
d6126ef5 | 822 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 823 | struct amd_northbridge *nb = NULL; |
92e26e2a | 824 | struct threshold_bank *b = NULL; |
336d335a | 825 | const char *name = th_names[bank]; |
92e26e2a | 826 | int err = 0; |
95268664 | 827 | |
c76e8164 | 828 | if (is_shared_bank(bank)) { |
019f34fc | 829 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
830 | |
831 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 832 | if (nb && nb->bank4) { |
019f34fc BP |
833 | /* yes, use it */ |
834 | b = nb->bank4; | |
835 | err = kobject_add(b->kobj, &dev->kobj, name); | |
836 | if (err) | |
837 | goto out; | |
838 | ||
839 | per_cpu(threshold_banks, cpu)[bank] = b; | |
840 | atomic_inc(&b->cpus); | |
841 | ||
842 | err = __threshold_add_blocks(b); | |
843 | ||
844 | goto out; | |
845 | } | |
846 | } | |
847 | ||
95268664 | 848 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
849 | if (!b) { |
850 | err = -ENOMEM; | |
851 | goto out; | |
852 | } | |
89b831ef | 853 | |
e032d807 | 854 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
855 | if (!b->kobj) { |
856 | err = -EINVAL; | |
a521cf20 | 857 | goto out_free; |
92e26e2a | 858 | } |
95268664 | 859 | |
89b831ef | 860 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 861 | |
c76e8164 | 862 | if (is_shared_bank(bank)) { |
019f34fc BP |
863 | atomic_set(&b->cpus, 1); |
864 | ||
865 | /* nb is already initialized, see above */ | |
21c5e50e DB |
866 | if (nb) { |
867 | WARN_ON(nb->bank4); | |
868 | nb->bank4 = b; | |
869 | } | |
019f34fc BP |
870 | } |
871 | ||
4b737d78 | 872 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
873 | if (!err) |
874 | goto out; | |
95268664 | 875 | |
019f34fc | 876 | out_free: |
95268664 | 877 | kfree(b); |
019f34fc BP |
878 | |
879 | out: | |
89b831ef JS |
880 | return err; |
881 | } | |
882 | ||
883 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 884 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 885 | { |
2903ee85 | 886 | unsigned int bank; |
bafcdd3b | 887 | struct threshold_bank **bp; |
89b831ef JS |
888 | int err = 0; |
889 | ||
bafcdd3b BO |
890 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
891 | GFP_KERNEL); | |
892 | if (!bp) | |
893 | return -ENOMEM; | |
894 | ||
895 | per_cpu(threshold_banks, cpu) = bp; | |
896 | ||
897 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 898 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
899 | continue; |
900 | err = threshold_create_bank(cpu, bank); | |
901 | if (err) | |
0a17941e | 902 | return err; |
89b831ef | 903 | } |
0a17941e | 904 | |
89b831ef JS |
905 | return err; |
906 | } | |
907 | ||
be6b5a35 | 908 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
909 | unsigned int bank) |
910 | { | |
911 | struct threshold_block *pos = NULL; | |
912 | struct threshold_block *tmp = NULL; | |
913 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
914 | ||
915 | if (!head) | |
916 | return; | |
917 | ||
918 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 919 | kobject_put(&pos->kobj); |
95268664 JS |
920 | list_del(&pos->miscj); |
921 | kfree(pos); | |
922 | } | |
923 | ||
924 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
925 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
926 | } | |
927 | ||
019f34fc BP |
928 | static void __threshold_remove_blocks(struct threshold_bank *b) |
929 | { | |
930 | struct threshold_block *pos = NULL; | |
931 | struct threshold_block *tmp = NULL; | |
932 | ||
933 | kobject_del(b->kobj); | |
934 | ||
935 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
936 | kobject_del(&pos->kobj); | |
937 | } | |
938 | ||
be6b5a35 | 939 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 940 | { |
019f34fc | 941 | struct amd_northbridge *nb; |
89b831ef | 942 | struct threshold_bank *b; |
89b831ef JS |
943 | |
944 | b = per_cpu(threshold_banks, cpu)[bank]; | |
945 | if (!b) | |
946 | return; | |
019f34fc | 947 | |
95268664 JS |
948 | if (!b->blocks) |
949 | goto free_out; | |
950 | ||
c76e8164 | 951 | if (is_shared_bank(bank)) { |
019f34fc BP |
952 | if (!atomic_dec_and_test(&b->cpus)) { |
953 | __threshold_remove_blocks(b); | |
954 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
955 | return; | |
956 | } else { | |
957 | /* | |
958 | * the last CPU on this node using the shared bank is | |
959 | * going away, remove that bank now. | |
960 | */ | |
961 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
962 | nb->bank4 = NULL; | |
963 | } | |
964 | } | |
965 | ||
95268664 JS |
966 | deallocate_threshold_block(cpu, bank); |
967 | ||
968 | free_out: | |
8735728e | 969 | kobject_del(b->kobj); |
38a382ae | 970 | kobject_put(b->kobj); |
95268664 JS |
971 | kfree(b); |
972 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
973 | } |
974 | ||
be6b5a35 | 975 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 976 | { |
2903ee85 | 977 | unsigned int bank; |
89b831ef | 978 | |
bafcdd3b | 979 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 980 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
981 | continue; |
982 | threshold_remove_bank(cpu, bank); | |
983 | } | |
bafcdd3b | 984 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
985 | } |
986 | ||
89b831ef | 987 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 988 | static void |
1cb2a8e1 | 989 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 990 | { |
89b831ef JS |
991 | switch (action) { |
992 | case CPU_ONLINE: | |
8bb78442 | 993 | case CPU_ONLINE_FROZEN: |
89b831ef | 994 | threshold_create_device(cpu); |
89b831ef JS |
995 | break; |
996 | case CPU_DEAD: | |
8bb78442 | 997 | case CPU_DEAD_FROZEN: |
89b831ef JS |
998 | threshold_remove_device(cpu); |
999 | break; | |
1000 | default: | |
1001 | break; | |
1002 | } | |
89b831ef JS |
1003 | } |
1004 | ||
89b831ef JS |
1005 | static __init int threshold_init_device(void) |
1006 | { | |
2903ee85 | 1007 | unsigned lcpu = 0; |
89b831ef | 1008 | |
89b831ef JS |
1009 | /* to hit CPUs online before the notifier is up */ |
1010 | for_each_online_cpu(lcpu) { | |
fff2e89f | 1011 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 1012 | |
89b831ef | 1013 | if (err) |
fff2e89f | 1014 | return err; |
89b831ef | 1015 | } |
8735728e | 1016 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 1017 | |
fff2e89f | 1018 | return 0; |
89b831ef | 1019 | } |
a8fccdb0 LJ |
1020 | /* |
1021 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1022 | * 1. xen_late_init_mcelog | |
1023 | * 2. mcheck_init_device | |
1024 | * 3. threshold_init_device | |
1025 | * | |
1026 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1027 | * native mce_chrdev_device registration if running under xen platform; | |
1028 | * | |
1029 | * mcheck_init_device should be inited before threshold_init_device to | |
1030 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1031 | * | |
1032 | * so we use following _initcalls | |
1033 | * 1. device_initcall(xen_late_init_mcelog); | |
1034 | * 2. device_initcall_sync(mcheck_init_device); | |
1035 | * 3. late_initcall(threshold_init_device); | |
1036 | * | |
1037 | * when running under xen, the initcall order is 1,2,3; | |
1038 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1039 | */ | |
1040 | late_initcall(threshold_init_device); |