Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
60f116fc | 31 | #define NR_BLOCKS 5 |
2903ee85 JS |
32 | #define THRESHOLD_MAX 0xFFF |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
f57a1f3c AG |
52 | /* Scalable MCA: */ |
53 | ||
54 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
55 | #define SMCA_THR_LVT_OFF 0xF000 | |
56 | ||
e6c8f187 AG |
57 | /* |
58 | * OS is required to set the MCAX bit to acknowledge that it is now using the | |
59 | * new MSR ranges and new registers under each bank. It also means that the OS | |
60 | * will configure deferred errors in the new MCx_CONFIG register. If the bit is | |
61 | * not set, uncorrectable errors will cause a system panic. | |
62 | */ | |
63 | #define SMCA_MCAX_EN_OFF 0x1 | |
64 | ||
336d335a BP |
65 | static const char * const th_names[] = { |
66 | "load_store", | |
67 | "insn_fetch", | |
68 | "combined_unit", | |
69 | "", | |
70 | "northbridge", | |
71 | "execution_unit", | |
72 | }; | |
73 | ||
be0aec23 AG |
74 | /* Define HWID to IP type mappings for Scalable MCA */ |
75 | struct amd_hwid amd_hwids[] = { | |
76 | [SMCA_F17H_CORE] = { "f17h_core", 0xB0 }, | |
77 | [SMCA_DF] = { "data_fabric", 0x2E }, | |
78 | [SMCA_UMC] = { "umc", 0x96 }, | |
79 | [SMCA_PB] = { "param_block", 0x5 }, | |
80 | [SMCA_PSP] = { "psp", 0xFF }, | |
81 | [SMCA_SMU] = { "smu", 0x1 }, | |
82 | }; | |
83 | EXPORT_SYMBOL_GPL(amd_hwids); | |
84 | ||
85 | const char * const amd_core_mcablock_names[] = { | |
86 | [SMCA_LS] = "load_store", | |
87 | [SMCA_IF] = "insn_fetch", | |
88 | [SMCA_L2_CACHE] = "l2_cache", | |
89 | [SMCA_DE] = "decode_unit", | |
90 | [RES] = "", | |
91 | [SMCA_EX] = "execution_unit", | |
92 | [SMCA_FP] = "floating_point", | |
93 | [SMCA_L3_CACHE] = "l3_cache", | |
94 | }; | |
95 | EXPORT_SYMBOL_GPL(amd_core_mcablock_names); | |
96 | ||
97 | const char * const amd_df_mcablock_names[] = { | |
98 | [SMCA_CS] = "coherent_slave", | |
99 | [SMCA_PIE] = "pie", | |
100 | }; | |
101 | EXPORT_SYMBOL_GPL(amd_df_mcablock_names); | |
102 | ||
bafcdd3b | 103 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
104 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
105 | ||
b2762686 | 106 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
107 | static void amd_deferred_error_interrupt(void); |
108 | ||
109 | static void default_deferred_error_interrupt(void) | |
110 | { | |
111 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
112 | } | |
113 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 114 | |
89b831ef JS |
115 | /* |
116 | * CPU Initialization | |
117 | */ | |
118 | ||
4cd4601d | 119 | struct thresh_restart { |
1cb2a8e1 IM |
120 | struct threshold_block *b; |
121 | int reset; | |
9c37c9d8 RR |
122 | int set_lvt_off; |
123 | int lvt_off; | |
1cb2a8e1 | 124 | u16 old_limit; |
4cd4601d MT |
125 | }; |
126 | ||
c76e8164 BO |
127 | static inline bool is_shared_bank(int bank) |
128 | { | |
284b965c AG |
129 | /* |
130 | * Scalable MCA provides for only one core to have access to the MSRs of | |
131 | * a shared bank. | |
132 | */ | |
133 | if (mce_flags.smca) | |
134 | return false; | |
135 | ||
c76e8164 BO |
136 | /* Bank 4 is for northbridge reporting and is thus shared */ |
137 | return (bank == 4); | |
138 | } | |
139 | ||
2cd4c303 | 140 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
141 | { |
142 | switch (b->address) { | |
143 | /* MSR4_MISC0 */ | |
144 | case 0x00000413: | |
145 | return "dram"; | |
146 | ||
147 | case 0xc0000408: | |
148 | return "ht_links"; | |
149 | ||
150 | case 0xc0000409: | |
151 | return "l3_cache"; | |
152 | ||
153 | default: | |
154 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
155 | return ""; | |
156 | } | |
157 | }; | |
158 | ||
159 | ||
f227d430 BP |
160 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
161 | { | |
162 | /* | |
163 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
164 | */ | |
165 | if (bank == 4) | |
166 | return true; | |
167 | ||
168 | /* | |
169 | * IntP: interrupt present; if this bit is set, the thresholding | |
170 | * bank can generate APIC LVT interrupts | |
171 | */ | |
172 | return msr_high_bits & BIT(28); | |
173 | } | |
174 | ||
bbaff08d RR |
175 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
176 | { | |
177 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
178 | ||
179 | if (apic < 0) { | |
180 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
181 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
182 | b->bank, b->block, b->address, hi, lo); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | if (apic != msr) { | |
f57a1f3c AG |
187 | /* |
188 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
189 | * the BIOS provides the value. The original field where LVT offset | |
190 | * was set is reserved. Return early here: | |
191 | */ | |
192 | if (mce_flags.smca) | |
193 | return 0; | |
194 | ||
bbaff08d RR |
195 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
196 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
197 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
198 | return 0; | |
199 | } | |
200 | ||
201 | return 1; | |
202 | }; | |
203 | ||
ea2ca36b | 204 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 205 | static void threshold_restart_bank(void *_tr) |
89b831ef | 206 | { |
4cd4601d | 207 | struct thresh_restart *tr = _tr; |
7203a049 | 208 | u32 hi, lo; |
89b831ef | 209 | |
7203a049 | 210 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 211 | |
7203a049 | 212 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 213 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 214 | |
4cd4601d | 215 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
216 | hi = |
217 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
218 | (THRESHOLD_MAX - tr->b->threshold_limit); |
219 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 220 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 221 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 222 | |
7203a049 | 223 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
224 | (new_count & THRESHOLD_MAX); |
225 | } | |
226 | ||
f227d430 BP |
227 | /* clear IntType */ |
228 | hi &= ~MASK_INT_TYPE_HI; | |
229 | ||
230 | if (!tr->b->interrupt_capable) | |
231 | goto done; | |
232 | ||
9c37c9d8 | 233 | if (tr->set_lvt_off) { |
bbaff08d RR |
234 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
235 | /* set new lvt offset */ | |
236 | hi &= ~MASK_LVTOFF_HI; | |
237 | hi |= tr->lvt_off << 20; | |
238 | } | |
9c37c9d8 RR |
239 | } |
240 | ||
f227d430 BP |
241 | if (tr->b->interrupt_enable) |
242 | hi |= INT_TYPE_APIC; | |
243 | ||
244 | done: | |
89b831ef | 245 | |
7203a049 RR |
246 | hi |= MASK_COUNT_EN_HI; |
247 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
248 | } |
249 | ||
9c37c9d8 RR |
250 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
251 | { | |
252 | struct thresh_restart tr = { | |
253 | .b = b, | |
254 | .set_lvt_off = 1, | |
255 | .lvt_off = offset, | |
256 | }; | |
257 | ||
258 | b->threshold_limit = THRESHOLD_MAX; | |
259 | threshold_restart_bank(&tr); | |
260 | }; | |
261 | ||
868c00bb | 262 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
263 | { |
264 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
265 | APIC_EILVT_MSG_FIX, 0)) | |
266 | return new; | |
267 | ||
268 | return reserved; | |
269 | } | |
270 | ||
24fd78a8 AG |
271 | static int setup_APIC_deferred_error(int reserved, int new) |
272 | { | |
273 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
274 | APIC_EILVT_MSG_FIX, 0)) | |
275 | return new; | |
276 | ||
277 | return reserved; | |
278 | } | |
279 | ||
280 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
281 | { | |
282 | u32 low = 0, high = 0; | |
283 | int def_offset = -1, def_new; | |
284 | ||
285 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
286 | return; | |
287 | ||
288 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
289 | if (!(low & MASK_DEF_LVTOFF)) { | |
290 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
291 | def_new = DEF_LVT_OFF; | |
292 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
293 | } | |
294 | ||
295 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
296 | if ((def_offset == def_new) && | |
297 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
298 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
299 | ||
300 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
301 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
302 | } | |
303 | ||
8dd1e17a AG |
304 | static u32 get_block_address(u32 current_addr, u32 low, u32 high, |
305 | unsigned int bank, unsigned int block) | |
306 | { | |
307 | u32 addr = 0, offset = 0; | |
308 | ||
309 | if (mce_flags.smca) { | |
310 | if (!block) { | |
311 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
312 | } else { | |
313 | /* | |
314 | * For SMCA enabled processors, BLKPTR field of the | |
315 | * first MISC register (MCx_MISC0) indicates presence of | |
316 | * additional MISC register set (MISC1-4). | |
317 | */ | |
318 | u32 low, high; | |
319 | ||
320 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) | |
321 | return addr; | |
322 | ||
323 | if (!(low & MCI_CONFIG_MCAX)) | |
324 | return addr; | |
325 | ||
326 | if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && | |
327 | (low & MASK_BLKPTR_LO)) | |
328 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
329 | } | |
330 | return addr; | |
331 | } | |
332 | ||
333 | /* Fall back to method we used for older processors: */ | |
334 | switch (block) { | |
335 | case 0: | |
336 | addr = MSR_IA32_MCx_MISC(bank); | |
337 | break; | |
338 | case 1: | |
339 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
340 | if (offset) | |
341 | addr = MCG_XBLK_ADDR + offset; | |
342 | break; | |
343 | default: | |
344 | addr = ++current_addr; | |
345 | } | |
346 | return addr; | |
347 | } | |
348 | ||
429893b1 BP |
349 | static int |
350 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
351 | int offset, u32 misc_high) | |
352 | { | |
353 | unsigned int cpu = smp_processor_id(); | |
354 | struct threshold_block b; | |
355 | int new; | |
356 | ||
357 | if (!block) | |
358 | per_cpu(bank_map, cpu) |= (1 << bank); | |
359 | ||
360 | memset(&b, 0, sizeof(b)); | |
361 | b.cpu = cpu; | |
362 | b.bank = bank; | |
363 | b.block = block; | |
364 | b.address = addr; | |
365 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
366 | ||
367 | if (!b.interrupt_capable) | |
368 | goto done; | |
369 | ||
370 | b.interrupt_enable = 1; | |
371 | ||
372 | if (mce_flags.smca) { | |
373 | u32 smca_low, smca_high; | |
e6c8f187 AG |
374 | u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
375 | ||
376 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { | |
377 | smca_high |= SMCA_MCAX_EN_OFF; | |
378 | wrmsr(smca_addr, smca_low, smca_high); | |
379 | } | |
429893b1 BP |
380 | |
381 | /* Gather LVT offset for thresholding: */ | |
382 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
383 | goto out; | |
384 | ||
385 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
386 | } else { | |
387 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
388 | } | |
389 | ||
390 | offset = setup_APIC_mce_threshold(offset, new); | |
391 | ||
392 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
393 | mce_threshold_vector = amd_threshold_interrupt; | |
394 | ||
395 | done: | |
396 | mce_threshold_block_init(&b, offset); | |
397 | ||
398 | out: | |
399 | return offset; | |
400 | } | |
401 | ||
95268664 | 402 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 403 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 404 | { |
95268664 | 405 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 406 | unsigned int bank, block; |
429893b1 | 407 | int offset = -1; |
89b831ef | 408 | |
bafcdd3b | 409 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 | 410 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
411 | address = get_block_address(address, low, high, bank, block); |
412 | if (!address) | |
413 | break; | |
95268664 JS |
414 | |
415 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 416 | break; |
95268664 | 417 | |
6dcbfe4f BP |
418 | if (!(high & MASK_VALID_HI)) |
419 | continue; | |
95268664 | 420 | |
24ce0e96 JB |
421 | if (!(high & MASK_CNTP_HI) || |
422 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
423 | continue; |
424 | ||
429893b1 | 425 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 426 | } |
89b831ef | 427 | } |
24fd78a8 AG |
428 | |
429 | if (mce_flags.succor) | |
430 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
431 | } |
432 | ||
afdf344e AG |
433 | static void __log_error(unsigned int bank, bool threshold_err, u64 misc) |
434 | { | |
435 | struct mce m; | |
436 | u64 status; | |
437 | ||
438 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
439 | if (!(status & MCI_STATUS_VAL)) | |
440 | return; | |
441 | ||
442 | mce_setup(&m); | |
443 | ||
444 | m.status = status; | |
445 | m.bank = bank; | |
6e6e746e | 446 | |
afdf344e AG |
447 | if (threshold_err) |
448 | m.misc = misc; | |
449 | ||
6e6e746e AG |
450 | if (m.status & MCI_STATUS_ADDRV) |
451 | rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr); | |
afdf344e | 452 | |
6e6e746e | 453 | mce_log(&m); |
afdf344e AG |
454 | wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); |
455 | } | |
456 | ||
24fd78a8 AG |
457 | static inline void __smp_deferred_error_interrupt(void) |
458 | { | |
459 | inc_irq_stat(irq_deferred_error_count); | |
460 | deferred_error_int_vector(); | |
461 | } | |
462 | ||
463 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
464 | { | |
465 | entering_irq(); | |
466 | __smp_deferred_error_interrupt(); | |
467 | exiting_ack_irq(); | |
468 | } | |
469 | ||
470 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
471 | { | |
472 | entering_irq(); | |
473 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
474 | __smp_deferred_error_interrupt(); | |
475 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
476 | exiting_ack_irq(); | |
477 | } | |
478 | ||
479 | /* APIC interrupt handler for deferred errors */ | |
480 | static void amd_deferred_error_interrupt(void) | |
481 | { | |
482 | u64 status; | |
483 | unsigned int bank; | |
484 | ||
485 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
486 | rdmsrl(MSR_IA32_MCx_STATUS(bank), status); | |
487 | ||
488 | if (!(status & MCI_STATUS_VAL) || | |
489 | !(status & MCI_STATUS_DEFERRED)) | |
490 | continue; | |
491 | ||
492 | __log_error(bank, false, 0); | |
493 | break; | |
494 | } | |
495 | } | |
496 | ||
89b831ef JS |
497 | /* |
498 | * APIC Interrupt Handler | |
499 | */ | |
500 | ||
501 | /* | |
502 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
503 | * the interrupt goes off when error_count reaches threshold_limit. | |
504 | * the handler will simply log mcelog w/ software defined bank number. | |
505 | */ | |
afdf344e | 506 | |
b2762686 | 507 | static void amd_threshold_interrupt(void) |
89b831ef | 508 | { |
1cb2a8e1 | 509 | u32 low = 0, high = 0, address = 0; |
44612a3a | 510 | int cpu = smp_processor_id(); |
95268664 | 511 | unsigned int bank, block; |
89b831ef | 512 | |
89b831ef | 513 | /* assume first bank caused it */ |
bafcdd3b | 514 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 515 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 516 | continue; |
95268664 | 517 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
518 | address = get_block_address(address, low, high, bank, block); |
519 | if (!address) | |
520 | break; | |
95268664 JS |
521 | |
522 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 523 | break; |
95268664 JS |
524 | |
525 | if (!(high & MASK_VALID_HI)) { | |
526 | if (block) | |
527 | continue; | |
528 | else | |
529 | break; | |
530 | } | |
531 | ||
24ce0e96 JB |
532 | if (!(high & MASK_CNTP_HI) || |
533 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
534 | continue; |
535 | ||
1cb2a8e1 IM |
536 | /* |
537 | * Log the machine check that caused the threshold | |
538 | * event. | |
539 | */ | |
44612a3a CY |
540 | if (high & MASK_OVERFLOW_HI) |
541 | goto log; | |
89b831ef JS |
542 | } |
543 | } | |
44612a3a CY |
544 | return; |
545 | ||
546 | log: | |
afdf344e | 547 | __log_error(bank, true, ((u64)high << 32) | low); |
89b831ef JS |
548 | } |
549 | ||
550 | /* | |
551 | * Sysfs Interface | |
552 | */ | |
553 | ||
89b831ef | 554 | struct threshold_attr { |
2903ee85 | 555 | struct attribute attr; |
1cb2a8e1 IM |
556 | ssize_t (*show) (struct threshold_block *, char *); |
557 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
558 | }; |
559 | ||
1cb2a8e1 IM |
560 | #define SHOW_FIELDS(name) \ |
561 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
562 | { \ | |
18c20f37 | 563 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 564 | } |
89b831ef JS |
565 | SHOW_FIELDS(interrupt_enable) |
566 | SHOW_FIELDS(threshold_limit) | |
567 | ||
1cb2a8e1 | 568 | static ssize_t |
9319cec8 | 569 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 570 | { |
4cd4601d | 571 | struct thresh_restart tr; |
1cb2a8e1 | 572 | unsigned long new; |
1cb2a8e1 | 573 | |
f227d430 BP |
574 | if (!b->interrupt_capable) |
575 | return -EINVAL; | |
576 | ||
164109e3 | 577 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 578 | return -EINVAL; |
1cb2a8e1 | 579 | |
89b831ef JS |
580 | b->interrupt_enable = !!new; |
581 | ||
9c37c9d8 | 582 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 583 | tr.b = b; |
1cb2a8e1 | 584 | |
a6b6a14e | 585 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 586 | |
9319cec8 | 587 | return size; |
89b831ef JS |
588 | } |
589 | ||
1cb2a8e1 | 590 | static ssize_t |
9319cec8 | 591 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 592 | { |
4cd4601d | 593 | struct thresh_restart tr; |
1cb2a8e1 | 594 | unsigned long new; |
1cb2a8e1 | 595 | |
164109e3 | 596 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 597 | return -EINVAL; |
1cb2a8e1 | 598 | |
89b831ef JS |
599 | if (new > THRESHOLD_MAX) |
600 | new = THRESHOLD_MAX; | |
601 | if (new < 1) | |
602 | new = 1; | |
1cb2a8e1 | 603 | |
9c37c9d8 | 604 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 605 | tr.old_limit = b->threshold_limit; |
89b831ef | 606 | b->threshold_limit = new; |
4cd4601d | 607 | tr.b = b; |
89b831ef | 608 | |
a6b6a14e | 609 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 610 | |
9319cec8 | 611 | return size; |
89b831ef JS |
612 | } |
613 | ||
4cd4601d MT |
614 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
615 | { | |
2c9c42fa BP |
616 | u32 lo, hi; |
617 | ||
618 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 619 | |
2c9c42fa BP |
620 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
621 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
622 | } |
623 | ||
6e927361 BP |
624 | static struct threshold_attr error_count = { |
625 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
626 | .show = show_error_count, | |
627 | }; | |
89b831ef | 628 | |
34fa1967 HS |
629 | #define RW_ATTR(val) \ |
630 | static struct threshold_attr val = { \ | |
631 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
632 | .show = show_## val, \ | |
633 | .store = store_## val, \ | |
89b831ef JS |
634 | }; |
635 | ||
2903ee85 JS |
636 | RW_ATTR(interrupt_enable); |
637 | RW_ATTR(threshold_limit); | |
89b831ef JS |
638 | |
639 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
640 | &threshold_limit.attr, |
641 | &error_count.attr, | |
d26ecc48 BP |
642 | NULL, /* possibly interrupt_enable if supported, see below */ |
643 | NULL, | |
89b831ef JS |
644 | }; |
645 | ||
1cb2a8e1 IM |
646 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
647 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
648 | |
649 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
650 | { | |
95268664 | 651 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
652 | struct threshold_attr *a = to_attr(attr); |
653 | ssize_t ret; | |
1cb2a8e1 | 654 | |
89b831ef | 655 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 656 | |
89b831ef JS |
657 | return ret; |
658 | } | |
659 | ||
660 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
661 | const char *buf, size_t count) | |
662 | { | |
95268664 | 663 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
664 | struct threshold_attr *a = to_attr(attr); |
665 | ssize_t ret; | |
1cb2a8e1 | 666 | |
89b831ef | 667 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 668 | |
89b831ef JS |
669 | return ret; |
670 | } | |
671 | ||
52cf25d0 | 672 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
673 | .show = show, |
674 | .store = store, | |
89b831ef JS |
675 | }; |
676 | ||
677 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
678 | .sysfs_ops = &threshold_ops, |
679 | .default_attrs = default_attrs, | |
89b831ef JS |
680 | }; |
681 | ||
148f9bb8 PG |
682 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
683 | unsigned int block, u32 address) | |
95268664 | 684 | { |
95268664 | 685 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
686 | u32 low, high; |
687 | int err; | |
95268664 | 688 | |
bafcdd3b | 689 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
690 | return 0; |
691 | ||
a6b6a14e | 692 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 693 | return 0; |
95268664 JS |
694 | |
695 | if (!(high & MASK_VALID_HI)) { | |
696 | if (block) | |
697 | goto recurse; | |
698 | else | |
699 | return 0; | |
700 | } | |
701 | ||
24ce0e96 JB |
702 | if (!(high & MASK_CNTP_HI) || |
703 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
704 | goto recurse; |
705 | ||
706 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
707 | if (!b) | |
708 | return -ENOMEM; | |
95268664 | 709 | |
1cb2a8e1 IM |
710 | b->block = block; |
711 | b->bank = bank; | |
712 | b->cpu = cpu; | |
713 | b->address = address; | |
714 | b->interrupt_enable = 0; | |
f227d430 | 715 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 716 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 717 | |
d79f931f | 718 | if (b->interrupt_capable) { |
d26ecc48 | 719 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
720 | b->interrupt_enable = 1; |
721 | } else { | |
d26ecc48 | 722 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 723 | } |
d26ecc48 | 724 | |
95268664 JS |
725 | INIT_LIST_HEAD(&b->miscj); |
726 | ||
1cb2a8e1 | 727 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
728 | list_add(&b->miscj, |
729 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 730 | } else { |
95268664 | 731 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 732 | } |
95268664 | 733 | |
542eb75a GKH |
734 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
735 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 736 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
737 | if (err) |
738 | goto out_free; | |
739 | recurse: | |
8dd1e17a AG |
740 | address = get_block_address(address, low, high, bank, ++block); |
741 | if (!address) | |
742 | return 0; | |
95268664 | 743 | |
8dd1e17a | 744 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
745 | if (err) |
746 | goto out_free; | |
747 | ||
213eca7f GK |
748 | if (b) |
749 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 750 | |
95268664 JS |
751 | return err; |
752 | ||
753 | out_free: | |
754 | if (b) { | |
38a382ae | 755 | kobject_put(&b->kobj); |
d9a5ac9e | 756 | list_del(&b->miscj); |
95268664 JS |
757 | kfree(b); |
758 | } | |
759 | return err; | |
760 | } | |
761 | ||
148f9bb8 | 762 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
763 | { |
764 | struct list_head *head = &b->blocks->miscj; | |
765 | struct threshold_block *pos = NULL; | |
766 | struct threshold_block *tmp = NULL; | |
767 | int err = 0; | |
768 | ||
769 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
770 | if (err) | |
771 | return err; | |
772 | ||
773 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
774 | ||
775 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
776 | if (err) { | |
777 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
778 | kobject_del(&pos->kobj); | |
779 | ||
780 | return err; | |
781 | } | |
782 | } | |
783 | return err; | |
784 | } | |
785 | ||
148f9bb8 | 786 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 787 | { |
d6126ef5 | 788 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 789 | struct amd_northbridge *nb = NULL; |
92e26e2a | 790 | struct threshold_bank *b = NULL; |
336d335a | 791 | const char *name = th_names[bank]; |
92e26e2a | 792 | int err = 0; |
95268664 | 793 | |
c76e8164 | 794 | if (is_shared_bank(bank)) { |
019f34fc | 795 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
796 | |
797 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 798 | if (nb && nb->bank4) { |
019f34fc BP |
799 | /* yes, use it */ |
800 | b = nb->bank4; | |
801 | err = kobject_add(b->kobj, &dev->kobj, name); | |
802 | if (err) | |
803 | goto out; | |
804 | ||
805 | per_cpu(threshold_banks, cpu)[bank] = b; | |
806 | atomic_inc(&b->cpus); | |
807 | ||
808 | err = __threshold_add_blocks(b); | |
809 | ||
810 | goto out; | |
811 | } | |
812 | } | |
813 | ||
95268664 | 814 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
815 | if (!b) { |
816 | err = -ENOMEM; | |
817 | goto out; | |
818 | } | |
89b831ef | 819 | |
e032d807 | 820 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
821 | if (!b->kobj) { |
822 | err = -EINVAL; | |
a521cf20 | 823 | goto out_free; |
92e26e2a | 824 | } |
95268664 | 825 | |
89b831ef | 826 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 827 | |
c76e8164 | 828 | if (is_shared_bank(bank)) { |
019f34fc BP |
829 | atomic_set(&b->cpus, 1); |
830 | ||
831 | /* nb is already initialized, see above */ | |
21c5e50e DB |
832 | if (nb) { |
833 | WARN_ON(nb->bank4); | |
834 | nb->bank4 = b; | |
835 | } | |
019f34fc BP |
836 | } |
837 | ||
4b737d78 | 838 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
839 | if (!err) |
840 | goto out; | |
95268664 | 841 | |
019f34fc | 842 | out_free: |
95268664 | 843 | kfree(b); |
019f34fc BP |
844 | |
845 | out: | |
89b831ef JS |
846 | return err; |
847 | } | |
848 | ||
849 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 850 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 851 | { |
2903ee85 | 852 | unsigned int bank; |
bafcdd3b | 853 | struct threshold_bank **bp; |
89b831ef JS |
854 | int err = 0; |
855 | ||
bafcdd3b BO |
856 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
857 | GFP_KERNEL); | |
858 | if (!bp) | |
859 | return -ENOMEM; | |
860 | ||
861 | per_cpu(threshold_banks, cpu) = bp; | |
862 | ||
863 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 864 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
865 | continue; |
866 | err = threshold_create_bank(cpu, bank); | |
867 | if (err) | |
0a17941e | 868 | return err; |
89b831ef | 869 | } |
0a17941e | 870 | |
89b831ef JS |
871 | return err; |
872 | } | |
873 | ||
be6b5a35 | 874 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
875 | unsigned int bank) |
876 | { | |
877 | struct threshold_block *pos = NULL; | |
878 | struct threshold_block *tmp = NULL; | |
879 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
880 | ||
881 | if (!head) | |
882 | return; | |
883 | ||
884 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 885 | kobject_put(&pos->kobj); |
95268664 JS |
886 | list_del(&pos->miscj); |
887 | kfree(pos); | |
888 | } | |
889 | ||
890 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
891 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
892 | } | |
893 | ||
019f34fc BP |
894 | static void __threshold_remove_blocks(struct threshold_bank *b) |
895 | { | |
896 | struct threshold_block *pos = NULL; | |
897 | struct threshold_block *tmp = NULL; | |
898 | ||
899 | kobject_del(b->kobj); | |
900 | ||
901 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
902 | kobject_del(&pos->kobj); | |
903 | } | |
904 | ||
be6b5a35 | 905 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 906 | { |
019f34fc | 907 | struct amd_northbridge *nb; |
89b831ef | 908 | struct threshold_bank *b; |
89b831ef JS |
909 | |
910 | b = per_cpu(threshold_banks, cpu)[bank]; | |
911 | if (!b) | |
912 | return; | |
019f34fc | 913 | |
95268664 JS |
914 | if (!b->blocks) |
915 | goto free_out; | |
916 | ||
c76e8164 | 917 | if (is_shared_bank(bank)) { |
019f34fc BP |
918 | if (!atomic_dec_and_test(&b->cpus)) { |
919 | __threshold_remove_blocks(b); | |
920 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
921 | return; | |
922 | } else { | |
923 | /* | |
924 | * the last CPU on this node using the shared bank is | |
925 | * going away, remove that bank now. | |
926 | */ | |
927 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
928 | nb->bank4 = NULL; | |
929 | } | |
930 | } | |
931 | ||
95268664 JS |
932 | deallocate_threshold_block(cpu, bank); |
933 | ||
934 | free_out: | |
8735728e | 935 | kobject_del(b->kobj); |
38a382ae | 936 | kobject_put(b->kobj); |
95268664 JS |
937 | kfree(b); |
938 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
939 | } |
940 | ||
be6b5a35 | 941 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 942 | { |
2903ee85 | 943 | unsigned int bank; |
89b831ef | 944 | |
bafcdd3b | 945 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 946 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
947 | continue; |
948 | threshold_remove_bank(cpu, bank); | |
949 | } | |
bafcdd3b | 950 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
951 | } |
952 | ||
89b831ef | 953 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 954 | static void |
1cb2a8e1 | 955 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 956 | { |
89b831ef JS |
957 | switch (action) { |
958 | case CPU_ONLINE: | |
8bb78442 | 959 | case CPU_ONLINE_FROZEN: |
89b831ef | 960 | threshold_create_device(cpu); |
89b831ef JS |
961 | break; |
962 | case CPU_DEAD: | |
8bb78442 | 963 | case CPU_DEAD_FROZEN: |
89b831ef JS |
964 | threshold_remove_device(cpu); |
965 | break; | |
966 | default: | |
967 | break; | |
968 | } | |
89b831ef JS |
969 | } |
970 | ||
89b831ef JS |
971 | static __init int threshold_init_device(void) |
972 | { | |
2903ee85 | 973 | unsigned lcpu = 0; |
89b831ef | 974 | |
89b831ef JS |
975 | /* to hit CPUs online before the notifier is up */ |
976 | for_each_online_cpu(lcpu) { | |
fff2e89f | 977 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 978 | |
89b831ef | 979 | if (err) |
fff2e89f | 980 | return err; |
89b831ef | 981 | } |
8735728e | 982 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 983 | |
fff2e89f | 984 | return 0; |
89b831ef | 985 | } |
a8fccdb0 LJ |
986 | /* |
987 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
988 | * 1. xen_late_init_mcelog | |
989 | * 2. mcheck_init_device | |
990 | * 3. threshold_init_device | |
991 | * | |
992 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
993 | * native mce_chrdev_device registration if running under xen platform; | |
994 | * | |
995 | * mcheck_init_device should be inited before threshold_init_device to | |
996 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
997 | * | |
998 | * so we use following _initcalls | |
999 | * 1. device_initcall(xen_late_init_mcelog); | |
1000 | * 2. device_initcall_sync(mcheck_init_device); | |
1001 | * 3. late_initcall(threshold_init_device); | |
1002 | * | |
1003 | * when running under xen, the initcall order is 1,2,3; | |
1004 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1005 | */ | |
1006 | late_initcall(threshold_init_device); |