Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
14a02530 | 31 | #include <linux/smp.h> |
e9eee03e IM |
32 | #include <linux/fs.h> |
33 | ||
d88203d1 | 34 | #include <asm/processor.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
1da177e4 | 38 | |
711c2e48 IM |
39 | #include "mce.h" |
40 | ||
5d727926 AK |
41 | /* Handle unconfigured int18 (should never happen) */ |
42 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
43 | { | |
44 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
45 | smp_processor_id()); | |
46 | } | |
47 | ||
48 | /* Call the installed machine check handler for this CPU setup. */ | |
49 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
50 | unexpected_machine_check; | |
04b2b1a4 AK |
51 | |
52 | int mce_disabled; | |
53 | ||
4efc0670 | 54 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 55 | |
e9eee03e | 56 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 57 | |
553f265f AK |
58 | atomic_t mce_entry; |
59 | ||
01ca79f1 AK |
60 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
61 | ||
bd78432c TH |
62 | /* |
63 | * Tolerant levels: | |
64 | * 0: always panic on uncorrected errors, log corrected errors | |
65 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
66 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
67 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
68 | */ | |
e9eee03e IM |
69 | static int tolerant = 1; |
70 | static int banks; | |
71 | static u64 *bank; | |
72 | static unsigned long notify_user; | |
73 | static int rip_msr; | |
74 | static int mce_bootlog = -1; | |
a98f0dd3 | 75 | |
e9eee03e IM |
76 | static char trigger[128]; |
77 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 78 | |
06b7a7a5 AK |
79 | static unsigned long dont_init_banks; |
80 | ||
e02e68d3 TH |
81 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
82 | ||
ee031c31 AK |
83 | /* MCA banks polled by the period polling timer for corrected events */ |
84 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
85 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
86 | }; | |
87 | ||
06b7a7a5 AK |
88 | static inline int skip_bank_init(int i) |
89 | { | |
90 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
91 | } | |
92 | ||
b5f2fa4e AK |
93 | /* Do initial initialization of a struct mce */ |
94 | void mce_setup(struct mce *m) | |
95 | { | |
96 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 97 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 98 | rdtscll(m->tsc); |
8ee08347 AK |
99 | /* We hope get_seconds stays lockless */ |
100 | m->time = get_seconds(); | |
101 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
102 | m->cpuid = cpuid_eax(1); | |
103 | #ifdef CONFIG_SMP | |
104 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
105 | #endif | |
106 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
107 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
108 | } |
109 | ||
ea149b36 AK |
110 | DEFINE_PER_CPU(struct mce, injectm); |
111 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * Lockless MCE logging infrastructure. | |
115 | * This avoids deadlocks on printk locks without having to break locks. Also | |
116 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
117 | */ | |
118 | ||
231fd906 | 119 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
120 | .signature = MCE_LOG_SIGNATURE, |
121 | .len = MCE_LOG_LEN, | |
122 | .recordlen = sizeof(struct mce), | |
d88203d1 | 123 | }; |
1da177e4 LT |
124 | |
125 | void mce_log(struct mce *mce) | |
126 | { | |
127 | unsigned next, entry; | |
e9eee03e | 128 | |
1da177e4 | 129 | mce->finished = 0; |
7644143c | 130 | wmb(); |
1da177e4 LT |
131 | for (;;) { |
132 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 133 | for (;;) { |
e9eee03e IM |
134 | /* |
135 | * When the buffer fills up discard new entries. | |
136 | * Assume that the earlier errors are the more | |
137 | * interesting ones: | |
138 | */ | |
673242c1 | 139 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
140 | set_bit(MCE_OVERFLOW, |
141 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
142 | return; |
143 | } | |
e9eee03e | 144 | /* Old left over entry. Skip: */ |
673242c1 AK |
145 | if (mcelog.entry[entry].finished) { |
146 | entry++; | |
147 | continue; | |
148 | } | |
7644143c | 149 | break; |
1da177e4 | 150 | } |
1da177e4 LT |
151 | smp_rmb(); |
152 | next = entry + 1; | |
153 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
154 | break; | |
155 | } | |
156 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 157 | wmb(); |
1da177e4 | 158 | mcelog.entry[entry].finished = 1; |
7644143c | 159 | wmb(); |
1da177e4 | 160 | |
e02e68d3 | 161 | set_bit(0, ¬ify_user); |
1da177e4 LT |
162 | } |
163 | ||
164 | static void print_mce(struct mce *m) | |
165 | { | |
166 | printk(KERN_EMERG "\n" | |
4855170f | 167 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
168 | KERN_EMERG |
169 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
d620c67f | 170 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 171 | if (m->ip) { |
d88203d1 | 172 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 173 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 174 | m->cs, m->ip); |
1da177e4 | 175 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 176 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
177 | printk("\n"); |
178 | } | |
f6d1826d | 179 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 180 | if (m->addr) |
f6d1826d | 181 | printk("ADDR %llx ", m->addr); |
1da177e4 | 182 | if (m->misc) |
f6d1826d | 183 | printk("MISC %llx ", m->misc); |
1da177e4 | 184 | printk("\n"); |
8ee08347 AK |
185 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
186 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
187 | m->apicid); | |
4855170f | 188 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
189 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
190 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
191 | } |
192 | ||
3cde5c8c | 193 | static void mce_panic(char *msg, struct mce *backup, u64 start) |
d88203d1 | 194 | { |
1da177e4 | 195 | int i; |
e02e68d3 | 196 | |
d896a940 AK |
197 | bust_spinlocks(1); |
198 | console_verbose(); | |
1da177e4 | 199 | for (i = 0; i < MCE_LOG_LEN; i++) { |
3cde5c8c | 200 | u64 tsc = mcelog.entry[i].tsc; |
d88203d1 | 201 | |
3cde5c8c | 202 | if ((s64)(tsc - start) < 0) |
1da177e4 | 203 | continue; |
d88203d1 | 204 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
205 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
206 | backup = NULL; | |
207 | } | |
208 | if (backup) | |
209 | print_mce(backup); | |
e02e68d3 | 210 | panic(msg); |
d88203d1 | 211 | } |
1da177e4 | 212 | |
ea149b36 AK |
213 | /* Support code for software error injection */ |
214 | ||
215 | static int msr_to_offset(u32 msr) | |
216 | { | |
217 | unsigned bank = __get_cpu_var(injectm.bank); | |
218 | if (msr == rip_msr) | |
219 | return offsetof(struct mce, ip); | |
220 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
221 | return offsetof(struct mce, status); | |
222 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
223 | return offsetof(struct mce, addr); | |
224 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
225 | return offsetof(struct mce, misc); | |
226 | if (msr == MSR_IA32_MCG_STATUS) | |
227 | return offsetof(struct mce, mcgstatus); | |
228 | return -1; | |
229 | } | |
230 | ||
5f8c1a54 AK |
231 | /* MSR access wrappers used for error injection */ |
232 | static u64 mce_rdmsrl(u32 msr) | |
233 | { | |
234 | u64 v; | |
ea149b36 AK |
235 | if (__get_cpu_var(injectm).finished) { |
236 | int offset = msr_to_offset(msr); | |
237 | if (offset < 0) | |
238 | return 0; | |
239 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
240 | } | |
5f8c1a54 AK |
241 | rdmsrl(msr, v); |
242 | return v; | |
243 | } | |
244 | ||
245 | static void mce_wrmsrl(u32 msr, u64 v) | |
246 | { | |
ea149b36 AK |
247 | if (__get_cpu_var(injectm).finished) { |
248 | int offset = msr_to_offset(msr); | |
249 | if (offset >= 0) | |
250 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
251 | return; | |
252 | } | |
5f8c1a54 AK |
253 | wrmsrl(msr, v); |
254 | } | |
255 | ||
88ccbedd | 256 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 257 | { |
04b2b1a4 | 258 | if (mce_disabled) |
5b4408fd | 259 | return 0; |
3d1712c9 | 260 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
261 | } |
262 | ||
94ad8474 AK |
263 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
264 | { | |
265 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 266 | m->ip = regs->ip; |
94ad8474 AK |
267 | m->cs = regs->cs; |
268 | } else { | |
65ea5b03 | 269 | m->ip = 0; |
94ad8474 AK |
270 | m->cs = 0; |
271 | } | |
272 | if (rip_msr) { | |
273 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
274 | m->mcgstatus |= MCG_STATUS_EIPV; | |
5f8c1a54 | 275 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
276 | m->cs = 0; |
277 | } | |
278 | } | |
279 | ||
ca84f696 AK |
280 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
281 | ||
d88203d1 | 282 | /* |
b79109c3 AK |
283 | * Poll for corrected events or events that happened before reset. |
284 | * Those are just logged through /dev/mcelog. | |
285 | * | |
286 | * This is executed in standard interrupt context. | |
287 | */ | |
ee031c31 | 288 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
289 | { |
290 | struct mce m; | |
291 | int i; | |
292 | ||
ca84f696 AK |
293 | __get_cpu_var(mce_poll_count)++; |
294 | ||
b79109c3 AK |
295 | mce_setup(&m); |
296 | ||
5f8c1a54 | 297 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 298 | for (i = 0; i < banks; i++) { |
ee031c31 | 299 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
300 | continue; |
301 | ||
302 | m.misc = 0; | |
303 | m.addr = 0; | |
304 | m.bank = i; | |
305 | m.tsc = 0; | |
306 | ||
307 | barrier(); | |
5f8c1a54 | 308 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
309 | if (!(m.status & MCI_STATUS_VAL)) |
310 | continue; | |
311 | ||
312 | /* | |
313 | * Uncorrected events are handled by the exception handler | |
314 | * when it is enabled. But when the exception is disabled log | |
315 | * everything. | |
316 | * | |
317 | * TBD do the same check for MCI_STATUS_EN here? | |
318 | */ | |
319 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
320 | continue; | |
321 | ||
322 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 323 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 324 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 325 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
326 | |
327 | if (!(flags & MCP_TIMESTAMP)) | |
328 | m.tsc = 0; | |
329 | /* | |
330 | * Don't get the IP here because it's unlikely to | |
331 | * have anything to do with the actual error location. | |
332 | */ | |
5679af4c AK |
333 | if (!(flags & MCP_DONTLOG)) { |
334 | mce_log(&m); | |
335 | add_taint(TAINT_MACHINE_CHECK); | |
336 | } | |
b79109c3 AK |
337 | |
338 | /* | |
339 | * Clear state for this bank. | |
340 | */ | |
5f8c1a54 | 341 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
342 | } |
343 | ||
344 | /* | |
345 | * Don't clear MCG_STATUS here because it's only defined for | |
346 | * exceptions. | |
347 | */ | |
88921be3 AK |
348 | |
349 | sync_core(); | |
b79109c3 | 350 | } |
ea149b36 | 351 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 AK |
352 | |
353 | /* | |
354 | * The actual machine check handler. This only handles real | |
355 | * exceptions when something got corrupted coming in through int 18. | |
356 | * | |
357 | * This is executed in NMI context not subject to normal locking rules. This | |
358 | * implies that most kernel services cannot be safely used. Don't even | |
359 | * think about putting a printk in there! | |
1da177e4 | 360 | */ |
e9eee03e | 361 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
362 | { |
363 | struct mce m, panicm; | |
e9eee03e | 364 | int panicm_found = 0; |
1da177e4 LT |
365 | u64 mcestart = 0; |
366 | int i; | |
bd78432c TH |
367 | /* |
368 | * If no_way_out gets set, there is no safe way to recover from this | |
369 | * MCE. If tolerant is cranked up, we'll try anyway. | |
370 | */ | |
371 | int no_way_out = 0; | |
372 | /* | |
373 | * If kill_it gets set, there might be a way to recover from this | |
374 | * error. | |
375 | */ | |
376 | int kill_it = 0; | |
b79109c3 | 377 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 378 | |
553f265f AK |
379 | atomic_inc(&mce_entry); |
380 | ||
01ca79f1 AK |
381 | __get_cpu_var(mce_exception_count)++; |
382 | ||
b79109c3 | 383 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 384 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 385 | goto out; |
b79109c3 | 386 | if (!banks) |
32561696 | 387 | goto out; |
1da177e4 | 388 | |
b5f2fa4e AK |
389 | mce_setup(&m); |
390 | ||
5f8c1a54 | 391 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
e9eee03e | 392 | |
bd78432c | 393 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 394 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 395 | no_way_out = 1; |
d88203d1 | 396 | |
1da177e4 LT |
397 | rdtscll(mcestart); |
398 | barrier(); | |
399 | ||
400 | for (i = 0; i < banks; i++) { | |
b79109c3 | 401 | __clear_bit(i, toclear); |
0d7482e3 | 402 | if (!bank[i]) |
1da177e4 | 403 | continue; |
d88203d1 TG |
404 | |
405 | m.misc = 0; | |
1da177e4 LT |
406 | m.addr = 0; |
407 | m.bank = i; | |
1da177e4 | 408 | |
5f8c1a54 | 409 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
410 | if ((m.status & MCI_STATUS_VAL) == 0) |
411 | continue; | |
412 | ||
b79109c3 AK |
413 | /* |
414 | * Non uncorrected errors are handled by machine_check_poll | |
de8a84d8 | 415 | * Leave them alone, unless this panics. |
b79109c3 | 416 | */ |
de8a84d8 | 417 | if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out) |
b79109c3 AK |
418 | continue; |
419 | ||
420 | /* | |
421 | * Set taint even when machine check was not enabled. | |
422 | */ | |
423 | add_taint(TAINT_MACHINE_CHECK); | |
424 | ||
425 | __set_bit(i, toclear); | |
426 | ||
1da177e4 | 427 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
428 | /* if PCC was set, there's no way out */ |
429 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
430 | /* | |
431 | * If this error was uncorrectable and there was | |
432 | * an overflow, we're in trouble. If no overflow, | |
433 | * we might get away with just killing a task. | |
434 | */ | |
435 | if (m.status & MCI_STATUS_UC) { | |
436 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
437 | no_way_out = 1; | |
438 | kill_it = 1; | |
439 | } | |
b79109c3 AK |
440 | } else { |
441 | /* | |
442 | * Machine check event was not enabled. Clear, but | |
443 | * ignore. | |
444 | */ | |
445 | continue; | |
1da177e4 LT |
446 | } |
447 | ||
448 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 449 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 450 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 451 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 452 | |
94ad8474 | 453 | mce_get_rip(&m, regs); |
b79109c3 | 454 | mce_log(&m); |
1da177e4 | 455 | |
e9eee03e IM |
456 | /* |
457 | * Did this bank cause the exception? | |
458 | * | |
459 | * Assume that the bank with uncorrectable errors did it, | |
460 | * and that there is only a single one: | |
461 | */ | |
462 | if ((m.status & MCI_STATUS_UC) && | |
463 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
464 | panicm = m; |
465 | panicm_found = 1; | |
466 | } | |
1da177e4 LT |
467 | } |
468 | ||
e9eee03e IM |
469 | /* |
470 | * If we didn't find an uncorrectable error, pick | |
471 | * the last one (shouldn't happen, just being safe). | |
472 | */ | |
1da177e4 LT |
473 | if (!panicm_found) |
474 | panicm = m; | |
bd78432c TH |
475 | |
476 | /* | |
477 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 478 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
479 | */ |
480 | if (no_way_out && tolerant < 3) | |
1da177e4 | 481 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
482 | |
483 | /* | |
484 | * If the error seems to be unrecoverable, something should be | |
485 | * done. Try to kill as little as possible. If we can kill just | |
486 | * one task, do that. If the user has set the tolerance very | |
487 | * high, don't try to do anything at all. | |
488 | */ | |
489 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
490 | int user_space = 0; |
491 | ||
bd78432c TH |
492 | /* |
493 | * If the EIPV bit is set, it means the saved IP is the | |
494 | * instruction which caused the MCE. | |
495 | */ | |
496 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 497 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
498 | |
499 | /* | |
500 | * If we know that the error was in user space, send a | |
501 | * SIGBUS. Otherwise, panic if tolerance is low. | |
502 | * | |
380851bc | 503 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
504 | * risk of deadlocking. |
505 | */ | |
506 | if (user_space) { | |
380851bc | 507 | force_sig(SIGBUS, current); |
bd78432c TH |
508 | } else if (panic_on_oops || tolerant < 2) { |
509 | mce_panic("Uncorrected machine check", | |
510 | &panicm, mcestart); | |
511 | } | |
1da177e4 LT |
512 | } |
513 | ||
e02e68d3 TH |
514 | /* notify userspace ASAP */ |
515 | set_thread_flag(TIF_MCE_NOTIFY); | |
516 | ||
bd78432c | 517 | /* the last thing we do is clear state */ |
b79109c3 AK |
518 | for (i = 0; i < banks; i++) { |
519 | if (test_bit(i, toclear)) | |
5f8c1a54 | 520 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 | 521 | } |
5f8c1a54 | 522 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 523 | out: |
553f265f | 524 | atomic_dec(&mce_entry); |
88921be3 | 525 | sync_core(); |
1da177e4 | 526 | } |
ea149b36 | 527 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 528 | |
15d5f839 DZ |
529 | #ifdef CONFIG_X86_MCE_INTEL |
530 | /*** | |
531 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 532 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
533 | * @status: Event status information |
534 | * | |
535 | * This function should be called by the thermal interrupt after the | |
536 | * event has been processed and the decision was made to log the event | |
537 | * further. | |
538 | * | |
539 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
540 | * and historically has been the register value of the | |
541 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
542 | */ | |
b5f2fa4e | 543 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
544 | { |
545 | struct mce m; | |
546 | ||
b5f2fa4e | 547 | mce_setup(&m); |
15d5f839 DZ |
548 | m.bank = MCE_THERMAL_BANK; |
549 | m.status = status; | |
15d5f839 DZ |
550 | mce_log(&m); |
551 | } | |
552 | #endif /* CONFIG_X86_MCE_INTEL */ | |
553 | ||
1da177e4 | 554 | /* |
8a336b0a TH |
555 | * Periodic polling timer for "silent" machine check errors. If the |
556 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
557 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 558 | */ |
1da177e4 | 559 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 560 | |
6298c512 | 561 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 562 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 563 | |
52d168e2 | 564 | static void mcheck_timer(unsigned long data) |
1da177e4 | 565 | { |
52d168e2 | 566 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 567 | int *n; |
52d168e2 AK |
568 | |
569 | WARN_ON(smp_processor_id() != data); | |
570 | ||
e9eee03e | 571 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
572 | machine_check_poll(MCP_TIMESTAMP, |
573 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 574 | } |
1da177e4 LT |
575 | |
576 | /* | |
e02e68d3 TH |
577 | * Alert userspace if needed. If we logged an MCE, reduce the |
578 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 579 | */ |
6298c512 | 580 | n = &__get_cpu_var(next_interval); |
14a02530 | 581 | if (mce_notify_user()) |
6298c512 | 582 | *n = max(*n/2, HZ/100); |
14a02530 | 583 | else |
6298c512 | 584 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 585 | |
6298c512 | 586 | t->expires = jiffies + *n; |
52d168e2 | 587 | add_timer(t); |
e02e68d3 TH |
588 | } |
589 | ||
9bd98405 AK |
590 | static void mce_do_trigger(struct work_struct *work) |
591 | { | |
592 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
593 | } | |
594 | ||
595 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
596 | ||
e02e68d3 | 597 | /* |
9bd98405 AK |
598 | * Notify the user(s) about new machine check events. |
599 | * Can be called from interrupt context, but not from machine check/NMI | |
600 | * context. | |
e02e68d3 TH |
601 | */ |
602 | int mce_notify_user(void) | |
603 | { | |
8457c84d AK |
604 | /* Not more than two messages every minute */ |
605 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
606 | ||
e02e68d3 | 607 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 608 | |
e02e68d3 | 609 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 610 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
611 | |
612 | /* | |
613 | * There is no risk of missing notifications because | |
614 | * work_pending is always cleared before the function is | |
615 | * executed. | |
616 | */ | |
617 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
618 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 619 | |
8457c84d | 620 | if (__ratelimit(&ratelimit)) |
8a336b0a | 621 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
622 | |
623 | return 1; | |
1da177e4 | 624 | } |
e02e68d3 TH |
625 | return 0; |
626 | } | |
ea149b36 | 627 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 628 | |
d88203d1 | 629 | /* |
1da177e4 LT |
630 | * Initialize Machine Checks for a CPU. |
631 | */ | |
0d7482e3 | 632 | static int mce_cap_init(void) |
1da177e4 | 633 | { |
0d7482e3 | 634 | unsigned b; |
e9eee03e | 635 | u64 cap; |
1da177e4 LT |
636 | |
637 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
638 | |
639 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
640 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
641 | ||
0d7482e3 AK |
642 | if (b > MAX_NR_BANKS) { |
643 | printk(KERN_WARNING | |
644 | "MCE: Using only %u machine check banks out of %u\n", | |
645 | MAX_NR_BANKS, b); | |
646 | b = MAX_NR_BANKS; | |
647 | } | |
648 | ||
649 | /* Don't support asymmetric configurations today */ | |
650 | WARN_ON(banks != 0 && b != banks); | |
651 | banks = b; | |
652 | if (!bank) { | |
653 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
654 | if (!bank) | |
655 | return -ENOMEM; | |
656 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 657 | } |
0d7482e3 | 658 | |
94ad8474 | 659 | /* Use accurate RIP reporting if available. */ |
01c6680a | 660 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 661 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 662 | |
0d7482e3 AK |
663 | return 0; |
664 | } | |
665 | ||
8be91105 | 666 | static void mce_init(void) |
0d7482e3 | 667 | { |
e9eee03e | 668 | mce_banks_t all_banks; |
0d7482e3 AK |
669 | u64 cap; |
670 | int i; | |
671 | ||
b79109c3 AK |
672 | /* |
673 | * Log the machine checks left over from the previous reset. | |
674 | */ | |
ee031c31 | 675 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 676 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
677 | |
678 | set_in_cr4(X86_CR4_MCE); | |
679 | ||
0d7482e3 | 680 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
681 | if (cap & MCG_CTL_P) |
682 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
683 | ||
684 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
685 | if (skip_bank_init(i)) |
686 | continue; | |
0d7482e3 | 687 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 688 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 689 | } |
1da177e4 LT |
690 | } |
691 | ||
692 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 693 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 694 | { |
1da177e4 | 695 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 696 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
697 | if (c->x86 == 15 && banks > 4) { |
698 | /* | |
699 | * disable GART TBL walk error reporting, which | |
700 | * trips off incorrectly with the IOMMU & 3ware | |
701 | * & Cerberus: | |
702 | */ | |
0d7482e3 | 703 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
704 | } |
705 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
706 | /* | |
707 | * Lots of broken BIOS around that don't clear them | |
708 | * by default and leave crap in there. Don't log: | |
709 | */ | |
911f6a7b | 710 | mce_bootlog = 0; |
e9eee03e | 711 | } |
2e6f694f AK |
712 | /* |
713 | * Various K7s with broken bank 0 around. Always disable | |
714 | * by default. | |
715 | */ | |
716 | if (c->x86 == 6) | |
717 | bank[0] = 0; | |
1da177e4 | 718 | } |
e583538f | 719 | |
06b7a7a5 AK |
720 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
721 | /* | |
722 | * SDM documents that on family 6 bank 0 should not be written | |
723 | * because it aliases to another special BIOS controlled | |
724 | * register. | |
725 | * But it's not aliased anymore on model 0x1a+ | |
726 | * Don't ignore bank 0 completely because there could be a | |
727 | * valid event later, merely don't write CTL0. | |
728 | */ | |
729 | ||
730 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
731 | __set_bit(0, &dont_init_banks); | |
732 | } | |
d88203d1 | 733 | } |
1da177e4 | 734 | |
4efc0670 AK |
735 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
736 | { | |
737 | if (c->x86 != 5) | |
738 | return; | |
739 | switch (c->x86_vendor) { | |
740 | case X86_VENDOR_INTEL: | |
741 | if (mce_p5_enabled()) | |
742 | intel_p5_mcheck_init(c); | |
743 | break; | |
744 | case X86_VENDOR_CENTAUR: | |
745 | winchip_mcheck_init(c); | |
746 | break; | |
747 | } | |
748 | } | |
749 | ||
cc3ca220 | 750 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
751 | { |
752 | switch (c->x86_vendor) { | |
753 | case X86_VENDOR_INTEL: | |
754 | mce_intel_feature_init(c); | |
755 | break; | |
89b831ef JS |
756 | case X86_VENDOR_AMD: |
757 | mce_amd_feature_init(c); | |
758 | break; | |
1da177e4 LT |
759 | default: |
760 | break; | |
761 | } | |
762 | } | |
763 | ||
52d168e2 AK |
764 | static void mce_init_timer(void) |
765 | { | |
766 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 767 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 768 | |
6298c512 AK |
769 | *n = check_interval * HZ; |
770 | if (!*n) | |
52d168e2 AK |
771 | return; |
772 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 773 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
774 | add_timer(t); |
775 | } | |
776 | ||
d88203d1 | 777 | /* |
1da177e4 | 778 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 779 | * Must be called with preempt off: |
1da177e4 | 780 | */ |
e6982c67 | 781 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 782 | { |
4efc0670 AK |
783 | if (mce_disabled) |
784 | return; | |
785 | ||
786 | mce_ancient_init(c); | |
787 | ||
5b4408fd | 788 | if (!mce_available(c)) |
1da177e4 LT |
789 | return; |
790 | ||
0d7482e3 | 791 | if (mce_cap_init() < 0) { |
04b2b1a4 | 792 | mce_disabled = 1; |
0d7482e3 AK |
793 | return; |
794 | } | |
795 | mce_cpu_quirks(c); | |
796 | ||
5d727926 AK |
797 | machine_check_vector = do_machine_check; |
798 | ||
8be91105 | 799 | mce_init(); |
1da177e4 | 800 | mce_cpu_features(c); |
52d168e2 | 801 | mce_init_timer(); |
1da177e4 LT |
802 | } |
803 | ||
804 | /* | |
805 | * Character device to read and clear the MCE log. | |
806 | */ | |
807 | ||
f528e7ba | 808 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
809 | static int open_count; /* #times opened */ |
810 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
811 | |
812 | static int mce_open(struct inode *inode, struct file *file) | |
813 | { | |
814 | spin_lock(&mce_state_lock); | |
815 | ||
816 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
817 | spin_unlock(&mce_state_lock); | |
e9eee03e | 818 | |
f528e7ba TH |
819 | return -EBUSY; |
820 | } | |
821 | ||
822 | if (file->f_flags & O_EXCL) | |
823 | open_exclu = 1; | |
824 | open_count++; | |
825 | ||
826 | spin_unlock(&mce_state_lock); | |
827 | ||
bd78432c | 828 | return nonseekable_open(inode, file); |
f528e7ba TH |
829 | } |
830 | ||
831 | static int mce_release(struct inode *inode, struct file *file) | |
832 | { | |
833 | spin_lock(&mce_state_lock); | |
834 | ||
835 | open_count--; | |
836 | open_exclu = 0; | |
837 | ||
838 | spin_unlock(&mce_state_lock); | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
d88203d1 TG |
843 | static void collect_tscs(void *data) |
844 | { | |
1da177e4 | 845 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 846 | |
1da177e4 | 847 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 848 | } |
1da177e4 | 849 | |
e9eee03e IM |
850 | static DEFINE_MUTEX(mce_read_mutex); |
851 | ||
d88203d1 TG |
852 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
853 | loff_t *off) | |
1da177e4 | 854 | { |
e9eee03e | 855 | char __user *buf = ubuf; |
f0de53bb | 856 | unsigned long *cpu_tsc; |
ef41df43 | 857 | unsigned prev, next; |
1da177e4 LT |
858 | int i, err; |
859 | ||
6bca67f9 | 860 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
861 | if (!cpu_tsc) |
862 | return -ENOMEM; | |
863 | ||
8c8b8859 | 864 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
865 | next = rcu_dereference(mcelog.next); |
866 | ||
867 | /* Only supports full reads right now */ | |
d88203d1 | 868 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 869 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 870 | kfree(cpu_tsc); |
e9eee03e | 871 | |
1da177e4 LT |
872 | return -EINVAL; |
873 | } | |
874 | ||
875 | err = 0; | |
ef41df43 HY |
876 | prev = 0; |
877 | do { | |
878 | for (i = prev; i < next; i++) { | |
879 | unsigned long start = jiffies; | |
880 | ||
881 | while (!mcelog.entry[i].finished) { | |
882 | if (time_after_eq(jiffies, start + 2)) { | |
883 | memset(mcelog.entry + i, 0, | |
884 | sizeof(struct mce)); | |
885 | goto timeout; | |
886 | } | |
887 | cpu_relax(); | |
673242c1 | 888 | } |
ef41df43 HY |
889 | smp_rmb(); |
890 | err |= copy_to_user(buf, mcelog.entry + i, | |
891 | sizeof(struct mce)); | |
892 | buf += sizeof(struct mce); | |
893 | timeout: | |
894 | ; | |
673242c1 | 895 | } |
1da177e4 | 896 | |
ef41df43 HY |
897 | memset(mcelog.entry + prev, 0, |
898 | (next - prev) * sizeof(struct mce)); | |
899 | prev = next; | |
900 | next = cmpxchg(&mcelog.next, prev, 0); | |
901 | } while (next != prev); | |
1da177e4 | 902 | |
b2b18660 | 903 | synchronize_sched(); |
1da177e4 | 904 | |
d88203d1 TG |
905 | /* |
906 | * Collect entries that were still getting written before the | |
907 | * synchronize. | |
908 | */ | |
15c8b6c1 | 909 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 910 | |
d88203d1 TG |
911 | for (i = next; i < MCE_LOG_LEN; i++) { |
912 | if (mcelog.entry[i].finished && | |
913 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
914 | err |= copy_to_user(buf, mcelog.entry+i, | |
915 | sizeof(struct mce)); | |
1da177e4 LT |
916 | smp_rmb(); |
917 | buf += sizeof(struct mce); | |
918 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
919 | } | |
d88203d1 | 920 | } |
8c8b8859 | 921 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 922 | kfree(cpu_tsc); |
e9eee03e | 923 | |
d88203d1 | 924 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
925 | } |
926 | ||
e02e68d3 TH |
927 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
928 | { | |
929 | poll_wait(file, &mce_wait, wait); | |
930 | if (rcu_dereference(mcelog.next)) | |
931 | return POLLIN | POLLRDNORM; | |
932 | return 0; | |
933 | } | |
934 | ||
c68461b6 | 935 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
936 | { |
937 | int __user *p = (int __user *)arg; | |
d88203d1 | 938 | |
1da177e4 | 939 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 940 | return -EPERM; |
e9eee03e | 941 | |
1da177e4 | 942 | switch (cmd) { |
d88203d1 | 943 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
944 | return put_user(sizeof(struct mce), p); |
945 | case MCE_GET_LOG_LEN: | |
d88203d1 | 946 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
947 | case MCE_GETCLEAR_FLAGS: { |
948 | unsigned flags; | |
d88203d1 TG |
949 | |
950 | do { | |
1da177e4 | 951 | flags = mcelog.flags; |
d88203d1 | 952 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 953 | |
d88203d1 | 954 | return put_user(flags, p); |
1da177e4 LT |
955 | } |
956 | default: | |
d88203d1 TG |
957 | return -ENOTTY; |
958 | } | |
1da177e4 LT |
959 | } |
960 | ||
a1ff41bf | 961 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 962 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
963 | .open = mce_open, |
964 | .release = mce_release, | |
965 | .read = mce_read, | |
966 | .poll = mce_poll, | |
967 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 968 | }; |
ea149b36 | 969 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
970 | |
971 | static struct miscdevice mce_log_device = { | |
972 | MISC_MCELOG_MINOR, | |
973 | "mcelog", | |
974 | &mce_chrdev_ops, | |
975 | }; | |
976 | ||
13503fa9 HS |
977 | /* |
978 | * mce=off disables machine check | |
979 | * mce=TOLERANCELEVEL (number, see above) | |
980 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
981 | * mce=nobootlog Don't log MCEs from before booting. | |
982 | */ | |
1da177e4 LT |
983 | static int __init mcheck_enable(char *str) |
984 | { | |
4efc0670 AK |
985 | if (*str == 0) |
986 | enable_p5_mce(); | |
987 | if (*str == '=') | |
988 | str++; | |
1da177e4 | 989 | if (!strcmp(str, "off")) |
04b2b1a4 | 990 | mce_disabled = 1; |
13503fa9 HS |
991 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
992 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
993 | else if (isdigit(str[0])) |
994 | get_option(&str, &tolerant); | |
13503fa9 | 995 | else { |
4efc0670 | 996 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
997 | str); |
998 | return 0; | |
999 | } | |
9b41046c | 1000 | return 1; |
1da177e4 | 1001 | } |
4efc0670 | 1002 | __setup("mce", mcheck_enable); |
1da177e4 | 1003 | |
d88203d1 | 1004 | /* |
1da177e4 | 1005 | * Sysfs support |
d88203d1 | 1006 | */ |
1da177e4 | 1007 | |
973a2dd1 AK |
1008 | /* |
1009 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1010 | * them later. | |
1011 | */ | |
1012 | static int mce_disable(void) | |
1013 | { | |
1014 | int i; | |
1015 | ||
06b7a7a5 AK |
1016 | for (i = 0; i < banks; i++) { |
1017 | if (!skip_bank_init(i)) | |
1018 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1019 | } | |
973a2dd1 AK |
1020 | return 0; |
1021 | } | |
1022 | ||
1023 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1024 | { | |
1025 | return mce_disable(); | |
1026 | } | |
1027 | ||
1028 | static int mce_shutdown(struct sys_device *dev) | |
1029 | { | |
1030 | return mce_disable(); | |
1031 | } | |
1032 | ||
e9eee03e IM |
1033 | /* |
1034 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1035 | * Only one CPU is active at this time, the others get re-added later using | |
1036 | * CPU hotplug: | |
1037 | */ | |
1da177e4 LT |
1038 | static int mce_resume(struct sys_device *dev) |
1039 | { | |
8be91105 | 1040 | mce_init(); |
6ec68bff | 1041 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1042 | |
1da177e4 LT |
1043 | return 0; |
1044 | } | |
1045 | ||
52d168e2 AK |
1046 | static void mce_cpu_restart(void *data) |
1047 | { | |
1048 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1049 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1050 | mce_init(); |
52d168e2 AK |
1051 | mce_init_timer(); |
1052 | } | |
1053 | ||
1da177e4 | 1054 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1055 | static void mce_restart(void) |
1056 | { | |
52d168e2 | 1057 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1058 | } |
1059 | ||
1060 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1061 | .suspend = mce_suspend, |
1062 | .shutdown = mce_shutdown, | |
1063 | .resume = mce_resume, | |
1064 | .name = "machinecheck", | |
1da177e4 LT |
1065 | }; |
1066 | ||
cb491fca | 1067 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1068 | |
1069 | __cpuinitdata | |
1070 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1071 | |
0d7482e3 AK |
1072 | static struct sysdev_attribute *bank_attrs; |
1073 | ||
1074 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1075 | char *buf) | |
1076 | { | |
1077 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1078 | |
f6d1826d | 1079 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1080 | } |
1081 | ||
1082 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1083 | const char *buf, size_t size) |
0d7482e3 | 1084 | { |
9319cec8 | 1085 | u64 new; |
e9eee03e | 1086 | |
9319cec8 | 1087 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1088 | return -EINVAL; |
e9eee03e | 1089 | |
0d7482e3 AK |
1090 | bank[attr - bank_attrs] = new; |
1091 | mce_restart(); | |
e9eee03e | 1092 | |
9319cec8 | 1093 | return size; |
0d7482e3 | 1094 | } |
a98f0dd3 | 1095 | |
e9eee03e IM |
1096 | static ssize_t |
1097 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1098 | { |
1099 | strcpy(buf, trigger); | |
1100 | strcat(buf, "\n"); | |
1101 | return strlen(trigger) + 1; | |
1102 | } | |
1103 | ||
4a0b2b4d | 1104 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1105 | const char *buf, size_t siz) |
a98f0dd3 AK |
1106 | { |
1107 | char *p; | |
1108 | int len; | |
e9eee03e | 1109 | |
a98f0dd3 AK |
1110 | strncpy(trigger, buf, sizeof(trigger)); |
1111 | trigger[sizeof(trigger)-1] = 0; | |
1112 | len = strlen(trigger); | |
1113 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1114 | |
1115 | if (*p) | |
1116 | *p = 0; | |
1117 | ||
a98f0dd3 AK |
1118 | return len; |
1119 | } | |
1120 | ||
b56f642d AK |
1121 | static ssize_t store_int_with_restart(struct sys_device *s, |
1122 | struct sysdev_attribute *attr, | |
1123 | const char *buf, size_t size) | |
1124 | { | |
1125 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1126 | mce_restart(); | |
1127 | return ret; | |
1128 | } | |
1129 | ||
a98f0dd3 | 1130 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1131 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e | 1132 | |
b56f642d AK |
1133 | static struct sysdev_ext_attribute attr_check_interval = { |
1134 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1135 | store_int_with_restart), | |
1136 | &check_interval | |
1137 | }; | |
e9eee03e | 1138 | |
cb491fca | 1139 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1140 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
a98f0dd3 AK |
1141 | NULL |
1142 | }; | |
1da177e4 | 1143 | |
cb491fca | 1144 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1145 | |
e9eee03e | 1146 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1147 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1148 | { |
1149 | int err; | |
73ca5358 | 1150 | int i; |
92cb7612 | 1151 | |
90367556 | 1152 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1153 | return -EIO; |
1154 | ||
cb491fca IM |
1155 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1156 | per_cpu(mce_dev, cpu).id = cpu; | |
1157 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1158 | |
cb491fca | 1159 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1160 | if (err) |
1161 | return err; | |
1162 | ||
cb491fca IM |
1163 | for (i = 0; mce_attrs[i]; i++) { |
1164 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1165 | if (err) |
1166 | goto error; | |
1167 | } | |
0d7482e3 | 1168 | for (i = 0; i < banks; i++) { |
cb491fca | 1169 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1170 | &bank_attrs[i]); |
1171 | if (err) | |
1172 | goto error2; | |
1173 | } | |
cb491fca | 1174 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1175 | |
d435d862 | 1176 | return 0; |
0d7482e3 | 1177 | error2: |
cb491fca IM |
1178 | while (--i >= 0) |
1179 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1180 | error: |
cb491fca IM |
1181 | while (--i >= 0) |
1182 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1183 | ||
1184 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1185 | |
91c6d400 AK |
1186 | return err; |
1187 | } | |
1188 | ||
2d9cd6c2 | 1189 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1190 | { |
73ca5358 SL |
1191 | int i; |
1192 | ||
cb491fca | 1193 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1194 | return; |
1195 | ||
cb491fca IM |
1196 | for (i = 0; mce_attrs[i]; i++) |
1197 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1198 | ||
0d7482e3 | 1199 | for (i = 0; i < banks; i++) |
cb491fca IM |
1200 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1201 | ||
1202 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1203 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1204 | } |
91c6d400 | 1205 | |
d6b75584 | 1206 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1207 | static void mce_disable_cpu(void *h) |
d6b75584 | 1208 | { |
88ccbedd | 1209 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1210 | int i; |
d6b75584 AK |
1211 | |
1212 | if (!mce_available(¤t_cpu_data)) | |
1213 | return; | |
88ccbedd AK |
1214 | if (!(action & CPU_TASKS_FROZEN)) |
1215 | cmci_clear(); | |
06b7a7a5 AK |
1216 | for (i = 0; i < banks; i++) { |
1217 | if (!skip_bank_init(i)) | |
1218 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1219 | } | |
d6b75584 AK |
1220 | } |
1221 | ||
ec5b3d32 | 1222 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1223 | { |
88ccbedd | 1224 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1225 | int i; |
d6b75584 AK |
1226 | |
1227 | if (!mce_available(¤t_cpu_data)) | |
1228 | return; | |
e9eee03e | 1229 | |
88ccbedd AK |
1230 | if (!(action & CPU_TASKS_FROZEN)) |
1231 | cmci_reenable(); | |
06b7a7a5 AK |
1232 | for (i = 0; i < banks; i++) { |
1233 | if (!skip_bank_init(i)) | |
1234 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1235 | } | |
d6b75584 AK |
1236 | } |
1237 | ||
91c6d400 | 1238 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1239 | static int __cpuinit |
1240 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1241 | { |
1242 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1243 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1244 | |
1245 | switch (action) { | |
bae19fe0 AH |
1246 | case CPU_ONLINE: |
1247 | case CPU_ONLINE_FROZEN: | |
1248 | mce_create_device(cpu); | |
8735728e RW |
1249 | if (threshold_cpu_callback) |
1250 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1251 | break; |
91c6d400 | 1252 | case CPU_DEAD: |
8bb78442 | 1253 | case CPU_DEAD_FROZEN: |
8735728e RW |
1254 | if (threshold_cpu_callback) |
1255 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1256 | mce_remove_device(cpu); |
1257 | break; | |
52d168e2 AK |
1258 | case CPU_DOWN_PREPARE: |
1259 | case CPU_DOWN_PREPARE_FROZEN: | |
1260 | del_timer_sync(t); | |
88ccbedd | 1261 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1262 | break; |
1263 | case CPU_DOWN_FAILED: | |
1264 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1265 | t->expires = round_jiffies(jiffies + |
1266 | __get_cpu_var(next_interval)); | |
52d168e2 | 1267 | add_timer_on(t, cpu); |
88ccbedd AK |
1268 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1269 | break; | |
1270 | case CPU_POST_DEAD: | |
1271 | /* intentionally ignoring frozen here */ | |
1272 | cmci_rediscover(cpu); | |
52d168e2 | 1273 | break; |
91c6d400 | 1274 | } |
bae19fe0 | 1275 | return NOTIFY_OK; |
91c6d400 AK |
1276 | } |
1277 | ||
1e35669d | 1278 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1279 | .notifier_call = mce_cpu_callback, |
1280 | }; | |
1281 | ||
0d7482e3 AK |
1282 | static __init int mce_init_banks(void) |
1283 | { | |
1284 | int i; | |
1285 | ||
1286 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1287 | GFP_KERNEL); | |
1288 | if (!bank_attrs) | |
1289 | return -ENOMEM; | |
1290 | ||
1291 | for (i = 0; i < banks; i++) { | |
1292 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1293 | |
1294 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1295 | if (!a->attr.name) |
1296 | goto nomem; | |
e9eee03e IM |
1297 | |
1298 | a->attr.mode = 0644; | |
1299 | a->show = show_bank; | |
1300 | a->store = set_bank; | |
0d7482e3 AK |
1301 | } |
1302 | return 0; | |
1303 | ||
1304 | nomem: | |
1305 | while (--i >= 0) | |
1306 | kfree(bank_attrs[i].attr.name); | |
1307 | kfree(bank_attrs); | |
1308 | bank_attrs = NULL; | |
e9eee03e | 1309 | |
0d7482e3 AK |
1310 | return -ENOMEM; |
1311 | } | |
1312 | ||
91c6d400 AK |
1313 | static __init int mce_init_device(void) |
1314 | { | |
1315 | int err; | |
1316 | int i = 0; | |
1317 | ||
1da177e4 LT |
1318 | if (!mce_available(&boot_cpu_data)) |
1319 | return -EIO; | |
0d7482e3 | 1320 | |
cb491fca | 1321 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1322 | |
0d7482e3 AK |
1323 | err = mce_init_banks(); |
1324 | if (err) | |
1325 | return err; | |
1326 | ||
1da177e4 | 1327 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1328 | if (err) |
1329 | return err; | |
91c6d400 AK |
1330 | |
1331 | for_each_online_cpu(i) { | |
d435d862 AM |
1332 | err = mce_create_device(i); |
1333 | if (err) | |
1334 | return err; | |
91c6d400 AK |
1335 | } |
1336 | ||
be6b5a35 | 1337 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1338 | misc_register(&mce_log_device); |
e9eee03e | 1339 | |
1da177e4 | 1340 | return err; |
1da177e4 | 1341 | } |
91c6d400 | 1342 | |
1da177e4 | 1343 | device_initcall(mce_init_device); |
a988d334 | 1344 | |
4efc0670 | 1345 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1346 | |
a988d334 IM |
1347 | int nr_mce_banks; |
1348 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1349 | ||
a988d334 IM |
1350 | /* This has to be run for each processor */ |
1351 | void mcheck_init(struct cpuinfo_x86 *c) | |
1352 | { | |
1353 | if (mce_disabled == 1) | |
1354 | return; | |
1355 | ||
1356 | switch (c->x86_vendor) { | |
1357 | case X86_VENDOR_AMD: | |
1358 | amd_mcheck_init(c); | |
1359 | break; | |
1360 | ||
1361 | case X86_VENDOR_INTEL: | |
1362 | if (c->x86 == 5) | |
1363 | intel_p5_mcheck_init(c); | |
1364 | if (c->x86 == 6) | |
1365 | intel_p6_mcheck_init(c); | |
1366 | if (c->x86 == 15) | |
1367 | intel_p4_mcheck_init(c); | |
1368 | break; | |
1369 | ||
1370 | case X86_VENDOR_CENTAUR: | |
1371 | if (c->x86 == 5) | |
1372 | winchip_mcheck_init(c); | |
1373 | break; | |
1374 | ||
1375 | default: | |
1376 | break; | |
1377 | } | |
b659294b | 1378 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1379 | } |
1380 | ||
a988d334 IM |
1381 | static int __init mcheck_enable(char *str) |
1382 | { | |
1383 | mce_disabled = -1; | |
1384 | return 1; | |
1385 | } | |
1386 | ||
a988d334 IM |
1387 | __setup("mce", mcheck_enable); |
1388 | ||
d7c3c9a6 AK |
1389 | #endif /* CONFIG_X86_OLD_MCE */ |
1390 | ||
1391 | /* | |
1392 | * Old style boot options parsing. Only for compatibility. | |
1393 | */ | |
1394 | static int __init mcheck_disable(char *str) | |
1395 | { | |
1396 | mce_disabled = 1; | |
1397 | return 1; | |
1398 | } | |
1399 | __setup("nomce", mcheck_disable); |