Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
95927475 | 46 | #include <asm/traps.h> |
375074cc | 47 | #include <asm/tlbflush.h> |
e9eee03e IM |
48 | #include <asm/mce.h> |
49 | #include <asm/msr.h> | |
1da177e4 | 50 | |
bd19a5e6 | 51 | #include "mce-internal.h" |
711c2e48 | 52 | |
93b62c3c | 53 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 54 | |
9a7783d0 | 55 | #define mce_log_get_idx_check(p) \ |
e90328b8 | 56 | ({ \ |
f78f5b90 PM |
57 | RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \ |
58 | !lockdep_is_held(&mce_chrdev_read_mutex), \ | |
3959df1d | 59 | "suspicious mce_log_get_idx_check() usage"); \ |
e90328b8 PM |
60 | smp_load_acquire(&(p)); \ |
61 | }) | |
f56e8a07 | 62 | |
8968f9d3 HS |
63 | #define CREATE_TRACE_POINTS |
64 | #include <trace/events/mce.h> | |
65 | ||
3f2f0680 | 66 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 67 | |
01ca79f1 AK |
68 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
69 | ||
1462594b | 70 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 71 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 72 | |
d203f0b8 | 73 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 74 | .bootlog = -1, |
d203f0b8 BP |
75 | /* |
76 | * Tolerant levels: | |
77 | * 0: always panic on uncorrected errors, log corrected errors | |
78 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
79 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
80 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
81 | */ | |
84c2559d BP |
82 | .tolerant = 1, |
83 | .monarch_timeout = -1 | |
d203f0b8 BP |
84 | }; |
85 | ||
1020bcbc HS |
86 | /* User mode helper program triggered by machine check event */ |
87 | static unsigned long mce_need_notify; | |
88 | static char mce_helper[128]; | |
89 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 90 | |
93b62c3c HS |
91 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
92 | ||
3c079792 AK |
93 | static DEFINE_PER_CPU(struct mce, mces_seen); |
94 | static int cpu_missing; | |
95 | ||
0644414e NR |
96 | /* |
97 | * MCA banks polled by the period polling timer for corrected events. | |
98 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
99 | */ | |
ee031c31 AK |
100 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
101 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
102 | }; | |
103 | ||
c3d1fb56 NR |
104 | /* |
105 | * MCA banks controlled through firmware first for corrected errors. | |
106 | * This is a global list of banks for which we won't enable CMCI and we | |
107 | * won't poll. Firmware controls these banks and is responsible for | |
108 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
109 | * errors are still notified through a machine check. | |
110 | */ | |
111 | mce_banks_t mce_banks_ce_disabled; | |
112 | ||
061120ae CG |
113 | static struct work_struct mce_work; |
114 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 115 | |
61b0fccd TL |
116 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
117 | ||
3653ada5 BP |
118 | /* |
119 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
120 | * MCE errors in a human-readable form. | |
121 | */ | |
648ed940 | 122 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 123 | |
b5f2fa4e AK |
124 | /* Do initial initialization of a struct mce */ |
125 | void mce_setup(struct mce *m) | |
126 | { | |
127 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 128 | m->cpu = m->extcpu = smp_processor_id(); |
4ea1636b | 129 | m->tsc = rdtsc(); |
8ee08347 AK |
130 | /* We hope get_seconds stays lockless */ |
131 | m->time = get_seconds(); | |
132 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
133 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 134 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
135 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
136 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
137 | } |
138 | ||
ea149b36 AK |
139 | DEFINE_PER_CPU(struct mce, injectm); |
140 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
141 | ||
1da177e4 LT |
142 | /* |
143 | * Lockless MCE logging infrastructure. | |
144 | * This avoids deadlocks on printk locks without having to break locks. Also | |
145 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
146 | */ | |
147 | ||
231fd906 | 148 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
149 | .signature = MCE_LOG_SIGNATURE, |
150 | .len = MCE_LOG_LEN, | |
151 | .recordlen = sizeof(struct mce), | |
d88203d1 | 152 | }; |
1da177e4 LT |
153 | |
154 | void mce_log(struct mce *mce) | |
155 | { | |
156 | unsigned next, entry; | |
e9eee03e | 157 | |
8968f9d3 HS |
158 | /* Emit the trace record: */ |
159 | trace_mce_record(mce); | |
160 | ||
f29a7aff CG |
161 | if (!mce_gen_pool_add(mce)) |
162 | irq_work_queue(&mce_irq_work); | |
f0cb5452 | 163 | |
7644143c | 164 | wmb(); |
1da177e4 | 165 | for (;;) { |
9a7783d0 | 166 | entry = mce_log_get_idx_check(mcelog.next); |
673242c1 | 167 | for (;;) { |
696e409d | 168 | |
e9eee03e IM |
169 | /* |
170 | * When the buffer fills up discard new entries. | |
171 | * Assume that the earlier errors are the more | |
172 | * interesting ones: | |
173 | */ | |
673242c1 | 174 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
175 | set_bit(MCE_OVERFLOW, |
176 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
177 | return; |
178 | } | |
e9eee03e | 179 | /* Old left over entry. Skip: */ |
673242c1 AK |
180 | if (mcelog.entry[entry].finished) { |
181 | entry++; | |
182 | continue; | |
183 | } | |
7644143c | 184 | break; |
1da177e4 | 185 | } |
1da177e4 LT |
186 | smp_rmb(); |
187 | next = entry + 1; | |
188 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
189 | break; | |
190 | } | |
191 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 192 | wmb(); |
1da177e4 | 193 | mcelog.entry[entry].finished = 1; |
7644143c | 194 | wmb(); |
1da177e4 | 195 | |
1020bcbc | 196 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
197 | } |
198 | ||
a79da384 | 199 | void mce_inject_log(struct mce *m) |
09371957 | 200 | { |
a79da384 BP |
201 | mutex_lock(&mce_chrdev_read_mutex); |
202 | mce_log(m); | |
203 | mutex_unlock(&mce_chrdev_read_mutex); | |
09371957 | 204 | } |
a79da384 | 205 | EXPORT_SYMBOL_GPL(mce_inject_log); |
09371957 | 206 | |
fd4cf79f | 207 | static struct notifier_block mce_srao_nb; |
09371957 | 208 | |
3653ada5 BP |
209 | void mce_register_decode_chain(struct notifier_block *nb) |
210 | { | |
fd4cf79f CG |
211 | /* Ensure SRAO notifier has the highest priority in the decode chain. */ |
212 | if (nb != &mce_srao_nb && nb->priority == INT_MAX) | |
213 | nb->priority -= 1; | |
214 | ||
3653ada5 BP |
215 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); |
216 | } | |
217 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
218 | ||
219 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
220 | { | |
221 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
222 | } | |
223 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
224 | ||
a9750a31 YG |
225 | static inline u32 ctl_reg(int bank) |
226 | { | |
227 | return MSR_IA32_MCx_CTL(bank); | |
228 | } | |
229 | ||
230 | static inline u32 status_reg(int bank) | |
231 | { | |
232 | return MSR_IA32_MCx_STATUS(bank); | |
233 | } | |
234 | ||
235 | static inline u32 addr_reg(int bank) | |
236 | { | |
237 | return MSR_IA32_MCx_ADDR(bank); | |
238 | } | |
239 | ||
240 | static inline u32 misc_reg(int bank) | |
241 | { | |
242 | return MSR_IA32_MCx_MISC(bank); | |
243 | } | |
244 | ||
245 | static inline u32 smca_ctl_reg(int bank) | |
246 | { | |
247 | return MSR_AMD64_SMCA_MCx_CTL(bank); | |
248 | } | |
249 | ||
250 | static inline u32 smca_status_reg(int bank) | |
251 | { | |
252 | return MSR_AMD64_SMCA_MCx_STATUS(bank); | |
253 | } | |
254 | ||
255 | static inline u32 smca_addr_reg(int bank) | |
256 | { | |
257 | return MSR_AMD64_SMCA_MCx_ADDR(bank); | |
258 | } | |
259 | ||
260 | static inline u32 smca_misc_reg(int bank) | |
261 | { | |
262 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
263 | } | |
264 | ||
265 | struct mca_msr_regs msr_ops = { | |
266 | .ctl = ctl_reg, | |
267 | .status = status_reg, | |
268 | .addr = addr_reg, | |
269 | .misc = misc_reg | |
270 | }; | |
271 | ||
77e26cca | 272 | static void print_mce(struct mce *m) |
1da177e4 | 273 | { |
dffa4b2f BP |
274 | int ret = 0; |
275 | ||
a2d7b0d4 | 276 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 277 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 278 | |
65ea5b03 | 279 | if (m->ip) { |
a2d7b0d4 | 280 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
281 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
282 | m->cs, m->ip); | |
283 | ||
1da177e4 | 284 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 285 | print_symbol("{%s}", m->ip); |
f436f8bb | 286 | pr_cont("\n"); |
1da177e4 | 287 | } |
f436f8bb | 288 | |
a2d7b0d4 | 289 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 290 | if (m->addr) |
f436f8bb | 291 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 292 | if (m->misc) |
f436f8bb | 293 | pr_cont("MISC %llx ", m->misc); |
549d042d | 294 | |
f436f8bb | 295 | pr_cont("\n"); |
506ed6b5 AK |
296 | /* |
297 | * Note this output is parsed by external tools and old fields | |
298 | * should not be changed. | |
299 | */ | |
881e23e5 | 300 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
301 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
302 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
303 | |
304 | /* | |
305 | * Print out human-readable details about the MCE error, | |
fb253195 | 306 | * (if the CPU has an implementation for that) |
f436f8bb | 307 | */ |
dffa4b2f BP |
308 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
309 | if (ret == NOTIFY_STOP) | |
310 | return; | |
311 | ||
312 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
313 | } |
314 | ||
f94b61c2 AK |
315 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
316 | ||
c7c9b392 | 317 | static atomic_t mce_panicked; |
f94b61c2 | 318 | |
bf783f9f | 319 | static int fake_panic; |
c7c9b392 | 320 | static atomic_t mce_fake_panicked; |
bf783f9f | 321 | |
f94b61c2 AK |
322 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
323 | static void wait_for_panic(void) | |
324 | { | |
325 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 326 | |
f94b61c2 AK |
327 | preempt_disable(); |
328 | local_irq_enable(); | |
329 | while (timeout-- > 0) | |
330 | udelay(1); | |
29b0f591 | 331 | if (panic_timeout == 0) |
7af19e4a | 332 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
333 | panic("Panicing machine check CPU died"); |
334 | } | |
335 | ||
6c80f87e | 336 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 337 | { |
5541c93c TL |
338 | int apei_err = 0; |
339 | struct llist_node *pending; | |
340 | struct mce_evt_llist *l; | |
e02e68d3 | 341 | |
bf783f9f HY |
342 | if (!fake_panic) { |
343 | /* | |
344 | * Make sure only one CPU runs in machine check panic | |
345 | */ | |
c7c9b392 | 346 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
347 | wait_for_panic(); |
348 | barrier(); | |
f94b61c2 | 349 | |
bf783f9f HY |
350 | bust_spinlocks(1); |
351 | console_verbose(); | |
352 | } else { | |
353 | /* Don't log too much for fake panic */ | |
c7c9b392 | 354 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
355 | return; |
356 | } | |
5541c93c | 357 | pending = mce_gen_pool_prepare_records(); |
a0189c70 | 358 | /* First print corrected ones that are still unlogged */ |
5541c93c TL |
359 | llist_for_each_entry(l, pending, llnode) { |
360 | struct mce *m = &l->mce; | |
482908b4 | 361 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 362 | print_mce(m); |
482908b4 HY |
363 | if (!apei_err) |
364 | apei_err = apei_write_mce(m); | |
365 | } | |
a0189c70 AK |
366 | } |
367 | /* Now print uncorrected but with the final one last */ | |
5541c93c TL |
368 | llist_for_each_entry(l, pending, llnode) { |
369 | struct mce *m = &l->mce; | |
77e26cca HS |
370 | if (!(m->status & MCI_STATUS_UC)) |
371 | continue; | |
5541c93c | 372 | if (!final || mce_cmp(m, final)) { |
77e26cca | 373 | print_mce(m); |
482908b4 HY |
374 | if (!apei_err) |
375 | apei_err = apei_write_mce(m); | |
376 | } | |
1da177e4 | 377 | } |
482908b4 | 378 | if (final) { |
77e26cca | 379 | print_mce(final); |
482908b4 HY |
380 | if (!apei_err) |
381 | apei_err = apei_write_mce(final); | |
382 | } | |
3c079792 | 383 | if (cpu_missing) |
a2d7b0d4 | 384 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 385 | if (exp) |
a2d7b0d4 | 386 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
387 | if (!fake_panic) { |
388 | if (panic_timeout == 0) | |
7af19e4a | 389 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
390 | panic(msg); |
391 | } else | |
a2d7b0d4 | 392 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 393 | } |
1da177e4 | 394 | |
ea149b36 AK |
395 | /* Support code for software error injection */ |
396 | ||
397 | static int msr_to_offset(u32 msr) | |
398 | { | |
0a3aee0d | 399 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 400 | |
84c2559d | 401 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 402 | return offsetof(struct mce, ip); |
d9d73fcc | 403 | if (msr == msr_ops.status(bank)) |
ea149b36 | 404 | return offsetof(struct mce, status); |
d9d73fcc | 405 | if (msr == msr_ops.addr(bank)) |
ea149b36 | 406 | return offsetof(struct mce, addr); |
d9d73fcc | 407 | if (msr == msr_ops.misc(bank)) |
ea149b36 AK |
408 | return offsetof(struct mce, misc); |
409 | if (msr == MSR_IA32_MCG_STATUS) | |
410 | return offsetof(struct mce, mcgstatus); | |
411 | return -1; | |
412 | } | |
413 | ||
5f8c1a54 AK |
414 | /* MSR access wrappers used for error injection */ |
415 | static u64 mce_rdmsrl(u32 msr) | |
416 | { | |
417 | u64 v; | |
11868a2d | 418 | |
0a3aee0d | 419 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 420 | int offset = msr_to_offset(msr); |
11868a2d | 421 | |
ea149b36 AK |
422 | if (offset < 0) |
423 | return 0; | |
89cbc767 | 424 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 425 | } |
11868a2d IM |
426 | |
427 | if (rdmsrl_safe(msr, &v)) { | |
428 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
429 | /* | |
430 | * Return zero in case the access faulted. This should | |
431 | * not happen normally but can happen if the CPU does | |
432 | * something weird, or if the code is buggy. | |
433 | */ | |
434 | v = 0; | |
435 | } | |
436 | ||
5f8c1a54 AK |
437 | return v; |
438 | } | |
439 | ||
440 | static void mce_wrmsrl(u32 msr, u64 v) | |
441 | { | |
0a3aee0d | 442 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 443 | int offset = msr_to_offset(msr); |
11868a2d | 444 | |
ea149b36 | 445 | if (offset >= 0) |
89cbc767 | 446 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
447 | return; |
448 | } | |
5f8c1a54 AK |
449 | wrmsrl(msr, v); |
450 | } | |
451 | ||
b8325c5b HS |
452 | /* |
453 | * Collect all global (w.r.t. this processor) status about this machine | |
454 | * check into our "mce" struct so that we can use it later to assess | |
455 | * the severity of the problem as we read per-bank specific details. | |
456 | */ | |
457 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
458 | { | |
459 | mce_setup(m); | |
460 | ||
461 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
462 | if (regs) { | |
463 | /* | |
464 | * Get the address of the instruction at the time of | |
465 | * the machine check error. | |
466 | */ | |
467 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
468 | m->ip = regs->ip; | |
469 | m->cs = regs->cs; | |
a129a7c8 AK |
470 | |
471 | /* | |
472 | * When in VM86 mode make the cs look like ring 3 | |
473 | * always. This is a lie, but it's better than passing | |
474 | * the additional vm86 bit around everywhere. | |
475 | */ | |
476 | if (v8086_mode(regs)) | |
477 | m->cs |= 3; | |
b8325c5b HS |
478 | } |
479 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
480 | if (mca_cfg.rip_msr) |
481 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
482 | } |
483 | } | |
484 | ||
88ccbedd | 485 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 486 | { |
1462594b | 487 | if (mca_cfg.disabled) |
5b4408fd | 488 | return 0; |
3d1712c9 | 489 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
490 | } |
491 | ||
9b1beaf2 AK |
492 | static void mce_schedule_work(void) |
493 | { | |
fd4cf79f | 494 | if (!mce_gen_pool_empty() && keventd_up()) |
061120ae | 495 | schedule_work(&mce_work); |
9b1beaf2 AK |
496 | } |
497 | ||
b77e70bf | 498 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 499 | { |
9ff36ee9 | 500 | mce_notify_irq(); |
9b1beaf2 | 501 | mce_schedule_work(); |
ccc3c319 | 502 | } |
ccc3c319 AK |
503 | |
504 | static void mce_report_event(struct pt_regs *regs) | |
505 | { | |
506 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 507 | mce_notify_irq(); |
9b1beaf2 AK |
508 | /* |
509 | * Triggering the work queue here is just an insurance | |
510 | * policy in case the syscall exit notify handler | |
511 | * doesn't run soon enough or ends up running on the | |
512 | * wrong CPU (can happen when audit sleeps) | |
513 | */ | |
514 | mce_schedule_work(); | |
ccc3c319 AK |
515 | return; |
516 | } | |
517 | ||
061120ae | 518 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
519 | } |
520 | ||
feab21f8 BP |
521 | /* |
522 | * Check if the address reported by the CPU is in a format we can parse. | |
523 | * It would be possible to add code for most other cases, but all would | |
524 | * be somewhat complicated (e.g. segment offset would require an instruction | |
525 | * parser). So only support physical addresses up to page granuality for now. | |
526 | */ | |
527 | static int mce_usable_address(struct mce *m) | |
528 | { | |
529 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
530 | return 0; | |
531 | ||
532 | /* Checks after this one are Intel-specific: */ | |
533 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
534 | return 1; | |
535 | ||
536 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) | |
537 | return 0; | |
538 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) | |
539 | return 0; | |
540 | return 1; | |
541 | } | |
542 | ||
fd4cf79f CG |
543 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
544 | void *data) | |
545 | { | |
546 | struct mce *mce = (struct mce *)data; | |
547 | unsigned long pfn; | |
548 | ||
549 | if (!mce) | |
550 | return NOTIFY_DONE; | |
551 | ||
c0ec382e | 552 | if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { |
fd4cf79f CG |
553 | pfn = mce->addr >> PAGE_SHIFT; |
554 | memory_failure(pfn, MCE_VECTOR, 0); | |
555 | } | |
556 | ||
557 | return NOTIFY_OK; | |
ccc3c319 | 558 | } |
fd4cf79f CG |
559 | static struct notifier_block mce_srao_nb = { |
560 | .notifier_call = srao_decode_notifier, | |
561 | .priority = INT_MAX, | |
562 | }; | |
ccc3c319 | 563 | |
85f92694 TL |
564 | /* |
565 | * Read ADDR and MISC registers. | |
566 | */ | |
567 | static void mce_read_aux(struct mce *m, int i) | |
568 | { | |
569 | if (m->status & MCI_STATUS_MISCV) | |
d9d73fcc | 570 | m->misc = mce_rdmsrl(msr_ops.misc(i)); |
85f92694 | 571 | if (m->status & MCI_STATUS_ADDRV) { |
d9d73fcc | 572 | m->addr = mce_rdmsrl(msr_ops.addr(i)); |
85f92694 TL |
573 | |
574 | /* | |
575 | * Mask the reported address by the reported granularity. | |
576 | */ | |
1462594b | 577 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
578 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
579 | m->addr >>= shift; | |
580 | m->addr <<= shift; | |
581 | } | |
582 | } | |
583 | } | |
584 | ||
fa92c586 CY |
585 | static bool memory_error(struct mce *m) |
586 | { | |
587 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
588 | ||
589 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
db548a28 BP |
590 | /* ErrCodeExt[20:16] */ |
591 | u8 xec = (m->status >> 16) & 0x1f; | |
592 | ||
593 | return (xec == 0x0 || xec == 0x8); | |
fa92c586 CY |
594 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { |
595 | /* | |
596 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
597 | * | |
598 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
599 | * indicating a memory error. Bit 8 is used for indicating a | |
600 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
601 | * is used for indicating a `generic' cache hierarchy error | |
602 | * But we can't just blindly check the above bits, because if | |
603 | * bit 11 is set, then it is a bus/interconnect error - and | |
604 | * either way the above bits just gives more detail on what | |
605 | * bus/interconnect error happened. Note that bit 12 can be | |
606 | * ignored, as it's the "filter" bit. | |
607 | */ | |
608 | return (m->status & 0xef80) == BIT(7) || | |
609 | (m->status & 0xef00) == BIT(8) || | |
610 | (m->status & 0xeffc) == 0xc; | |
611 | } | |
612 | ||
613 | return false; | |
614 | } | |
615 | ||
ca84f696 AK |
616 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
617 | ||
d88203d1 | 618 | /* |
b79109c3 AK |
619 | * Poll for corrected events or events that happened before reset. |
620 | * Those are just logged through /dev/mcelog. | |
621 | * | |
622 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
623 | * |
624 | * Note: spec recommends to panic for fatal unsignalled | |
625 | * errors here. However this would be quite problematic -- | |
626 | * we would need to reimplement the Monarch handling and | |
627 | * it would mess up the exclusion between exception handler | |
628 | * and poll hander -- * so we skip this for now. | |
629 | * These cases should not happen anyways, or only when the CPU | |
630 | * is already totally * confused. In this case it's likely it will | |
631 | * not fully execute the machine check handler either. | |
b79109c3 | 632 | */ |
3f2f0680 | 633 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 634 | { |
8b38937b | 635 | bool error_seen = false; |
b79109c3 | 636 | struct mce m; |
fa92c586 | 637 | int severity; |
b79109c3 AK |
638 | int i; |
639 | ||
c6ae41e7 | 640 | this_cpu_inc(mce_poll_count); |
ca84f696 | 641 | |
b8325c5b | 642 | mce_gather_info(&m, NULL); |
b79109c3 | 643 | |
d203f0b8 | 644 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 645 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
646 | continue; |
647 | ||
648 | m.misc = 0; | |
649 | m.addr = 0; | |
650 | m.bank = i; | |
651 | m.tsc = 0; | |
652 | ||
653 | barrier(); | |
d9d73fcc | 654 | m.status = mce_rdmsrl(msr_ops.status(i)); |
b79109c3 AK |
655 | if (!(m.status & MCI_STATUS_VAL)) |
656 | continue; | |
657 | ||
3f2f0680 | 658 | |
b79109c3 | 659 | /* |
ed7290d0 AK |
660 | * Uncorrected or signalled events are handled by the exception |
661 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
662 | * |
663 | * TBD do the same check for MCI_STATUS_EN here? | |
664 | */ | |
ed7290d0 | 665 | if (!(flags & MCP_UC) && |
1462594b | 666 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
667 | continue; |
668 | ||
8b38937b TL |
669 | error_seen = true; |
670 | ||
85f92694 | 671 | mce_read_aux(&m, i); |
b79109c3 AK |
672 | |
673 | if (!(flags & MCP_TIMESTAMP)) | |
674 | m.tsc = 0; | |
fa92c586 CY |
675 | |
676 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
677 | ||
c0ec382e BP |
678 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) |
679 | if (m.status & MCI_STATUS_ADDRV) | |
fd4cf79f | 680 | m.severity = severity; |
fa92c586 | 681 | |
b79109c3 AK |
682 | /* |
683 | * Don't get the IP here because it's unlikely to | |
684 | * have anything to do with the actual error location. | |
685 | */ | |
8b38937b | 686 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 687 | mce_log(&m); |
c0ec382e | 688 | else if (mce_usable_address(&m)) { |
8b38937b TL |
689 | /* |
690 | * Although we skipped logging this, we still want | |
691 | * to take action. Add to the pool so the registered | |
692 | * notifiers will see it. | |
693 | */ | |
694 | if (!mce_gen_pool_add(&m)) | |
695 | mce_schedule_work(); | |
3f2f0680 | 696 | } |
b79109c3 AK |
697 | |
698 | /* | |
699 | * Clear state for this bank. | |
700 | */ | |
d9d73fcc | 701 | mce_wrmsrl(msr_ops.status(i), 0); |
b79109c3 AK |
702 | } |
703 | ||
704 | /* | |
705 | * Don't clear MCG_STATUS here because it's only defined for | |
706 | * exceptions. | |
707 | */ | |
88921be3 AK |
708 | |
709 | sync_core(); | |
3f2f0680 | 710 | |
8b38937b | 711 | return error_seen; |
b79109c3 | 712 | } |
ea149b36 | 713 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 714 | |
bd19a5e6 AK |
715 | /* |
716 | * Do a quick check if any of the events requires a panic. | |
717 | * This decides if we keep the events around or clear them. | |
718 | */ | |
61b0fccd TL |
719 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
720 | struct pt_regs *regs) | |
bd19a5e6 | 721 | { |
95022b8c | 722 | int i, ret = 0; |
17fea54b | 723 | char *tmp; |
bd19a5e6 | 724 | |
d203f0b8 | 725 | for (i = 0; i < mca_cfg.banks; i++) { |
d9d73fcc | 726 | m->status = mce_rdmsrl(msr_ops.status(i)); |
61b0fccd | 727 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 728 | __set_bit(i, validp); |
61b0fccd TL |
729 | if (quirk_no_way_out) |
730 | quirk_no_way_out(i, m, regs); | |
731 | } | |
17fea54b BP |
732 | |
733 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
734 | *msg = tmp; | |
95022b8c | 735 | ret = 1; |
17fea54b | 736 | } |
bd19a5e6 | 737 | } |
95022b8c | 738 | return ret; |
bd19a5e6 AK |
739 | } |
740 | ||
3c079792 AK |
741 | /* |
742 | * Variable to establish order between CPUs while scanning. | |
743 | * Each CPU spins initially until executing is equal its number. | |
744 | */ | |
745 | static atomic_t mce_executing; | |
746 | ||
747 | /* | |
748 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
749 | */ | |
750 | static atomic_t mce_callin; | |
751 | ||
752 | /* | |
753 | * Check if a timeout waiting for other CPUs happened. | |
754 | */ | |
6c80f87e | 755 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
756 | { |
757 | /* | |
758 | * The others already did panic for some reason. | |
759 | * Bail out like in a timeout. | |
760 | * rmb() to tell the compiler that system_state | |
761 | * might have been modified by someone else. | |
762 | */ | |
763 | rmb(); | |
c7c9b392 | 764 | if (atomic_read(&mce_panicked)) |
3c079792 | 765 | wait_for_panic(); |
84c2559d | 766 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
767 | goto out; |
768 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 769 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 770 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
771 | cpu_missing = 1; |
772 | return 1; | |
773 | } | |
774 | *t -= SPINUNIT; | |
775 | out: | |
776 | touch_nmi_watchdog(); | |
777 | return 0; | |
778 | } | |
779 | ||
780 | /* | |
781 | * The Monarch's reign. The Monarch is the CPU who entered | |
782 | * the machine check handler first. It waits for the others to | |
783 | * raise the exception too and then grades them. When any | |
784 | * error is fatal panic. Only then let the others continue. | |
785 | * | |
786 | * The other CPUs entering the MCE handler will be controlled by the | |
787 | * Monarch. They are called Subjects. | |
788 | * | |
789 | * This way we prevent any potential data corruption in a unrecoverable case | |
790 | * and also makes sure always all CPU's errors are examined. | |
791 | * | |
680b6cfd | 792 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
793 | * space (not detected by any CPUs) In this case some external agent wants |
794 | * us to shut down, so panic too. | |
795 | * | |
796 | * The other CPUs might still decide to panic if the handler happens | |
797 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
798 | * state and won't corrupt anything by itself. It's ok to let the others | |
799 | * continue for a bit first. | |
800 | * | |
801 | * All the spin loops have timeouts; when a timeout happens a CPU | |
802 | * typically elects itself to be Monarch. | |
803 | */ | |
804 | static void mce_reign(void) | |
805 | { | |
806 | int cpu; | |
807 | struct mce *m = NULL; | |
808 | int global_worst = 0; | |
809 | char *msg = NULL; | |
810 | char *nmsg = NULL; | |
811 | ||
812 | /* | |
813 | * This CPU is the Monarch and the other CPUs have run | |
814 | * through their handlers. | |
815 | * Grade the severity of the errors of all the CPUs. | |
816 | */ | |
817 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
818 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
819 | mca_cfg.tolerant, | |
e3480271 | 820 | &nmsg, true); |
3c079792 AK |
821 | if (severity > global_worst) { |
822 | msg = nmsg; | |
823 | global_worst = severity; | |
824 | m = &per_cpu(mces_seen, cpu); | |
825 | } | |
826 | } | |
827 | ||
828 | /* | |
829 | * Cannot recover? Panic here then. | |
830 | * This dumps all the mces in the log buffer and stops the | |
831 | * other CPUs. | |
832 | */ | |
d203f0b8 | 833 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 834 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
835 | |
836 | /* | |
837 | * For UC somewhere we let the CPU who detects it handle it. | |
838 | * Also must let continue the others, otherwise the handling | |
839 | * CPU could deadlock on a lock. | |
840 | */ | |
841 | ||
842 | /* | |
843 | * No machine check event found. Must be some external | |
844 | * source or one CPU is hung. Panic. | |
845 | */ | |
d203f0b8 | 846 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 847 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
848 | |
849 | /* | |
850 | * Now clear all the mces_seen so that they don't reappear on | |
851 | * the next mce. | |
852 | */ | |
853 | for_each_possible_cpu(cpu) | |
854 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
855 | } | |
856 | ||
857 | static atomic_t global_nwo; | |
858 | ||
859 | /* | |
860 | * Start of Monarch synchronization. This waits until all CPUs have | |
861 | * entered the exception handler and then determines if any of them | |
862 | * saw a fatal event that requires panic. Then it executes them | |
863 | * in the entry order. | |
864 | * TBD double check parallel CPU hotunplug | |
865 | */ | |
7fb06fc9 | 866 | static int mce_start(int *no_way_out) |
3c079792 | 867 | { |
7fb06fc9 | 868 | int order; |
3c079792 | 869 | int cpus = num_online_cpus(); |
84c2559d | 870 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 871 | |
7fb06fc9 HS |
872 | if (!timeout) |
873 | return -1; | |
3c079792 | 874 | |
7fb06fc9 | 875 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf | 876 | /* |
bf92b1fe DB |
877 | * Rely on the implied barrier below, such that global_nwo |
878 | * is updated before mce_callin. | |
184e1fdf | 879 | */ |
a95436e4 | 880 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
881 | |
882 | /* | |
883 | * Wait for everyone. | |
884 | */ | |
885 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
886 | if (mce_timed_out(&timeout, |
887 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 888 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 889 | return -1; |
3c079792 AK |
890 | } |
891 | ndelay(SPINUNIT); | |
892 | } | |
893 | ||
184e1fdf HY |
894 | /* |
895 | * mce_callin should be read before global_nwo | |
896 | */ | |
897 | smp_rmb(); | |
3c079792 | 898 | |
7fb06fc9 HS |
899 | if (order == 1) { |
900 | /* | |
901 | * Monarch: Starts executing now, the others wait. | |
902 | */ | |
3c079792 | 903 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
904 | } else { |
905 | /* | |
906 | * Subject: Now start the scanning loop one by one in | |
907 | * the original callin order. | |
908 | * This way when there are any shared banks it will be | |
909 | * only seen by one CPU before cleared, avoiding duplicates. | |
910 | */ | |
911 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
912 | if (mce_timed_out(&timeout, |
913 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
914 | atomic_set(&global_nwo, 0); |
915 | return -1; | |
916 | } | |
917 | ndelay(SPINUNIT); | |
918 | } | |
3c079792 AK |
919 | } |
920 | ||
921 | /* | |
7fb06fc9 | 922 | * Cache the global no_way_out state. |
3c079792 | 923 | */ |
7fb06fc9 HS |
924 | *no_way_out = atomic_read(&global_nwo); |
925 | ||
926 | return order; | |
3c079792 AK |
927 | } |
928 | ||
929 | /* | |
930 | * Synchronize between CPUs after main scanning loop. | |
931 | * This invokes the bulk of the Monarch processing. | |
932 | */ | |
933 | static int mce_end(int order) | |
934 | { | |
935 | int ret = -1; | |
84c2559d | 936 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
937 | |
938 | if (!timeout) | |
939 | goto reset; | |
940 | if (order < 0) | |
941 | goto reset; | |
942 | ||
943 | /* | |
944 | * Allow others to run. | |
945 | */ | |
946 | atomic_inc(&mce_executing); | |
947 | ||
948 | if (order == 1) { | |
949 | /* CHECKME: Can this race with a parallel hotplug? */ | |
950 | int cpus = num_online_cpus(); | |
951 | ||
952 | /* | |
953 | * Monarch: Wait for everyone to go through their scanning | |
954 | * loops. | |
955 | */ | |
956 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
957 | if (mce_timed_out(&timeout, |
958 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
959 | goto reset; |
960 | ndelay(SPINUNIT); | |
961 | } | |
962 | ||
963 | mce_reign(); | |
964 | barrier(); | |
965 | ret = 0; | |
966 | } else { | |
967 | /* | |
968 | * Subject: Wait for Monarch to finish. | |
969 | */ | |
970 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
971 | if (mce_timed_out(&timeout, |
972 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
973 | goto reset; |
974 | ndelay(SPINUNIT); | |
975 | } | |
976 | ||
977 | /* | |
978 | * Don't reset anything. That's done by the Monarch. | |
979 | */ | |
980 | return 0; | |
981 | } | |
982 | ||
983 | /* | |
984 | * Reset all global state. | |
985 | */ | |
986 | reset: | |
987 | atomic_set(&global_nwo, 0); | |
988 | atomic_set(&mce_callin, 0); | |
989 | barrier(); | |
990 | ||
991 | /* | |
992 | * Let others run again. | |
993 | */ | |
994 | atomic_set(&mce_executing, 0); | |
995 | return ret; | |
996 | } | |
997 | ||
998 | static void mce_clear_state(unsigned long *toclear) | |
999 | { | |
1000 | int i; | |
1001 | ||
d203f0b8 | 1002 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1003 | if (test_bit(i, toclear)) |
d9d73fcc | 1004 | mce_wrmsrl(msr_ops.status(i), 0); |
3c079792 AK |
1005 | } |
1006 | } | |
1007 | ||
b2f9d678 TL |
1008 | static int do_memory_failure(struct mce *m) |
1009 | { | |
1010 | int flags = MF_ACTION_REQUIRED; | |
1011 | int ret; | |
1012 | ||
1013 | pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); | |
1014 | if (!(m->mcgstatus & MCG_STATUS_RIPV)) | |
1015 | flags |= MF_MUST_KILL; | |
1016 | ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags); | |
1017 | if (ret) | |
1018 | pr_err("Memory error not recovered"); | |
1019 | return ret; | |
1020 | } | |
1021 | ||
b79109c3 AK |
1022 | /* |
1023 | * The actual machine check handler. This only handles real | |
1024 | * exceptions when something got corrupted coming in through int 18. | |
1025 | * | |
1026 | * This is executed in NMI context not subject to normal locking rules. This | |
1027 | * implies that most kernel services cannot be safely used. Don't even | |
1028 | * think about putting a printk in there! | |
3c079792 AK |
1029 | * |
1030 | * On Intel systems this is entered on all CPUs in parallel through | |
1031 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1032 | * so be always careful when synchronizing with others. | |
1da177e4 | 1033 | */ |
e9eee03e | 1034 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1035 | { |
1462594b | 1036 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1037 | struct mce m, *final; |
1da177e4 | 1038 | int i; |
3c079792 AK |
1039 | int worst = 0; |
1040 | int severity; | |
fead35c6 | 1041 | |
3c079792 AK |
1042 | /* |
1043 | * Establish sequential order between the CPUs entering the machine | |
1044 | * check handler. | |
1045 | */ | |
fead35c6 | 1046 | int order = -1; |
bd78432c TH |
1047 | /* |
1048 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1049 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1050 | */ |
1051 | int no_way_out = 0; | |
1052 | /* | |
1053 | * If kill_it gets set, there might be a way to recover from this | |
1054 | * error. | |
1055 | */ | |
1056 | int kill_it = 0; | |
b79109c3 | 1057 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1058 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1059 | char *msg = "Unknown"; |
fead35c6 YG |
1060 | |
1061 | /* | |
1062 | * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES | |
1063 | * on Intel. | |
1064 | */ | |
1065 | int lmce = 1; | |
1da177e4 | 1066 | |
d90167a9 AR |
1067 | /* If this CPU is offline, just bail out. */ |
1068 | if (cpu_is_offline(smp_processor_id())) { | |
1069 | u64 mcgstatus; | |
1070 | ||
1071 | mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
1072 | if (mcgstatus & MCG_STATUS_RIPV) { | |
1073 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
1074 | return; | |
1075 | } | |
1076 | } | |
1077 | ||
8c84014f | 1078 | ist_enter(regs); |
95927475 | 1079 | |
c6ae41e7 | 1080 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1081 | |
1462594b | 1082 | if (!cfg->banks) |
32561696 | 1083 | goto out; |
1da177e4 | 1084 | |
b8325c5b | 1085 | mce_gather_info(&m, regs); |
b5f2fa4e | 1086 | |
89cbc767 | 1087 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1088 | *final = m; |
1089 | ||
95022b8c | 1090 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1091 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1092 | |
1da177e4 LT |
1093 | barrier(); |
1094 | ||
ed7290d0 | 1095 | /* |
a8c321fb TL |
1096 | * When no restart IP might need to kill or panic. |
1097 | * Assume the worst for now, but if we find the | |
1098 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1099 | */ |
1100 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1101 | kill_it = 1; | |
1102 | ||
3c079792 | 1103 | /* |
fead35c6 YG |
1104 | * Check if this MCE is signaled to only this logical processor, |
1105 | * on Intel only. | |
3c079792 | 1106 | */ |
fead35c6 YG |
1107 | if (m.cpuvendor == X86_VENDOR_INTEL) |
1108 | lmce = m.mcgstatus & MCG_STATUS_LMCES; | |
1109 | ||
1110 | /* | |
1111 | * Go through all banks in exclusion of the other CPUs. This way we | |
1112 | * don't report duplicated events on shared banks because the first one | |
1113 | * to see it will clear it. If this is a Local MCE, then no need to | |
1114 | * perform rendezvous. | |
1115 | */ | |
1116 | if (!lmce) | |
243d657e | 1117 | order = mce_start(&no_way_out); |
243d657e | 1118 | |
1462594b | 1119 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1120 | __clear_bit(i, toclear); |
95022b8c TL |
1121 | if (!test_bit(i, valid_banks)) |
1122 | continue; | |
cebe1820 | 1123 | if (!mce_banks[i].ctl) |
1da177e4 | 1124 | continue; |
d88203d1 TG |
1125 | |
1126 | m.misc = 0; | |
1da177e4 LT |
1127 | m.addr = 0; |
1128 | m.bank = i; | |
1da177e4 | 1129 | |
d9d73fcc | 1130 | m.status = mce_rdmsrl(msr_ops.status(i)); |
1da177e4 LT |
1131 | if ((m.status & MCI_STATUS_VAL) == 0) |
1132 | continue; | |
1133 | ||
b79109c3 | 1134 | /* |
ed7290d0 AK |
1135 | * Non uncorrected or non signaled errors are handled by |
1136 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1137 | */ |
1462594b | 1138 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1139 | !no_way_out) |
b79109c3 AK |
1140 | continue; |
1141 | ||
1142 | /* | |
1143 | * Set taint even when machine check was not enabled. | |
1144 | */ | |
373d4d09 | 1145 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1146 | |
e3480271 | 1147 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1148 | |
ed7290d0 | 1149 | /* |
e3480271 CY |
1150 | * When machine check was for corrected/deferred handler don't |
1151 | * touch, unless we're panicing. | |
ed7290d0 | 1152 | */ |
e3480271 CY |
1153 | if ((severity == MCE_KEEP_SEVERITY || |
1154 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1155 | continue; |
1156 | __set_bit(i, toclear); | |
1157 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1158 | /* |
1159 | * Machine check event was not enabled. Clear, but | |
1160 | * ignore. | |
1161 | */ | |
1162 | continue; | |
1da177e4 LT |
1163 | } |
1164 | ||
85f92694 | 1165 | mce_read_aux(&m, i); |
1da177e4 | 1166 | |
fd4cf79f CG |
1167 | /* assuming valid severity level != 0 */ |
1168 | m.severity = severity; | |
9b1beaf2 | 1169 | |
b79109c3 | 1170 | mce_log(&m); |
1da177e4 | 1171 | |
3c079792 AK |
1172 | if (severity > worst) { |
1173 | *final = m; | |
1174 | worst = severity; | |
1da177e4 | 1175 | } |
1da177e4 LT |
1176 | } |
1177 | ||
a8c321fb TL |
1178 | /* mce_clear_state will clear *final, save locally for use later */ |
1179 | m = *final; | |
1180 | ||
3c079792 AK |
1181 | if (!no_way_out) |
1182 | mce_clear_state(toclear); | |
1183 | ||
e9eee03e | 1184 | /* |
3c079792 AK |
1185 | * Do most of the synchronization with other CPUs. |
1186 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1187 | */ |
243d657e AR |
1188 | if (!lmce) { |
1189 | if (mce_end(order) < 0) | |
1190 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1191 | } else { | |
1192 | /* | |
1193 | * Local MCE skipped calling mce_reign() | |
1194 | * If we found a fatal error, we need to panic here. | |
1195 | */ | |
1196 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1197 | mce_panic("Machine check from unknown source", | |
1198 | NULL, NULL); | |
1199 | } | |
bd78432c TH |
1200 | |
1201 | /* | |
b2f9d678 TL |
1202 | * If tolerant is at an insane level we drop requests to kill |
1203 | * processes and continue even when there is no way out. | |
bd78432c | 1204 | */ |
b2f9d678 TL |
1205 | if (cfg->tolerant == 3) |
1206 | kill_it = 0; | |
1207 | else if (no_way_out) | |
1208 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
e02e68d3 | 1209 | |
3c079792 AK |
1210 | if (worst > 0) |
1211 | mce_report_event(regs); | |
5f8c1a54 | 1212 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1213 | out: |
88921be3 | 1214 | sync_core(); |
d4812e16 | 1215 | |
b2f9d678 TL |
1216 | if (worst != MCE_AR_SEVERITY && !kill_it) |
1217 | goto out_ist; | |
d4812e16 | 1218 | |
b2f9d678 TL |
1219 | /* Fault was in user mode and we need to take some action */ |
1220 | if ((m.cs & 3) == 3) { | |
1221 | ist_begin_non_atomic(regs); | |
1222 | local_irq_enable(); | |
1223 | ||
1224 | if (kill_it || do_memory_failure(&m)) | |
1225 | force_sig(SIGBUS, current); | |
1226 | local_irq_disable(); | |
1227 | ist_end_non_atomic(); | |
1228 | } else { | |
1229 | if (!fixup_exception(regs, X86_TRAP_MC)) | |
1230 | mce_panic("Failed kernel mode recovery", &m, NULL); | |
d4812e16 | 1231 | } |
b2f9d678 TL |
1232 | |
1233 | out_ist: | |
8c84014f | 1234 | ist_exit(regs); |
1da177e4 | 1235 | } |
ea149b36 | 1236 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1237 | |
cd42f4a3 TL |
1238 | #ifndef CONFIG_MEMORY_FAILURE |
1239 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1240 | { |
a8c321fb TL |
1241 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1242 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1243 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1244 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1245 | pfn); | |
cd42f4a3 TL |
1246 | |
1247 | return 0; | |
9b1beaf2 | 1248 | } |
cd42f4a3 | 1249 | #endif |
9b1beaf2 | 1250 | |
a8c321fb TL |
1251 | /* |
1252 | * Action optional processing happens here (picking up | |
1253 | * from the list of faulting pages that do_machine_check() | |
fd4cf79f | 1254 | * placed into the genpool). |
a8c321fb | 1255 | */ |
9b1beaf2 AK |
1256 | static void mce_process_work(struct work_struct *dummy) |
1257 | { | |
fd4cf79f | 1258 | mce_gen_pool_process(); |
9b1beaf2 AK |
1259 | } |
1260 | ||
15d5f839 DZ |
1261 | #ifdef CONFIG_X86_MCE_INTEL |
1262 | /*** | |
1263 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1264 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1265 | * @status: Event status information |
1266 | * | |
1267 | * This function should be called by the thermal interrupt after the | |
1268 | * event has been processed and the decision was made to log the event | |
1269 | * further. | |
1270 | * | |
1271 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1272 | * and historically has been the register value of the | |
1273 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1274 | */ | |
b5f2fa4e | 1275 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1276 | { |
1277 | struct mce m; | |
1278 | ||
b5f2fa4e | 1279 | mce_setup(&m); |
15d5f839 DZ |
1280 | m.bank = MCE_THERMAL_BANK; |
1281 | m.status = status; | |
15d5f839 DZ |
1282 | mce_log(&m); |
1283 | } | |
1284 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1285 | ||
1da177e4 | 1286 | /* |
8a336b0a TH |
1287 | * Periodic polling timer for "silent" machine check errors. If the |
1288 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1289 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1290 | */ |
3f2f0680 | 1291 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1292 | |
82f7af09 | 1293 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1294 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1295 | |
55babd8f CG |
1296 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1297 | { | |
1298 | return interval; | |
1299 | } | |
1300 | ||
3f2f0680 | 1301 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1302 | |
3f2f0680 | 1303 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1304 | { |
3f2f0680 BP |
1305 | unsigned long when = jiffies + interval; |
1306 | unsigned long flags; | |
27f6c573 | 1307 | |
3f2f0680 | 1308 | local_irq_save(flags); |
27f6c573 | 1309 | |
3f2f0680 BP |
1310 | if (timer_pending(t)) { |
1311 | if (time_before(when, t->expires)) | |
1312 | mod_timer_pinned(t, when); | |
1313 | } else { | |
1314 | t->expires = round_jiffies(when); | |
1315 | add_timer_on(t, smp_processor_id()); | |
1316 | } | |
1317 | ||
1318 | local_irq_restore(flags); | |
27f6c573 CG |
1319 | } |
1320 | ||
82f7af09 | 1321 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1322 | { |
89cbc767 | 1323 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1324 | int cpu = smp_processor_id(); |
82f7af09 | 1325 | unsigned long iv; |
52d168e2 | 1326 | |
3f2f0680 BP |
1327 | WARN_ON(cpu != data); |
1328 | ||
1329 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1330 | |
89cbc767 | 1331 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1332 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1333 | ||
1334 | if (mce_intel_cmci_poll()) { | |
1335 | iv = mce_adjust_timer(iv); | |
1336 | goto done; | |
1337 | } | |
e9eee03e | 1338 | } |
1da177e4 LT |
1339 | |
1340 | /* | |
3f2f0680 BP |
1341 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1342 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1343 | */ |
3f2f0680 | 1344 | if (mce_notify_irq()) |
958fb3c5 | 1345 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1346 | else |
82f7af09 | 1347 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1348 | |
1349 | done: | |
82f7af09 | 1350 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1351 | __restart_timer(t, iv); |
55babd8f | 1352 | } |
e02e68d3 | 1353 | |
55babd8f CG |
1354 | /* |
1355 | * Ensure that the timer is firing in @interval from now. | |
1356 | */ | |
1357 | void mce_timer_kick(unsigned long interval) | |
1358 | { | |
89cbc767 | 1359 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1360 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1361 | ||
3f2f0680 BP |
1362 | __restart_timer(t, interval); |
1363 | ||
55babd8f CG |
1364 | if (interval < iv) |
1365 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1366 | } |
1367 | ||
9aaef96f HS |
1368 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1369 | static void mce_timer_delete_all(void) | |
1370 | { | |
1371 | int cpu; | |
1372 | ||
1373 | for_each_online_cpu(cpu) | |
1374 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1375 | } | |
1376 | ||
9bd98405 AK |
1377 | static void mce_do_trigger(struct work_struct *work) |
1378 | { | |
1020bcbc | 1379 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1380 | } |
1381 | ||
1382 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1383 | ||
e02e68d3 | 1384 | /* |
9bd98405 AK |
1385 | * Notify the user(s) about new machine check events. |
1386 | * Can be called from interrupt context, but not from machine check/NMI | |
1387 | * context. | |
e02e68d3 | 1388 | */ |
9ff36ee9 | 1389 | int mce_notify_irq(void) |
e02e68d3 | 1390 | { |
8457c84d AK |
1391 | /* Not more than two messages every minute */ |
1392 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1393 | ||
1020bcbc | 1394 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1395 | /* wake processes polling /dev/mcelog */ |
1396 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1397 | |
4d899be5 | 1398 | if (mce_helper[0]) |
9bd98405 | 1399 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1400 | |
8457c84d | 1401 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1402 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1403 | |
1404 | return 1; | |
1da177e4 | 1405 | } |
e02e68d3 TH |
1406 | return 0; |
1407 | } | |
9ff36ee9 | 1408 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1409 | |
148f9bb8 | 1410 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1411 | { |
1412 | int i; | |
d203f0b8 | 1413 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1414 | |
d203f0b8 | 1415 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1416 | if (!mce_banks) |
1417 | return -ENOMEM; | |
d203f0b8 BP |
1418 | |
1419 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1420 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1421 | |
cebe1820 AK |
1422 | b->ctl = -1ULL; |
1423 | b->init = 1; | |
1424 | } | |
1425 | return 0; | |
1426 | } | |
1427 | ||
d88203d1 | 1428 | /* |
1da177e4 LT |
1429 | * Initialize Machine Checks for a CPU. |
1430 | */ | |
148f9bb8 | 1431 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1432 | { |
0d7482e3 | 1433 | unsigned b; |
e9eee03e | 1434 | u64 cap; |
1da177e4 LT |
1435 | |
1436 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1437 | |
1438 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1439 | if (!mca_cfg.banks) |
c767a54b | 1440 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1441 | |
0d7482e3 | 1442 | if (b > MAX_NR_BANKS) { |
c767a54b | 1443 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1444 | MAX_NR_BANKS, b); |
1445 | b = MAX_NR_BANKS; | |
1446 | } | |
1447 | ||
1448 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1449 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1450 | mca_cfg.banks = b; | |
1451 | ||
cebe1820 | 1452 | if (!mce_banks) { |
cffd377e | 1453 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1454 | |
cebe1820 AK |
1455 | if (err) |
1456 | return err; | |
1da177e4 | 1457 | } |
0d7482e3 | 1458 | |
94ad8474 | 1459 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1460 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1461 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1462 | |
ed7290d0 | 1463 | if (cap & MCG_SER_P) |
1462594b | 1464 | mca_cfg.ser = true; |
ed7290d0 | 1465 | |
0d7482e3 AK |
1466 | return 0; |
1467 | } | |
1468 | ||
5e09954a | 1469 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1470 | { |
84c2559d | 1471 | enum mcp_flags m_fl = 0; |
e9eee03e | 1472 | mce_banks_t all_banks; |
0d7482e3 | 1473 | u64 cap; |
0d7482e3 | 1474 | |
84c2559d BP |
1475 | if (!mca_cfg.bootlog) |
1476 | m_fl = MCP_DONTLOG; | |
1477 | ||
b79109c3 AK |
1478 | /* |
1479 | * Log the machine checks left over from the previous reset. | |
1480 | */ | |
ee031c31 | 1481 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1482 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1483 | |
375074cc | 1484 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1485 | |
0d7482e3 | 1486 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1487 | if (cap & MCG_CTL_P) |
1488 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
bb91f8c0 AG |
1489 | } |
1490 | ||
1491 | static void __mcheck_cpu_init_clear_banks(void) | |
1492 | { | |
1493 | int i; | |
1da177e4 | 1494 | |
d203f0b8 | 1495 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1496 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1497 | |
cebe1820 | 1498 | if (!b->init) |
06b7a7a5 | 1499 | continue; |
d9d73fcc YG |
1500 | wrmsrl(msr_ops.ctl(i), b->ctl); |
1501 | wrmsrl(msr_ops.status(i), 0); | |
d88203d1 | 1502 | } |
1da177e4 LT |
1503 | } |
1504 | ||
61b0fccd TL |
1505 | /* |
1506 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1507 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1508 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1509 | * whether the machine check occurred in kernel or user mode, and also | |
1510 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1511 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1512 | */ | |
1513 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1514 | { | |
1515 | if (bank != 0) | |
1516 | return; | |
1517 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1518 | return; | |
1519 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1520 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1521 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1522 | MCACOD)) != | |
1523 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1524 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1525 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1526 | return; | |
1527 | ||
1528 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1529 | m->ip = regs->ip; | |
1530 | m->cs = regs->cs; | |
1531 | } | |
1532 | ||
1da177e4 | 1533 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1534 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1535 | { |
d203f0b8 BP |
1536 | struct mca_config *cfg = &mca_cfg; |
1537 | ||
e412cd25 | 1538 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1539 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1540 | return -EOPNOTSUPP; |
1541 | } | |
1542 | ||
1da177e4 | 1543 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1544 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1545 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1546 | /* |
1547 | * disable GART TBL walk error reporting, which | |
1548 | * trips off incorrectly with the IOMMU & 3ware | |
1549 | * & Cerberus: | |
1550 | */ | |
cebe1820 | 1551 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1552 | } |
10001d91 | 1553 | if (c->x86 < 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1554 | /* |
1555 | * Lots of broken BIOS around that don't clear them | |
1556 | * by default and leave crap in there. Don't log: | |
1557 | */ | |
84c2559d | 1558 | cfg->bootlog = 0; |
e9eee03e | 1559 | } |
2e6f694f AK |
1560 | /* |
1561 | * Various K7s with broken bank 0 around. Always disable | |
1562 | * by default. | |
1563 | */ | |
c9ce8712 | 1564 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1565 | mce_banks[0].ctl = 0; |
575203b4 | 1566 | |
bf80bbd7 AG |
1567 | /* |
1568 | * overflow_recov is supported for F15h Models 00h-0fh | |
1569 | * even though we don't have a CPUID bit for it. | |
1570 | */ | |
1571 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1572 | mce_flags.overflow_recov = 1; | |
1573 | ||
c9ce8712 BP |
1574 | /* |
1575 | * Turn off MC4_MISC thresholding banks on those models since | |
1576 | * they're not supported there. | |
1577 | */ | |
1578 | if (c->x86 == 0x15 && | |
1579 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1580 | int i; | |
1581 | u64 hwcr; | |
1582 | bool need_toggle; | |
1583 | u32 msrs[] = { | |
575203b4 BP |
1584 | 0x00000413, /* MC4_MISC0 */ |
1585 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1586 | }; |
575203b4 | 1587 | |
c9ce8712 | 1588 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1589 | |
c9ce8712 BP |
1590 | /* McStatusWrEn has to be set */ |
1591 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1592 | |
c9ce8712 BP |
1593 | if (need_toggle) |
1594 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1595 | |
c9ce8712 BP |
1596 | /* Clear CntP bit safely */ |
1597 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1598 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1599 | |
c9ce8712 BP |
1600 | /* restore old settings */ |
1601 | if (need_toggle) | |
1602 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1603 | } | |
1da177e4 | 1604 | } |
e583538f | 1605 | |
06b7a7a5 AK |
1606 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1607 | /* | |
1608 | * SDM documents that on family 6 bank 0 should not be written | |
1609 | * because it aliases to another special BIOS controlled | |
1610 | * register. | |
1611 | * But it's not aliased anymore on model 0x1a+ | |
1612 | * Don't ignore bank 0 completely because there could be a | |
1613 | * valid event later, merely don't write CTL0. | |
1614 | */ | |
1615 | ||
d203f0b8 | 1616 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1617 | mce_banks[0].init = 0; |
3c079792 AK |
1618 | |
1619 | /* | |
1620 | * All newer Intel systems support MCE broadcasting. Enable | |
1621 | * synchronization with a one second timeout. | |
1622 | */ | |
1623 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1624 | cfg->monarch_timeout < 0) |
1625 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1626 | |
e412cd25 IM |
1627 | /* |
1628 | * There are also broken BIOSes on some Pentium M and | |
1629 | * earlier systems: | |
1630 | */ | |
84c2559d BP |
1631 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1632 | cfg->bootlog = 0; | |
61b0fccd TL |
1633 | |
1634 | if (c->x86 == 6 && c->x86_model == 45) | |
1635 | quirk_no_way_out = quirk_sandybridge_ifu; | |
0f68c088 TL |
1636 | /* |
1637 | * MCG_CAP.MCG_SER_P is necessary but not sufficient to know | |
1638 | * whether this processor will actually generate recoverable | |
1639 | * machine checks. Check to see if this is an E7 model Xeon. | |
1640 | * We can't do a model number check because E5 and E7 use the | |
1641 | * same model number. E5 doesn't support recovery, E7 does. | |
1642 | */ | |
1643 | if (mca_cfg.recovery || (mca_cfg.ser && | |
1644 | !strncmp(c->x86_model_id, | |
1645 | "Intel(R) Xeon(R) CPU E7-", 24))) | |
1646 | set_cpu_cap(c, X86_FEATURE_MCE_RECOVERY); | |
06b7a7a5 | 1647 | } |
84c2559d BP |
1648 | if (cfg->monarch_timeout < 0) |
1649 | cfg->monarch_timeout = 0; | |
1650 | if (cfg->bootlog != 0) | |
7af19e4a | 1651 | cfg->panic_timeout = 30; |
e412cd25 IM |
1652 | |
1653 | return 0; | |
d88203d1 | 1654 | } |
1da177e4 | 1655 | |
148f9bb8 | 1656 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1657 | { |
1658 | if (c->x86 != 5) | |
3a97fc34 HS |
1659 | return 0; |
1660 | ||
4efc0670 AK |
1661 | switch (c->x86_vendor) { |
1662 | case X86_VENDOR_INTEL: | |
c6978369 | 1663 | intel_p5_mcheck_init(c); |
3a97fc34 | 1664 | return 1; |
4efc0670 AK |
1665 | break; |
1666 | case X86_VENDOR_CENTAUR: | |
1667 | winchip_mcheck_init(c); | |
3a97fc34 | 1668 | return 1; |
4efc0670 | 1669 | break; |
dc34bdd2 BP |
1670 | default: |
1671 | return 0; | |
4efc0670 | 1672 | } |
3a97fc34 HS |
1673 | |
1674 | return 0; | |
4efc0670 AK |
1675 | } |
1676 | ||
5e09954a | 1677 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1678 | { |
1679 | switch (c->x86_vendor) { | |
1680 | case X86_VENDOR_INTEL: | |
1681 | mce_intel_feature_init(c); | |
3f2f0680 | 1682 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1683 | break; |
7559e13f AG |
1684 | |
1685 | case X86_VENDOR_AMD: { | |
14cddfd5 YG |
1686 | mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); |
1687 | mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); | |
1688 | mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); | |
d9d73fcc YG |
1689 | |
1690 | /* | |
1691 | * Install proper ops for Scalable MCA enabled processors | |
1692 | */ | |
1693 | if (mce_flags.smca) { | |
1694 | msr_ops.ctl = smca_ctl_reg; | |
1695 | msr_ops.status = smca_status_reg; | |
1696 | msr_ops.addr = smca_addr_reg; | |
1697 | msr_ops.misc = smca_misc_reg; | |
1698 | } | |
bfbe0eeb | 1699 | mce_amd_feature_init(c); |
c7f54d21 | 1700 | |
89b831ef | 1701 | break; |
7559e13f AG |
1702 | } |
1703 | ||
1da177e4 LT |
1704 | default: |
1705 | break; | |
1706 | } | |
1707 | } | |
1708 | ||
8838eb6c AR |
1709 | static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) |
1710 | { | |
1711 | switch (c->x86_vendor) { | |
1712 | case X86_VENDOR_INTEL: | |
1713 | mce_intel_feature_clear(c); | |
1714 | break; | |
1715 | default: | |
1716 | break; | |
1717 | } | |
1718 | } | |
1719 | ||
26c3c283 | 1720 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1721 | { |
4f75d841 | 1722 | unsigned long iv = check_interval * HZ; |
bc09effa | 1723 | |
7af19e4a | 1724 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1725 | return; |
1726 | ||
4f75d841 BP |
1727 | per_cpu(mce_next_interval, cpu) = iv; |
1728 | ||
82f7af09 | 1729 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1730 | add_timer_on(t, cpu); |
52d168e2 AK |
1731 | } |
1732 | ||
26c3c283 TG |
1733 | static void __mcheck_cpu_init_timer(void) |
1734 | { | |
89cbc767 | 1735 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1736 | unsigned int cpu = smp_processor_id(); |
1737 | ||
1738 | setup_timer(t, mce_timer_fn, cpu); | |
1739 | mce_start_timer(cpu, t); | |
1740 | } | |
1741 | ||
9eda8cb3 AK |
1742 | /* Handle unconfigured int18 (should never happen) */ |
1743 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1744 | { | |
c767a54b | 1745 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1746 | smp_processor_id()); |
1747 | } | |
1748 | ||
1749 | /* Call the installed machine check handler for this CPU setup. */ | |
1750 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1751 | unexpected_machine_check; | |
1752 | ||
d88203d1 | 1753 | /* |
1da177e4 | 1754 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1755 | * Must be called with preempt off: |
1da177e4 | 1756 | */ |
148f9bb8 | 1757 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1758 | { |
1462594b | 1759 | if (mca_cfg.disabled) |
4efc0670 AK |
1760 | return; |
1761 | ||
3a97fc34 HS |
1762 | if (__mcheck_cpu_ancient_init(c)) |
1763 | return; | |
4efc0670 | 1764 | |
5b4408fd | 1765 | if (!mce_available(c)) |
1da177e4 LT |
1766 | return; |
1767 | ||
5e09954a | 1768 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1769 | mca_cfg.disabled = true; |
0d7482e3 AK |
1770 | return; |
1771 | } | |
0d7482e3 | 1772 | |
648ed940 CG |
1773 | if (mce_gen_pool_init()) { |
1774 | mca_cfg.disabled = true; | |
1775 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1776 | return; | |
1777 | } | |
1778 | ||
5d727926 AK |
1779 | machine_check_vector = do_machine_check; |
1780 | ||
5e09954a BP |
1781 | __mcheck_cpu_init_generic(); |
1782 | __mcheck_cpu_init_vendor(c); | |
bb91f8c0 | 1783 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 1784 | __mcheck_cpu_init_timer(); |
1da177e4 LT |
1785 | } |
1786 | ||
8838eb6c AR |
1787 | /* |
1788 | * Called for each booted CPU to clear some machine checks opt-ins | |
1789 | */ | |
1790 | void mcheck_cpu_clear(struct cpuinfo_x86 *c) | |
1791 | { | |
1792 | if (mca_cfg.disabled) | |
1793 | return; | |
1794 | ||
1795 | if (!mce_available(c)) | |
1796 | return; | |
1797 | ||
1798 | /* | |
1799 | * Possibly to clear general settings generic to x86 | |
1800 | * __mcheck_cpu_clear_generic(c); | |
1801 | */ | |
1802 | __mcheck_cpu_clear_vendor(c); | |
1803 | ||
1da177e4 LT |
1804 | } |
1805 | ||
1806 | /* | |
93b62c3c | 1807 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1808 | */ |
1809 | ||
93b62c3c HS |
1810 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1811 | static int mce_chrdev_open_count; /* #times opened */ | |
1812 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1813 | |
93b62c3c | 1814 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1815 | { |
93b62c3c | 1816 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1817 | |
93b62c3c HS |
1818 | if (mce_chrdev_open_exclu || |
1819 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1820 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1821 | |
f528e7ba TH |
1822 | return -EBUSY; |
1823 | } | |
1824 | ||
1825 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1826 | mce_chrdev_open_exclu = 1; |
1827 | mce_chrdev_open_count++; | |
f528e7ba | 1828 | |
93b62c3c | 1829 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1830 | |
bd78432c | 1831 | return nonseekable_open(inode, file); |
f528e7ba TH |
1832 | } |
1833 | ||
93b62c3c | 1834 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1835 | { |
93b62c3c | 1836 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1837 | |
93b62c3c HS |
1838 | mce_chrdev_open_count--; |
1839 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1840 | |
93b62c3c | 1841 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1842 | |
1843 | return 0; | |
1844 | } | |
1845 | ||
d88203d1 TG |
1846 | static void collect_tscs(void *data) |
1847 | { | |
1da177e4 | 1848 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1849 | |
4ea1636b | 1850 | cpu_tsc[smp_processor_id()] = rdtsc(); |
d88203d1 | 1851 | } |
1da177e4 | 1852 | |
482908b4 HY |
1853 | static int mce_apei_read_done; |
1854 | ||
1855 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1856 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1857 | { | |
1858 | int rc; | |
1859 | u64 record_id; | |
1860 | struct mce m; | |
1861 | ||
1862 | if (usize < sizeof(struct mce)) | |
1863 | return -EINVAL; | |
1864 | ||
1865 | rc = apei_read_mce(&m, &record_id); | |
1866 | /* Error or no more MCE record */ | |
1867 | if (rc <= 0) { | |
1868 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1869 | /* |
1870 | * When ERST is disabled, mce_chrdev_read() should return | |
1871 | * "no record" instead of "no device." | |
1872 | */ | |
1873 | if (rc == -ENODEV) | |
1874 | return 0; | |
482908b4 HY |
1875 | return rc; |
1876 | } | |
1877 | rc = -EFAULT; | |
1878 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1879 | return rc; | |
1880 | /* | |
1881 | * In fact, we should have cleared the record after that has | |
1882 | * been flushed to the disk or sent to network in | |
1883 | * /sbin/mcelog, but we have no interface to support that now, | |
1884 | * so just clear it to avoid duplication. | |
1885 | */ | |
1886 | rc = apei_clear_mce(record_id); | |
1887 | if (rc) { | |
1888 | mce_apei_read_done = 1; | |
1889 | return rc; | |
1890 | } | |
1891 | *ubuf += sizeof(struct mce); | |
1892 | ||
1893 | return 0; | |
1894 | } | |
1895 | ||
93b62c3c HS |
1896 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1897 | size_t usize, loff_t *off) | |
1da177e4 | 1898 | { |
e9eee03e | 1899 | char __user *buf = ubuf; |
f0de53bb | 1900 | unsigned long *cpu_tsc; |
ef41df43 | 1901 | unsigned prev, next; |
1da177e4 LT |
1902 | int i, err; |
1903 | ||
6bca67f9 | 1904 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1905 | if (!cpu_tsc) |
1906 | return -ENOMEM; | |
1907 | ||
93b62c3c | 1908 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1909 | |
1910 | if (!mce_apei_read_done) { | |
1911 | err = __mce_read_apei(&buf, usize); | |
1912 | if (err || buf != ubuf) | |
1913 | goto out; | |
1914 | } | |
1915 | ||
9a7783d0 | 1916 | next = mce_log_get_idx_check(mcelog.next); |
1da177e4 LT |
1917 | |
1918 | /* Only supports full reads right now */ | |
482908b4 HY |
1919 | err = -EINVAL; |
1920 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1921 | goto out; | |
1da177e4 LT |
1922 | |
1923 | err = 0; | |
ef41df43 HY |
1924 | prev = 0; |
1925 | do { | |
1926 | for (i = prev; i < next; i++) { | |
1927 | unsigned long start = jiffies; | |
559faa6b | 1928 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1929 | |
559faa6b | 1930 | while (!m->finished) { |
ef41df43 | 1931 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1932 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1933 | goto timeout; |
1934 | } | |
1935 | cpu_relax(); | |
673242c1 | 1936 | } |
ef41df43 | 1937 | smp_rmb(); |
559faa6b HS |
1938 | err |= copy_to_user(buf, m, sizeof(*m)); |
1939 | buf += sizeof(*m); | |
ef41df43 HY |
1940 | timeout: |
1941 | ; | |
673242c1 | 1942 | } |
1da177e4 | 1943 | |
ef41df43 HY |
1944 | memset(mcelog.entry + prev, 0, |
1945 | (next - prev) * sizeof(struct mce)); | |
1946 | prev = next; | |
1947 | next = cmpxchg(&mcelog.next, prev, 0); | |
1948 | } while (next != prev); | |
1da177e4 | 1949 | |
b2b18660 | 1950 | synchronize_sched(); |
1da177e4 | 1951 | |
d88203d1 TG |
1952 | /* |
1953 | * Collect entries that were still getting written before the | |
1954 | * synchronize. | |
1955 | */ | |
15c8b6c1 | 1956 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1957 | |
d88203d1 | 1958 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1959 | struct mce *m = &mcelog.entry[i]; |
1960 | ||
1961 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1962 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1963 | smp_rmb(); |
559faa6b HS |
1964 | buf += sizeof(*m); |
1965 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1966 | } |
d88203d1 | 1967 | } |
482908b4 HY |
1968 | |
1969 | if (err) | |
1970 | err = -EFAULT; | |
1971 | ||
1972 | out: | |
93b62c3c | 1973 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1974 | kfree(cpu_tsc); |
e9eee03e | 1975 | |
482908b4 | 1976 | return err ? err : buf - ubuf; |
1da177e4 LT |
1977 | } |
1978 | ||
93b62c3c | 1979 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1980 | { |
93b62c3c | 1981 | poll_wait(file, &mce_chrdev_wait, wait); |
e90328b8 | 1982 | if (READ_ONCE(mcelog.next)) |
e02e68d3 | 1983 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1984 | if (!mce_apei_read_done && apei_check_mce()) |
1985 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1986 | return 0; |
1987 | } | |
1988 | ||
93b62c3c HS |
1989 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1990 | unsigned long arg) | |
1da177e4 LT |
1991 | { |
1992 | int __user *p = (int __user *)arg; | |
d88203d1 | 1993 | |
1da177e4 | 1994 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1995 | return -EPERM; |
e9eee03e | 1996 | |
1da177e4 | 1997 | switch (cmd) { |
d88203d1 | 1998 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1999 | return put_user(sizeof(struct mce), p); |
2000 | case MCE_GET_LOG_LEN: | |
d88203d1 | 2001 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
2002 | case MCE_GETCLEAR_FLAGS: { |
2003 | unsigned flags; | |
d88203d1 TG |
2004 | |
2005 | do { | |
1da177e4 | 2006 | flags = mcelog.flags; |
d88203d1 | 2007 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 2008 | |
d88203d1 | 2009 | return put_user(flags, p); |
1da177e4 LT |
2010 | } |
2011 | default: | |
d88203d1 TG |
2012 | return -ENOTTY; |
2013 | } | |
1da177e4 LT |
2014 | } |
2015 | ||
66f5ddf3 LT |
2016 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
2017 | size_t usize, loff_t *off); | |
2018 | ||
2019 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
2020 | const char __user *ubuf, | |
2021 | size_t usize, loff_t *off)) | |
2022 | { | |
2023 | mce_write = fn; | |
2024 | } | |
2025 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
2026 | ||
29c6820f PM |
2027 | static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, |
2028 | size_t usize, loff_t *off) | |
66f5ddf3 LT |
2029 | { |
2030 | if (mce_write) | |
2031 | return mce_write(filp, ubuf, usize, off); | |
2032 | else | |
2033 | return -EINVAL; | |
2034 | } | |
2035 | ||
2036 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
2037 | .open = mce_chrdev_open, |
2038 | .release = mce_chrdev_release, | |
2039 | .read = mce_chrdev_read, | |
66f5ddf3 | 2040 | .write = mce_chrdev_write, |
93b62c3c HS |
2041 | .poll = mce_chrdev_poll, |
2042 | .unlocked_ioctl = mce_chrdev_ioctl, | |
2043 | .llseek = no_llseek, | |
1da177e4 LT |
2044 | }; |
2045 | ||
93b62c3c | 2046 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
2047 | MISC_MCELOG_MINOR, |
2048 | "mcelog", | |
2049 | &mce_chrdev_ops, | |
2050 | }; | |
2051 | ||
c3d1fb56 NR |
2052 | static void __mce_disable_bank(void *arg) |
2053 | { | |
2054 | int bank = *((int *)arg); | |
89cbc767 | 2055 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
2056 | cmci_disable_bank(bank); |
2057 | } | |
2058 | ||
2059 | void mce_disable_bank(int bank) | |
2060 | { | |
2061 | if (bank >= mca_cfg.banks) { | |
2062 | pr_warn(FW_BUG | |
2063 | "Ignoring request to disable invalid MCA bank %d.\n", | |
2064 | bank); | |
2065 | return; | |
2066 | } | |
2067 | set_bit(bank, mce_banks_ce_disabled); | |
2068 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
2069 | } | |
2070 | ||
13503fa9 | 2071 | /* |
62fdac59 HS |
2072 | * mce=off Disables machine check |
2073 | * mce=no_cmci Disables CMCI | |
88d53867 | 2074 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
2075 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
2076 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
2077 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
2078 | * monarchtimeout is how long to wait for other CPUs on machine | |
2079 | * check, or 0 to not wait | |
13503fa9 HS |
2080 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
2081 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 2082 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 2083 | */ |
1da177e4 LT |
2084 | static int __init mcheck_enable(char *str) |
2085 | { | |
d203f0b8 BP |
2086 | struct mca_config *cfg = &mca_cfg; |
2087 | ||
e3346fc4 | 2088 | if (*str == 0) { |
4efc0670 | 2089 | enable_p5_mce(); |
e3346fc4 BZ |
2090 | return 1; |
2091 | } | |
4efc0670 AK |
2092 | if (*str == '=') |
2093 | str++; | |
1da177e4 | 2094 | if (!strcmp(str, "off")) |
1462594b | 2095 | cfg->disabled = true; |
62fdac59 | 2096 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2097 | cfg->cmci_disabled = true; |
88d53867 AR |
2098 | else if (!strcmp(str, "no_lmce")) |
2099 | cfg->lmce_disabled = true; | |
62fdac59 | 2100 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2101 | cfg->dont_log_ce = true; |
62fdac59 | 2102 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2103 | cfg->ignore_ce = true; |
13503fa9 | 2104 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2105 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2106 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2107 | cfg->bios_cmci_threshold = true; |
0f68c088 TL |
2108 | else if (!strcmp(str, "recovery")) |
2109 | cfg->recovery = true; | |
3c079792 | 2110 | else if (isdigit(str[0])) { |
5c31b280 | 2111 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 2112 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 2113 | } else { |
c767a54b | 2114 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2115 | return 0; |
2116 | } | |
9b41046c | 2117 | return 1; |
1da177e4 | 2118 | } |
4efc0670 | 2119 | __setup("mce", mcheck_enable); |
1da177e4 | 2120 | |
a2202aa2 | 2121 | int __init mcheck_init(void) |
b33a6363 | 2122 | { |
a2202aa2 | 2123 | mcheck_intel_therm_init(); |
eef4dfa0 | 2124 | mce_register_decode_chain(&mce_srao_nb); |
43eaa2a1 | 2125 | mcheck_vendor_init_severity(); |
a2202aa2 | 2126 | |
061120ae CG |
2127 | INIT_WORK(&mce_work, mce_process_work); |
2128 | init_irq_work(&mce_irq_work, mce_irq_work_cb); | |
2129 | ||
b33a6363 BP |
2130 | return 0; |
2131 | } | |
b33a6363 | 2132 | |
d88203d1 | 2133 | /* |
c7cece89 | 2134 | * mce_syscore: PM support |
d88203d1 | 2135 | */ |
1da177e4 | 2136 | |
973a2dd1 AK |
2137 | /* |
2138 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2139 | * them later. | |
2140 | */ | |
6e06780a | 2141 | static void mce_disable_error_reporting(void) |
973a2dd1 AK |
2142 | { |
2143 | int i; | |
2144 | ||
d203f0b8 | 2145 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2146 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2147 | |
cebe1820 | 2148 | if (b->init) |
d9d73fcc | 2149 | wrmsrl(msr_ops.ctl(i), 0); |
06b7a7a5 | 2150 | } |
6e06780a AR |
2151 | return; |
2152 | } | |
2153 | ||
2154 | static void vendor_disable_error_reporting(void) | |
2155 | { | |
2156 | /* | |
2157 | * Don't clear on Intel CPUs. Some of these MSRs are socket-wide. | |
2158 | * Disabling them for just a single offlined CPU is bad, since it will | |
2159 | * inhibit reporting for all shared resources on the socket like the | |
2160 | * last level cache (LLC), the integrated memory controller (iMC), etc. | |
2161 | */ | |
2162 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2163 | return; | |
2164 | ||
2165 | mce_disable_error_reporting(); | |
973a2dd1 AK |
2166 | } |
2167 | ||
c7cece89 | 2168 | static int mce_syscore_suspend(void) |
973a2dd1 | 2169 | { |
6e06780a AR |
2170 | vendor_disable_error_reporting(); |
2171 | return 0; | |
973a2dd1 AK |
2172 | } |
2173 | ||
c7cece89 | 2174 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2175 | { |
6e06780a | 2176 | vendor_disable_error_reporting(); |
973a2dd1 AK |
2177 | } |
2178 | ||
e9eee03e IM |
2179 | /* |
2180 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2181 | * Only one CPU is active at this time, the others get re-added later using | |
2182 | * CPU hotplug: | |
2183 | */ | |
c7cece89 | 2184 | static void mce_syscore_resume(void) |
1da177e4 | 2185 | { |
5e09954a | 2186 | __mcheck_cpu_init_generic(); |
89cbc767 | 2187 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
bb91f8c0 | 2188 | __mcheck_cpu_init_clear_banks(); |
1da177e4 LT |
2189 | } |
2190 | ||
f3c6ea1b | 2191 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2192 | .suspend = mce_syscore_suspend, |
2193 | .shutdown = mce_syscore_shutdown, | |
2194 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2195 | }; |
2196 | ||
c7cece89 | 2197 | /* |
8a25a2fd | 2198 | * mce_device: Sysfs support |
c7cece89 HS |
2199 | */ |
2200 | ||
52d168e2 AK |
2201 | static void mce_cpu_restart(void *data) |
2202 | { | |
89cbc767 | 2203 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2204 | return; |
5e09954a | 2205 | __mcheck_cpu_init_generic(); |
bb91f8c0 | 2206 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 2207 | __mcheck_cpu_init_timer(); |
52d168e2 AK |
2208 | } |
2209 | ||
1da177e4 | 2210 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2211 | static void mce_restart(void) |
2212 | { | |
9aaef96f | 2213 | mce_timer_delete_all(); |
52d168e2 | 2214 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2215 | } |
2216 | ||
9af43b54 | 2217 | /* Toggle features for corrected errors */ |
9aaef96f | 2218 | static void mce_disable_cmci(void *data) |
9af43b54 | 2219 | { |
89cbc767 | 2220 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2221 | return; |
9af43b54 HS |
2222 | cmci_clear(); |
2223 | } | |
2224 | ||
2225 | static void mce_enable_ce(void *all) | |
2226 | { | |
89cbc767 | 2227 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2228 | return; |
2229 | cmci_reenable(); | |
2230 | cmci_recheck(); | |
2231 | if (all) | |
5e09954a | 2232 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2233 | } |
2234 | ||
8a25a2fd | 2235 | static struct bus_type mce_subsys = { |
e9eee03e | 2236 | .name = "machinecheck", |
8a25a2fd | 2237 | .dev_name = "machinecheck", |
1da177e4 LT |
2238 | }; |
2239 | ||
d6126ef5 | 2240 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2241 | |
e9eee03e | 2242 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2243 | |
8a25a2fd | 2244 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2245 | { |
2246 | return container_of(attr, struct mce_bank, attr); | |
2247 | } | |
0d7482e3 | 2248 | |
8a25a2fd | 2249 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2250 | char *buf) |
2251 | { | |
cebe1820 | 2252 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2253 | } |
2254 | ||
8a25a2fd | 2255 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2256 | const char *buf, size_t size) |
0d7482e3 | 2257 | { |
9319cec8 | 2258 | u64 new; |
e9eee03e | 2259 | |
164109e3 | 2260 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2261 | return -EINVAL; |
e9eee03e | 2262 | |
cebe1820 | 2263 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2264 | mce_restart(); |
e9eee03e | 2265 | |
9319cec8 | 2266 | return size; |
0d7482e3 | 2267 | } |
a98f0dd3 | 2268 | |
e9eee03e | 2269 | static ssize_t |
8a25a2fd | 2270 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2271 | { |
1020bcbc | 2272 | strcpy(buf, mce_helper); |
a98f0dd3 | 2273 | strcat(buf, "\n"); |
1020bcbc | 2274 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2275 | } |
2276 | ||
8a25a2fd | 2277 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2278 | const char *buf, size_t siz) |
a98f0dd3 AK |
2279 | { |
2280 | char *p; | |
e9eee03e | 2281 | |
1020bcbc HS |
2282 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2283 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2284 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2285 | |
e9084ec9 | 2286 | if (p) |
e9eee03e IM |
2287 | *p = 0; |
2288 | ||
e9084ec9 | 2289 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2290 | } |
2291 | ||
8a25a2fd KS |
2292 | static ssize_t set_ignore_ce(struct device *s, |
2293 | struct device_attribute *attr, | |
9af43b54 HS |
2294 | const char *buf, size_t size) |
2295 | { | |
2296 | u64 new; | |
2297 | ||
164109e3 | 2298 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2299 | return -EINVAL; |
2300 | ||
7af19e4a | 2301 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2302 | if (new) { |
2303 | /* disable ce features */ | |
9aaef96f HS |
2304 | mce_timer_delete_all(); |
2305 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2306 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2307 | } else { |
2308 | /* enable ce features */ | |
7af19e4a | 2309 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2310 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2311 | } | |
2312 | } | |
2313 | return size; | |
2314 | } | |
2315 | ||
8a25a2fd KS |
2316 | static ssize_t set_cmci_disabled(struct device *s, |
2317 | struct device_attribute *attr, | |
9af43b54 HS |
2318 | const char *buf, size_t size) |
2319 | { | |
2320 | u64 new; | |
2321 | ||
164109e3 | 2322 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2323 | return -EINVAL; |
2324 | ||
7af19e4a | 2325 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2326 | if (new) { |
2327 | /* disable cmci */ | |
9aaef96f | 2328 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2329 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2330 | } else { |
2331 | /* enable cmci */ | |
7af19e4a | 2332 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2333 | on_each_cpu(mce_enable_ce, NULL, 1); |
2334 | } | |
2335 | } | |
2336 | return size; | |
2337 | } | |
2338 | ||
8a25a2fd KS |
2339 | static ssize_t store_int_with_restart(struct device *s, |
2340 | struct device_attribute *attr, | |
b56f642d AK |
2341 | const char *buf, size_t size) |
2342 | { | |
8a25a2fd | 2343 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2344 | mce_restart(); |
2345 | return ret; | |
2346 | } | |
2347 | ||
8a25a2fd | 2348 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2349 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2350 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2351 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2352 | |
8a25a2fd KS |
2353 | static struct dev_ext_attribute dev_attr_check_interval = { |
2354 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2355 | &check_interval |
2356 | }; | |
e9eee03e | 2357 | |
8a25a2fd | 2358 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2359 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2360 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2361 | }; |
2362 | ||
8a25a2fd | 2363 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2364 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2365 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2366 | }; |
2367 | ||
8a25a2fd KS |
2368 | static struct device_attribute *mce_device_attrs[] = { |
2369 | &dev_attr_tolerant.attr, | |
2370 | &dev_attr_check_interval.attr, | |
2371 | &dev_attr_trigger, | |
2372 | &dev_attr_monarch_timeout.attr, | |
2373 | &dev_attr_dont_log_ce.attr, | |
2374 | &dev_attr_ignore_ce.attr, | |
2375 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2376 | NULL |
2377 | }; | |
1da177e4 | 2378 | |
8a25a2fd | 2379 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2380 | |
e032d807 GKH |
2381 | static void mce_device_release(struct device *dev) |
2382 | { | |
2383 | kfree(dev); | |
2384 | } | |
2385 | ||
8a25a2fd | 2386 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2387 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2388 | { |
e032d807 | 2389 | struct device *dev; |
1da177e4 | 2390 | int err; |
b1f49f95 | 2391 | int i, j; |
92cb7612 | 2392 | |
90367556 | 2393 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2394 | return -EIO; |
2395 | ||
e032d807 GKH |
2396 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2397 | if (!dev) | |
2398 | return -ENOMEM; | |
8a25a2fd KS |
2399 | dev->id = cpu; |
2400 | dev->bus = &mce_subsys; | |
e032d807 | 2401 | dev->release = &mce_device_release; |
91c6d400 | 2402 | |
8a25a2fd | 2403 | err = device_register(dev); |
853d9b18 LK |
2404 | if (err) { |
2405 | put_device(dev); | |
d435d862 | 2406 | return err; |
853d9b18 | 2407 | } |
d435d862 | 2408 | |
8a25a2fd KS |
2409 | for (i = 0; mce_device_attrs[i]; i++) { |
2410 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2411 | if (err) |
2412 | goto error; | |
2413 | } | |
d203f0b8 | 2414 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2415 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2416 | if (err) |
2417 | goto error2; | |
2418 | } | |
8a25a2fd | 2419 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2420 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2421 | |
d435d862 | 2422 | return 0; |
0d7482e3 | 2423 | error2: |
b1f49f95 | 2424 | while (--j >= 0) |
8a25a2fd | 2425 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2426 | error: |
cb491fca | 2427 | while (--i >= 0) |
8a25a2fd | 2428 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2429 | |
8a25a2fd | 2430 | device_unregister(dev); |
d435d862 | 2431 | |
91c6d400 AK |
2432 | return err; |
2433 | } | |
2434 | ||
148f9bb8 | 2435 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2436 | { |
d6126ef5 | 2437 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2438 | int i; |
2439 | ||
8a25a2fd | 2440 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2441 | return; |
2442 | ||
8a25a2fd KS |
2443 | for (i = 0; mce_device_attrs[i]; i++) |
2444 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2445 | |
d203f0b8 | 2446 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2447 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2448 | |
8a25a2fd KS |
2449 | device_unregister(dev); |
2450 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2451 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2452 | } |
91c6d400 | 2453 | |
d6b75584 | 2454 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2455 | static void mce_disable_cpu(void *h) |
d6b75584 | 2456 | { |
88ccbedd | 2457 | unsigned long action = *(unsigned long *)h; |
d6b75584 | 2458 | |
89cbc767 | 2459 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2460 | return; |
767df1bd | 2461 | |
88ccbedd AK |
2462 | if (!(action & CPU_TASKS_FROZEN)) |
2463 | cmci_clear(); | |
11868a2d | 2464 | |
6e06780a | 2465 | vendor_disable_error_reporting(); |
d6b75584 AK |
2466 | } |
2467 | ||
148f9bb8 | 2468 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2469 | { |
88ccbedd | 2470 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2471 | int i; |
d6b75584 | 2472 | |
89cbc767 | 2473 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2474 | return; |
e9eee03e | 2475 | |
88ccbedd AK |
2476 | if (!(action & CPU_TASKS_FROZEN)) |
2477 | cmci_reenable(); | |
d203f0b8 | 2478 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2479 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2480 | |
cebe1820 | 2481 | if (b->init) |
d9d73fcc | 2482 | wrmsrl(msr_ops.ctl(i), b->ctl); |
06b7a7a5 | 2483 | } |
d6b75584 AK |
2484 | } |
2485 | ||
91c6d400 | 2486 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2487 | static int |
e9eee03e | 2488 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2489 | { |
2490 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2491 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2492 | |
1a65f970 | 2493 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2494 | case CPU_ONLINE: |
8a25a2fd | 2495 | mce_device_create(cpu); |
8735728e RW |
2496 | if (threshold_cpu_callback) |
2497 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2498 | break; |
91c6d400 | 2499 | case CPU_DEAD: |
8735728e RW |
2500 | if (threshold_cpu_callback) |
2501 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2502 | mce_device_remove(cpu); |
55babd8f | 2503 | mce_intel_hcpu_update(cpu); |
38356c1f BP |
2504 | |
2505 | /* intentionally ignoring frozen here */ | |
2506 | if (!(action & CPU_TASKS_FROZEN)) | |
2507 | cmci_rediscover(); | |
91c6d400 | 2508 | break; |
52d168e2 | 2509 | case CPU_DOWN_PREPARE: |
88ccbedd | 2510 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2511 | del_timer_sync(t); |
52d168e2 AK |
2512 | break; |
2513 | case CPU_DOWN_FAILED: | |
88ccbedd | 2514 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2515 | mce_start_timer(cpu, t); |
88ccbedd | 2516 | break; |
1a65f970 TG |
2517 | } |
2518 | ||
bae19fe0 | 2519 | return NOTIFY_OK; |
91c6d400 AK |
2520 | } |
2521 | ||
148f9bb8 | 2522 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2523 | .notifier_call = mce_cpu_callback, |
2524 | }; | |
2525 | ||
cebe1820 | 2526 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2527 | { |
2528 | int i; | |
2529 | ||
d203f0b8 | 2530 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2531 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2532 | struct device_attribute *a = &b->attr; |
e9eee03e | 2533 | |
a07e4156 | 2534 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2535 | a->attr.name = b->attrname; |
2536 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2537 | |
2538 | a->attr.mode = 0644; | |
2539 | a->show = show_bank; | |
2540 | a->store = set_bank; | |
0d7482e3 | 2541 | } |
0d7482e3 AK |
2542 | } |
2543 | ||
5e09954a | 2544 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2545 | { |
2546 | int err; | |
2547 | int i = 0; | |
2548 | ||
9c15a24b MS |
2549 | if (!mce_available(&boot_cpu_data)) { |
2550 | err = -EIO; | |
2551 | goto err_out; | |
2552 | } | |
0d7482e3 | 2553 | |
9c15a24b MS |
2554 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2555 | err = -ENOMEM; | |
2556 | goto err_out; | |
2557 | } | |
996867d0 | 2558 | |
cebe1820 | 2559 | mce_init_banks(); |
0d7482e3 | 2560 | |
8a25a2fd | 2561 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2562 | if (err) |
9c15a24b | 2563 | goto err_out_mem; |
91c6d400 | 2564 | |
82a8f131 | 2565 | cpu_notifier_register_begin(); |
91c6d400 | 2566 | for_each_online_cpu(i) { |
8a25a2fd | 2567 | err = mce_device_create(i); |
82a8f131 | 2568 | if (err) { |
27c93415 BP |
2569 | /* |
2570 | * Register notifier anyway (and do not unreg it) so | |
2571 | * that we don't leave undeleted timers, see notifier | |
2572 | * callback above. | |
2573 | */ | |
2574 | __register_hotcpu_notifier(&mce_cpu_notifier); | |
82a8f131 | 2575 | cpu_notifier_register_done(); |
9c15a24b | 2576 | goto err_device_create; |
82a8f131 | 2577 | } |
91c6d400 AK |
2578 | } |
2579 | ||
82a8f131 SB |
2580 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2581 | cpu_notifier_register_done(); | |
93b62c3c | 2582 | |
9c15a24b MS |
2583 | register_syscore_ops(&mce_syscore_ops); |
2584 | ||
93b62c3c | 2585 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2586 | err = misc_register(&mce_chrdev_device); |
2587 | if (err) | |
2588 | goto err_register; | |
2589 | ||
2590 | return 0; | |
2591 | ||
2592 | err_register: | |
2593 | unregister_syscore_ops(&mce_syscore_ops); | |
2594 | ||
9c15a24b MS |
2595 | err_device_create: |
2596 | /* | |
2597 | * We didn't keep track of which devices were created above, but | |
2598 | * even if we had, the set of online cpus might have changed. | |
2599 | * Play safe and remove for every possible cpu, since | |
2600 | * mce_device_remove() will do the right thing. | |
2601 | */ | |
2602 | for_each_possible_cpu(i) | |
2603 | mce_device_remove(i); | |
2604 | ||
2605 | err_out_mem: | |
2606 | free_cpumask_var(mce_device_initialized); | |
2607 | ||
2608 | err_out: | |
2609 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2610 | |
1da177e4 | 2611 | return err; |
1da177e4 | 2612 | } |
cef12ee5 | 2613 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2614 | |
d7c3c9a6 AK |
2615 | /* |
2616 | * Old style boot options parsing. Only for compatibility. | |
2617 | */ | |
2618 | static int __init mcheck_disable(char *str) | |
2619 | { | |
1462594b | 2620 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2621 | return 1; |
2622 | } | |
2623 | __setup("nomce", mcheck_disable); | |
a988d334 | 2624 | |
5be9ed25 HY |
2625 | #ifdef CONFIG_DEBUG_FS |
2626 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2627 | { |
5be9ed25 | 2628 | static struct dentry *dmce; |
a988d334 | 2629 | |
5be9ed25 HY |
2630 | if (!dmce) |
2631 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2632 | |
5be9ed25 HY |
2633 | return dmce; |
2634 | } | |
a988d334 | 2635 | |
bf783f9f HY |
2636 | static void mce_reset(void) |
2637 | { | |
2638 | cpu_missing = 0; | |
c7c9b392 | 2639 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2640 | atomic_set(&mce_executing, 0); |
2641 | atomic_set(&mce_callin, 0); | |
2642 | atomic_set(&global_nwo, 0); | |
2643 | } | |
a988d334 | 2644 | |
bf783f9f HY |
2645 | static int fake_panic_get(void *data, u64 *val) |
2646 | { | |
2647 | *val = fake_panic; | |
2648 | return 0; | |
a988d334 IM |
2649 | } |
2650 | ||
bf783f9f | 2651 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2652 | { |
bf783f9f HY |
2653 | mce_reset(); |
2654 | fake_panic = val; | |
2655 | return 0; | |
a988d334 | 2656 | } |
a988d334 | 2657 | |
bf783f9f HY |
2658 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2659 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2660 | |
5e09954a | 2661 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2662 | { |
bf783f9f HY |
2663 | struct dentry *dmce, *ffake_panic; |
2664 | ||
2665 | dmce = mce_get_debugfs_dir(); | |
2666 | if (!dmce) | |
2667 | return -ENOMEM; | |
2668 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2669 | &fake_panic_fops); | |
2670 | if (!ffake_panic) | |
2671 | return -ENOMEM; | |
2672 | ||
2673 | return 0; | |
d7c3c9a6 | 2674 | } |
fd4cf79f CG |
2675 | #else |
2676 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2677 | #endif |
fd4cf79f CG |
2678 | |
2679 | static int __init mcheck_late_init(void) | |
2680 | { | |
2681 | mcheck_debugfs_init(); | |
2682 | ||
2683 | /* | |
2684 | * Flush out everything that has been logged during early boot, now that | |
2685 | * everything has been initialized (workqueues, decoders, ...). | |
2686 | */ | |
2687 | mce_schedule_work(); | |
2688 | ||
2689 | return 0; | |
2690 | } | |
2691 | late_initcall(mcheck_late_init); |