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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | #include <linux/kernel.h> |
65fddcfc | 3 | #include <linux/pgtable.h> |
1da177e4 LT |
4 | |
5 | #include <linux/string.h> | |
6 | #include <linux/bitops.h> | |
7 | #include <linux/smp.h> | |
83ce4009 | 8 | #include <linux/sched.h> |
e6017571 | 9 | #include <linux/sched/clock.h> |
b041b525 | 10 | #include <linux/semaphore.h> |
1da177e4 | 11 | #include <linux/thread_info.h> |
186f4360 | 12 | #include <linux/init.h> |
8bdbd962 | 13 | #include <linux/uaccess.h> |
b041b525 | 14 | #include <linux/workqueue.h> |
ef4ae6e4 | 15 | #include <linux/delay.h> |
b041b525 | 16 | #include <linux/cpuhotplug.h> |
1da177e4 | 17 | |
cd4d09ec | 18 | #include <asm/cpufeature.h> |
1da177e4 | 19 | #include <asm/msr.h> |
73bdb73f | 20 | #include <asm/bugs.h> |
1f442d70 | 21 | #include <asm/cpu.h> |
08e237fa | 22 | #include <asm/intel-family.h> |
4167709b | 23 | #include <asm/microcode_intel.h> |
e16fd002 GA |
24 | #include <asm/hwcap2.h> |
25 | #include <asm/elf.h> | |
6650cdd9 PZI |
26 | #include <asm/cpu_device_id.h> |
27 | #include <asm/cmdline.h> | |
d7e94dbd | 28 | #include <asm/traps.h> |
923f3a2b | 29 | #include <asm/resctrl.h> |
0cd39f46 | 30 | #include <asm/numa.h> |
9223d0dc | 31 | #include <asm/thermal.h> |
1da177e4 | 32 | |
185f3b9d | 33 | #ifdef CONFIG_X86_64 |
8bdbd962 | 34 | #include <linux/topology.h> |
185f3b9d YL |
35 | #endif |
36 | ||
1da177e4 LT |
37 | #include "cpu.h" |
38 | ||
39 | #ifdef CONFIG_X86_LOCAL_APIC | |
40 | #include <asm/mpspec.h> | |
41 | #include <asm/apic.h> | |
1da177e4 LT |
42 | #endif |
43 | ||
6650cdd9 PZI |
44 | enum split_lock_detect_state { |
45 | sld_off = 0, | |
46 | sld_warn, | |
47 | sld_fatal, | |
ef4ae6e4 | 48 | sld_ratelimit, |
6650cdd9 PZI |
49 | }; |
50 | ||
51 | /* | |
ebb1064e FY |
52 | * Default to sld_off because most systems do not support split lock detection. |
53 | * sld_state_setup() will switch this to sld_warn on systems that support | |
54 | * split lock/bus lock detect, unless there is a command line override. | |
6650cdd9 | 55 | */ |
dbaba470 | 56 | static enum split_lock_detect_state sld_state __ro_after_init = sld_off; |
a6a60741 | 57 | static u64 msr_test_ctrl_cache __ro_after_init; |
6650cdd9 | 58 | |
009bce1d SC |
59 | /* |
60 | * With a name like MSR_TEST_CTL it should go without saying, but don't touch | |
61 | * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it | |
62 | * on CPUs that do not support SLD can cause fireworks, even when writing '0'. | |
63 | */ | |
64 | static bool cpu_model_supports_sld __ro_after_init; | |
65 | ||
1e03bff3 RN |
66 | /* |
67 | * Processors which have self-snooping capability can handle conflicting | |
68 | * memory type across CPUs by snooping its own cache. However, there exists | |
69 | * CPU models in which having conflicting memory types still leads to | |
70 | * unpredictable behavior, machine check errors, or hangs. Clear this | |
71 | * feature to prevent its use on machines with known erratas. | |
72 | */ | |
73 | static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) | |
74 | { | |
75 | switch (c->x86_model) { | |
76 | case INTEL_FAM6_CORE_YONAH: | |
77 | case INTEL_FAM6_CORE2_MEROM: | |
78 | case INTEL_FAM6_CORE2_MEROM_L: | |
79 | case INTEL_FAM6_CORE2_PENRYN: | |
80 | case INTEL_FAM6_CORE2_DUNNINGTON: | |
81 | case INTEL_FAM6_NEHALEM: | |
82 | case INTEL_FAM6_NEHALEM_G: | |
83 | case INTEL_FAM6_NEHALEM_EP: | |
84 | case INTEL_FAM6_NEHALEM_EX: | |
85 | case INTEL_FAM6_WESTMERE: | |
86 | case INTEL_FAM6_WESTMERE_EP: | |
87 | case INTEL_FAM6_SANDYBRIDGE: | |
88 | setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP); | |
89 | } | |
90 | } | |
91 | ||
e16fd002 GA |
92 | static bool ring3mwait_disabled __read_mostly; |
93 | ||
94 | static int __init ring3mwait_disable(char *__unused) | |
95 | { | |
96 | ring3mwait_disabled = true; | |
12441ccd | 97 | return 1; |
e16fd002 GA |
98 | } |
99 | __setup("ring3mwait=disable", ring3mwait_disable); | |
100 | ||
101 | static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) | |
102 | { | |
103 | /* | |
104 | * Ring 3 MONITOR/MWAIT feature cannot be detected without | |
105 | * cpu model and family comparison. | |
106 | */ | |
4d8bb006 | 107 | if (c->x86 != 6) |
e16fd002 | 108 | return; |
4d8bb006 PL |
109 | switch (c->x86_model) { |
110 | case INTEL_FAM6_XEON_PHI_KNL: | |
111 | case INTEL_FAM6_XEON_PHI_KNM: | |
112 | break; | |
113 | default: | |
114 | return; | |
115 | } | |
e16fd002 | 116 | |
e9ea1e7f | 117 | if (ring3mwait_disabled) |
e16fd002 | 118 | return; |
e16fd002 GA |
119 | |
120 | set_cpu_cap(c, X86_FEATURE_RING3MWAIT); | |
e9ea1e7f KH |
121 | this_cpu_or(msr_misc_features_shadow, |
122 | 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); | |
e16fd002 GA |
123 | |
124 | if (c == &boot_cpu_data) | |
125 | ELF_HWCAP2 |= HWCAP2_RING3MWAIT; | |
126 | } | |
127 | ||
a5b29663 DW |
128 | /* |
129 | * Early microcode releases for the Spectre v2 mitigation were broken. | |
130 | * Information taken from; | |
e3b3121f | 131 | * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf |
a5b29663 DW |
132 | * - https://kb.vmware.com/s/article/52345 |
133 | * - Microcode revisions observed in the wild | |
134 | * - Release note from 20180108 microcode release | |
135 | */ | |
136 | struct sku_microcode { | |
137 | u8 model; | |
138 | u8 stepping; | |
139 | u32 microcode; | |
140 | }; | |
141 | static const struct sku_microcode spectre_bad_microcodes[] = { | |
c66f78a6 PZ |
142 | { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 }, |
143 | { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 }, | |
144 | { INTEL_FAM6_KABYLAKE, 0x09, 0x80 }, | |
af239c44 PZ |
145 | { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 }, |
146 | { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 }, | |
a5b29663 DW |
147 | { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, |
148 | { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, | |
c66f78a6 | 149 | { INTEL_FAM6_BROADWELL, 0x04, 0x28 }, |
5e741407 | 150 | { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b }, |
5ebb34ed PZ |
151 | { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 }, |
152 | { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 }, | |
a5b29663 | 153 | { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, |
af239c44 | 154 | { INTEL_FAM6_HASWELL_L, 0x01, 0x21 }, |
5e741407 | 155 | { INTEL_FAM6_HASWELL_G, 0x01, 0x18 }, |
c66f78a6 | 156 | { INTEL_FAM6_HASWELL, 0x03, 0x23 }, |
a5b29663 DW |
157 | { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, |
158 | { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, | |
159 | { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, | |
a5b29663 DW |
160 | /* Observed in the wild */ |
161 | { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, | |
162 | { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, | |
163 | }; | |
164 | ||
165 | static bool bad_spectre_microcode(struct cpuinfo_x86 *c) | |
166 | { | |
167 | int i; | |
168 | ||
36268223 KRW |
169 | /* |
170 | * We know that the hypervisor lie to us on the microcode version so | |
171 | * we may as well hope that it is running the correct version. | |
172 | */ | |
173 | if (cpu_has(c, X86_FEATURE_HYPERVISOR)) | |
174 | return false; | |
175 | ||
1ab534e8 AK |
176 | if (c->x86 != 6) |
177 | return false; | |
178 | ||
a5b29663 DW |
179 | for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { |
180 | if (c->x86_model == spectre_bad_microcodes[i].model && | |
b399151c | 181 | c->x86_stepping == spectre_bad_microcodes[i].stepping) |
a5b29663 DW |
182 | return (c->microcode <= spectre_bad_microcodes[i].microcode); |
183 | } | |
184 | return false; | |
185 | } | |
186 | ||
d3287fb0 JJ |
187 | int intel_cpu_collect_info(struct ucode_cpu_info *uci) |
188 | { | |
189 | unsigned int val[2]; | |
190 | unsigned int family, model; | |
191 | struct cpu_signature csig = { 0 }; | |
192 | unsigned int eax, ebx, ecx, edx; | |
193 | ||
194 | memset(uci, 0, sizeof(*uci)); | |
195 | ||
196 | eax = 0x00000001; | |
197 | ecx = 0; | |
198 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
199 | csig.sig = eax; | |
200 | ||
201 | family = x86_family(eax); | |
202 | model = x86_model(eax); | |
203 | ||
204 | if (model >= 5 || family > 6) { | |
205 | /* get processor flags from MSR 0x17 */ | |
206 | native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
207 | csig.pf = 1 << ((val[1] >> 18) & 7); | |
208 | } | |
209 | ||
210 | csig.rev = intel_get_microcode_revision(); | |
211 | ||
212 | uci->cpu_sig = csig; | |
213 | uci->valid = 1; | |
214 | ||
215 | return 0; | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(intel_cpu_collect_info); | |
218 | ||
148f9bb8 | 219 | static void early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 220 | { |
161ec53c FY |
221 | u64 misc_enable; |
222 | ||
99fb4d34 | 223 | /* Unmask CPUID levels if masked: */ |
30a0fb94 | 224 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
0b131be8 PA |
225 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
226 | MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { | |
99fb4d34 | 227 | c->cpuid_level = cpuid_eax(0); |
d900329e | 228 | get_cpu_cap(c); |
99fb4d34 | 229 | } |
066941bd PA |
230 | } |
231 | ||
2b16a235 AK |
232 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
233 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
234 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d | 235 | |
4167709b BP |
236 | if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) |
237 | c->microcode = intel_get_microcode_revision(); | |
506ed6b5 | 238 | |
2961298e | 239 | /* Now if any of them are set, check the blacklist and clear the lot */ |
7fcae111 DW |
240 | if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || |
241 | cpu_has(c, X86_FEATURE_INTEL_STIBP) || | |
242 | cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || | |
2961298e DW |
243 | cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { |
244 | pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); | |
7fcae111 DW |
245 | setup_clear_cpu_cap(X86_FEATURE_IBRS); |
246 | setup_clear_cpu_cap(X86_FEATURE_IBPB); | |
247 | setup_clear_cpu_cap(X86_FEATURE_STIBP); | |
248 | setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); | |
7eb8956a | 249 | setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 250 | setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); |
9f65fb29 | 251 | setup_clear_cpu_cap(X86_FEATURE_SSBD); |
52817587 | 252 | setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD); |
a5b29663 DW |
253 | } |
254 | ||
7a0fc404 PA |
255 | /* |
256 | * Atom erratum AAE44/AAF40/AAG38/AAH41: | |
257 | * | |
258 | * A race condition between speculative fetches and invalidating | |
259 | * a large page. This is worked around in microcode, but we | |
260 | * need the microcode to have already been loaded... so if it is | |
261 | * not, recommend a BIOS update and disable large pages. | |
262 | */ | |
b399151c | 263 | if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && |
30963c0a | 264 | c->microcode < 0x20e) { |
1b74dde7 | 265 | pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); |
30963c0a | 266 | clear_cpu_cap(c, X86_FEATURE_PSE); |
7a0fc404 PA |
267 | } |
268 | ||
185f3b9d YL |
269 | #ifdef CONFIG_X86_64 |
270 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
271 | #else | |
272 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
273 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
274 | c->x86_cache_alignment = 128; | |
275 | #endif | |
40fb1715 | 276 | |
13c6c532 JB |
277 | /* CPUID workaround for 0F33/0F34 CPU */ |
278 | if (c->x86 == 0xF && c->x86_model == 0x3 | |
b399151c | 279 | && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) |
13c6c532 JB |
280 | c->x86_phys_bits = 36; |
281 | ||
40fb1715 VP |
282 | /* |
283 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
83ce4009 IM |
284 | * with P/T states and does not stop in deep C-states. |
285 | * | |
286 | * It is also reliable across cores and sockets. (but not across | |
287 | * cabinets - we turn it off in that case explicitly.) | |
40fb1715 VP |
288 | */ |
289 | if (c->x86_power & (1 << 8)) { | |
290 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
291 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
292 | } | |
293 | ||
c54fdbb2 FT |
294 | /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ |
295 | if (c->x86 == 6) { | |
296 | switch (c->x86_model) { | |
bba10c5c RT |
297 | case INTEL_FAM6_ATOM_SALTWELL_MID: |
298 | case INTEL_FAM6_ATOM_SALTWELL_TABLET: | |
299 | case INTEL_FAM6_ATOM_SILVERMONT_MID: | |
0cc5359d | 300 | case INTEL_FAM6_ATOM_AIRMONT_NP: |
c54fdbb2 FT |
301 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); |
302 | break; | |
303 | default: | |
304 | break; | |
305 | } | |
306 | } | |
307 | ||
75a04811 PA |
308 | /* |
309 | * There is a known erratum on Pentium III and Core Solo | |
310 | * and Core Duo CPUs. | |
311 | * " Page with PAT set to WC while associated MTRR is UC | |
312 | * may consolidate to UC " | |
313 | * Because of this erratum, it is better to stick with | |
314 | * setting WC in MTRR rather than using PAT on these CPUs. | |
315 | * | |
316 | * Enable PAT WC only on P4, Core 2 or later CPUs. | |
317 | */ | |
318 | if (c->x86 == 6 && c->x86_model < 15) | |
319 | clear_cpu_cap(c, X86_FEATURE_PAT); | |
f8561296 | 320 | |
161ec53c FY |
321 | /* |
322 | * If fast string is not enabled in IA32_MISC_ENABLE for any reason, | |
323 | * clear the fast string and enhanced fast string CPU capabilities. | |
324 | */ | |
325 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { | |
326 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
327 | if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { | |
1b74dde7 | 328 | pr_info("Disabled fast string operations\n"); |
161ec53c FY |
329 | setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); |
330 | setup_clear_cpu_cap(X86_FEATURE_ERMS); | |
331 | } | |
332 | } | |
ee1b5b16 BD |
333 | |
334 | /* | |
335 | * Intel Quark Core DevMan_001.pdf section 6.4.11 | |
336 | * "The operating system also is required to invalidate (i.e., flush) | |
337 | * the TLB when any changes are made to any of the page table entries. | |
338 | * The operating system must reload CR3 to cause the TLB to be flushed" | |
339 | * | |
c109bf95 | 340 | * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h |
163b0991 | 341 | * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE |
c109bf95 | 342 | * to be modified. |
ee1b5b16 BD |
343 | */ |
344 | if (c->x86 == 5 && c->x86_model == 9) { | |
345 | pr_info("Disabling PGE capability bit\n"); | |
346 | setup_clear_cpu_cap(X86_FEATURE_PGE); | |
347 | } | |
1f12e32f TG |
348 | |
349 | if (c->cpuid_level >= 0x00000001) { | |
350 | u32 eax, ebx, ecx, edx; | |
351 | ||
352 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); | |
353 | /* | |
354 | * If HTT (EDX[28]) is set EBX[16:23] contain the number of | |
355 | * apicids which are reserved per package. Store the resulting | |
356 | * shift value for the package management code. | |
357 | */ | |
358 | if (edx & (1U << 28)) | |
359 | c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); | |
360 | } | |
0f6ff2bc | 361 | |
1e03bff3 | 362 | check_memory_type_self_snoop_errata(c); |
1910ad56 TG |
363 | |
364 | /* | |
365 | * Get the number of SMT siblings early from the extended topology | |
366 | * leaf, if available. Otherwise try the legacy SMT detection. | |
367 | */ | |
368 | if (detect_extended_topology_early(c) < 0) | |
369 | detect_ht_early(c); | |
1da177e4 LT |
370 | } |
371 | ||
923f3a2b RC |
372 | static void bsp_init_intel(struct cpuinfo_x86 *c) |
373 | { | |
374 | resctrl_cpu_detect(c); | |
375 | } | |
376 | ||
185f3b9d | 377 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
378 | /* |
379 | * Early probe support logic for ppro memory erratum #50 | |
380 | * | |
381 | * This is called before we do cpu ident work | |
382 | */ | |
65eb6b43 | 383 | |
148f9bb8 | 384 | int ppro_with_ram_bug(void) |
1da177e4 LT |
385 | { |
386 | /* Uses data from early_cpu_detect now */ | |
387 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
388 | boot_cpu_data.x86 == 6 && | |
389 | boot_cpu_data.x86_model == 1 && | |
b399151c | 390 | boot_cpu_data.x86_stepping < 8) { |
1b74dde7 | 391 | pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); |
1da177e4 LT |
392 | return 1; |
393 | } | |
394 | return 0; | |
395 | } | |
65eb6b43 | 396 | |
148f9bb8 | 397 | static void intel_smp_check(struct cpuinfo_x86 *c) |
1f442d70 | 398 | { |
1f442d70 | 399 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 400 | if (!c->cpu_index) |
1f442d70 YL |
401 | return; |
402 | ||
403 | /* | |
404 | * Mask B, Pentium, but not Pentium MMX | |
405 | */ | |
406 | if (c->x86 == 5 && | |
b399151c | 407 | c->x86_stepping >= 1 && c->x86_stepping <= 4 && |
1f442d70 YL |
408 | c->x86_model <= 3) { |
409 | /* | |
410 | * Remember we have B step Pentia with bugs | |
411 | */ | |
412 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | |
413 | "with B stepping processors.\n"); | |
414 | } | |
1f442d70 YL |
415 | } |
416 | ||
69f2366c CB |
417 | static int forcepae; |
418 | static int __init forcepae_setup(char *__unused) | |
419 | { | |
420 | forcepae = 1; | |
421 | return 1; | |
422 | } | |
423 | __setup("forcepae", forcepae_setup); | |
424 | ||
148f9bb8 | 425 | static void intel_workarounds(struct cpuinfo_x86 *c) |
1da177e4 | 426 | { |
4052704d YL |
427 | #ifdef CONFIG_X86_F00F_BUG |
428 | /* | |
d4e1a0af | 429 | * All models of Pentium and Pentium with MMX technology CPUs |
8bdbd962 | 430 | * have the F0 0F bug, which lets nonprivileged users lock up the |
4eefbe79 | 431 | * system. Announce that the fault handler will be checking for it. |
d4e1a0af | 432 | * The Quark is also family 5, but does not have the same bug. |
4052704d | 433 | */ |
e2604b49 | 434 | clear_cpu_bug(c, X86_BUG_F00F); |
fa392794 | 435 | if (c->x86 == 5 && c->x86_model < 9) { |
4052704d YL |
436 | static int f00f_workaround_enabled; |
437 | ||
e2604b49 | 438 | set_cpu_bug(c, X86_BUG_F00F); |
4052704d | 439 | if (!f00f_workaround_enabled) { |
1b74dde7 | 440 | pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); |
4052704d YL |
441 | f00f_workaround_enabled = 1; |
442 | } | |
443 | } | |
444 | #endif | |
445 | ||
446 | /* | |
447 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
448 | * model 3 mask 3 | |
449 | */ | |
b399151c | 450 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) |
4052704d YL |
451 | clear_cpu_cap(c, X86_FEATURE_SEP); |
452 | ||
69f2366c CB |
453 | /* |
454 | * PAE CPUID issue: many Pentium M report no PAE but may have a | |
455 | * functionally usable PAE implementation. | |
456 | * Forcefully enable PAE if kernel parameter "forcepae" is present. | |
457 | */ | |
458 | if (forcepae) { | |
1b74dde7 | 459 | pr_warn("PAE forced!\n"); |
69f2366c CB |
460 | set_cpu_cap(c, X86_FEATURE_PAE); |
461 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); | |
462 | } | |
463 | ||
4052704d | 464 | /* |
f0133acc | 465 | * P4 Xeon erratum 037 workaround. |
4052704d YL |
466 | * Hardware prefetcher may cause stale data to be loaded into the cache. |
467 | */ | |
b399151c | 468 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { |
0b131be8 | 469 | if (msr_set_bit(MSR_IA32_MISC_ENABLE, |
f0133acc | 470 | MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { |
c0a639ad | 471 | pr_info("CPU: C0 stepping P4 Xeon detected.\n"); |
f0133acc | 472 | pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); |
1da177e4 LT |
473 | } |
474 | } | |
1da177e4 | 475 | |
4052704d YL |
476 | /* |
477 | * See if we have a good local APIC by checking for buggy Pentia, | |
478 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
479 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
480 | * Specification Update"). | |
481 | */ | |
93984fbd | 482 | if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && |
b399151c | 483 | (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) |
9b13a93d | 484 | set_cpu_bug(c, X86_BUG_11AP); |
185f3b9d | 485 | |
185f3b9d | 486 | |
4052704d | 487 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 488 | /* |
4052704d | 489 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 490 | */ |
4052704d YL |
491 | switch (c->x86) { |
492 | case 4: /* 486: untested */ | |
493 | break; | |
494 | case 5: /* Old Pentia: untested */ | |
495 | break; | |
496 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
497 | movsl_mask.mask = 7; | |
498 | break; | |
499 | case 15: /* P4 is OK down to 8-byte alignment */ | |
500 | movsl_mask.mask = 7; | |
501 | break; | |
502 | } | |
185f3b9d | 503 | #endif |
4052704d | 504 | |
1f442d70 | 505 | intel_smp_check(c); |
4052704d YL |
506 | } |
507 | #else | |
148f9bb8 | 508 | static void intel_workarounds(struct cpuinfo_x86 *c) |
4052704d YL |
509 | { |
510 | } | |
185f3b9d YL |
511 | #endif |
512 | ||
148f9bb8 | 513 | static void srat_detect_node(struct cpuinfo_x86 *c) |
185f3b9d | 514 | { |
645a7919 | 515 | #ifdef CONFIG_NUMA |
185f3b9d YL |
516 | unsigned node; |
517 | int cpu = smp_processor_id(); | |
185f3b9d YL |
518 | |
519 | /* Don't do the funky fallback heuristics the AMD version employs | |
520 | for now. */ | |
bbc9e2f4 | 521 | node = numa_cpu_node(cpu); |
50f2d7f6 | 522 | if (node == NUMA_NO_NODE || !node_online(node)) { |
d9c2d5ac YL |
523 | /* reuse the value from init_cpu_to_node() */ |
524 | node = cpu_to_node(cpu); | |
525 | } | |
185f3b9d | 526 | numa_set_node(cpu, node); |
185f3b9d YL |
527 | #endif |
528 | } | |
529 | ||
cb06d8e3 KS |
530 | #define MSR_IA32_TME_ACTIVATE 0x982 |
531 | ||
532 | /* Helpers to access TME_ACTIVATE MSR */ | |
533 | #define TME_ACTIVATE_LOCKED(x) (x & 0x1) | |
534 | #define TME_ACTIVATE_ENABLED(x) (x & 0x2) | |
535 | ||
536 | #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ | |
537 | #define TME_ACTIVATE_POLICY_AES_XTS_128 0 | |
538 | ||
539 | #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ | |
540 | ||
541 | #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ | |
542 | #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 | |
543 | ||
544 | /* Values for mktme_status (SW only construct) */ | |
545 | #define MKTME_ENABLED 0 | |
546 | #define MKTME_DISABLED 1 | |
547 | #define MKTME_UNINITIALIZED 2 | |
548 | static int mktme_status = MKTME_UNINITIALIZED; | |
549 | ||
550 | static void detect_tme(struct cpuinfo_x86 *c) | |
551 | { | |
552 | u64 tme_activate, tme_policy, tme_crypto_algs; | |
553 | int keyid_bits = 0, nr_keyids = 0; | |
554 | static u64 tme_activate_cpu0 = 0; | |
555 | ||
556 | rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); | |
557 | ||
558 | if (mktme_status != MKTME_UNINITIALIZED) { | |
559 | if (tme_activate != tme_activate_cpu0) { | |
560 | /* Broken BIOS? */ | |
eaeb8e76 | 561 | pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); |
cb06d8e3 KS |
562 | pr_err_once("x86/tme: MKTME is not usable\n"); |
563 | mktme_status = MKTME_DISABLED; | |
564 | ||
565 | /* Proceed. We may need to exclude bits from x86_phys_bits. */ | |
566 | } | |
567 | } else { | |
568 | tme_activate_cpu0 = tme_activate; | |
569 | } | |
570 | ||
571 | if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { | |
572 | pr_info_once("x86/tme: not enabled by BIOS\n"); | |
573 | mktme_status = MKTME_DISABLED; | |
574 | return; | |
575 | } | |
576 | ||
577 | if (mktme_status != MKTME_UNINITIALIZED) | |
578 | goto detect_keyid_bits; | |
579 | ||
580 | pr_info("x86/tme: enabled by BIOS\n"); | |
581 | ||
582 | tme_policy = TME_ACTIVATE_POLICY(tme_activate); | |
583 | if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) | |
584 | pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); | |
585 | ||
586 | tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); | |
587 | if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { | |
588 | pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", | |
589 | tme_crypto_algs); | |
590 | mktme_status = MKTME_DISABLED; | |
591 | } | |
592 | detect_keyid_bits: | |
593 | keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); | |
594 | nr_keyids = (1UL << keyid_bits) - 1; | |
595 | if (nr_keyids) { | |
596 | pr_info_once("x86/mktme: enabled by BIOS\n"); | |
597 | pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); | |
598 | } else { | |
599 | pr_info_once("x86/mktme: disabled by BIOS\n"); | |
600 | } | |
601 | ||
602 | if (mktme_status == MKTME_UNINITIALIZED) { | |
603 | /* MKTME is usable */ | |
604 | mktme_status = MKTME_ENABLED; | |
605 | } | |
606 | ||
607 | /* | |
547edaca KS |
608 | * KeyID bits effectively lower the number of physical address |
609 | * bits. Update cpuinfo_x86::x86_phys_bits accordingly. | |
cb06d8e3 KS |
610 | */ |
611 | c->x86_phys_bits -= keyid_bits; | |
612 | } | |
613 | ||
90218ac7 KH |
614 | static void init_cpuid_fault(struct cpuinfo_x86 *c) |
615 | { | |
616 | u64 msr; | |
617 | ||
618 | if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { | |
619 | if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) | |
620 | set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); | |
621 | } | |
622 | } | |
623 | ||
624 | static void init_intel_misc_features(struct cpuinfo_x86 *c) | |
625 | { | |
626 | u64 msr; | |
627 | ||
628 | if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) | |
629 | return; | |
630 | ||
e9ea1e7f KH |
631 | /* Clear all MISC features */ |
632 | this_cpu_write(msr_misc_features_shadow, 0); | |
633 | ||
634 | /* Check features and update capabilities and shadow control bits */ | |
90218ac7 KH |
635 | init_cpuid_fault(c); |
636 | probe_xeon_phi_r3mwait(c); | |
e9ea1e7f KH |
637 | |
638 | msr = this_cpu_read(msr_misc_features_shadow); | |
639 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); | |
90218ac7 KH |
640 | } |
641 | ||
6650cdd9 | 642 | static void split_lock_init(void); |
ebb1064e | 643 | static void bus_lock_init(void); |
6650cdd9 | 644 | |
148f9bb8 | 645 | static void init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 646 | { |
2b16a235 AK |
647 | early_init_intel(c); |
648 | ||
4052704d | 649 | intel_workarounds(c); |
1da177e4 | 650 | |
345077cd SS |
651 | /* |
652 | * Detect the extended topology information if available. This | |
653 | * will reinitialise the initial_apicid which will be used | |
654 | * in init_intel_cacheinfo() | |
655 | */ | |
656 | detect_extended_topology(c); | |
657 | ||
2a226155 PZ |
658 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
659 | /* | |
660 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
661 | * detection. | |
662 | */ | |
9305bd6c | 663 | detect_num_cpu_cores(c); |
2a226155 PZ |
664 | #ifdef CONFIG_X86_32 |
665 | detect_ht(c); | |
666 | #endif | |
667 | } | |
668 | ||
807e9bc8 | 669 | init_intel_cacheinfo(c); |
aece118e | 670 | |
65eb6b43 | 671 | if (c->cpuid_level > 9) { |
0080e667 VP |
672 | unsigned eax = cpuid_eax(10); |
673 | /* Check for version and the number of counters */ | |
674 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 675 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 676 | } |
1da177e4 | 677 | |
054efb64 | 678 | if (cpu_has(c, X86_FEATURE_XMM2)) |
4052704d | 679 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
362f924b BP |
680 | |
681 | if (boot_cpu_has(X86_FEATURE_DS)) { | |
807e9bc8 DW |
682 | unsigned int l1, l2; |
683 | ||
4052704d | 684 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); |
3f2adf00 | 685 | if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) |
4052704d | 686 | set_cpu_cap(c, X86_FEATURE_BTS); |
3f2adf00 | 687 | if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) |
4052704d | 688 | set_cpu_cap(c, X86_FEATURE_PEBS); |
4052704d | 689 | } |
1da177e4 | 690 | |
906bf7fd | 691 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && |
40e2d7f9 | 692 | (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) |
9b13a93d | 693 | set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); |
e736ad54 | 694 | |
08e237fa PZ |
695 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && |
696 | ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) | |
697 | set_cpu_bug(c, X86_BUG_MONITOR); | |
698 | ||
4052704d YL |
699 | #ifdef CONFIG_X86_64 |
700 | if (c->x86 == 15) | |
701 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
702 | if (c->x86 == 6) | |
703 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
704 | #else | |
65eb6b43 PC |
705 | /* |
706 | * Names for the Pentium II/Celeron processors | |
707 | * detectable only by also checking the cache size. | |
708 | * Dixon is NOT a Celeron. | |
709 | */ | |
1da177e4 | 710 | if (c->x86 == 6) { |
807e9bc8 | 711 | unsigned int l2 = c->x86_cache_size; |
4052704d YL |
712 | char *p = NULL; |
713 | ||
1da177e4 LT |
714 | switch (c->x86_model) { |
715 | case 5: | |
865be7a8 OZ |
716 | if (l2 == 0) |
717 | p = "Celeron (Covington)"; | |
718 | else if (l2 == 256) | |
719 | p = "Mobile Pentium II (Dixon)"; | |
1da177e4 | 720 | break; |
65eb6b43 | 721 | |
1da177e4 LT |
722 | case 6: |
723 | if (l2 == 128) | |
724 | p = "Celeron (Mendocino)"; | |
b399151c | 725 | else if (c->x86_stepping == 0 || c->x86_stepping == 5) |
1da177e4 LT |
726 | p = "Celeron-A"; |
727 | break; | |
65eb6b43 | 728 | |
1da177e4 LT |
729 | case 8: |
730 | if (l2 == 128) | |
731 | p = "Celeron (Coppermine)"; | |
732 | break; | |
733 | } | |
1da177e4 | 734 | |
4052704d YL |
735 | if (p) |
736 | strcpy(c->x86_model_id, p); | |
1da177e4 | 737 | } |
1da177e4 | 738 | |
185f3b9d YL |
739 | if (c->x86 == 15) |
740 | set_cpu_cap(c, X86_FEATURE_P4); | |
741 | if (c->x86 == 6) | |
742 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 743 | #endif |
185f3b9d | 744 | |
185f3b9d | 745 | /* Work around errata */ |
2759c328 | 746 | srat_detect_node(c); |
e38e05a8 | 747 | |
1db2a6e1 SC |
748 | init_ia32_feat_ctl(c); |
749 | ||
cb06d8e3 KS |
750 | if (cpu_has(c, X86_FEATURE_TME)) |
751 | detect_tme(c); | |
752 | ||
90218ac7 | 753 | init_intel_misc_features(c); |
95c5824f | 754 | |
6650cdd9 | 755 | split_lock_init(); |
ebb1064e | 756 | bus_lock_init(); |
9223d0dc BP |
757 | |
758 | intel_init_thermal(c); | |
42ed458a | 759 | } |
1da177e4 | 760 | |
185f3b9d | 761 | #ifdef CONFIG_X86_32 |
148f9bb8 | 762 | static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 763 | { |
65eb6b43 PC |
764 | /* |
765 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
766 | * One has 256kb of cache, the other 512. We have no way |
767 | * to determine which, so we use a boottime override | |
768 | * for the 512kb model, and assume 256 otherwise. | |
769 | */ | |
770 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
771 | size = 256; | |
aece118e BD |
772 | |
773 | /* | |
774 | * Intel Quark SoC X1000 contains a 4-way set associative | |
775 | * 16K cache with a 16 byte cache line and 256 lines per tag | |
776 | */ | |
777 | if ((c->x86 == 5) && (c->x86_model == 9)) | |
778 | size = 16; | |
1da177e4 LT |
779 | return size; |
780 | } | |
185f3b9d | 781 | #endif |
1da177e4 | 782 | |
e0ba94f1 AS |
783 | #define TLB_INST_4K 0x01 |
784 | #define TLB_INST_4M 0x02 | |
785 | #define TLB_INST_2M_4M 0x03 | |
786 | ||
787 | #define TLB_INST_ALL 0x05 | |
788 | #define TLB_INST_1G 0x06 | |
789 | ||
790 | #define TLB_DATA_4K 0x11 | |
791 | #define TLB_DATA_4M 0x12 | |
792 | #define TLB_DATA_2M_4M 0x13 | |
793 | #define TLB_DATA_4K_4M 0x14 | |
794 | ||
795 | #define TLB_DATA_1G 0x16 | |
796 | ||
797 | #define TLB_DATA0_4K 0x21 | |
798 | #define TLB_DATA0_4M 0x22 | |
799 | #define TLB_DATA0_2M_4M 0x23 | |
800 | ||
801 | #define STLB_4K 0x41 | |
dd360393 | 802 | #define STLB_4K_2M 0x42 |
e0ba94f1 | 803 | |
148f9bb8 | 804 | static const struct _tlb_table intel_tlb_table[] = { |
e0ba94f1 AS |
805 | { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, |
806 | { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, | |
807 | { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
808 | { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
809 | { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
810 | { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, | |
77df779d | 811 | { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" }, |
e0ba94f1 AS |
812 | { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, |
813 | { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
814 | { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
815 | { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
816 | { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, | |
817 | { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, | |
818 | { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, | |
819 | { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, | |
820 | { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
821 | { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
822 | { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
dd360393 KS |
823 | { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, |
824 | { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, | |
b837913f | 825 | { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, |
826 | { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, | |
827 | { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, | |
dd360393 | 828 | { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, |
e0ba94f1 AS |
829 | { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, |
830 | { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, | |
831 | { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, | |
832 | { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
833 | { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, | |
a927792c YG |
834 | { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, |
835 | { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, | |
e0ba94f1 AS |
836 | { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, |
837 | { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, | |
dd360393 | 838 | { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, |
77df779d | 839 | { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" }, |
e0ba94f1 AS |
840 | { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, |
841 | { 0x00, 0, 0 } | |
842 | }; | |
843 | ||
148f9bb8 | 844 | static void intel_tlb_lookup(const unsigned char desc) |
e0ba94f1 AS |
845 | { |
846 | unsigned char k; | |
847 | if (desc == 0) | |
848 | return; | |
849 | ||
850 | /* look up this descriptor in the table */ | |
77df779d SH |
851 | for (k = 0; intel_tlb_table[k].descriptor != desc && |
852 | intel_tlb_table[k].descriptor != 0; k++) | |
e0ba94f1 AS |
853 | ; |
854 | ||
855 | if (intel_tlb_table[k].tlb_type == 0) | |
856 | return; | |
857 | ||
858 | switch (intel_tlb_table[k].tlb_type) { | |
859 | case STLB_4K: | |
860 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
861 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
862 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
863 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
864 | break; | |
dd360393 KS |
865 | case STLB_4K_2M: |
866 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
867 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
868 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
869 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
870 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
871 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
872 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
873 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
874 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
875 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
876 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
877 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
878 | break; | |
e0ba94f1 AS |
879 | case TLB_INST_ALL: |
880 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
881 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
882 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
883 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
884 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
885 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
886 | break; | |
887 | case TLB_INST_4K: | |
888 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
889 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
890 | break; | |
891 | case TLB_INST_4M: | |
892 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
893 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
894 | break; | |
895 | case TLB_INST_2M_4M: | |
896 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
897 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
898 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
899 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
900 | break; | |
901 | case TLB_DATA_4K: | |
902 | case TLB_DATA0_4K: | |
903 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
904 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
905 | break; | |
906 | case TLB_DATA_4M: | |
907 | case TLB_DATA0_4M: | |
908 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
909 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
910 | break; | |
911 | case TLB_DATA_2M_4M: | |
912 | case TLB_DATA0_2M_4M: | |
913 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
914 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
915 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
916 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
917 | break; | |
918 | case TLB_DATA_4K_4M: | |
919 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
920 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
921 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
922 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
923 | break; | |
dd360393 KS |
924 | case TLB_DATA_1G: |
925 | if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) | |
926 | tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; | |
e0ba94f1 AS |
927 | break; |
928 | } | |
929 | } | |
930 | ||
148f9bb8 | 931 | static void intel_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
932 | { |
933 | int i, j, n; | |
934 | unsigned int regs[4]; | |
935 | unsigned char *desc = (unsigned char *)regs; | |
5b556332 BP |
936 | |
937 | if (c->cpuid_level < 2) | |
938 | return; | |
939 | ||
e0ba94f1 AS |
940 | /* Number of times to iterate */ |
941 | n = cpuid_eax(2) & 0xFF; | |
942 | ||
943 | for (i = 0 ; i < n ; i++) { | |
944 | cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); | |
945 | ||
946 | /* If bit 31 is set, this is an unknown format */ | |
947 | for (j = 0 ; j < 3 ; j++) | |
948 | if (regs[j] & (1 << 31)) | |
949 | regs[j] = 0; | |
950 | ||
951 | /* Byte 0 is level count, not a descriptor */ | |
952 | for (j = 1 ; j < 16 ; j++) | |
953 | intel_tlb_lookup(desc[j]); | |
954 | } | |
955 | } | |
956 | ||
148f9bb8 | 957 | static const struct cpu_dev intel_cpu_dev = { |
1da177e4 | 958 | .c_vendor = "Intel", |
65eb6b43 | 959 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 960 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
961 | .legacy_models = { |
962 | { .family = 4, .model_names = | |
65eb6b43 PC |
963 | { |
964 | [0] = "486 DX-25/33", | |
965 | [1] = "486 DX-50", | |
966 | [2] = "486 SX", | |
967 | [3] = "486 DX/2", | |
968 | [4] = "486 SL", | |
969 | [5] = "486 SX/2", | |
970 | [7] = "486 DX/2-WB", | |
971 | [8] = "486 DX/4", | |
1da177e4 LT |
972 | [9] = "486 DX/4-WB" |
973 | } | |
974 | }, | |
09dc68d9 | 975 | { .family = 5, .model_names = |
65eb6b43 PC |
976 | { |
977 | [0] = "Pentium 60/66 A-step", | |
978 | [1] = "Pentium 60/66", | |
1da177e4 | 979 | [2] = "Pentium 75 - 200", |
65eb6b43 | 980 | [3] = "OverDrive PODP5V83", |
1da177e4 | 981 | [4] = "Pentium MMX", |
65eb6b43 | 982 | [7] = "Mobile Pentium 75 - 200", |
aece118e BD |
983 | [8] = "Mobile Pentium MMX", |
984 | [9] = "Quark SoC X1000", | |
1da177e4 LT |
985 | } |
986 | }, | |
09dc68d9 | 987 | { .family = 6, .model_names = |
65eb6b43 | 988 | { |
1da177e4 | 989 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
990 | [1] = "Pentium Pro", |
991 | [3] = "Pentium II (Klamath)", | |
992 | [4] = "Pentium II (Deschutes)", | |
993 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 994 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
995 | [7] = "Pentium III (Katmai)", |
996 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
997 | [10] = "Pentium III (Cascades)", |
998 | [11] = "Pentium III (Tualatin)", | |
999 | } | |
1000 | }, | |
09dc68d9 | 1001 | { .family = 15, .model_names = |
1da177e4 LT |
1002 | { |
1003 | [0] = "Pentium 4 (Unknown)", | |
1004 | [1] = "Pentium 4 (Willamette)", | |
1005 | [2] = "Pentium 4 (Northwood)", | |
1006 | [4] = "Pentium 4 (Foster)", | |
1007 | [5] = "Pentium 4 (Foster)", | |
1008 | } | |
1009 | }, | |
1010 | }, | |
09dc68d9 | 1011 | .legacy_cache_size = intel_size_cache, |
185f3b9d | 1012 | #endif |
e0ba94f1 | 1013 | .c_detect_tlb = intel_detect_tlb, |
03ae5768 | 1014 | .c_early_init = early_init_intel, |
923f3a2b | 1015 | .c_bsp_init = bsp_init_intel, |
1da177e4 | 1016 | .c_init = init_intel, |
10a434fc | 1017 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
1018 | }; |
1019 | ||
10a434fc | 1020 | cpu_dev_register(intel_cpu_dev); |
6650cdd9 PZI |
1021 | |
1022 | #undef pr_fmt | |
1023 | #define pr_fmt(fmt) "x86/split lock detection: " fmt | |
1024 | ||
1025 | static const struct { | |
1026 | const char *option; | |
1027 | enum split_lock_detect_state state; | |
1028 | } sld_options[] __initconst = { | |
1029 | { "off", sld_off }, | |
1030 | { "warn", sld_warn }, | |
1031 | { "fatal", sld_fatal }, | |
ef4ae6e4 | 1032 | { "ratelimit:", sld_ratelimit }, |
6650cdd9 PZI |
1033 | }; |
1034 | ||
ef4ae6e4 FY |
1035 | static struct ratelimit_state bld_ratelimit; |
1036 | ||
b041b525 TL |
1037 | static DEFINE_SEMAPHORE(buslock_sem); |
1038 | ||
6650cdd9 PZI |
1039 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
1040 | { | |
ef4ae6e4 FY |
1041 | int len = strlen(opt), ratelimit; |
1042 | ||
1043 | if (strncmp(arg, opt, len)) | |
1044 | return false; | |
1045 | ||
1046 | /* | |
1047 | * Min ratelimit is 1 bus lock/sec. | |
1048 | * Max ratelimit is 1000 bus locks/sec. | |
1049 | */ | |
1050 | if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 && | |
1051 | ratelimit > 0 && ratelimit <= 1000) { | |
1052 | ratelimit_state_init(&bld_ratelimit, HZ, ratelimit); | |
1053 | ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE); | |
1054 | return true; | |
1055 | } | |
6650cdd9 | 1056 | |
ef4ae6e4 | 1057 | return len == arglen; |
6650cdd9 PZI |
1058 | } |
1059 | ||
dbaba470 XL |
1060 | static bool split_lock_verify_msr(bool on) |
1061 | { | |
1062 | u64 ctrl, tmp; | |
1063 | ||
1064 | if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl)) | |
1065 | return false; | |
1066 | if (on) | |
1067 | ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; | |
1068 | else | |
1069 | ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT; | |
1070 | if (wrmsrl_safe(MSR_TEST_CTRL, ctrl)) | |
1071 | return false; | |
1072 | rdmsrl(MSR_TEST_CTRL, tmp); | |
1073 | return ctrl == tmp; | |
1074 | } | |
1075 | ||
ebb1064e | 1076 | static void __init sld_state_setup(void) |
6650cdd9 | 1077 | { |
dbaba470 | 1078 | enum split_lock_detect_state state = sld_warn; |
6650cdd9 PZI |
1079 | char arg[20]; |
1080 | int i, ret; | |
1081 | ||
ebb1064e FY |
1082 | if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) && |
1083 | !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) | |
dbaba470 | 1084 | return; |
6650cdd9 PZI |
1085 | |
1086 | ret = cmdline_find_option(boot_command_line, "split_lock_detect", | |
1087 | arg, sizeof(arg)); | |
1088 | if (ret >= 0) { | |
1089 | for (i = 0; i < ARRAY_SIZE(sld_options); i++) { | |
1090 | if (match_option(arg, ret, sld_options[i].option)) { | |
dbaba470 | 1091 | state = sld_options[i].state; |
6650cdd9 PZI |
1092 | break; |
1093 | } | |
1094 | } | |
1095 | } | |
ebb1064e FY |
1096 | sld_state = state; |
1097 | } | |
6650cdd9 | 1098 | |
ebb1064e FY |
1099 | static void __init __split_lock_setup(void) |
1100 | { | |
1101 | if (!split_lock_verify_msr(false)) { | |
1102 | pr_info("MSR access failed: Disabled\n"); | |
dbaba470 | 1103 | return; |
6650cdd9 | 1104 | } |
dbaba470 | 1105 | |
a6a60741 XL |
1106 | rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); |
1107 | ||
dbaba470 XL |
1108 | if (!split_lock_verify_msr(true)) { |
1109 | pr_info("MSR access failed: Disabled\n"); | |
1110 | return; | |
1111 | } | |
1112 | ||
ebb1064e FY |
1113 | /* Restore the MSR to its cached value. */ |
1114 | wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache); | |
1115 | ||
dbaba470 | 1116 | setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); |
6650cdd9 PZI |
1117 | } |
1118 | ||
1119 | /* | |
dbaba470 XL |
1120 | * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking |
1121 | * is not implemented as one thread could undo the setting of the other | |
1122 | * thread immediately after dropping the lock anyway. | |
6650cdd9 | 1123 | */ |
dbaba470 | 1124 | static void sld_update_msr(bool on) |
6650cdd9 | 1125 | { |
a6a60741 | 1126 | u64 test_ctrl_val = msr_test_ctrl_cache; |
6650cdd9 PZI |
1127 | |
1128 | if (on) | |
1129 | test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT; | |
6650cdd9 | 1130 | |
dbaba470 | 1131 | wrmsrl(MSR_TEST_CTRL, test_ctrl_val); |
6650cdd9 PZI |
1132 | } |
1133 | ||
1134 | static void split_lock_init(void) | |
1135 | { | |
ef4ae6e4 FY |
1136 | /* |
1137 | * #DB for bus lock handles ratelimit and #AC for split lock is | |
1138 | * disabled. | |
1139 | */ | |
1140 | if (sld_state == sld_ratelimit) { | |
1141 | split_lock_verify_msr(false); | |
1142 | return; | |
1143 | } | |
1144 | ||
009bce1d SC |
1145 | if (cpu_model_supports_sld) |
1146 | split_lock_verify_msr(sld_state != sld_off); | |
6650cdd9 PZI |
1147 | } |
1148 | ||
b041b525 TL |
1149 | static void __split_lock_reenable(struct work_struct *work) |
1150 | { | |
1151 | sld_update_msr(true); | |
1152 | up(&buslock_sem); | |
1153 | } | |
1154 | ||
1155 | /* | |
1156 | * If a CPU goes offline with pending delayed work to re-enable split lock | |
1157 | * detection then the delayed work will be executed on some other CPU. That | |
1158 | * handles releasing the buslock_sem, but because it executes on a | |
1159 | * different CPU probably won't re-enable split lock detection. This is a | |
1160 | * problem on HT systems since the sibling CPU on the same core may then be | |
1161 | * left running with split lock detection disabled. | |
1162 | * | |
1163 | * Unconditionally re-enable detection here. | |
1164 | */ | |
1165 | static int splitlock_cpu_offline(unsigned int cpu) | |
1166 | { | |
1167 | sld_update_msr(true); | |
1168 | ||
1169 | return 0; | |
1170 | } | |
1171 | ||
1172 | static DECLARE_DELAYED_WORK(split_lock_reenable, __split_lock_reenable); | |
1173 | ||
d7e94dbd | 1174 | static void split_lock_warn(unsigned long ip) |
6650cdd9 | 1175 | { |
b041b525 | 1176 | int cpu; |
6650cdd9 | 1177 | |
b041b525 TL |
1178 | if (!current->reported_split_lock) |
1179 | pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n", | |
1180 | current->comm, current->pid, ip); | |
1181 | current->reported_split_lock = 1; | |
1182 | ||
1183 | /* misery factor #1, sleep 10ms before trying to execute split lock */ | |
1184 | if (msleep_interruptible(10) > 0) | |
1185 | return; | |
1186 | /* Misery factor #2, only allow one buslocked disabled core at a time */ | |
1187 | if (down_interruptible(&buslock_sem) == -EINTR) | |
1188 | return; | |
1189 | cpu = get_cpu(); | |
1190 | schedule_delayed_work_on(cpu, &split_lock_reenable, 2); | |
1191 | ||
1192 | /* Disable split lock detection on this CPU to make progress */ | |
dbaba470 | 1193 | sld_update_msr(false); |
b041b525 | 1194 | put_cpu(); |
d7e94dbd TG |
1195 | } |
1196 | ||
1197 | bool handle_guest_split_lock(unsigned long ip) | |
1198 | { | |
1199 | if (sld_state == sld_warn) { | |
1200 | split_lock_warn(ip); | |
1201 | return true; | |
1202 | } | |
1203 | ||
1204 | pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n", | |
1205 | current->comm, current->pid, | |
1206 | sld_state == sld_fatal ? "fatal" : "bogus", ip); | |
1207 | ||
1208 | current->thread.error_code = 0; | |
1209 | current->thread.trap_nr = X86_TRAP_AC; | |
1210 | force_sig_fault(SIGBUS, BUS_ADRALN, NULL); | |
1211 | return false; | |
1212 | } | |
1213 | EXPORT_SYMBOL_GPL(handle_guest_split_lock); | |
1214 | ||
ebb1064e FY |
1215 | static void bus_lock_init(void) |
1216 | { | |
1217 | u64 val; | |
1218 | ||
ffa6482e | 1219 | if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) |
ebb1064e FY |
1220 | return; |
1221 | ||
ebb1064e | 1222 | rdmsrl(MSR_IA32_DEBUGCTLMSR, val); |
ffa6482e CQ |
1223 | |
1224 | if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) && | |
1225 | (sld_state == sld_warn || sld_state == sld_fatal)) || | |
1226 | sld_state == sld_off) { | |
1227 | /* | |
1228 | * Warn and fatal are handled by #AC for split lock if #AC for | |
1229 | * split lock is supported. | |
1230 | */ | |
1231 | val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT; | |
1232 | } else { | |
1233 | val |= DEBUGCTLMSR_BUS_LOCK_DETECT; | |
1234 | } | |
1235 | ||
ebb1064e FY |
1236 | wrmsrl(MSR_IA32_DEBUGCTLMSR, val); |
1237 | } | |
1238 | ||
d7e94dbd TG |
1239 | bool handle_user_split_lock(struct pt_regs *regs, long error_code) |
1240 | { | |
1241 | if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal) | |
1242 | return false; | |
1243 | split_lock_warn(regs->ip); | |
6650cdd9 PZI |
1244 | return true; |
1245 | } | |
1246 | ||
ebb1064e FY |
1247 | void handle_bus_lock(struct pt_regs *regs) |
1248 | { | |
1249 | switch (sld_state) { | |
1250 | case sld_off: | |
1251 | break; | |
ef4ae6e4 FY |
1252 | case sld_ratelimit: |
1253 | /* Enforce no more than bld_ratelimit bus locks/sec. */ | |
1254 | while (!__ratelimit(&bld_ratelimit)) | |
1255 | msleep(20); | |
1256 | /* Warn on the bus lock. */ | |
1257 | fallthrough; | |
ebb1064e FY |
1258 | case sld_warn: |
1259 | pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n", | |
1260 | current->comm, current->pid, regs->ip); | |
1261 | break; | |
1262 | case sld_fatal: | |
1263 | force_sig_fault(SIGBUS, BUS_ADRALN, NULL); | |
1264 | break; | |
1265 | } | |
1266 | } | |
1267 | ||
6650cdd9 | 1268 | /* |
48fd5b5e TL |
1269 | * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should |
1270 | * only be trusted if it is confirmed that a CPU model implements a | |
1271 | * specific feature at a particular bit position. | |
1272 | * | |
1273 | * The possible driver data field values: | |
1274 | * | |
1275 | * - 0: CPU models that are known to have the per-core split-lock detection | |
1276 | * feature even though they do not enumerate IA32_CORE_CAPABILITIES. | |
1277 | * | |
1278 | * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use | |
1279 | * bit 5 to enumerate the per-core split-lock detection feature. | |
6650cdd9 PZI |
1280 | */ |
1281 | static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = { | |
3ab0762d TL |
1282 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, 0), |
1283 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, 0), | |
429ac8b7 | 1284 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, 0), |
8b9a18a9 TL |
1285 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, 1), |
1286 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, 1), | |
1287 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, 1), | |
429ac8b7 FY |
1288 | X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, 1), |
1289 | X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, 1), | |
3aae57f0 FY |
1290 | X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 1), |
1291 | X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 1), | |
8acf4178 | 1292 | X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 1), |
0180a1e8 | 1293 | X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 1), |
6650cdd9 PZI |
1294 | {} |
1295 | }; | |
1296 | ||
ebb1064e | 1297 | static void __init split_lock_setup(struct cpuinfo_x86 *c) |
6650cdd9 | 1298 | { |
48fd5b5e TL |
1299 | const struct x86_cpu_id *m; |
1300 | u64 ia32_core_caps; | |
1301 | ||
1302 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) | |
1303 | return; | |
6650cdd9 | 1304 | |
48fd5b5e TL |
1305 | m = x86_match_cpu(split_lock_cpu_ids); |
1306 | if (!m) | |
6650cdd9 | 1307 | return; |
48fd5b5e TL |
1308 | |
1309 | switch (m->driver_data) { | |
1310 | case 0: | |
1311 | break; | |
1312 | case 1: | |
1313 | if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) | |
1314 | return; | |
6650cdd9 | 1315 | rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps); |
48fd5b5e TL |
1316 | if (!(ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)) |
1317 | return; | |
1318 | break; | |
1319 | default: | |
1320 | return; | |
6650cdd9 PZI |
1321 | } |
1322 | ||
009bce1d | 1323 | cpu_model_supports_sld = true; |
ebb1064e FY |
1324 | __split_lock_setup(); |
1325 | } | |
1326 | ||
1327 | static void sld_state_show(void) | |
1328 | { | |
1329 | if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) && | |
1330 | !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
1331 | return; | |
1332 | ||
1333 | switch (sld_state) { | |
1334 | case sld_off: | |
1335 | pr_info("disabled\n"); | |
1336 | break; | |
1337 | case sld_warn: | |
b041b525 | 1338 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { |
ebb1064e | 1339 | pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n"); |
b041b525 TL |
1340 | if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, |
1341 | "x86/splitlock", NULL, splitlock_cpu_offline) < 0) | |
1342 | pr_warn("No splitlock CPU offline handler\n"); | |
1343 | } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { | |
ebb1064e | 1344 | pr_info("#DB: warning on user-space bus_locks\n"); |
b041b525 | 1345 | } |
ebb1064e FY |
1346 | break; |
1347 | case sld_fatal: | |
1348 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) { | |
1349 | pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n"); | |
1350 | } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) { | |
1351 | pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n", | |
1352 | boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ? | |
1353 | " from non-WB" : ""); | |
1354 | } | |
1355 | break; | |
ef4ae6e4 FY |
1356 | case sld_ratelimit: |
1357 | if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) | |
1358 | pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst); | |
1359 | break; | |
ebb1064e FY |
1360 | } |
1361 | } | |
1362 | ||
1363 | void __init sld_setup(struct cpuinfo_x86 *c) | |
1364 | { | |
1365 | split_lock_setup(c); | |
1366 | sld_state_setup(); | |
1367 | sld_state_show(); | |
6650cdd9 | 1368 | } |
250b3c0d RN |
1369 | |
1370 | #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 | |
1371 | ||
1372 | /** | |
1373 | * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU | |
1374 | * | |
1375 | * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in | |
1376 | * a hybrid processor. If the processor is not hybrid, returns 0. | |
1377 | */ | |
1378 | u8 get_this_hybrid_cpu_type(void) | |
1379 | { | |
1380 | if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) | |
1381 | return 0; | |
1382 | ||
1383 | return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT; | |
1384 | } |