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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/kernel.h> | |
3 | ||
4 | #include <linux/string.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/smp.h> | |
83ce4009 | 7 | #include <linux/sched.h> |
1da177e4 | 8 | #include <linux/thread_info.h> |
53e86b91 | 9 | #include <linux/module.h> |
1da177e4 LT |
10 | |
11 | #include <asm/processor.h> | |
d72b1b4f | 12 | #include <asm/pgtable.h> |
1da177e4 LT |
13 | #include <asm/msr.h> |
14 | #include <asm/uaccess.h> | |
eee3af4a | 15 | #include <asm/ds.h> |
73bdb73f | 16 | #include <asm/bugs.h> |
1f442d70 | 17 | #include <asm/cpu.h> |
1da177e4 | 18 | |
185f3b9d YL |
19 | #ifdef CONFIG_X86_64 |
20 | #include <asm/topology.h> | |
21 | #include <asm/numa_64.h> | |
22 | #endif | |
23 | ||
1da177e4 LT |
24 | #include "cpu.h" |
25 | ||
26 | #ifdef CONFIG_X86_LOCAL_APIC | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/apic.h> | |
1da177e4 LT |
29 | #endif |
30 | ||
03ae5768 | 31 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 32 | { |
99fb4d34 | 33 | /* Unmask CPUID levels if masked: */ |
30a0fb94 | 34 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
99fb4d34 | 35 | u64 misc_enable; |
066941bd | 36 | |
99fb4d34 IM |
37 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); |
38 | ||
39 | if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { | |
40 | misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; | |
41 | wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
42 | c->cpuid_level = cpuid_eax(0); | |
43 | } | |
066941bd PA |
44 | } |
45 | ||
2b16a235 AK |
46 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
47 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
48 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d YL |
49 | |
50 | #ifdef CONFIG_X86_64 | |
51 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
52 | #else | |
53 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
54 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
55 | c->x86_cache_alignment = 128; | |
56 | #endif | |
40fb1715 | 57 | |
13c6c532 JB |
58 | /* CPUID workaround for 0F33/0F34 CPU */ |
59 | if (c->x86 == 0xF && c->x86_model == 0x3 | |
60 | && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) | |
61 | c->x86_phys_bits = 36; | |
62 | ||
40fb1715 VP |
63 | /* |
64 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
83ce4009 IM |
65 | * with P/T states and does not stop in deep C-states. |
66 | * | |
67 | * It is also reliable across cores and sockets. (but not across | |
68 | * cabinets - we turn it off in that case explicitly.) | |
40fb1715 VP |
69 | */ |
70 | if (c->x86_power & (1 << 8)) { | |
71 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
72 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
83ce4009 IM |
73 | set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE); |
74 | sched_clock_stable = 1; | |
40fb1715 VP |
75 | } |
76 | ||
75a04811 PA |
77 | /* |
78 | * There is a known erratum on Pentium III and Core Solo | |
79 | * and Core Duo CPUs. | |
80 | * " Page with PAT set to WC while associated MTRR is UC | |
81 | * may consolidate to UC " | |
82 | * Because of this erratum, it is better to stick with | |
83 | * setting WC in MTRR rather than using PAT on these CPUs. | |
84 | * | |
85 | * Enable PAT WC only on P4, Core 2 or later CPUs. | |
86 | */ | |
87 | if (c->x86 == 6 && c->x86_model < 15) | |
88 | clear_cpu_cap(c, X86_FEATURE_PAT); | |
f8561296 VN |
89 | |
90 | #ifdef CONFIG_KMEMCHECK | |
91 | /* | |
92 | * P4s have a "fast strings" feature which causes single- | |
93 | * stepping REP instructions to only generate a #DB on | |
94 | * cache-line boundaries. | |
95 | * | |
96 | * Ingo Molnar reported a Pentium D (model 6) and a Xeon | |
97 | * (model 2) with the same problem. | |
98 | */ | |
99 | if (c->x86 == 15) { | |
100 | u64 misc_enable; | |
101 | ||
102 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
103 | ||
104 | if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) { | |
105 | printk(KERN_INFO "kmemcheck: Disabling fast string operations\n"); | |
106 | ||
107 | misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING; | |
108 | wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
109 | } | |
110 | } | |
111 | #endif | |
1da177e4 LT |
112 | } |
113 | ||
185f3b9d | 114 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
115 | /* |
116 | * Early probe support logic for ppro memory erratum #50 | |
117 | * | |
118 | * This is called before we do cpu ident work | |
119 | */ | |
65eb6b43 | 120 | |
3bc9b76b | 121 | int __cpuinit ppro_with_ram_bug(void) |
1da177e4 LT |
122 | { |
123 | /* Uses data from early_cpu_detect now */ | |
124 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
125 | boot_cpu_data.x86 == 6 && | |
126 | boot_cpu_data.x86_model == 1 && | |
127 | boot_cpu_data.x86_mask < 8) { | |
128 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); | |
129 | return 1; | |
130 | } | |
131 | return 0; | |
132 | } | |
65eb6b43 | 133 | |
4052704d YL |
134 | #ifdef CONFIG_X86_F00F_BUG |
135 | static void __cpuinit trap_init_f00f_bug(void) | |
136 | { | |
137 | __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); | |
1da177e4 | 138 | |
4052704d YL |
139 | /* |
140 | * Update the IDT descriptor and reload the IDT so that | |
141 | * it uses the read-only mapped virtual address. | |
142 | */ | |
143 | idt_descr.address = fix_to_virt(FIX_F00F_IDT); | |
144 | load_idt(&idt_descr); | |
145 | } | |
146 | #endif | |
147 | ||
1f442d70 YL |
148 | static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) |
149 | { | |
150 | #ifdef CONFIG_SMP | |
151 | /* calling is from identify_secondary_cpu() ? */ | |
152 | if (c->cpu_index == boot_cpu_id) | |
153 | return; | |
154 | ||
155 | /* | |
156 | * Mask B, Pentium, but not Pentium MMX | |
157 | */ | |
158 | if (c->x86 == 5 && | |
159 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
160 | c->x86_model <= 3) { | |
161 | /* | |
162 | * Remember we have B step Pentia with bugs | |
163 | */ | |
164 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | |
165 | "with B stepping processors.\n"); | |
166 | } | |
167 | #endif | |
168 | } | |
169 | ||
4052704d | 170 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
1da177e4 LT |
171 | { |
172 | unsigned long lo, hi; | |
173 | ||
4052704d YL |
174 | #ifdef CONFIG_X86_F00F_BUG |
175 | /* | |
176 | * All current models of Pentium and Pentium with MMX technology CPUs | |
177 | * have the F0 0F bug, which lets nonprivileged users lock up the system. | |
178 | * Note that the workaround only should be initialized once... | |
179 | */ | |
180 | c->f00f_bug = 0; | |
181 | if (!paravirt_enabled() && c->x86 == 5) { | |
182 | static int f00f_workaround_enabled; | |
183 | ||
184 | c->f00f_bug = 1; | |
185 | if (!f00f_workaround_enabled) { | |
186 | trap_init_f00f_bug(); | |
187 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); | |
188 | f00f_workaround_enabled = 1; | |
189 | } | |
190 | } | |
191 | #endif | |
192 | ||
193 | /* | |
194 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
195 | * model 3 mask 3 | |
196 | */ | |
197 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
198 | clear_cpu_cap(c, X86_FEATURE_SEP); | |
199 | ||
200 | /* | |
201 | * P4 Xeon errata 037 workaround. | |
202 | * Hardware prefetcher may cause stale data to be loaded into the cache. | |
203 | */ | |
1da177e4 | 204 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { |
65eb6b43 | 205 | rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); |
ecab22aa | 206 | if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) { |
1da177e4 LT |
207 | printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); |
208 | printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); | |
ecab22aa | 209 | lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE; |
1da177e4 LT |
210 | wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); |
211 | } | |
212 | } | |
1da177e4 | 213 | |
4052704d YL |
214 | /* |
215 | * See if we have a good local APIC by checking for buggy Pentia, | |
216 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
217 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
218 | * Specification Update"). | |
219 | */ | |
220 | if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && | |
221 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) | |
222 | set_cpu_cap(c, X86_FEATURE_11AP); | |
185f3b9d | 223 | |
185f3b9d | 224 | |
4052704d | 225 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 226 | /* |
4052704d | 227 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 228 | */ |
4052704d YL |
229 | switch (c->x86) { |
230 | case 4: /* 486: untested */ | |
231 | break; | |
232 | case 5: /* Old Pentia: untested */ | |
233 | break; | |
234 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
235 | movsl_mask.mask = 7; | |
236 | break; | |
237 | case 15: /* P4 is OK down to 8-byte alignment */ | |
238 | movsl_mask.mask = 7; | |
239 | break; | |
240 | } | |
185f3b9d | 241 | #endif |
4052704d YL |
242 | |
243 | #ifdef CONFIG_X86_NUMAQ | |
244 | numaq_tsc_disable(); | |
245 | #endif | |
1f442d70 YL |
246 | |
247 | intel_smp_check(c); | |
4052704d YL |
248 | } |
249 | #else | |
250 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | |
251 | { | |
252 | } | |
185f3b9d YL |
253 | #endif |
254 | ||
2759c328 | 255 | static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) |
185f3b9d YL |
256 | { |
257 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
258 | unsigned node; | |
259 | int cpu = smp_processor_id(); | |
2759c328 | 260 | int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid; |
185f3b9d YL |
261 | |
262 | /* Don't do the funky fallback heuristics the AMD version employs | |
263 | for now. */ | |
264 | node = apicid_to_node[apicid]; | |
265 | if (node == NUMA_NO_NODE || !node_online(node)) | |
266 | node = first_node(node_online_map); | |
267 | numa_set_node(cpu, node); | |
268 | ||
823b259b | 269 | printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); |
185f3b9d YL |
270 | #endif |
271 | } | |
272 | ||
3dd9d514 AK |
273 | /* |
274 | * find out the number of processor cores on the die | |
275 | */ | |
f69feff7 | 276 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 277 | { |
f2ab4461 | 278 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 AK |
279 | |
280 | if (c->cpuid_level < 4) | |
281 | return 1; | |
282 | ||
f2ab4461 ZA |
283 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
284 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 AK |
285 | if (eax & 0x1f) |
286 | return ((eax >> 26) + 1); | |
287 | else | |
288 | return 1; | |
289 | } | |
290 | ||
e38e05a8 SY |
291 | static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) |
292 | { | |
293 | /* Intel VMX MSR indicated features */ | |
294 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 | |
295 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
296 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
297 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
298 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
299 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
300 | ||
301 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
302 | ||
303 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
304 | clear_cpu_cap(c, X86_FEATURE_VNMI); | |
305 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
306 | clear_cpu_cap(c, X86_FEATURE_EPT); | |
307 | clear_cpu_cap(c, X86_FEATURE_VPID); | |
308 | ||
309 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
310 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
311 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
312 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
313 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
314 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
315 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
316 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
317 | vmx_msr_low, vmx_msr_high); | |
318 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
319 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
320 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
321 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
322 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
323 | set_cpu_cap(c, X86_FEATURE_EPT); | |
324 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
325 | set_cpu_cap(c, X86_FEATURE_VPID); | |
326 | } | |
327 | } | |
328 | ||
3bc9b76b | 329 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
330 | { |
331 | unsigned int l2 = 0; | |
1da177e4 | 332 | |
2b16a235 AK |
333 | early_init_intel(c); |
334 | ||
4052704d | 335 | intel_workarounds(c); |
1da177e4 | 336 | |
345077cd SS |
337 | /* |
338 | * Detect the extended topology information if available. This | |
339 | * will reinitialise the initial_apicid which will be used | |
340 | * in init_intel_cacheinfo() | |
341 | */ | |
342 | detect_extended_topology(c); | |
343 | ||
1da177e4 | 344 | l2 = init_intel_cacheinfo(c); |
65eb6b43 | 345 | if (c->cpuid_level > 9) { |
0080e667 VP |
346 | unsigned eax = cpuid_eax(10); |
347 | /* Check for version and the number of counters */ | |
348 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 349 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 350 | } |
1da177e4 | 351 | |
4052704d YL |
352 | if (cpu_has_xmm2) |
353 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
354 | if (cpu_has_ds) { | |
355 | unsigned int l1; | |
356 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
357 | if (!(l1 & (1<<11))) | |
358 | set_cpu_cap(c, X86_FEATURE_BTS); | |
359 | if (!(l1 & (1<<12))) | |
360 | set_cpu_cap(c, X86_FEATURE_PEBS); | |
361 | ds_init_intel(c); | |
362 | } | |
1da177e4 | 363 | |
e736ad54 PV |
364 | if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush) |
365 | set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR); | |
366 | ||
4052704d YL |
367 | #ifdef CONFIG_X86_64 |
368 | if (c->x86 == 15) | |
369 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
370 | if (c->x86 == 6) | |
371 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
372 | #else | |
65eb6b43 PC |
373 | /* |
374 | * Names for the Pentium II/Celeron processors | |
375 | * detectable only by also checking the cache size. | |
376 | * Dixon is NOT a Celeron. | |
377 | */ | |
1da177e4 | 378 | if (c->x86 == 6) { |
4052704d YL |
379 | char *p = NULL; |
380 | ||
1da177e4 LT |
381 | switch (c->x86_model) { |
382 | case 5: | |
383 | if (c->x86_mask == 0) { | |
384 | if (l2 == 0) | |
385 | p = "Celeron (Covington)"; | |
386 | else if (l2 == 256) | |
387 | p = "Mobile Pentium II (Dixon)"; | |
388 | } | |
389 | break; | |
65eb6b43 | 390 | |
1da177e4 LT |
391 | case 6: |
392 | if (l2 == 128) | |
393 | p = "Celeron (Mendocino)"; | |
394 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
395 | p = "Celeron-A"; | |
396 | break; | |
65eb6b43 | 397 | |
1da177e4 LT |
398 | case 8: |
399 | if (l2 == 128) | |
400 | p = "Celeron (Coppermine)"; | |
401 | break; | |
402 | } | |
1da177e4 | 403 | |
4052704d YL |
404 | if (p) |
405 | strcpy(c->x86_model_id, p); | |
1da177e4 | 406 | } |
1da177e4 | 407 | |
185f3b9d YL |
408 | if (c->x86 == 15) |
409 | set_cpu_cap(c, X86_FEATURE_P4); | |
410 | if (c->x86 == 6) | |
411 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 412 | #endif |
185f3b9d | 413 | |
185f3b9d YL |
414 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
415 | /* | |
416 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
417 | * detection. | |
418 | */ | |
419 | c->x86_max_cores = intel_num_cpu_cores(c); | |
420 | #ifdef CONFIG_X86_32 | |
421 | detect_ht(c); | |
422 | #endif | |
423 | } | |
424 | ||
425 | /* Work around errata */ | |
2759c328 | 426 | srat_detect_node(c); |
e38e05a8 SY |
427 | |
428 | if (cpu_has(c, X86_FEATURE_VMX)) | |
429 | detect_vmx_virtcap(c); | |
42ed458a | 430 | } |
1da177e4 | 431 | |
185f3b9d | 432 | #ifdef CONFIG_X86_32 |
65eb6b43 | 433 | static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 434 | { |
65eb6b43 PC |
435 | /* |
436 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
437 | * One has 256kb of cache, the other 512. We have no way |
438 | * to determine which, so we use a boottime override | |
439 | * for the 512kb model, and assume 256 otherwise. | |
440 | */ | |
441 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
442 | size = 256; | |
443 | return size; | |
444 | } | |
185f3b9d | 445 | #endif |
1da177e4 | 446 | |
02dde8b4 | 447 | static const struct cpu_dev __cpuinitconst intel_cpu_dev = { |
1da177e4 | 448 | .c_vendor = "Intel", |
65eb6b43 | 449 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 450 | #ifdef CONFIG_X86_32 |
1da177e4 | 451 | .c_models = { |
65eb6b43 PC |
452 | { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = |
453 | { | |
454 | [0] = "486 DX-25/33", | |
455 | [1] = "486 DX-50", | |
456 | [2] = "486 SX", | |
457 | [3] = "486 DX/2", | |
458 | [4] = "486 SL", | |
459 | [5] = "486 SX/2", | |
460 | [7] = "486 DX/2-WB", | |
461 | [8] = "486 DX/4", | |
1da177e4 LT |
462 | [9] = "486 DX/4-WB" |
463 | } | |
464 | }, | |
465 | { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = | |
65eb6b43 PC |
466 | { |
467 | [0] = "Pentium 60/66 A-step", | |
468 | [1] = "Pentium 60/66", | |
1da177e4 | 469 | [2] = "Pentium 75 - 200", |
65eb6b43 | 470 | [3] = "OverDrive PODP5V83", |
1da177e4 | 471 | [4] = "Pentium MMX", |
65eb6b43 | 472 | [7] = "Mobile Pentium 75 - 200", |
1da177e4 LT |
473 | [8] = "Mobile Pentium MMX" |
474 | } | |
475 | }, | |
476 | { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = | |
65eb6b43 | 477 | { |
1da177e4 | 478 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
479 | [1] = "Pentium Pro", |
480 | [3] = "Pentium II (Klamath)", | |
481 | [4] = "Pentium II (Deschutes)", | |
482 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 483 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
484 | [7] = "Pentium III (Katmai)", |
485 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
486 | [10] = "Pentium III (Cascades)", |
487 | [11] = "Pentium III (Tualatin)", | |
488 | } | |
489 | }, | |
490 | { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = | |
491 | { | |
492 | [0] = "Pentium 4 (Unknown)", | |
493 | [1] = "Pentium 4 (Willamette)", | |
494 | [2] = "Pentium 4 (Northwood)", | |
495 | [4] = "Pentium 4 (Foster)", | |
496 | [5] = "Pentium 4 (Foster)", | |
497 | } | |
498 | }, | |
499 | }, | |
185f3b9d YL |
500 | .c_size_cache = intel_size_cache, |
501 | #endif | |
03ae5768 | 502 | .c_early_init = early_init_intel, |
1da177e4 | 503 | .c_init = init_intel, |
10a434fc | 504 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
505 | }; |
506 | ||
10a434fc | 507 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 508 |