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1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/kernel.h> | |
3 | ||
4 | #include <linux/string.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/smp.h> | |
7 | #include <linux/thread_info.h> | |
53e86b91 | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | |
10 | #include <asm/processor.h> | |
d72b1b4f | 11 | #include <asm/pgtable.h> |
1da177e4 LT |
12 | #include <asm/msr.h> |
13 | #include <asm/uaccess.h> | |
eee3af4a | 14 | #include <asm/ds.h> |
73bdb73f | 15 | #include <asm/bugs.h> |
1da177e4 | 16 | |
185f3b9d YL |
17 | #ifdef CONFIG_X86_64 |
18 | #include <asm/topology.h> | |
19 | #include <asm/numa_64.h> | |
20 | #endif | |
21 | ||
1da177e4 LT |
22 | #include "cpu.h" |
23 | ||
24 | #ifdef CONFIG_X86_LOCAL_APIC | |
25 | #include <asm/mpspec.h> | |
26 | #include <asm/apic.h> | |
27 | #include <mach_apic.h> | |
28 | #endif | |
29 | ||
03ae5768 | 30 | static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 31 | { |
99fb4d34 IM |
32 | /* Unmask CPUID levels if masked: */ |
33 | if (c->x86 == 6 && c->x86_model >= 15) { | |
34 | u64 misc_enable; | |
066941bd | 35 | |
99fb4d34 IM |
36 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); |
37 | ||
38 | if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) { | |
39 | misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID; | |
40 | wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
41 | c->cpuid_level = cpuid_eax(0); | |
42 | } | |
066941bd PA |
43 | } |
44 | ||
2b16a235 AK |
45 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
46 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
47 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d YL |
48 | |
49 | #ifdef CONFIG_X86_64 | |
50 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
51 | #else | |
52 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
53 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
54 | c->x86_cache_alignment = 128; | |
55 | #endif | |
40fb1715 VP |
56 | |
57 | /* | |
58 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
59 | * with P/T states and does not stop in deep C-states | |
60 | */ | |
61 | if (c->x86_power & (1 << 8)) { | |
62 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
63 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
64 | } | |
65 | ||
1da177e4 LT |
66 | } |
67 | ||
185f3b9d | 68 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
69 | /* |
70 | * Early probe support logic for ppro memory erratum #50 | |
71 | * | |
72 | * This is called before we do cpu ident work | |
73 | */ | |
65eb6b43 | 74 | |
3bc9b76b | 75 | int __cpuinit ppro_with_ram_bug(void) |
1da177e4 LT |
76 | { |
77 | /* Uses data from early_cpu_detect now */ | |
78 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
79 | boot_cpu_data.x86 == 6 && | |
80 | boot_cpu_data.x86_model == 1 && | |
81 | boot_cpu_data.x86_mask < 8) { | |
82 | printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); | |
83 | return 1; | |
84 | } | |
85 | return 0; | |
86 | } | |
65eb6b43 | 87 | |
4052704d YL |
88 | #ifdef CONFIG_X86_F00F_BUG |
89 | static void __cpuinit trap_init_f00f_bug(void) | |
90 | { | |
91 | __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO); | |
1da177e4 | 92 | |
4052704d YL |
93 | /* |
94 | * Update the IDT descriptor and reload the IDT so that | |
95 | * it uses the read-only mapped virtual address. | |
96 | */ | |
97 | idt_descr.address = fix_to_virt(FIX_F00F_IDT); | |
98 | load_idt(&idt_descr); | |
99 | } | |
100 | #endif | |
101 | ||
102 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | |
1da177e4 LT |
103 | { |
104 | unsigned long lo, hi; | |
105 | ||
4052704d YL |
106 | #ifdef CONFIG_X86_F00F_BUG |
107 | /* | |
108 | * All current models of Pentium and Pentium with MMX technology CPUs | |
109 | * have the F0 0F bug, which lets nonprivileged users lock up the system. | |
110 | * Note that the workaround only should be initialized once... | |
111 | */ | |
112 | c->f00f_bug = 0; | |
113 | if (!paravirt_enabled() && c->x86 == 5) { | |
114 | static int f00f_workaround_enabled; | |
115 | ||
116 | c->f00f_bug = 1; | |
117 | if (!f00f_workaround_enabled) { | |
118 | trap_init_f00f_bug(); | |
119 | printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); | |
120 | f00f_workaround_enabled = 1; | |
121 | } | |
122 | } | |
123 | #endif | |
124 | ||
125 | /* | |
126 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
127 | * model 3 mask 3 | |
128 | */ | |
129 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | |
130 | clear_cpu_cap(c, X86_FEATURE_SEP); | |
131 | ||
132 | /* | |
133 | * P4 Xeon errata 037 workaround. | |
134 | * Hardware prefetcher may cause stale data to be loaded into the cache. | |
135 | */ | |
1da177e4 | 136 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { |
65eb6b43 | 137 | rdmsr(MSR_IA32_MISC_ENABLE, lo, hi); |
1da177e4 LT |
138 | if ((lo & (1<<9)) == 0) { |
139 | printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); | |
140 | printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); | |
141 | lo |= (1<<9); /* Disable hw prefetching */ | |
142 | wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); | |
143 | } | |
144 | } | |
1da177e4 | 145 | |
4052704d YL |
146 | /* |
147 | * See if we have a good local APIC by checking for buggy Pentia, | |
148 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
149 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
150 | * Specification Update"). | |
151 | */ | |
152 | if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && | |
153 | (c->x86_mask < 0x6 || c->x86_mask == 0xb)) | |
154 | set_cpu_cap(c, X86_FEATURE_11AP); | |
185f3b9d | 155 | |
185f3b9d | 156 | |
4052704d | 157 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 158 | /* |
4052704d | 159 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 160 | */ |
4052704d YL |
161 | switch (c->x86) { |
162 | case 4: /* 486: untested */ | |
163 | break; | |
164 | case 5: /* Old Pentia: untested */ | |
165 | break; | |
166 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
167 | movsl_mask.mask = 7; | |
168 | break; | |
169 | case 15: /* P4 is OK down to 8-byte alignment */ | |
170 | movsl_mask.mask = 7; | |
171 | break; | |
172 | } | |
185f3b9d | 173 | #endif |
4052704d YL |
174 | |
175 | #ifdef CONFIG_X86_NUMAQ | |
176 | numaq_tsc_disable(); | |
177 | #endif | |
178 | } | |
179 | #else | |
180 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | |
181 | { | |
182 | } | |
185f3b9d YL |
183 | #endif |
184 | ||
185 | static void __cpuinit srat_detect_node(void) | |
186 | { | |
187 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
188 | unsigned node; | |
189 | int cpu = smp_processor_id(); | |
190 | int apicid = hard_smp_processor_id(); | |
191 | ||
192 | /* Don't do the funky fallback heuristics the AMD version employs | |
193 | for now. */ | |
194 | node = apicid_to_node[apicid]; | |
195 | if (node == NUMA_NO_NODE || !node_online(node)) | |
196 | node = first_node(node_online_map); | |
197 | numa_set_node(cpu, node); | |
198 | ||
823b259b | 199 | printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node); |
185f3b9d YL |
200 | #endif |
201 | } | |
202 | ||
3dd9d514 AK |
203 | /* |
204 | * find out the number of processor cores on the die | |
205 | */ | |
f69feff7 | 206 | static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 207 | { |
f2ab4461 | 208 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 AK |
209 | |
210 | if (c->cpuid_level < 4) | |
211 | return 1; | |
212 | ||
f2ab4461 ZA |
213 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
214 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 AK |
215 | if (eax & 0x1f) |
216 | return ((eax >> 26) + 1); | |
217 | else | |
218 | return 1; | |
219 | } | |
220 | ||
e38e05a8 SY |
221 | static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c) |
222 | { | |
223 | /* Intel VMX MSR indicated features */ | |
224 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 | |
225 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
226 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
227 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
228 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
229 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
230 | ||
231 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
232 | ||
233 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
234 | clear_cpu_cap(c, X86_FEATURE_VNMI); | |
235 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
236 | clear_cpu_cap(c, X86_FEATURE_EPT); | |
237 | clear_cpu_cap(c, X86_FEATURE_VPID); | |
238 | ||
239 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
240 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
241 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
242 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
243 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
244 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
245 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
246 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
247 | vmx_msr_low, vmx_msr_high); | |
248 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
249 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
250 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
251 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
252 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
253 | set_cpu_cap(c, X86_FEATURE_EPT); | |
254 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
255 | set_cpu_cap(c, X86_FEATURE_VPID); | |
256 | } | |
257 | } | |
258 | ||
3bc9b76b | 259 | static void __cpuinit init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
260 | { |
261 | unsigned int l2 = 0; | |
1da177e4 | 262 | |
2b16a235 AK |
263 | early_init_intel(c); |
264 | ||
4052704d | 265 | intel_workarounds(c); |
1da177e4 | 266 | |
345077cd SS |
267 | /* |
268 | * Detect the extended topology information if available. This | |
269 | * will reinitialise the initial_apicid which will be used | |
270 | * in init_intel_cacheinfo() | |
271 | */ | |
272 | detect_extended_topology(c); | |
273 | ||
1da177e4 | 274 | l2 = init_intel_cacheinfo(c); |
65eb6b43 | 275 | if (c->cpuid_level > 9) { |
0080e667 VP |
276 | unsigned eax = cpuid_eax(10); |
277 | /* Check for version and the number of counters */ | |
278 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 279 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 280 | } |
1da177e4 | 281 | |
4052704d YL |
282 | if (cpu_has_xmm2) |
283 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
284 | if (cpu_has_ds) { | |
285 | unsigned int l1; | |
286 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
287 | if (!(l1 & (1<<11))) | |
288 | set_cpu_cap(c, X86_FEATURE_BTS); | |
289 | if (!(l1 & (1<<12))) | |
290 | set_cpu_cap(c, X86_FEATURE_PEBS); | |
291 | ds_init_intel(c); | |
292 | } | |
1da177e4 | 293 | |
4052704d YL |
294 | #ifdef CONFIG_X86_64 |
295 | if (c->x86 == 15) | |
296 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
297 | if (c->x86 == 6) | |
298 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
299 | #else | |
65eb6b43 PC |
300 | /* |
301 | * Names for the Pentium II/Celeron processors | |
302 | * detectable only by also checking the cache size. | |
303 | * Dixon is NOT a Celeron. | |
304 | */ | |
1da177e4 | 305 | if (c->x86 == 6) { |
4052704d YL |
306 | char *p = NULL; |
307 | ||
1da177e4 LT |
308 | switch (c->x86_model) { |
309 | case 5: | |
310 | if (c->x86_mask == 0) { | |
311 | if (l2 == 0) | |
312 | p = "Celeron (Covington)"; | |
313 | else if (l2 == 256) | |
314 | p = "Mobile Pentium II (Dixon)"; | |
315 | } | |
316 | break; | |
65eb6b43 | 317 | |
1da177e4 LT |
318 | case 6: |
319 | if (l2 == 128) | |
320 | p = "Celeron (Mendocino)"; | |
321 | else if (c->x86_mask == 0 || c->x86_mask == 5) | |
322 | p = "Celeron-A"; | |
323 | break; | |
65eb6b43 | 324 | |
1da177e4 LT |
325 | case 8: |
326 | if (l2 == 128) | |
327 | p = "Celeron (Coppermine)"; | |
328 | break; | |
329 | } | |
1da177e4 | 330 | |
4052704d YL |
331 | if (p) |
332 | strcpy(c->x86_model_id, p); | |
1da177e4 | 333 | } |
1da177e4 | 334 | |
185f3b9d YL |
335 | if (c->x86 == 15) |
336 | set_cpu_cap(c, X86_FEATURE_P4); | |
337 | if (c->x86 == 6) | |
338 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 339 | #endif |
185f3b9d | 340 | |
185f3b9d YL |
341 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
342 | /* | |
343 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
344 | * detection. | |
345 | */ | |
346 | c->x86_max_cores = intel_num_cpu_cores(c); | |
347 | #ifdef CONFIG_X86_32 | |
348 | detect_ht(c); | |
349 | #endif | |
350 | } | |
351 | ||
352 | /* Work around errata */ | |
353 | srat_detect_node(); | |
e38e05a8 SY |
354 | |
355 | if (cpu_has(c, X86_FEATURE_VMX)) | |
356 | detect_vmx_virtcap(c); | |
42ed458a | 357 | } |
1da177e4 | 358 | |
185f3b9d | 359 | #ifdef CONFIG_X86_32 |
65eb6b43 | 360 | static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 361 | { |
65eb6b43 PC |
362 | /* |
363 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
364 | * One has 256kb of cache, the other 512. We have no way |
365 | * to determine which, so we use a boottime override | |
366 | * for the 512kb model, and assume 256 otherwise. | |
367 | */ | |
368 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
369 | size = 256; | |
370 | return size; | |
371 | } | |
185f3b9d | 372 | #endif |
1da177e4 | 373 | |
3bc9b76b | 374 | static struct cpu_dev intel_cpu_dev __cpuinitdata = { |
1da177e4 | 375 | .c_vendor = "Intel", |
65eb6b43 | 376 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 377 | #ifdef CONFIG_X86_32 |
1da177e4 | 378 | .c_models = { |
65eb6b43 PC |
379 | { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names = |
380 | { | |
381 | [0] = "486 DX-25/33", | |
382 | [1] = "486 DX-50", | |
383 | [2] = "486 SX", | |
384 | [3] = "486 DX/2", | |
385 | [4] = "486 SL", | |
386 | [5] = "486 SX/2", | |
387 | [7] = "486 DX/2-WB", | |
388 | [8] = "486 DX/4", | |
1da177e4 LT |
389 | [9] = "486 DX/4-WB" |
390 | } | |
391 | }, | |
392 | { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names = | |
65eb6b43 PC |
393 | { |
394 | [0] = "Pentium 60/66 A-step", | |
395 | [1] = "Pentium 60/66", | |
1da177e4 | 396 | [2] = "Pentium 75 - 200", |
65eb6b43 | 397 | [3] = "OverDrive PODP5V83", |
1da177e4 | 398 | [4] = "Pentium MMX", |
65eb6b43 | 399 | [7] = "Mobile Pentium 75 - 200", |
1da177e4 LT |
400 | [8] = "Mobile Pentium MMX" |
401 | } | |
402 | }, | |
403 | { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names = | |
65eb6b43 | 404 | { |
1da177e4 | 405 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
406 | [1] = "Pentium Pro", |
407 | [3] = "Pentium II (Klamath)", | |
408 | [4] = "Pentium II (Deschutes)", | |
409 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 410 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
411 | [7] = "Pentium III (Katmai)", |
412 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
413 | [10] = "Pentium III (Cascades)", |
414 | [11] = "Pentium III (Tualatin)", | |
415 | } | |
416 | }, | |
417 | { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names = | |
418 | { | |
419 | [0] = "Pentium 4 (Unknown)", | |
420 | [1] = "Pentium 4 (Willamette)", | |
421 | [2] = "Pentium 4 (Northwood)", | |
422 | [4] = "Pentium 4 (Foster)", | |
423 | [5] = "Pentium 4 (Foster)", | |
424 | } | |
425 | }, | |
426 | }, | |
185f3b9d YL |
427 | .c_size_cache = intel_size_cache, |
428 | #endif | |
03ae5768 | 429 | .c_early_init = early_init_intel, |
1da177e4 | 430 | .c_init = init_intel, |
10a434fc | 431 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
432 | }; |
433 | ||
10a434fc | 434 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 435 |