[linux-2.6-block.git] / arch / x86 / kernel / cpu / intel.c

#include <linux/init.h>
#include <linux/kernel.h>

#include <linux/string.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <linux/sched.h>
#include <linux/thread_info.h>
#include <linux/module.h>
#include <linux/uaccess.h>

#include <asm/processor.h>
#include <asm/pgtable.h>
#include <asm/msr.h>
#include <asm/ds.h>
#include <asm/bugs.h>
#include <asm/cpu.h>

#ifdef CONFIG_X86_64
#include <linux/topology.h>
#include <asm/numa_64.h>
#endif

#include "cpu.h"

#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#endif

static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
{
	/* Unmask CPUID levels if masked: */
	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
		u64 misc_enable;

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
			c->cpuid_level = cpuid_eax(0);
		}
	}

	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
		(c->x86 == 0x6 && c->x86_model >= 0x0e))
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

	/*
	 * Atom erratum AAE44/AAF40/AAG38/AAH41:
	 *
	 * A race condition between speculative fetches and invalidating
	 * a large page.  This is worked around in microcode, but we
	 * need the microcode to have already been loaded... so if it is
	 * not, recommend a BIOS update and disable large pages.
	 */
	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
		u32 ucode, junk;

		wrmsr(MSR_IA32_UCODE_REV, 0, 0);
		sync_core();
		rdmsr(MSR_IA32_UCODE_REV, junk, ucode);

		if (ucode < 0x20e) {
			printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
			clear_cpu_cap(c, X86_FEATURE_PSE);
		}
	}

#ifdef CONFIG_X86_64
	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#else
	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	if (c->x86 == 15 && c->x86_cache_alignment == 64)
		c->x86_cache_alignment = 128;
#endif

	/* CPUID workaround for 0F33/0F34 CPU */
	if (c->x86 == 0xF && c->x86_model == 0x3
	    && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
		c->x86_phys_bits = 36;

	/*
	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
	 * with P/T states and does not stop in deep C-states.
	 *
	 * It is also reliable across cores and sockets. (but not across
	 * cabinets - we turn it off in that case explicitly.)
	 */
	if (c->x86_power & (1 << 8)) {
		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
		if (!check_tsc_unstable())
			sched_clock_stable = 1;
	}

	/*
	 * There is a known erratum on Pentium III and Core Solo
	 * and Core Duo CPUs.
	 * " Page with PAT set to WC while associated MTRR is UC
	 *   may consolidate to UC "
	 * Because of this erratum, it is better to stick with
	 * setting WC in MTRR rather than using PAT on these CPUs.
	 *
	 * Enable PAT WC only on P4, Core 2 or later CPUs.
	 */
	if (c->x86 == 6 && c->x86_model < 15)
		clear_cpu_cap(c, X86_FEATURE_PAT);

#ifdef CONFIG_KMEMCHECK
	/*
	 * P4s have a "fast strings" feature which causes single-
	 * stepping REP instructions to only generate a #DB on
	 * cache-line boundaries.
	 *
	 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
	 * (model 2) with the same problem.
	 */
	if (c->x86 == 15) {
		u64 misc_enable;

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
			printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");

			misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
		}
	}
#endif
}

#ifdef CONFIG_X86_32
/*
 *	Early probe support logic for ppro memory erratum #50
 *
 *	This is called before we do cpu ident work
 */

int __cpuinit ppro_with_ram_bug(void)
{
	/* Uses data from early_cpu_detect now */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6 &&
	    boot_cpu_data.x86_model == 1 &&
	    boot_cpu_data.x86_mask < 8) {
		printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
		return 1;
	}
	return 0;
}

#ifdef CONFIG_X86_F00F_BUG
static void __cpuinit trap_init_f00f_bug(void)
{
	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);

	/*
	 * Update the IDT descriptor and reload the IDT so that
	 * it uses the read-only mapped virtual address.
	 */
	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	load_idt(&idt_descr);
}
#endif

static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
	/* calling is from identify_secondary_cpu() ? */
	if (c->cpu_index == boot_cpu_id)
		return;

	/*
	 * Mask B, Pentium, but not Pentium MMX
	 */
	if (c->x86 == 5 &&
	    c->x86_mask >= 1 && c->x86_mask <= 4 &&
	    c->x86_model <= 3) {
		/*
		 * Remember we have B step Pentia with bugs
		 */
		WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
				    "with B stepping processors.\n");
	}
#endif
}

static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
	unsigned long lo, hi;

#ifdef CONFIG_X86_F00F_BUG
	/*
	 * All current models of Pentium and Pentium with MMX technology CPUs
	 * have the F0 0F bug, which lets nonprivileged users lock up the
	 * system.
	 * Note that the workaround only should be initialized once...
	 */
	c->f00f_bug = 0;
	if (!paravirt_enabled() && c->x86 == 5) {
		static int f00f_workaround_enabled;

		c->f00f_bug = 1;
		if (!f00f_workaround_enabled) {
			trap_init_f00f_bug();
			printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
			f00f_workaround_enabled = 1;
		}
	}
#endif

	/*
	 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	 * model 3 mask 3
	 */
	if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
		clear_cpu_cap(c, X86_FEATURE_SEP);

	/*
	 * P4 Xeon errata 037 workaround.
	 * Hardware prefetcher may cause stale data to be loaded into the cache.
	 */
	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
			lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
			wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
		}
	}

	/*
	 * See if we have a good local APIC by checking for buggy Pentia,
	 * i.e. all B steppings and the C2 stepping of P54C when using their
	 * integrated APIC (see 11AP erratum in "Pentium Processor
	 * Specification Update").
	 */
	if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
	    (c->x86_mask < 0x6 || c->x86_mask == 0xb))
		set_cpu_cap(c, X86_FEATURE_11AP);


#ifdef CONFIG_X86_INTEL_USERCOPY
	/*
	 * Set up the preferred alignment for movsl bulk memory moves
	 */
	switch (c->x86) {
	case 4:		/* 486: untested */
		break;
	case 5:		/* Old Pentia: untested */
		break;
	case 6:		/* PII/PIII only like movsl with 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	case 15:	/* P4 is OK down to 8-byte alignment */
		movsl_mask.mask = 7;
		break;
	}
#endif

#ifdef CONFIG_X86_NUMAQ
	numaq_tsc_disable();
#endif

	intel_smp_check(c);
}
#else
static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
{
}
#endif

static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
{
#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	unsigned node;
	int cpu = smp_processor_id();
	int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;

	/* Don't do the funky fallback heuristics the AMD version employs
	   for now. */
	node = apicid_to_node[apicid];
	if (node == NUMA_NO_NODE)
		node = first_node(node_online_map);
	else if (!node_online(node)) {
		/* reuse the value from init_cpu_to_node() */
		node = cpu_to_node(cpu);
	}
	numa_set_node(cpu, node);
#endif
}

/*
 * find out the number of processor cores on the die
 */
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
{
	unsigned int eax, ebx, ecx, edx;

	if (c->cpuid_level < 4)
		return 1;

	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
	if (eax & 0x1f)
		return (eax >> 26) + 1;
	else
		return 1;
}

static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
{
	/* Intel VMX MSR indicated features */
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW	0x00200000
#define X86_VMX_FEATURE_PROC_CTLS_VNMI		0x00400000
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS	0x80000000
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC	0x00000001
#define X86_VMX_FEATURE_PROC_CTLS2_EPT		0x00000002
#define X86_VMX_FEATURE_PROC_CTLS2_VPID		0x00000020

	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;

	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	clear_cpu_cap(c, X86_FEATURE_VNMI);
	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	clear_cpu_cap(c, X86_FEATURE_EPT);
	clear_cpu_cap(c, X86_FEATURE_VPID);

	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	msr_ctl = vmx_msr_high | vmx_msr_low;
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
		set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
		set_cpu_cap(c, X86_FEATURE_VNMI);
	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
		rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
		      vmx_msr_low, vmx_msr_high);
		msr_ctl2 = vmx_msr_high | vmx_msr_low;
		if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
		    (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
			set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
			set_cpu_cap(c, X86_FEATURE_EPT);
		if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
			set_cpu_cap(c, X86_FEATURE_VPID);
	}
}

static void __cpuinit init_intel(struct cpuinfo_x86 *c)
{
	unsigned int l2 = 0;

	early_init_intel(c);

	intel_workarounds(c);

	/*
	 * Detect the extended topology information if available. This
	 * will reinitialise the initial_apicid which will be used
	 * in init_intel_cacheinfo()
	 */
	detect_extended_topology(c);

	l2 = init_intel_cacheinfo(c);
	if (c->cpuid_level > 9) {
		unsigned eax = cpuid_eax(10);
		/* Check for version and the number of counters */
		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
	}

	if (c->cpuid_level > 6) {
		unsigned ecx = cpuid_ecx(6);
		if (ecx & 0x01)
			set_cpu_cap(c, X86_FEATURE_APERFMPERF);
	}

	if (cpu_has_xmm2)
		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	if (cpu_has_ds) {
		unsigned int l1;
		rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
		if (!(l1 & (1<<11)))
			set_cpu_cap(c, X86_FEATURE_BTS);
		if (!(l1 & (1<<12)))
			set_cpu_cap(c, X86_FEATURE_PEBS);
		ds_init_intel(c);
	}

	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
		set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);

#ifdef CONFIG_X86_64
	if (c->x86 == 15)
		c->x86_cache_alignment = c->x86_clflush_size * 2;
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
#else
	/*
	 * Names for the Pentium II/Celeron processors
	 * detectable only by also checking the cache size.
	 * Dixon is NOT a Celeron.
	 */
	if (c->x86 == 6) {
		char *p = NULL;

		switch (c->x86_model) {
		case 5:
			if (c->x86_mask == 0) {
				if (l2 == 0)
					p = "Celeron (Covington)";
				else if (l2 == 256)
					p = "Mobile Pentium II (Dixon)";
			}
			break;

		case 6:
			if (l2 == 128)
				p = "Celeron (Mendocino)";
			else if (c->x86_mask == 0 || c->x86_mask == 5)
				p = "Celeron-A";
			break;

		case 8:
			if (l2 == 128)
				p = "Celeron (Coppermine)";
			break;
		}

		if (p)
			strcpy(c->x86_model_id, p);
	}

	if (c->x86 == 15)
		set_cpu_cap(c, X86_FEATURE_P4);
	if (c->x86 == 6)
		set_cpu_cap(c, X86_FEATURE_P3);
#endif

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
		/*
		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
		 * detection.
		 */
		c->x86_max_cores = intel_num_cpu_cores(c);
#ifdef CONFIG_X86_32
		detect_ht(c);
#endif
	}

	/* Work around errata */
	srat_detect_node(c);

	if (cpu_has(c, X86_FEATURE_VMX))
		detect_vmx_virtcap(c);
}

#ifdef CONFIG_X86_32
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
	/*
	 * Intel PIII Tualatin. This comes in two flavours.
	 * One has 256kb of cache, the other 512. We have no way
	 * to determine which, so we use a boottime override
	 * for the 512kb model, and assume 256 otherwise.
	 */
	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
		size = 256;
	return size;
}
#endif

static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
	.c_vendor	= "Intel",
	.c_ident	= { "GenuineIntel" },
#ifdef CONFIG_X86_32
	.c_models = {
		{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
		  {
			  [0] = "486 DX-25/33",
			  [1] = "486 DX-50",
			  [2] = "486 SX",
			  [3] = "486 DX/2",
			  [4] = "486 SL",
			  [5] = "486 SX/2",
			  [7] = "486 DX/2-WB",
			  [8] = "486 DX/4",
			  [9] = "486 DX/4-WB"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
		  {
			  [0] = "Pentium 60/66 A-step",
			  [1] = "Pentium 60/66",
			  [2] = "Pentium 75 - 200",
			  [3] = "OverDrive PODP5V83",
			  [4] = "Pentium MMX",
			  [7] = "Mobile Pentium 75 - 200",
			  [8] = "Mobile Pentium MMX"
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
		  {
			  [0] = "Pentium Pro A-step",
			  [1] = "Pentium Pro",
			  [3] = "Pentium II (Klamath)",
			  [4] = "Pentium II (Deschutes)",
			  [5] = "Pentium II (Deschutes)",
			  [6] = "Mobile Pentium II",
			  [7] = "Pentium III (Katmai)",
			  [8] = "Pentium III (Coppermine)",
			  [10] = "Pentium III (Cascades)",
			  [11] = "Pentium III (Tualatin)",
		  }
		},
		{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
		  {
			  [0] = "Pentium 4 (Unknown)",
			  [1] = "Pentium 4 (Willamette)",
			  [2] = "Pentium 4 (Northwood)",
			  [4] = "Pentium 4 (Foster)",
			  [5] = "Pentium 4 (Foster)",
		  }
		},
	},
	.c_size_cache	= intel_size_cache,
#endif
	.c_early_init   = early_init_intel,
	.c_init		= init_intel,
	.c_x86_vendor	= X86_VENDOR_INTEL,
};

cpu_dev_register(intel_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/kernel.h>
	3
	4	#include <linux/string.h>
	5	#include <linux/bitops.h>
	6	#include <linux/smp.h>
83ce4009	7	#include <linux/sched.h>
1da177e4	8	#include <linux/thread_info.h>
53e86b91	9	#include <linux/module.h>
8bdbd962	10	#include <linux/uaccess.h>
1da177e4 LT	11
1da177e4 LT	12	#include <asm/processor.h>
d72b1b4f	13	#include <asm/pgtable.h>
1da177e4	14	#include <asm/msr.h>
eee3af4a	15	#include <asm/ds.h>
73bdb73f	16	#include <asm/bugs.h>
1f442d70	17	#include <asm/cpu.h>
1da177e4	18
185f3b9d	19	#ifdef CONFIG_X86_64
8bdbd962	20	#include <linux/topology.h>
185f3b9d YL	21	#include <asm/numa_64.h>
	22	#endif
	23
1da177e4 LT	24	#include "cpu.h"
	25
	26	#ifdef CONFIG_X86_LOCAL_APIC
	27	#include <asm/mpspec.h>
	28	#include <asm/apic.h>
1da177e4 LT	29	#endif
1da177e4 LT	30
03ae5768	31	static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
1da177e4	32	{
99fb4d34	33	/* Unmask CPUID levels if masked: */
30a0fb94	34	if (c->x86 > 6 \|\| (c->x86 == 6 && c->x86_model >= 0xd)) {
99fb4d34	35	u64 misc_enable;
066941bd	36
99fb4d34 IM	37	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	38
	39	if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
	40	misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
	41	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	42	c->cpuid_level = cpuid_eax(0);
	43	}
066941bd PA	44	}
066941bd PA	45
2b16a235 AK	46	if ((c->x86 == 0xf && c->x86_model >= 0x03) \|\|
	47	(c->x86 == 0x6 && c->x86_model >= 0x0e))
	48	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d	49
7a0fc404 PA	50	/*
	51	* Atom erratum AAE44/AAF40/AAG38/AAH41:
	52	*
	53	* A race condition between speculative fetches and invalidating
	54	* a large page. This is worked around in microcode, but we
	55	* need the microcode to have already been loaded... so if it is
	56	* not, recommend a BIOS update and disable large pages.
	57	*/
	58	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
	59	u32 ucode, junk;
	60
	61	wrmsr(MSR_IA32_UCODE_REV, 0, 0);
	62	sync_core();
	63	rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
	64
	65	if (ucode < 0x20e) {
	66	printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
	67	clear_cpu_cap(c, X86_FEATURE_PSE);
	68	}
	69	}
	70
185f3b9d YL	71	#ifdef CONFIG_X86_64
	72	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
	73	#else
	74	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
	75	if (c->x86 == 15 && c->x86_cache_alignment == 64)
	76	c->x86_cache_alignment = 128;
	77	#endif
40fb1715	78
13c6c532 JB	79	/* CPUID workaround for 0F33/0F34 CPU */
	80	if (c->x86 == 0xF && c->x86_model == 0x3
	81	&& (c->x86_mask == 0x3 \|\| c->x86_mask == 0x4))
	82	c->x86_phys_bits = 36;
	83
40fb1715 VP	84	/*
40fb1715 VP	85	* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83ce4009 IM	86	* with P/T states and does not stop in deep C-states.
	87	*
	88	* It is also reliable across cores and sockets. (but not across
	89	* cabinets - we turn it off in that case explicitly.)
40fb1715 VP	90	*/
	91	if (c->x86_power & (1 << 8)) {
	92	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
	93	set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
14be1f74 DS	94	if (!check_tsc_unstable())
14be1f74 DS	95	sched_clock_stable = 1;
40fb1715 VP	96	}
40fb1715 VP	97
75a04811 PA	98	/*
	99	* There is a known erratum on Pentium III and Core Solo
	100	* and Core Duo CPUs.
	101	* " Page with PAT set to WC while associated MTRR is UC
	102	* may consolidate to UC "
	103	* Because of this erratum, it is better to stick with
	104	* setting WC in MTRR rather than using PAT on these CPUs.
	105	*
	106	* Enable PAT WC only on P4, Core 2 or later CPUs.
	107	*/
	108	if (c->x86 == 6 && c->x86_model < 15)
	109	clear_cpu_cap(c, X86_FEATURE_PAT);
f8561296 VN	110
	111	#ifdef CONFIG_KMEMCHECK
	112	/*
	113	* P4s have a "fast strings" feature which causes single-
	114	* stepping REP instructions to only generate a #DB on
	115	* cache-line boundaries.
	116	*
	117	* Ingo Molnar reported a Pentium D (model 6) and a Xeon
	118	* (model 2) with the same problem.
	119	*/
	120	if (c->x86 == 15) {
	121	u64 misc_enable;
	122
	123	rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	124
	125	if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
	126	printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
	127
	128	misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
	129	wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
	130	}
	131	}
	132	#endif
1da177e4 LT	133	}
1da177e4 LT	134
185f3b9d	135	#ifdef CONFIG_X86_32
1da177e4 LT	136	/*
	137	* Early probe support logic for ppro memory erratum #50
	138	*
	139	* This is called before we do cpu ident work
	140	*/
65eb6b43	141
3bc9b76b	142	int __cpuinit ppro_with_ram_bug(void)
1da177e4 LT	143	{
	144	/* Uses data from early_cpu_detect now */
	145	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	146	boot_cpu_data.x86 == 6 &&
	147	boot_cpu_data.x86_model == 1 &&
	148	boot_cpu_data.x86_mask < 8) {
	149	printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
	150	return 1;
	151	}
	152	return 0;
	153	}
65eb6b43	154
4052704d YL	155	#ifdef CONFIG_X86_F00F_BUG
	156	static void __cpuinit trap_init_f00f_bug(void)
	157	{
	158	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
1da177e4	159
4052704d YL	160	/*
	161	* Update the IDT descriptor and reload the IDT so that
	162	* it uses the read-only mapped virtual address.
	163	*/
	164	idt_descr.address = fix_to_virt(FIX_F00F_IDT);
	165	load_idt(&idt_descr);
	166	}
	167	#endif
	168
1f442d70 YL	169	static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
	170	{
	171	#ifdef CONFIG_SMP
	172	/* calling is from identify_secondary_cpu() ? */
	173	if (c->cpu_index == boot_cpu_id)
	174	return;
	175
	176	/*
	177	* Mask B, Pentium, but not Pentium MMX
	178	*/
	179	if (c->x86 == 5 &&
	180	c->x86_mask >= 1 && c->x86_mask <= 4 &&
	181	c->x86_model <= 3) {
	182	/*
	183	* Remember we have B step Pentia with bugs
	184	*/
	185	WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
	186	"with B stepping processors.\n");
	187	}
	188	#endif
	189	}
	190
4052704d	191	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 LT	192	{
	193	unsigned long lo, hi;
	194
4052704d YL	195	#ifdef CONFIG_X86_F00F_BUG
	196	/*
	197	* All current models of Pentium and Pentium with MMX technology CPUs
8bdbd962 AC	198	* have the F0 0F bug, which lets nonprivileged users lock up the
8bdbd962 AC	199	* system.
4052704d YL	200	* Note that the workaround only should be initialized once...
	201	*/
	202	c->f00f_bug = 0;
	203	if (!paravirt_enabled() && c->x86 == 5) {
	204	static int f00f_workaround_enabled;
	205
	206	c->f00f_bug = 1;
	207	if (!f00f_workaround_enabled) {
	208	trap_init_f00f_bug();
	209	printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
	210	f00f_workaround_enabled = 1;
	211	}
	212	}
	213	#endif
	214
	215	/*
	216	* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
	217	* model 3 mask 3
	218	*/
	219	if ((c->x86<<8 \| c->x86_model<<4 \| c->x86_mask) < 0x633)
	220	clear_cpu_cap(c, X86_FEATURE_SEP);
	221
	222	/*
	223	* P4 Xeon errata 037 workaround.
	224	* Hardware prefetcher may cause stale data to be loaded into the cache.
	225	*/
1da177e4	226	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
65eb6b43	227	rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
ecab22aa	228	if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
1da177e4 LT	229	printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
1da177e4 LT	230	printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
ecab22aa	231	lo \|= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
8bdbd962	232	wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
1da177e4 LT	233	}
1da177e4 LT	234	}
1da177e4	235
4052704d YL	236	/*
	237	* See if we have a good local APIC by checking for buggy Pentia,
	238	* i.e. all B steppings and the C2 stepping of P54C when using their
	239	* integrated APIC (see 11AP erratum in "Pentium Processor
	240	* Specification Update").
	241	*/
	242	if (cpu_has_apic && (c->x86<<8 \| c->x86_model<<4) == 0x520 &&
	243	(c->x86_mask < 0x6 \|\| c->x86_mask == 0xb))
	244	set_cpu_cap(c, X86_FEATURE_11AP);
185f3b9d	245
185f3b9d	246
4052704d	247	#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d	248	/*
4052704d	249	* Set up the preferred alignment for movsl bulk memory moves
185f3b9d	250	*/
4052704d YL	251	switch (c->x86) {
	252	case 4: /* 486: untested */
	253	break;
	254	case 5: /* Old Pentia: untested */
	255	break;
	256	case 6: /* PII/PIII only like movsl with 8-byte alignment */
	257	movsl_mask.mask = 7;
	258	break;
	259	case 15: /* P4 is OK down to 8-byte alignment */
	260	movsl_mask.mask = 7;
	261	break;
	262	}
185f3b9d	263	#endif
4052704d YL	264
	265	#ifdef CONFIG_X86_NUMAQ
	266	numaq_tsc_disable();
	267	#endif
1f442d70 YL	268
1f442d70 YL	269	intel_smp_check(c);
4052704d YL	270	}
	271	#else
	272	static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
	273	{
	274	}
185f3b9d YL	275	#endif
185f3b9d YL	276
2759c328	277	static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
185f3b9d YL	278	{
	279	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	280	unsigned node;
	281	int cpu = smp_processor_id();
2759c328	282	int apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
185f3b9d YL	283
	284	/* Don't do the funky fallback heuristics the AMD version employs
	285	for now. */
	286	node = apicid_to_node[apicid];
d9c2d5ac	287	if (node == NUMA_NO_NODE)
185f3b9d	288	node = first_node(node_online_map);
d9c2d5ac YL	289	else if (!node_online(node)) {
	290	/* reuse the value from init_cpu_to_node() */
	291	node = cpu_to_node(cpu);
	292	}
185f3b9d	293	numa_set_node(cpu, node);
185f3b9d YL	294	#endif
	295	}
	296
3dd9d514 AK	297	/*
	298	* find out the number of processor cores on the die
	299	*/
f69feff7	300	static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514	301	{
f2ab4461	302	unsigned int eax, ebx, ecx, edx;
3dd9d514 AK	303
	304	if (c->cpuid_level < 4)
	305	return 1;
	306
f2ab4461 ZA	307	/* Intel has a non-standard dependency on %ecx for this CPUID level. */
f2ab4461 ZA	308	cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514	309	if (eax & 0x1f)
8bdbd962	310	return (eax >> 26) + 1;
3dd9d514 AK	311	else
	312	return 1;
	313	}
	314
e38e05a8 SY	315	static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
	316	{
	317	/* Intel VMX MSR indicated features */
	318	#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
	319	#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
	320	#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
	321	#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
	322	#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
	323	#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
	324
	325	u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
	326
	327	clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	328	clear_cpu_cap(c, X86_FEATURE_VNMI);
	329	clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	330	clear_cpu_cap(c, X86_FEATURE_EPT);
	331	clear_cpu_cap(c, X86_FEATURE_VPID);
	332
	333	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
	334	msr_ctl = vmx_msr_high \| vmx_msr_low;
	335	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
	336	set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
	337	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
	338	set_cpu_cap(c, X86_FEATURE_VNMI);
	339	if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
	340	rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
	341	vmx_msr_low, vmx_msr_high);
	342	msr_ctl2 = vmx_msr_high \| vmx_msr_low;
	343	if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
	344	(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
	345	set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
	346	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
	347	set_cpu_cap(c, X86_FEATURE_EPT);
	348	if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
	349	set_cpu_cap(c, X86_FEATURE_VPID);
	350	}
	351	}
	352
3bc9b76b	353	static void __cpuinit init_intel(struct cpuinfo_x86 *c)
1da177e4 LT	354	{
1da177e4 LT	355	unsigned int l2 = 0;
1da177e4	356
2b16a235 AK	357	early_init_intel(c);
2b16a235 AK	358
4052704d	359	intel_workarounds(c);
1da177e4	360
345077cd SS	361	/*
	362	* Detect the extended topology information if available. This
	363	* will reinitialise the initial_apicid which will be used
	364	* in init_intel_cacheinfo()
	365	*/
	366	detect_extended_topology(c);
	367
1da177e4	368	l2 = init_intel_cacheinfo(c);
65eb6b43	369	if (c->cpuid_level > 9) {
0080e667 VP	370	unsigned eax = cpuid_eax(10);
	371	/* Check for version and the number of counters */
	372	if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd	373	set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667	374	}
1da177e4	375
a8303aaf PZ	376	if (c->cpuid_level > 6) {
	377	unsigned ecx = cpuid_ecx(6);
	378	if (ecx & 0x01)
	379	set_cpu_cap(c, X86_FEATURE_APERFMPERF);
	380	}
	381
4052704d YL	382	if (cpu_has_xmm2)
	383	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
	384	if (cpu_has_ds) {
	385	unsigned int l1;
	386	rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
	387	if (!(l1 & (1<<11)))
	388	set_cpu_cap(c, X86_FEATURE_BTS);
	389	if (!(l1 & (1<<12)))
	390	set_cpu_cap(c, X86_FEATURE_PEBS);
	391	ds_init_intel(c);
	392	}
1da177e4	393
e736ad54 PV	394	if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
	395	set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
	396
4052704d YL	397	#ifdef CONFIG_X86_64
	398	if (c->x86 == 15)
	399	c->x86_cache_alignment = c->x86_clflush_size * 2;
	400	if (c->x86 == 6)
	401	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
	402	#else
65eb6b43 PC	403	/*
	404	* Names for the Pentium II/Celeron processors
	405	* detectable only by also checking the cache size.
	406	* Dixon is NOT a Celeron.
	407	*/
1da177e4	408	if (c->x86 == 6) {
4052704d YL	409	char *p = NULL;
4052704d YL	410
1da177e4 LT	411	switch (c->x86_model) {
	412	case 5:
	413	if (c->x86_mask == 0) {
	414	if (l2 == 0)
	415	p = "Celeron (Covington)";
	416	else if (l2 == 256)
	417	p = "Mobile Pentium II (Dixon)";
	418	}
	419	break;
65eb6b43	420
1da177e4 LT	421	case 6:
	422	if (l2 == 128)
	423	p = "Celeron (Mendocino)";
	424	else if (c->x86_mask == 0 \|\| c->x86_mask == 5)
	425	p = "Celeron-A";
	426	break;
65eb6b43	427
1da177e4 LT	428	case 8:
	429	if (l2 == 128)
	430	p = "Celeron (Coppermine)";
	431	break;
	432	}
1da177e4	433
4052704d YL	434	if (p)
4052704d YL	435	strcpy(c->x86_model_id, p);
1da177e4	436	}
1da177e4	437
185f3b9d YL	438	if (c->x86 == 15)
	439	set_cpu_cap(c, X86_FEATURE_P4);
	440	if (c->x86 == 6)
	441	set_cpu_cap(c, X86_FEATURE_P3);
f4166c54	442	#endif
185f3b9d	443
185f3b9d YL	444	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
	445	/*
	446	* let's use the legacy cpuid vector 0x1 and 0x4 for topology
	447	* detection.
	448	*/
	449	c->x86_max_cores = intel_num_cpu_cores(c);
	450	#ifdef CONFIG_X86_32
	451	detect_ht(c);
	452	#endif
	453	}
	454
	455	/* Work around errata */
2759c328	456	srat_detect_node(c);
e38e05a8 SY	457
	458	if (cpu_has(c, X86_FEATURE_VMX))
	459	detect_vmx_virtcap(c);
42ed458a	460	}
1da177e4	461
185f3b9d	462	#ifdef CONFIG_X86_32
65eb6b43	463	static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4	464	{
65eb6b43 PC	465	/*
65eb6b43 PC	466	* Intel PIII Tualatin. This comes in two flavours.
1da177e4 LT	467	* One has 256kb of cache, the other 512. We have no way
	468	* to determine which, so we use a boottime override
	469	* for the 512kb model, and assume 256 otherwise.
	470	*/
	471	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
	472	size = 256;
	473	return size;
	474	}
185f3b9d	475	#endif
1da177e4	476
02dde8b4	477	static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
1da177e4	478	.c_vendor = "Intel",
65eb6b43	479	.c_ident = { "GenuineIntel" },
185f3b9d	480	#ifdef CONFIG_X86_32
1da177e4	481	.c_models = {
65eb6b43 PC	482	{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
	483	{
	484	[0] = "486 DX-25/33",
	485	[1] = "486 DX-50",
	486	[2] = "486 SX",
	487	[3] = "486 DX/2",
	488	[4] = "486 SL",
	489	[5] = "486 SX/2",
	490	[7] = "486 DX/2-WB",
	491	[8] = "486 DX/4",
1da177e4 LT	492	[9] = "486 DX/4-WB"
	493	}
	494	},
	495	{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
65eb6b43 PC	496	{
	497	[0] = "Pentium 60/66 A-step",
	498	[1] = "Pentium 60/66",
1da177e4	499	[2] = "Pentium 75 - 200",
65eb6b43	500	[3] = "OverDrive PODP5V83",
1da177e4	501	[4] = "Pentium MMX",
65eb6b43	502	[7] = "Mobile Pentium 75 - 200",
1da177e4 LT	503	[8] = "Mobile Pentium MMX"
	504	}
	505	},
	506	{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
65eb6b43	507	{
1da177e4	508	[0] = "Pentium Pro A-step",
65eb6b43 PC	509	[1] = "Pentium Pro",
	510	[3] = "Pentium II (Klamath)",
	511	[4] = "Pentium II (Deschutes)",
	512	[5] = "Pentium II (Deschutes)",
1da177e4	513	[6] = "Mobile Pentium II",
65eb6b43 PC	514	[7] = "Pentium III (Katmai)",
65eb6b43 PC	515	[8] = "Pentium III (Coppermine)",
1da177e4 LT	516	[10] = "Pentium III (Cascades)",
	517	[11] = "Pentium III (Tualatin)",
	518	}
	519	},
	520	{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
	521	{
	522	[0] = "Pentium 4 (Unknown)",
	523	[1] = "Pentium 4 (Willamette)",
	524	[2] = "Pentium 4 (Northwood)",
	525	[4] = "Pentium 4 (Foster)",
	526	[5] = "Pentium 4 (Foster)",
	527	}
	528	},
	529	},
185f3b9d YL	530	.c_size_cache = intel_size_cache,
185f3b9d YL	531	#endif
03ae5768	532	.c_early_init = early_init_intel,
1da177e4	533	.c_init = init_intel,
10a434fc	534	.c_x86_vendor = X86_VENDOR_INTEL,
1da177e4 LT	535	};
1da177e4 LT	536
10a434fc	537	cpu_dev_register(intel_cpu_dev);
1da177e4	538