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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | #include <linux/kernel.h> |
3 | ||
4 | #include <linux/string.h> | |
5 | #include <linux/bitops.h> | |
6 | #include <linux/smp.h> | |
83ce4009 | 7 | #include <linux/sched.h> |
e6017571 | 8 | #include <linux/sched/clock.h> |
1da177e4 | 9 | #include <linux/thread_info.h> |
186f4360 | 10 | #include <linux/init.h> |
8bdbd962 | 11 | #include <linux/uaccess.h> |
1da177e4 | 12 | |
cd4d09ec | 13 | #include <asm/cpufeature.h> |
d72b1b4f | 14 | #include <asm/pgtable.h> |
1da177e4 | 15 | #include <asm/msr.h> |
73bdb73f | 16 | #include <asm/bugs.h> |
1f442d70 | 17 | #include <asm/cpu.h> |
08e237fa | 18 | #include <asm/intel-family.h> |
4167709b | 19 | #include <asm/microcode_intel.h> |
e16fd002 GA |
20 | #include <asm/hwcap2.h> |
21 | #include <asm/elf.h> | |
1da177e4 | 22 | |
185f3b9d | 23 | #ifdef CONFIG_X86_64 |
8bdbd962 | 24 | #include <linux/topology.h> |
185f3b9d YL |
25 | #endif |
26 | ||
1da177e4 LT |
27 | #include "cpu.h" |
28 | ||
29 | #ifdef CONFIG_X86_LOCAL_APIC | |
30 | #include <asm/mpspec.h> | |
31 | #include <asm/apic.h> | |
1da177e4 LT |
32 | #endif |
33 | ||
0f6ff2bc DH |
34 | /* |
35 | * Just in case our CPU detection goes bad, or you have a weird system, | |
36 | * allow a way to override the automatic disabling of MPX. | |
37 | */ | |
38 | static int forcempx; | |
39 | ||
40 | static int __init forcempx_setup(char *__unused) | |
41 | { | |
42 | forcempx = 1; | |
43 | ||
44 | return 1; | |
45 | } | |
46 | __setup("intel-skd-046-workaround=disable", forcempx_setup); | |
47 | ||
48 | void check_mpx_erratum(struct cpuinfo_x86 *c) | |
49 | { | |
50 | if (forcempx) | |
51 | return; | |
52 | /* | |
53 | * Turn off the MPX feature on CPUs where SMEP is not | |
54 | * available or disabled. | |
55 | * | |
56 | * Works around Intel Erratum SKD046: "Branch Instructions | |
57 | * May Initialize MPX Bound Registers Incorrectly". | |
58 | * | |
59 | * This might falsely disable MPX on systems without | |
60 | * SMEP, like Atom processors without SMEP. But there | |
61 | * is no such hardware known at the moment. | |
62 | */ | |
63 | if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) { | |
64 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
65 | pr_warn("x86/mpx: Disabling MPX since SMEP not present\n"); | |
66 | } | |
67 | } | |
68 | ||
e16fd002 GA |
69 | static bool ring3mwait_disabled __read_mostly; |
70 | ||
71 | static int __init ring3mwait_disable(char *__unused) | |
72 | { | |
73 | ring3mwait_disabled = true; | |
74 | return 0; | |
75 | } | |
76 | __setup("ring3mwait=disable", ring3mwait_disable); | |
77 | ||
78 | static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) | |
79 | { | |
80 | /* | |
81 | * Ring 3 MONITOR/MWAIT feature cannot be detected without | |
82 | * cpu model and family comparison. | |
83 | */ | |
4d8bb006 | 84 | if (c->x86 != 6) |
e16fd002 | 85 | return; |
4d8bb006 PL |
86 | switch (c->x86_model) { |
87 | case INTEL_FAM6_XEON_PHI_KNL: | |
88 | case INTEL_FAM6_XEON_PHI_KNM: | |
89 | break; | |
90 | default: | |
91 | return; | |
92 | } | |
e16fd002 | 93 | |
e9ea1e7f | 94 | if (ring3mwait_disabled) |
e16fd002 | 95 | return; |
e16fd002 GA |
96 | |
97 | set_cpu_cap(c, X86_FEATURE_RING3MWAIT); | |
e9ea1e7f KH |
98 | this_cpu_or(msr_misc_features_shadow, |
99 | 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT); | |
e16fd002 GA |
100 | |
101 | if (c == &boot_cpu_data) | |
102 | ELF_HWCAP2 |= HWCAP2_RING3MWAIT; | |
103 | } | |
104 | ||
a5b29663 DW |
105 | /* |
106 | * Early microcode releases for the Spectre v2 mitigation were broken. | |
107 | * Information taken from; | |
e3b3121f | 108 | * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf |
a5b29663 DW |
109 | * - https://kb.vmware.com/s/article/52345 |
110 | * - Microcode revisions observed in the wild | |
111 | * - Release note from 20180108 microcode release | |
112 | */ | |
113 | struct sku_microcode { | |
114 | u8 model; | |
115 | u8 stepping; | |
116 | u32 microcode; | |
117 | }; | |
118 | static const struct sku_microcode spectre_bad_microcodes[] = { | |
d37fc6d3 DW |
119 | { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 }, |
120 | { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 }, | |
121 | { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 }, | |
122 | { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 }, | |
123 | { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 }, | |
a5b29663 DW |
124 | { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e }, |
125 | { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c }, | |
a5b29663 DW |
126 | { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 }, |
127 | { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b }, | |
128 | { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 }, | |
129 | { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 }, | |
130 | { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 }, | |
131 | { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 }, | |
132 | { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 }, | |
133 | { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 }, | |
134 | { INTEL_FAM6_HASWELL_X, 0x02, 0x3b }, | |
135 | { INTEL_FAM6_HASWELL_X, 0x04, 0x10 }, | |
136 | { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a }, | |
a5b29663 DW |
137 | /* Observed in the wild */ |
138 | { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b }, | |
139 | { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 }, | |
140 | }; | |
141 | ||
142 | static bool bad_spectre_microcode(struct cpuinfo_x86 *c) | |
143 | { | |
144 | int i; | |
145 | ||
36268223 KRW |
146 | /* |
147 | * We know that the hypervisor lie to us on the microcode version so | |
148 | * we may as well hope that it is running the correct version. | |
149 | */ | |
150 | if (cpu_has(c, X86_FEATURE_HYPERVISOR)) | |
151 | return false; | |
152 | ||
a5b29663 DW |
153 | for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { |
154 | if (c->x86_model == spectre_bad_microcodes[i].model && | |
b399151c | 155 | c->x86_stepping == spectre_bad_microcodes[i].stepping) |
a5b29663 DW |
156 | return (c->microcode <= spectre_bad_microcodes[i].microcode); |
157 | } | |
158 | return false; | |
159 | } | |
160 | ||
148f9bb8 | 161 | static void early_init_intel(struct cpuinfo_x86 *c) |
1da177e4 | 162 | { |
161ec53c FY |
163 | u64 misc_enable; |
164 | ||
99fb4d34 | 165 | /* Unmask CPUID levels if masked: */ |
30a0fb94 | 166 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { |
0b131be8 PA |
167 | if (msr_clear_bit(MSR_IA32_MISC_ENABLE, |
168 | MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { | |
99fb4d34 | 169 | c->cpuid_level = cpuid_eax(0); |
d900329e | 170 | get_cpu_cap(c); |
99fb4d34 | 171 | } |
066941bd PA |
172 | } |
173 | ||
2b16a235 AK |
174 | if ((c->x86 == 0xf && c->x86_model >= 0x03) || |
175 | (c->x86 == 0x6 && c->x86_model >= 0x0e)) | |
176 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
185f3b9d | 177 | |
4167709b BP |
178 | if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) |
179 | c->microcode = intel_get_microcode_revision(); | |
506ed6b5 | 180 | |
2961298e | 181 | /* Now if any of them are set, check the blacklist and clear the lot */ |
7fcae111 DW |
182 | if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || |
183 | cpu_has(c, X86_FEATURE_INTEL_STIBP) || | |
184 | cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || | |
2961298e DW |
185 | cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { |
186 | pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); | |
7fcae111 DW |
187 | setup_clear_cpu_cap(X86_FEATURE_IBRS); |
188 | setup_clear_cpu_cap(X86_FEATURE_IBPB); | |
189 | setup_clear_cpu_cap(X86_FEATURE_STIBP); | |
190 | setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL); | |
7eb8956a | 191 | setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 192 | setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP); |
9f65fb29 | 193 | setup_clear_cpu_cap(X86_FEATURE_SSBD); |
a5b29663 DW |
194 | } |
195 | ||
7a0fc404 PA |
196 | /* |
197 | * Atom erratum AAE44/AAF40/AAG38/AAH41: | |
198 | * | |
199 | * A race condition between speculative fetches and invalidating | |
200 | * a large page. This is worked around in microcode, but we | |
201 | * need the microcode to have already been loaded... so if it is | |
202 | * not, recommend a BIOS update and disable large pages. | |
203 | */ | |
b399151c | 204 | if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && |
30963c0a | 205 | c->microcode < 0x20e) { |
1b74dde7 | 206 | pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); |
30963c0a | 207 | clear_cpu_cap(c, X86_FEATURE_PSE); |
7a0fc404 PA |
208 | } |
209 | ||
185f3b9d YL |
210 | #ifdef CONFIG_X86_64 |
211 | set_cpu_cap(c, X86_FEATURE_SYSENTER32); | |
212 | #else | |
213 | /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ | |
214 | if (c->x86 == 15 && c->x86_cache_alignment == 64) | |
215 | c->x86_cache_alignment = 128; | |
216 | #endif | |
40fb1715 | 217 | |
13c6c532 JB |
218 | /* CPUID workaround for 0F33/0F34 CPU */ |
219 | if (c->x86 == 0xF && c->x86_model == 0x3 | |
b399151c | 220 | && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) |
13c6c532 JB |
221 | c->x86_phys_bits = 36; |
222 | ||
40fb1715 VP |
223 | /* |
224 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
83ce4009 IM |
225 | * with P/T states and does not stop in deep C-states. |
226 | * | |
227 | * It is also reliable across cores and sockets. (but not across | |
228 | * cabinets - we turn it off in that case explicitly.) | |
40fb1715 VP |
229 | */ |
230 | if (c->x86_power & (1 << 8)) { | |
231 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); | |
232 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); | |
233 | } | |
234 | ||
c54fdbb2 FT |
235 | /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ |
236 | if (c->x86 == 6) { | |
237 | switch (c->x86_model) { | |
238 | case 0x27: /* Penwell */ | |
239 | case 0x35: /* Cloverview */ | |
354dbaa7 | 240 | case 0x4a: /* Merrifield */ |
c54fdbb2 FT |
241 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); |
242 | break; | |
243 | default: | |
244 | break; | |
245 | } | |
246 | } | |
247 | ||
75a04811 PA |
248 | /* |
249 | * There is a known erratum on Pentium III and Core Solo | |
250 | * and Core Duo CPUs. | |
251 | * " Page with PAT set to WC while associated MTRR is UC | |
252 | * may consolidate to UC " | |
253 | * Because of this erratum, it is better to stick with | |
254 | * setting WC in MTRR rather than using PAT on these CPUs. | |
255 | * | |
256 | * Enable PAT WC only on P4, Core 2 or later CPUs. | |
257 | */ | |
258 | if (c->x86 == 6 && c->x86_model < 15) | |
259 | clear_cpu_cap(c, X86_FEATURE_PAT); | |
f8561296 | 260 | |
161ec53c FY |
261 | /* |
262 | * If fast string is not enabled in IA32_MISC_ENABLE for any reason, | |
263 | * clear the fast string and enhanced fast string CPU capabilities. | |
264 | */ | |
265 | if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { | |
266 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); | |
267 | if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { | |
1b74dde7 | 268 | pr_info("Disabled fast string operations\n"); |
161ec53c FY |
269 | setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); |
270 | setup_clear_cpu_cap(X86_FEATURE_ERMS); | |
271 | } | |
272 | } | |
ee1b5b16 BD |
273 | |
274 | /* | |
275 | * Intel Quark Core DevMan_001.pdf section 6.4.11 | |
276 | * "The operating system also is required to invalidate (i.e., flush) | |
277 | * the TLB when any changes are made to any of the page table entries. | |
278 | * The operating system must reload CR3 to cause the TLB to be flushed" | |
279 | * | |
c109bf95 BP |
280 | * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h |
281 | * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE | |
282 | * to be modified. | |
ee1b5b16 BD |
283 | */ |
284 | if (c->x86 == 5 && c->x86_model == 9) { | |
285 | pr_info("Disabling PGE capability bit\n"); | |
286 | setup_clear_cpu_cap(X86_FEATURE_PGE); | |
287 | } | |
1f12e32f TG |
288 | |
289 | if (c->cpuid_level >= 0x00000001) { | |
290 | u32 eax, ebx, ecx, edx; | |
291 | ||
292 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); | |
293 | /* | |
294 | * If HTT (EDX[28]) is set EBX[16:23] contain the number of | |
295 | * apicids which are reserved per package. Store the resulting | |
296 | * shift value for the package management code. | |
297 | */ | |
298 | if (edx & (1U << 28)) | |
299 | c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); | |
300 | } | |
0f6ff2bc DH |
301 | |
302 | check_mpx_erratum(c); | |
1da177e4 LT |
303 | } |
304 | ||
185f3b9d | 305 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
306 | /* |
307 | * Early probe support logic for ppro memory erratum #50 | |
308 | * | |
309 | * This is called before we do cpu ident work | |
310 | */ | |
65eb6b43 | 311 | |
148f9bb8 | 312 | int ppro_with_ram_bug(void) |
1da177e4 LT |
313 | { |
314 | /* Uses data from early_cpu_detect now */ | |
315 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
316 | boot_cpu_data.x86 == 6 && | |
317 | boot_cpu_data.x86_model == 1 && | |
b399151c | 318 | boot_cpu_data.x86_stepping < 8) { |
1b74dde7 | 319 | pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n"); |
1da177e4 LT |
320 | return 1; |
321 | } | |
322 | return 0; | |
323 | } | |
65eb6b43 | 324 | |
148f9bb8 | 325 | static void intel_smp_check(struct cpuinfo_x86 *c) |
1f442d70 | 326 | { |
1f442d70 | 327 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 328 | if (!c->cpu_index) |
1f442d70 YL |
329 | return; |
330 | ||
331 | /* | |
332 | * Mask B, Pentium, but not Pentium MMX | |
333 | */ | |
334 | if (c->x86 == 5 && | |
b399151c | 335 | c->x86_stepping >= 1 && c->x86_stepping <= 4 && |
1f442d70 YL |
336 | c->x86_model <= 3) { |
337 | /* | |
338 | * Remember we have B step Pentia with bugs | |
339 | */ | |
340 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | |
341 | "with B stepping processors.\n"); | |
342 | } | |
1f442d70 YL |
343 | } |
344 | ||
69f2366c CB |
345 | static int forcepae; |
346 | static int __init forcepae_setup(char *__unused) | |
347 | { | |
348 | forcepae = 1; | |
349 | return 1; | |
350 | } | |
351 | __setup("forcepae", forcepae_setup); | |
352 | ||
148f9bb8 | 353 | static void intel_workarounds(struct cpuinfo_x86 *c) |
1da177e4 | 354 | { |
4052704d YL |
355 | #ifdef CONFIG_X86_F00F_BUG |
356 | /* | |
d4e1a0af | 357 | * All models of Pentium and Pentium with MMX technology CPUs |
8bdbd962 | 358 | * have the F0 0F bug, which lets nonprivileged users lock up the |
4eefbe79 | 359 | * system. Announce that the fault handler will be checking for it. |
d4e1a0af | 360 | * The Quark is also family 5, but does not have the same bug. |
4052704d | 361 | */ |
e2604b49 | 362 | clear_cpu_bug(c, X86_BUG_F00F); |
fa392794 | 363 | if (c->x86 == 5 && c->x86_model < 9) { |
4052704d YL |
364 | static int f00f_workaround_enabled; |
365 | ||
e2604b49 | 366 | set_cpu_bug(c, X86_BUG_F00F); |
4052704d | 367 | if (!f00f_workaround_enabled) { |
1b74dde7 | 368 | pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); |
4052704d YL |
369 | f00f_workaround_enabled = 1; |
370 | } | |
371 | } | |
372 | #endif | |
373 | ||
374 | /* | |
375 | * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until | |
376 | * model 3 mask 3 | |
377 | */ | |
b399151c | 378 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) |
4052704d YL |
379 | clear_cpu_cap(c, X86_FEATURE_SEP); |
380 | ||
69f2366c CB |
381 | /* |
382 | * PAE CPUID issue: many Pentium M report no PAE but may have a | |
383 | * functionally usable PAE implementation. | |
384 | * Forcefully enable PAE if kernel parameter "forcepae" is present. | |
385 | */ | |
386 | if (forcepae) { | |
1b74dde7 | 387 | pr_warn("PAE forced!\n"); |
69f2366c CB |
388 | set_cpu_cap(c, X86_FEATURE_PAE); |
389 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); | |
390 | } | |
391 | ||
4052704d | 392 | /* |
f0133acc | 393 | * P4 Xeon erratum 037 workaround. |
4052704d YL |
394 | * Hardware prefetcher may cause stale data to be loaded into the cache. |
395 | */ | |
b399151c | 396 | if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { |
0b131be8 | 397 | if (msr_set_bit(MSR_IA32_MISC_ENABLE, |
f0133acc | 398 | MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) { |
c0a639ad | 399 | pr_info("CPU: C0 stepping P4 Xeon detected.\n"); |
f0133acc | 400 | pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n"); |
1da177e4 LT |
401 | } |
402 | } | |
1da177e4 | 403 | |
4052704d YL |
404 | /* |
405 | * See if we have a good local APIC by checking for buggy Pentia, | |
406 | * i.e. all B steppings and the C2 stepping of P54C when using their | |
407 | * integrated APIC (see 11AP erratum in "Pentium Processor | |
408 | * Specification Update"). | |
409 | */ | |
93984fbd | 410 | if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && |
b399151c | 411 | (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) |
9b13a93d | 412 | set_cpu_bug(c, X86_BUG_11AP); |
185f3b9d | 413 | |
185f3b9d | 414 | |
4052704d | 415 | #ifdef CONFIG_X86_INTEL_USERCOPY |
185f3b9d | 416 | /* |
4052704d | 417 | * Set up the preferred alignment for movsl bulk memory moves |
185f3b9d | 418 | */ |
4052704d YL |
419 | switch (c->x86) { |
420 | case 4: /* 486: untested */ | |
421 | break; | |
422 | case 5: /* Old Pentia: untested */ | |
423 | break; | |
424 | case 6: /* PII/PIII only like movsl with 8-byte alignment */ | |
425 | movsl_mask.mask = 7; | |
426 | break; | |
427 | case 15: /* P4 is OK down to 8-byte alignment */ | |
428 | movsl_mask.mask = 7; | |
429 | break; | |
430 | } | |
185f3b9d | 431 | #endif |
4052704d | 432 | |
1f442d70 | 433 | intel_smp_check(c); |
4052704d YL |
434 | } |
435 | #else | |
148f9bb8 | 436 | static void intel_workarounds(struct cpuinfo_x86 *c) |
4052704d YL |
437 | { |
438 | } | |
185f3b9d YL |
439 | #endif |
440 | ||
148f9bb8 | 441 | static void srat_detect_node(struct cpuinfo_x86 *c) |
185f3b9d | 442 | { |
645a7919 | 443 | #ifdef CONFIG_NUMA |
185f3b9d YL |
444 | unsigned node; |
445 | int cpu = smp_processor_id(); | |
185f3b9d YL |
446 | |
447 | /* Don't do the funky fallback heuristics the AMD version employs | |
448 | for now. */ | |
bbc9e2f4 | 449 | node = numa_cpu_node(cpu); |
50f2d7f6 | 450 | if (node == NUMA_NO_NODE || !node_online(node)) { |
d9c2d5ac YL |
451 | /* reuse the value from init_cpu_to_node() */ |
452 | node = cpu_to_node(cpu); | |
453 | } | |
185f3b9d | 454 | numa_set_node(cpu, node); |
185f3b9d YL |
455 | #endif |
456 | } | |
457 | ||
3dd9d514 AK |
458 | /* |
459 | * find out the number of processor cores on the die | |
460 | */ | |
148f9bb8 | 461 | static int intel_num_cpu_cores(struct cpuinfo_x86 *c) |
3dd9d514 | 462 | { |
f2ab4461 | 463 | unsigned int eax, ebx, ecx, edx; |
3dd9d514 | 464 | |
8d415ee2 | 465 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
3dd9d514 AK |
466 | return 1; |
467 | ||
f2ab4461 ZA |
468 | /* Intel has a non-standard dependency on %ecx for this CPUID level. */ |
469 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
3dd9d514 | 470 | if (eax & 0x1f) |
8bdbd962 | 471 | return (eax >> 26) + 1; |
3dd9d514 AK |
472 | else |
473 | return 1; | |
474 | } | |
475 | ||
148f9bb8 | 476 | static void detect_vmx_virtcap(struct cpuinfo_x86 *c) |
e38e05a8 SY |
477 | { |
478 | /* Intel VMX MSR indicated features */ | |
479 | #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 | |
480 | #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 | |
481 | #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 | |
482 | #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 | |
483 | #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 | |
484 | #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 | |
485 | ||
486 | u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; | |
487 | ||
488 | clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
489 | clear_cpu_cap(c, X86_FEATURE_VNMI); | |
490 | clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
491 | clear_cpu_cap(c, X86_FEATURE_EPT); | |
492 | clear_cpu_cap(c, X86_FEATURE_VPID); | |
493 | ||
494 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); | |
495 | msr_ctl = vmx_msr_high | vmx_msr_low; | |
496 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) | |
497 | set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); | |
498 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) | |
499 | set_cpu_cap(c, X86_FEATURE_VNMI); | |
500 | if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { | |
501 | rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, | |
502 | vmx_msr_low, vmx_msr_high); | |
503 | msr_ctl2 = vmx_msr_high | vmx_msr_low; | |
504 | if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && | |
505 | (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) | |
506 | set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); | |
507 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) | |
508 | set_cpu_cap(c, X86_FEATURE_EPT); | |
509 | if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) | |
510 | set_cpu_cap(c, X86_FEATURE_VPID); | |
511 | } | |
512 | } | |
513 | ||
cb06d8e3 KS |
514 | #define MSR_IA32_TME_ACTIVATE 0x982 |
515 | ||
516 | /* Helpers to access TME_ACTIVATE MSR */ | |
517 | #define TME_ACTIVATE_LOCKED(x) (x & 0x1) | |
518 | #define TME_ACTIVATE_ENABLED(x) (x & 0x2) | |
519 | ||
520 | #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */ | |
521 | #define TME_ACTIVATE_POLICY_AES_XTS_128 0 | |
522 | ||
523 | #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */ | |
524 | ||
525 | #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */ | |
526 | #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1 | |
527 | ||
528 | /* Values for mktme_status (SW only construct) */ | |
529 | #define MKTME_ENABLED 0 | |
530 | #define MKTME_DISABLED 1 | |
531 | #define MKTME_UNINITIALIZED 2 | |
532 | static int mktme_status = MKTME_UNINITIALIZED; | |
533 | ||
534 | static void detect_tme(struct cpuinfo_x86 *c) | |
535 | { | |
536 | u64 tme_activate, tme_policy, tme_crypto_algs; | |
537 | int keyid_bits = 0, nr_keyids = 0; | |
538 | static u64 tme_activate_cpu0 = 0; | |
539 | ||
540 | rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate); | |
541 | ||
542 | if (mktme_status != MKTME_UNINITIALIZED) { | |
543 | if (tme_activate != tme_activate_cpu0) { | |
544 | /* Broken BIOS? */ | |
eaeb8e76 | 545 | pr_err_once("x86/tme: configuration is inconsistent between CPUs\n"); |
cb06d8e3 KS |
546 | pr_err_once("x86/tme: MKTME is not usable\n"); |
547 | mktme_status = MKTME_DISABLED; | |
548 | ||
549 | /* Proceed. We may need to exclude bits from x86_phys_bits. */ | |
550 | } | |
551 | } else { | |
552 | tme_activate_cpu0 = tme_activate; | |
553 | } | |
554 | ||
555 | if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) { | |
556 | pr_info_once("x86/tme: not enabled by BIOS\n"); | |
557 | mktme_status = MKTME_DISABLED; | |
558 | return; | |
559 | } | |
560 | ||
561 | if (mktme_status != MKTME_UNINITIALIZED) | |
562 | goto detect_keyid_bits; | |
563 | ||
564 | pr_info("x86/tme: enabled by BIOS\n"); | |
565 | ||
566 | tme_policy = TME_ACTIVATE_POLICY(tme_activate); | |
567 | if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128) | |
568 | pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy); | |
569 | ||
570 | tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate); | |
571 | if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) { | |
572 | pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n", | |
573 | tme_crypto_algs); | |
574 | mktme_status = MKTME_DISABLED; | |
575 | } | |
576 | detect_keyid_bits: | |
577 | keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate); | |
578 | nr_keyids = (1UL << keyid_bits) - 1; | |
579 | if (nr_keyids) { | |
580 | pr_info_once("x86/mktme: enabled by BIOS\n"); | |
581 | pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids); | |
582 | } else { | |
583 | pr_info_once("x86/mktme: disabled by BIOS\n"); | |
584 | } | |
585 | ||
586 | if (mktme_status == MKTME_UNINITIALIZED) { | |
587 | /* MKTME is usable */ | |
588 | mktme_status = MKTME_ENABLED; | |
589 | } | |
590 | ||
591 | /* | |
547edaca KS |
592 | * KeyID bits effectively lower the number of physical address |
593 | * bits. Update cpuinfo_x86::x86_phys_bits accordingly. | |
cb06d8e3 KS |
594 | */ |
595 | c->x86_phys_bits -= keyid_bits; | |
596 | } | |
597 | ||
b51ef52d LA |
598 | static void init_intel_energy_perf(struct cpuinfo_x86 *c) |
599 | { | |
600 | u64 epb; | |
601 | ||
602 | /* | |
603 | * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized. | |
604 | * (x86_energy_perf_policy(8) is available to change it at run-time.) | |
605 | */ | |
606 | if (!cpu_has(c, X86_FEATURE_EPB)) | |
607 | return; | |
608 | ||
609 | rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
610 | if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE) | |
611 | return; | |
612 | ||
613 | pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); | |
614 | pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n"); | |
615 | epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; | |
616 | wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); | |
617 | } | |
618 | ||
619 | static void intel_bsp_resume(struct cpuinfo_x86 *c) | |
620 | { | |
621 | /* | |
622 | * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume, | |
623 | * so reinitialize it properly like during bootup: | |
624 | */ | |
625 | init_intel_energy_perf(c); | |
626 | } | |
627 | ||
90218ac7 KH |
628 | static void init_cpuid_fault(struct cpuinfo_x86 *c) |
629 | { | |
630 | u64 msr; | |
631 | ||
632 | if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { | |
633 | if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) | |
634 | set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); | |
635 | } | |
636 | } | |
637 | ||
638 | static void init_intel_misc_features(struct cpuinfo_x86 *c) | |
639 | { | |
640 | u64 msr; | |
641 | ||
642 | if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) | |
643 | return; | |
644 | ||
e9ea1e7f KH |
645 | /* Clear all MISC features */ |
646 | this_cpu_write(msr_misc_features_shadow, 0); | |
647 | ||
648 | /* Check features and update capabilities and shadow control bits */ | |
90218ac7 KH |
649 | init_cpuid_fault(c); |
650 | probe_xeon_phi_r3mwait(c); | |
e9ea1e7f KH |
651 | |
652 | msr = this_cpu_read(msr_misc_features_shadow); | |
653 | wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); | |
90218ac7 KH |
654 | } |
655 | ||
148f9bb8 | 656 | static void init_intel(struct cpuinfo_x86 *c) |
1da177e4 LT |
657 | { |
658 | unsigned int l2 = 0; | |
1da177e4 | 659 | |
2b16a235 AK |
660 | early_init_intel(c); |
661 | ||
4052704d | 662 | intel_workarounds(c); |
1da177e4 | 663 | |
345077cd SS |
664 | /* |
665 | * Detect the extended topology information if available. This | |
666 | * will reinitialise the initial_apicid which will be used | |
667 | * in init_intel_cacheinfo() | |
668 | */ | |
669 | detect_extended_topology(c); | |
670 | ||
2a226155 PZ |
671 | if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { |
672 | /* | |
673 | * let's use the legacy cpuid vector 0x1 and 0x4 for topology | |
674 | * detection. | |
675 | */ | |
676 | c->x86_max_cores = intel_num_cpu_cores(c); | |
677 | #ifdef CONFIG_X86_32 | |
678 | detect_ht(c); | |
679 | #endif | |
680 | } | |
681 | ||
1da177e4 | 682 | l2 = init_intel_cacheinfo(c); |
aece118e BD |
683 | |
684 | /* Detect legacy cache sizes if init_intel_cacheinfo did not */ | |
685 | if (l2 == 0) { | |
686 | cpu_detect_cache_sizes(c); | |
687 | l2 = c->x86_cache_size; | |
688 | } | |
689 | ||
65eb6b43 | 690 | if (c->cpuid_level > 9) { |
0080e667 VP |
691 | unsigned eax = cpuid_eax(10); |
692 | /* Check for version and the number of counters */ | |
693 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | |
d0e95ebd | 694 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
0080e667 | 695 | } |
1da177e4 | 696 | |
054efb64 | 697 | if (cpu_has(c, X86_FEATURE_XMM2)) |
4052704d | 698 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
362f924b BP |
699 | |
700 | if (boot_cpu_has(X86_FEATURE_DS)) { | |
4052704d YL |
701 | unsigned int l1; |
702 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | |
703 | if (!(l1 & (1<<11))) | |
704 | set_cpu_cap(c, X86_FEATURE_BTS); | |
705 | if (!(l1 & (1<<12))) | |
706 | set_cpu_cap(c, X86_FEATURE_PEBS); | |
4052704d | 707 | } |
1da177e4 | 708 | |
906bf7fd | 709 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && |
40e2d7f9 | 710 | (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) |
9b13a93d | 711 | set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); |
e736ad54 | 712 | |
08e237fa PZ |
713 | if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && |
714 | ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) | |
715 | set_cpu_bug(c, X86_BUG_MONITOR); | |
716 | ||
4052704d YL |
717 | #ifdef CONFIG_X86_64 |
718 | if (c->x86 == 15) | |
719 | c->x86_cache_alignment = c->x86_clflush_size * 2; | |
720 | if (c->x86 == 6) | |
721 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
722 | #else | |
65eb6b43 PC |
723 | /* |
724 | * Names for the Pentium II/Celeron processors | |
725 | * detectable only by also checking the cache size. | |
726 | * Dixon is NOT a Celeron. | |
727 | */ | |
1da177e4 | 728 | if (c->x86 == 6) { |
4052704d YL |
729 | char *p = NULL; |
730 | ||
1da177e4 LT |
731 | switch (c->x86_model) { |
732 | case 5: | |
865be7a8 OZ |
733 | if (l2 == 0) |
734 | p = "Celeron (Covington)"; | |
735 | else if (l2 == 256) | |
736 | p = "Mobile Pentium II (Dixon)"; | |
1da177e4 | 737 | break; |
65eb6b43 | 738 | |
1da177e4 LT |
739 | case 6: |
740 | if (l2 == 128) | |
741 | p = "Celeron (Mendocino)"; | |
b399151c | 742 | else if (c->x86_stepping == 0 || c->x86_stepping == 5) |
1da177e4 LT |
743 | p = "Celeron-A"; |
744 | break; | |
65eb6b43 | 745 | |
1da177e4 LT |
746 | case 8: |
747 | if (l2 == 128) | |
748 | p = "Celeron (Coppermine)"; | |
749 | break; | |
750 | } | |
1da177e4 | 751 | |
4052704d YL |
752 | if (p) |
753 | strcpy(c->x86_model_id, p); | |
1da177e4 | 754 | } |
1da177e4 | 755 | |
185f3b9d YL |
756 | if (c->x86 == 15) |
757 | set_cpu_cap(c, X86_FEATURE_P4); | |
758 | if (c->x86 == 6) | |
759 | set_cpu_cap(c, X86_FEATURE_P3); | |
f4166c54 | 760 | #endif |
185f3b9d | 761 | |
185f3b9d | 762 | /* Work around errata */ |
2759c328 | 763 | srat_detect_node(c); |
e38e05a8 SY |
764 | |
765 | if (cpu_has(c, X86_FEATURE_VMX)) | |
766 | detect_vmx_virtcap(c); | |
abe48b10 | 767 | |
cb06d8e3 KS |
768 | if (cpu_has(c, X86_FEATURE_TME)) |
769 | detect_tme(c); | |
770 | ||
b51ef52d | 771 | init_intel_energy_perf(c); |
e16fd002 | 772 | |
90218ac7 | 773 | init_intel_misc_features(c); |
42ed458a | 774 | } |
1da177e4 | 775 | |
185f3b9d | 776 | #ifdef CONFIG_X86_32 |
148f9bb8 | 777 | static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 | 778 | { |
65eb6b43 PC |
779 | /* |
780 | * Intel PIII Tualatin. This comes in two flavours. | |
1da177e4 LT |
781 | * One has 256kb of cache, the other 512. We have no way |
782 | * to determine which, so we use a boottime override | |
783 | * for the 512kb model, and assume 256 otherwise. | |
784 | */ | |
785 | if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) | |
786 | size = 256; | |
aece118e BD |
787 | |
788 | /* | |
789 | * Intel Quark SoC X1000 contains a 4-way set associative | |
790 | * 16K cache with a 16 byte cache line and 256 lines per tag | |
791 | */ | |
792 | if ((c->x86 == 5) && (c->x86_model == 9)) | |
793 | size = 16; | |
1da177e4 LT |
794 | return size; |
795 | } | |
185f3b9d | 796 | #endif |
1da177e4 | 797 | |
e0ba94f1 AS |
798 | #define TLB_INST_4K 0x01 |
799 | #define TLB_INST_4M 0x02 | |
800 | #define TLB_INST_2M_4M 0x03 | |
801 | ||
802 | #define TLB_INST_ALL 0x05 | |
803 | #define TLB_INST_1G 0x06 | |
804 | ||
805 | #define TLB_DATA_4K 0x11 | |
806 | #define TLB_DATA_4M 0x12 | |
807 | #define TLB_DATA_2M_4M 0x13 | |
808 | #define TLB_DATA_4K_4M 0x14 | |
809 | ||
810 | #define TLB_DATA_1G 0x16 | |
811 | ||
812 | #define TLB_DATA0_4K 0x21 | |
813 | #define TLB_DATA0_4M 0x22 | |
814 | #define TLB_DATA0_2M_4M 0x23 | |
815 | ||
816 | #define STLB_4K 0x41 | |
dd360393 | 817 | #define STLB_4K_2M 0x42 |
e0ba94f1 | 818 | |
148f9bb8 | 819 | static const struct _tlb_table intel_tlb_table[] = { |
e0ba94f1 AS |
820 | { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, |
821 | { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, | |
822 | { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
823 | { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
824 | { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, | |
825 | { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, | |
826 | { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, | |
827 | { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
828 | { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
829 | { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, | |
830 | { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, | |
831 | { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, | |
832 | { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, | |
833 | { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, | |
834 | { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, | |
835 | { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
836 | { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
837 | { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, | |
dd360393 KS |
838 | { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, |
839 | { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, | |
b837913f | 840 | { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, |
841 | { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, | |
842 | { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, | |
dd360393 | 843 | { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, |
e0ba94f1 AS |
844 | { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, |
845 | { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, | |
846 | { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, | |
847 | { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, | |
848 | { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, | |
a927792c YG |
849 | { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" }, |
850 | { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" }, | |
e0ba94f1 AS |
851 | { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, |
852 | { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, | |
dd360393 KS |
853 | { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, |
854 | { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, | |
e0ba94f1 AS |
855 | { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, |
856 | { 0x00, 0, 0 } | |
857 | }; | |
858 | ||
148f9bb8 | 859 | static void intel_tlb_lookup(const unsigned char desc) |
e0ba94f1 AS |
860 | { |
861 | unsigned char k; | |
862 | if (desc == 0) | |
863 | return; | |
864 | ||
865 | /* look up this descriptor in the table */ | |
866 | for (k = 0; intel_tlb_table[k].descriptor != desc && \ | |
867 | intel_tlb_table[k].descriptor != 0; k++) | |
868 | ; | |
869 | ||
870 | if (intel_tlb_table[k].tlb_type == 0) | |
871 | return; | |
872 | ||
873 | switch (intel_tlb_table[k].tlb_type) { | |
874 | case STLB_4K: | |
875 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
876 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
877 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
878 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
879 | break; | |
dd360393 KS |
880 | case STLB_4K_2M: |
881 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
882 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
883 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
884 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
885 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
886 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
887 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
888 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
889 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
890 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
891 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
892 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
893 | break; | |
e0ba94f1 AS |
894 | case TLB_INST_ALL: |
895 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
896 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
897 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
898 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
899 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
900 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
901 | break; | |
902 | case TLB_INST_4K: | |
903 | if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) | |
904 | tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; | |
905 | break; | |
906 | case TLB_INST_4M: | |
907 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
908 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
909 | break; | |
910 | case TLB_INST_2M_4M: | |
911 | if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) | |
912 | tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; | |
913 | if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) | |
914 | tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; | |
915 | break; | |
916 | case TLB_DATA_4K: | |
917 | case TLB_DATA0_4K: | |
918 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
919 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
920 | break; | |
921 | case TLB_DATA_4M: | |
922 | case TLB_DATA0_4M: | |
923 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
924 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
925 | break; | |
926 | case TLB_DATA_2M_4M: | |
927 | case TLB_DATA0_2M_4M: | |
928 | if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) | |
929 | tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; | |
930 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
931 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
932 | break; | |
933 | case TLB_DATA_4K_4M: | |
934 | if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) | |
935 | tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; | |
936 | if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) | |
937 | tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; | |
938 | break; | |
dd360393 KS |
939 | case TLB_DATA_1G: |
940 | if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) | |
941 | tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; | |
e0ba94f1 AS |
942 | break; |
943 | } | |
944 | } | |
945 | ||
148f9bb8 | 946 | static void intel_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
947 | { |
948 | int i, j, n; | |
949 | unsigned int regs[4]; | |
950 | unsigned char *desc = (unsigned char *)regs; | |
5b556332 BP |
951 | |
952 | if (c->cpuid_level < 2) | |
953 | return; | |
954 | ||
e0ba94f1 AS |
955 | /* Number of times to iterate */ |
956 | n = cpuid_eax(2) & 0xFF; | |
957 | ||
958 | for (i = 0 ; i < n ; i++) { | |
959 | cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); | |
960 | ||
961 | /* If bit 31 is set, this is an unknown format */ | |
962 | for (j = 0 ; j < 3 ; j++) | |
963 | if (regs[j] & (1 << 31)) | |
964 | regs[j] = 0; | |
965 | ||
966 | /* Byte 0 is level count, not a descriptor */ | |
967 | for (j = 1 ; j < 16 ; j++) | |
968 | intel_tlb_lookup(desc[j]); | |
969 | } | |
970 | } | |
971 | ||
148f9bb8 | 972 | static const struct cpu_dev intel_cpu_dev = { |
1da177e4 | 973 | .c_vendor = "Intel", |
65eb6b43 | 974 | .c_ident = { "GenuineIntel" }, |
185f3b9d | 975 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
976 | .legacy_models = { |
977 | { .family = 4, .model_names = | |
65eb6b43 PC |
978 | { |
979 | [0] = "486 DX-25/33", | |
980 | [1] = "486 DX-50", | |
981 | [2] = "486 SX", | |
982 | [3] = "486 DX/2", | |
983 | [4] = "486 SL", | |
984 | [5] = "486 SX/2", | |
985 | [7] = "486 DX/2-WB", | |
986 | [8] = "486 DX/4", | |
1da177e4 LT |
987 | [9] = "486 DX/4-WB" |
988 | } | |
989 | }, | |
09dc68d9 | 990 | { .family = 5, .model_names = |
65eb6b43 PC |
991 | { |
992 | [0] = "Pentium 60/66 A-step", | |
993 | [1] = "Pentium 60/66", | |
1da177e4 | 994 | [2] = "Pentium 75 - 200", |
65eb6b43 | 995 | [3] = "OverDrive PODP5V83", |
1da177e4 | 996 | [4] = "Pentium MMX", |
65eb6b43 | 997 | [7] = "Mobile Pentium 75 - 200", |
aece118e BD |
998 | [8] = "Mobile Pentium MMX", |
999 | [9] = "Quark SoC X1000", | |
1da177e4 LT |
1000 | } |
1001 | }, | |
09dc68d9 | 1002 | { .family = 6, .model_names = |
65eb6b43 | 1003 | { |
1da177e4 | 1004 | [0] = "Pentium Pro A-step", |
65eb6b43 PC |
1005 | [1] = "Pentium Pro", |
1006 | [3] = "Pentium II (Klamath)", | |
1007 | [4] = "Pentium II (Deschutes)", | |
1008 | [5] = "Pentium II (Deschutes)", | |
1da177e4 | 1009 | [6] = "Mobile Pentium II", |
65eb6b43 PC |
1010 | [7] = "Pentium III (Katmai)", |
1011 | [8] = "Pentium III (Coppermine)", | |
1da177e4 LT |
1012 | [10] = "Pentium III (Cascades)", |
1013 | [11] = "Pentium III (Tualatin)", | |
1014 | } | |
1015 | }, | |
09dc68d9 | 1016 | { .family = 15, .model_names = |
1da177e4 LT |
1017 | { |
1018 | [0] = "Pentium 4 (Unknown)", | |
1019 | [1] = "Pentium 4 (Willamette)", | |
1020 | [2] = "Pentium 4 (Northwood)", | |
1021 | [4] = "Pentium 4 (Foster)", | |
1022 | [5] = "Pentium 4 (Foster)", | |
1023 | } | |
1024 | }, | |
1025 | }, | |
09dc68d9 | 1026 | .legacy_cache_size = intel_size_cache, |
185f3b9d | 1027 | #endif |
e0ba94f1 | 1028 | .c_detect_tlb = intel_detect_tlb, |
03ae5768 | 1029 | .c_early_init = early_init_intel, |
1da177e4 | 1030 | .c_init = init_intel, |
b51ef52d | 1031 | .c_bsp_resume = intel_bsp_resume, |
10a434fc | 1032 | .c_x86_vendor = X86_VENDOR_INTEL, |
1da177e4 LT |
1033 | }; |
1034 | ||
10a434fc | 1035 | cpu_dev_register(intel_cpu_dev); |
1da177e4 | 1036 |