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Merge remote-tracking branch 'asoc/topic/pcm5102a' into asoc-next
[linux-2.6-block.git] / arch / x86 / kernel / cpu / intel.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4
LT		 2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
83ce4009 7#include <linux/sched.h>
e6017571 8#include <linux/sched/clock.h>
1da177e4 9#include <linux/thread_info.h>
186f4360 10#include <linux/init.h>
8bdbd962 11#include <linux/uaccess.h>
1da177e4 12
cd4d09ec 13#include <asm/cpufeature.h>
d72b1b4f 14#include <asm/pgtable.h>
1da177e4 15#include <asm/msr.h>
73bdb73f 16#include <asm/bugs.h>
1f442d70 17#include <asm/cpu.h>
08e237fa 18#include <asm/intel-family.h>
4167709b 19#include <asm/microcode_intel.h>
e16fd002
GA		 20#include <asm/hwcap2.h>
21#include <asm/elf.h>
1da177e4 22
185f3b9d 23#ifdef CONFIG_X86_64
8bdbd962 24#include <linux/topology.h>
185f3b9d
YL		 25#endif
26
1da177e4
LT		 27#include "cpu.h"
28
29#ifdef CONFIG_X86_LOCAL_APIC
30#include <asm/mpspec.h>
31#include <asm/apic.h>
1da177e4
LT		 32#endif
33
0f6ff2bc
DH		 34/*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38static int forcempx;
39
40static int __init forcempx_setup(char *__unused)
41{
42 forcempx = 1;
43
44 return 1;
45}
46__setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48void check_mpx_erratum(struct cpuinfo_x86 *c)
49{
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67}
68
e16fd002
GA		 69static bool ring3mwait_disabled __read_mostly;
70
71static int __init ring3mwait_disable(char *__unused)
72{
73 ring3mwait_disabled = true;
74 return 0;
75}
76__setup("ring3mwait=disable", ring3mwait_disable);
77
78static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
79{
80 /*
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
83 */
4d8bb006 84 if (c->x86 != 6)
e16fd002 85 return;
4d8bb006
PL		 86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
89 break;
90 default:
91 return;
92 }
e16fd002 93
e9ea1e7f 94 if (ring3mwait_disabled)
e16fd002 95 return;
e16fd002
GA		 96
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
e9ea1e7f
KH		 98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
e16fd002
GA		 100
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
103}
104
a5b29663
DW		 105/*
106 * Early microcode releases for the Spectre v2 mitigation were broken.
107 * Information taken from;
e3b3121f 108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
a5b29663
DW		 109 * - https://kb.vmware.com/s/article/52345
110 * - Microcode revisions observed in the wild
111 * - Release note from 20180108 microcode release
112 */
113struct sku_microcode {
114 u8 model;
115 u8 stepping;
116 u32 microcode;
117};
118static const struct sku_microcode spectre_bad_microcodes[] = {
d37fc6d3
DW		 119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
a5b29663
DW		 124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
a5b29663
DW		 126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
a5b29663
DW		 137 /* Observed in the wild */
138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
140};
141
142static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
143{
144 int i;
145
36268223
KRW		 146 /*
147 * We know that the hypervisor lie to us on the microcode version so
148 * we may as well hope that it is running the correct version.
149 */
150 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
151 return false;
152
a5b29663
DW		 153 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
154 if (c->x86_model == spectre_bad_microcodes[i].model &&
b399151c 155 c->x86_stepping == spectre_bad_microcodes[i].stepping)
a5b29663
DW		 156 return (c->microcode <= spectre_bad_microcodes[i].microcode);
157 }
158 return false;
159}
160
148f9bb8 161static void early_init_intel(struct cpuinfo_x86 *c)
1da177e4 162{
161ec53c
FY		 163 u64 misc_enable;
164
99fb4d34 165 /* Unmask CPUID levels if masked: */
30a0fb94 166 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
0b131be8
PA		 167 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
168 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
99fb4d34 169 c->cpuid_level = cpuid_eax(0);
d900329e 170 get_cpu_cap(c);
99fb4d34 171 }
066941bd
PA		 172 }
173
2b16a235
AK		 174 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
175 (c->x86 == 0x6 && c->x86_model >= 0x0e))
176 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
185f3b9d 177
4167709b
BP		 178 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
179 c->microcode = intel_get_microcode_revision();
506ed6b5 180
2961298e 181 /* Now if any of them are set, check the blacklist and clear the lot */
7fcae111
DW		 182 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
183 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
184 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
2961298e
DW		 185 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
186 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
7fcae111
DW		 187 setup_clear_cpu_cap(X86_FEATURE_IBRS);
188 setup_clear_cpu_cap(X86_FEATURE_IBPB);
189 setup_clear_cpu_cap(X86_FEATURE_STIBP);
190 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
191 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
a5b29663
DW		 192 }
193
7a0fc404
PA		 194 /*
195 * Atom erratum AAE44/AAF40/AAG38/AAH41:
196 *
197 * A race condition between speculative fetches and invalidating
198 * a large page. This is worked around in microcode, but we
199 * need the microcode to have already been loaded... so if it is
200 * not, recommend a BIOS update and disable large pages.
201 */
b399151c 202 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
30963c0a 203 c->microcode < 0x20e) {
1b74dde7 204 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
30963c0a 205 clear_cpu_cap(c, X86_FEATURE_PSE);
7a0fc404
PA		 206 }
207
185f3b9d
YL		 208#ifdef CONFIG_X86_64
209 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
210#else
211 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
212 if (c->x86 == 15 && c->x86_cache_alignment == 64)
213 c->x86_cache_alignment = 128;
214#endif
40fb1715 215
13c6c532
JB		 216 /* CPUID workaround for 0F33/0F34 CPU */
217 if (c->x86 == 0xF && c->x86_model == 0x3
b399151c 218 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
13c6c532
JB		 219 c->x86_phys_bits = 36;
220
40fb1715
VP		 221 /*
222 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83ce4009
IM		 223 * with P/T states and does not stop in deep C-states.
224 *
225 * It is also reliable across cores and sockets. (but not across
226 * cabinets - we turn it off in that case explicitly.)
40fb1715
VP		 227 */
228 if (c->x86_power & (1 << 8)) {
229 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
230 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
231 }
232
c54fdbb2
FT		 233 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
234 if (c->x86 == 6) {
235 switch (c->x86_model) {
236 case 0x27: /* Penwell */
237 case 0x35: /* Cloverview */
354dbaa7 238 case 0x4a: /* Merrifield */
c54fdbb2
FT		 239 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
240 break;
241 default:
242 break;
243 }
244 }
245
75a04811
PA		 246 /*
247 * There is a known erratum on Pentium III and Core Solo
248 * and Core Duo CPUs.
249 * " Page with PAT set to WC while associated MTRR is UC
250 * may consolidate to UC "
251 * Because of this erratum, it is better to stick with
252 * setting WC in MTRR rather than using PAT on these CPUs.
253 *
254 * Enable PAT WC only on P4, Core 2 or later CPUs.
255 */
256 if (c->x86 == 6 && c->x86_model < 15)
257 clear_cpu_cap(c, X86_FEATURE_PAT);
f8561296 258
161ec53c
FY		 259 /*
260 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
261 * clear the fast string and enhanced fast string CPU capabilities.
262 */
263 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
264 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
265 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
1b74dde7 266 pr_info("Disabled fast string operations\n");
161ec53c
FY		 267 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
268 setup_clear_cpu_cap(X86_FEATURE_ERMS);
269 }
270 }
ee1b5b16
BD		 271
272 /*
273 * Intel Quark Core DevMan_001.pdf section 6.4.11
274 * "The operating system also is required to invalidate (i.e., flush)
275 * the TLB when any changes are made to any of the page table entries.
276 * The operating system must reload CR3 to cause the TLB to be flushed"
277 *
c109bf95
BP		 278 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
279 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
280 * to be modified.
ee1b5b16
BD		 281 */
282 if (c->x86 == 5 && c->x86_model == 9) {
283 pr_info("Disabling PGE capability bit\n");
284 setup_clear_cpu_cap(X86_FEATURE_PGE);
285 }
1f12e32f
TG		 286
287 if (c->cpuid_level >= 0x00000001) {
288 u32 eax, ebx, ecx, edx;
289
290 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
291 /*
292 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
293 * apicids which are reserved per package. Store the resulting
294 * shift value for the package management code.
295 */
296 if (edx & (1U << 28))
297 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
298 }
0f6ff2bc
DH		 299
300 check_mpx_erratum(c);
1da177e4
LT		 301}
302
185f3b9d 303#ifdef CONFIG_X86_32
1da177e4
LT		 304/*
305 * Early probe support logic for ppro memory erratum #50
306 *
307 * This is called before we do cpu ident work
308 */
65eb6b43 309
148f9bb8 310int ppro_with_ram_bug(void)
1da177e4
LT		 311{
312 /* Uses data from early_cpu_detect now */
313 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
314 boot_cpu_data.x86 == 6 &&
315 boot_cpu_data.x86_model == 1 &&
b399151c 316 boot_cpu_data.x86_stepping < 8) {
1b74dde7 317 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
1da177e4
LT		 318 return 1;
319 }
320 return 0;
321}
65eb6b43 322
148f9bb8 323static void intel_smp_check(struct cpuinfo_x86 *c)
1f442d70 324{
1f442d70 325 /* calling is from identify_secondary_cpu() ? */
f6e9456c 326 if (!c->cpu_index)
1f442d70
YL		 327 return;
328
329 /*
330 * Mask B, Pentium, but not Pentium MMX
331 */
332 if (c->x86 == 5 &&
b399151c 333 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
1f442d70
YL		 334 c->x86_model <= 3) {
335 /*
336 * Remember we have B step Pentia with bugs
337 */
338 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
339 "with B stepping processors.\n");
340 }
1f442d70
YL		 341}
342
69f2366c
CB		 343static int forcepae;
344static int __init forcepae_setup(char *__unused)
345{
346 forcepae = 1;
347 return 1;
348}
349__setup("forcepae", forcepae_setup);
350
148f9bb8 351static void intel_workarounds(struct cpuinfo_x86 *c)
1da177e4 352{
4052704d
YL		 353#ifdef CONFIG_X86_F00F_BUG
354 /*
d4e1a0af 355 * All models of Pentium and Pentium with MMX technology CPUs
8bdbd962 356 * have the F0 0F bug, which lets nonprivileged users lock up the
4eefbe79 357 * system. Announce that the fault handler will be checking for it.
d4e1a0af 358 * The Quark is also family 5, but does not have the same bug.
4052704d 359 */
e2604b49 360 clear_cpu_bug(c, X86_BUG_F00F);
fa392794 361 if (c->x86 == 5 && c->x86_model < 9) {
4052704d
YL		 362 static int f00f_workaround_enabled;
363
e2604b49 364 set_cpu_bug(c, X86_BUG_F00F);
4052704d 365 if (!f00f_workaround_enabled) {
1b74dde7 366 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
4052704d
YL		 367 f00f_workaround_enabled = 1;
368 }
369 }
370#endif
371
372 /*
373 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
374 * model 3 mask 3
375 */
b399151c 376 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
4052704d
YL		 377 clear_cpu_cap(c, X86_FEATURE_SEP);
378
69f2366c
CB		 379 /*
380 * PAE CPUID issue: many Pentium M report no PAE but may have a
381 * functionally usable PAE implementation.
382 * Forcefully enable PAE if kernel parameter "forcepae" is present.
383 */
384 if (forcepae) {
1b74dde7 385 pr_warn("PAE forced!\n");
69f2366c
CB		 386 set_cpu_cap(c, X86_FEATURE_PAE);
387 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
388 }
389
4052704d 390 /*
f0133acc 391 * P4 Xeon erratum 037 workaround.
4052704d
YL		 392 * Hardware prefetcher may cause stale data to be loaded into the cache.
393 */
b399151c 394 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
0b131be8 395 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
f0133acc 396 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
c0a639ad 397 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
f0133acc 398 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
1da177e4
LT		 399 }
400 }
1da177e4 401
4052704d
YL		 402 /*
403 * See if we have a good local APIC by checking for buggy Pentia,
404 * i.e. all B steppings and the C2 stepping of P54C when using their
405 * integrated APIC (see 11AP erratum in "Pentium Processor
406 * Specification Update").
407 */
93984fbd 408 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
b399151c 409 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
9b13a93d 410 set_cpu_bug(c, X86_BUG_11AP);
185f3b9d 411
185f3b9d 412
4052704d 413#ifdef CONFIG_X86_INTEL_USERCOPY
185f3b9d 414 /*
4052704d 415 * Set up the preferred alignment for movsl bulk memory moves
185f3b9d 416 */
4052704d
YL		 417 switch (c->x86) {
418 case 4: /* 486: untested */
419 break;
420 case 5: /* Old Pentia: untested */
421 break;
422 case 6: /* PII/PIII only like movsl with 8-byte alignment */
423 movsl_mask.mask = 7;
424 break;
425 case 15: /* P4 is OK down to 8-byte alignment */
426 movsl_mask.mask = 7;
427 break;
428 }
185f3b9d 429#endif
4052704d 430
1f442d70 431 intel_smp_check(c);
4052704d
YL		 432}
433#else
148f9bb8 434static void intel_workarounds(struct cpuinfo_x86 *c)
4052704d
YL		 435{
436}
185f3b9d
YL		 437#endif
438
148f9bb8 439static void srat_detect_node(struct cpuinfo_x86 *c)
185f3b9d 440{
645a7919 441#ifdef CONFIG_NUMA
185f3b9d
YL		 442 unsigned node;
443 int cpu = smp_processor_id();
185f3b9d
YL		 444
445 /* Don't do the funky fallback heuristics the AMD version employs
446 for now. */
bbc9e2f4 447 node = numa_cpu_node(cpu);
50f2d7f6 448 if (node == NUMA_NO_NODE || !node_online(node)) {
d9c2d5ac
YL		 449 /* reuse the value from init_cpu_to_node() */
450 node = cpu_to_node(cpu);
451 }
185f3b9d 452 numa_set_node(cpu, node);
185f3b9d
YL		 453#endif
454}
455
3dd9d514
AK		 456/*
457 * find out the number of processor cores on the die
458 */
148f9bb8 459static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
3dd9d514 460{
f2ab4461 461 unsigned int eax, ebx, ecx, edx;
3dd9d514 462
8d415ee2 463 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
3dd9d514
AK		 464 return 1;
465
f2ab4461
ZA		 466 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
467 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
3dd9d514 468 if (eax & 0x1f)
8bdbd962 469 return (eax >> 26) + 1;
3dd9d514
AK		 470 else
471 return 1;
472}
473
148f9bb8 474static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
e38e05a8
SY		 475{
476 /* Intel VMX MSR indicated features */
477#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
478#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
479#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
480#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
481#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
482#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
483
484 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
485
486 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
487 clear_cpu_cap(c, X86_FEATURE_VNMI);
488 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
489 clear_cpu_cap(c, X86_FEATURE_EPT);
490 clear_cpu_cap(c, X86_FEATURE_VPID);
491
492 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
493 msr_ctl = vmx_msr_high | vmx_msr_low;
494 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
495 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
496 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
497 set_cpu_cap(c, X86_FEATURE_VNMI);
498 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
499 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
500 vmx_msr_low, vmx_msr_high);
501 msr_ctl2 = vmx_msr_high | vmx_msr_low;
502 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
503 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
504 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
505 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
506 set_cpu_cap(c, X86_FEATURE_EPT);
507 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
508 set_cpu_cap(c, X86_FEATURE_VPID);
509 }
510}
511
b51ef52d
LA		 512static void init_intel_energy_perf(struct cpuinfo_x86 *c)
513{
514 u64 epb;
515
516 /*
517 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
518 * (x86_energy_perf_policy(8) is available to change it at run-time.)
519 */
520 if (!cpu_has(c, X86_FEATURE_EPB))
521 return;
522
523 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
524 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
525 return;
526
527 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
528 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
529 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
530 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
531}
532
533static void intel_bsp_resume(struct cpuinfo_x86 *c)
534{
535 /*
536 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
537 * so reinitialize it properly like during bootup:
538 */
539 init_intel_energy_perf(c);
540}
541
90218ac7
KH		 542static void init_cpuid_fault(struct cpuinfo_x86 *c)
543{
544 u64 msr;
545
546 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
547 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
548 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
549 }
550}
551
552static void init_intel_misc_features(struct cpuinfo_x86 *c)
553{
554 u64 msr;
555
556 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
557 return;
558
e9ea1e7f
KH		 559 /* Clear all MISC features */
560 this_cpu_write(msr_misc_features_shadow, 0);
561
562 /* Check features and update capabilities and shadow control bits */
90218ac7
KH		 563 init_cpuid_fault(c);
564 probe_xeon_phi_r3mwait(c);
e9ea1e7f
KH		 565
566 msr = this_cpu_read(msr_misc_features_shadow);
567 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
90218ac7
KH		 568}
569
148f9bb8 570static void init_intel(struct cpuinfo_x86 *c)
1da177e4
LT		 571{
572 unsigned int l2 = 0;
1da177e4 573
2b16a235
AK		 574 early_init_intel(c);
575
4052704d 576 intel_workarounds(c);
1da177e4 577
345077cd
SS		 578 /*
579 * Detect the extended topology information if available. This
580 * will reinitialise the initial_apicid which will be used
581 * in init_intel_cacheinfo()
582 */
583 detect_extended_topology(c);
584
2a226155
PZ		 585 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
586 /*
587 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
588 * detection.
589 */
590 c->x86_max_cores = intel_num_cpu_cores(c);
591#ifdef CONFIG_X86_32
592 detect_ht(c);
593#endif
594 }
595
1da177e4 596 l2 = init_intel_cacheinfo(c);
aece118e
BD		 597
598 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
599 if (l2 == 0) {
600 cpu_detect_cache_sizes(c);
601 l2 = c->x86_cache_size;
602 }
603
65eb6b43 604 if (c->cpuid_level > 9) {
0080e667
VP		 605 unsigned eax = cpuid_eax(10);
606 /* Check for version and the number of counters */
607 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
d0e95ebd 608 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0080e667 609 }
1da177e4 610
054efb64 611 if (cpu_has(c, X86_FEATURE_XMM2))
4052704d 612 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
362f924b
BP		 613
614 if (boot_cpu_has(X86_FEATURE_DS)) {
4052704d
YL		 615 unsigned int l1;
616 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
617 if (!(l1 & (1<<11)))
618 set_cpu_cap(c, X86_FEATURE_BTS);
619 if (!(l1 & (1<<12)))
620 set_cpu_cap(c, X86_FEATURE_PEBS);
4052704d 621 }
1da177e4 622
906bf7fd 623 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
40e2d7f9 624 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
9b13a93d 625 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
e736ad54 626
08e237fa
PZ		 627 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
628 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
629 set_cpu_bug(c, X86_BUG_MONITOR);
630
4052704d
YL		 631#ifdef CONFIG_X86_64
632 if (c->x86 == 15)
633 c->x86_cache_alignment = c->x86_clflush_size * 2;
634 if (c->x86 == 6)
635 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
636#else
65eb6b43
PC		 637 /*
638 * Names for the Pentium II/Celeron processors
639 * detectable only by also checking the cache size.
640 * Dixon is NOT a Celeron.
641 */
1da177e4 642 if (c->x86 == 6) {
4052704d
YL		 643 char *p = NULL;
644
1da177e4
LT		 645 switch (c->x86_model) {
646 case 5:
865be7a8
OZ		 647 if (l2 == 0)
648 p = "Celeron (Covington)";
649 else if (l2 == 256)
650 p = "Mobile Pentium II (Dixon)";
1da177e4 651 break;
65eb6b43 652
1da177e4
LT		 653 case 6:
654 if (l2 == 128)
655 p = "Celeron (Mendocino)";
b399151c 656 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
1da177e4
LT		 657 p = "Celeron-A";
658 break;
65eb6b43 659
1da177e4
LT		 660 case 8:
661 if (l2 == 128)
662 p = "Celeron (Coppermine)";
663 break;
664 }
1da177e4 665
4052704d
YL		 666 if (p)
667 strcpy(c->x86_model_id, p);
1da177e4 668 }
1da177e4 669
185f3b9d
YL		 670 if (c->x86 == 15)
671 set_cpu_cap(c, X86_FEATURE_P4);
672 if (c->x86 == 6)
673 set_cpu_cap(c, X86_FEATURE_P3);
f4166c54 674#endif
185f3b9d 675
185f3b9d 676 /* Work around errata */
2759c328 677 srat_detect_node(c);
e38e05a8
SY		 678
679 if (cpu_has(c, X86_FEATURE_VMX))
680 detect_vmx_virtcap(c);
abe48b10 681
b51ef52d 682 init_intel_energy_perf(c);
e16fd002 683
90218ac7 684 init_intel_misc_features(c);
42ed458a 685}
1da177e4 686
185f3b9d 687#ifdef CONFIG_X86_32
148f9bb8 688static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
1da177e4 689{
65eb6b43
PC		 690 /*
691 * Intel PIII Tualatin. This comes in two flavours.
1da177e4
LT		 692 * One has 256kb of cache, the other 512. We have no way
693 * to determine which, so we use a boottime override
694 * for the 512kb model, and assume 256 otherwise.
695 */
696 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
697 size = 256;
aece118e
BD		 698
699 /*
700 * Intel Quark SoC X1000 contains a 4-way set associative
701 * 16K cache with a 16 byte cache line and 256 lines per tag
702 */
703 if ((c->x86 == 5) && (c->x86_model == 9))
704 size = 16;
1da177e4
LT		 705 return size;
706}
185f3b9d 707#endif
1da177e4 708
e0ba94f1
AS		 709#define TLB_INST_4K 0x01
710#define TLB_INST_4M 0x02
711#define TLB_INST_2M_4M 0x03
712
713#define TLB_INST_ALL 0x05
714#define TLB_INST_1G 0x06
715
716#define TLB_DATA_4K 0x11
717#define TLB_DATA_4M 0x12
718#define TLB_DATA_2M_4M 0x13
719#define TLB_DATA_4K_4M 0x14
720
721#define TLB_DATA_1G 0x16
722
723#define TLB_DATA0_4K 0x21
724#define TLB_DATA0_4M 0x22
725#define TLB_DATA0_2M_4M 0x23
726
727#define STLB_4K 0x41
dd360393 728#define STLB_4K_2M 0x42
e0ba94f1 729
148f9bb8 730static const struct _tlb_table intel_tlb_table[] = {
e0ba94f1
AS		 731 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
732 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
733 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
734 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
735 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
736 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
737 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
738 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
739 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
740 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
741 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
742 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
743 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
744 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
745 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
746 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
747 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
748 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
dd360393
KS		 749 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
750 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
751 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
e0ba94f1
AS		 752 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
753 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
754 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
755 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
756 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
a927792c
YG		 757 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
758 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
e0ba94f1
AS		 759 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
760 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
dd360393
KS		 761 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
762 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
e0ba94f1
AS		 763 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
764 { 0x00, 0, 0 }
765};
766
148f9bb8 767static void intel_tlb_lookup(const unsigned char desc)
e0ba94f1
AS		 768{
769 unsigned char k;
770 if (desc == 0)
771 return;
772
773 /* look up this descriptor in the table */
774 for (k = 0; intel_tlb_table[k].descriptor != desc && \
775 intel_tlb_table[k].descriptor != 0; k++)
776 ;
777
778 if (intel_tlb_table[k].tlb_type == 0)
779 return;
780
781 switch (intel_tlb_table[k].tlb_type) {
782 case STLB_4K:
783 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
784 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
785 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
786 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
787 break;
dd360393
KS		 788 case STLB_4K_2M:
789 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
790 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
791 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
792 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
793 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
794 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
795 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
796 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
797 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
798 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
799 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
800 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
801 break;
e0ba94f1
AS		 802 case TLB_INST_ALL:
803 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
804 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
805 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
806 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
807 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
808 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
809 break;
810 case TLB_INST_4K:
811 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
812 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
813 break;
814 case TLB_INST_4M:
815 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
816 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
817 break;
818 case TLB_INST_2M_4M:
819 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
820 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
821 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
822 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
823 break;
824 case TLB_DATA_4K:
825 case TLB_DATA0_4K:
826 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
827 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
828 break;
829 case TLB_DATA_4M:
830 case TLB_DATA0_4M:
831 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
832 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
833 break;
834 case TLB_DATA_2M_4M:
835 case TLB_DATA0_2M_4M:
836 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
837 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
838 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
839 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
840 break;
841 case TLB_DATA_4K_4M:
842 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
843 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
844 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
845 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
846 break;
dd360393
KS		 847 case TLB_DATA_1G:
848 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
849 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
e0ba94f1
AS		 850 break;
851 }
852}
853
148f9bb8 854static void intel_detect_tlb(struct cpuinfo_x86 *c)
e0ba94f1
AS		 855{
856 int i, j, n;
857 unsigned int regs[4];
858 unsigned char *desc = (unsigned char *)regs;
5b556332
BP		 859
860 if (c->cpuid_level < 2)
861 return;
862
e0ba94f1
AS		 863 /* Number of times to iterate */
864 n = cpuid_eax(2) & 0xFF;
865
866 for (i = 0 ; i < n ; i++) {
867 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
868
869 /* If bit 31 is set, this is an unknown format */
870 for (j = 0 ; j < 3 ; j++)
871 if (regs[j] & (1 << 31))
872 regs[j] = 0;
873
874 /* Byte 0 is level count, not a descriptor */
875 for (j = 1 ; j < 16 ; j++)
876 intel_tlb_lookup(desc[j]);
877 }
878}
879
148f9bb8 880static const struct cpu_dev intel_cpu_dev = {
1da177e4 881 .c_vendor = "Intel",
65eb6b43 882 .c_ident = { "GenuineIntel" },
185f3b9d 883#ifdef CONFIG_X86_32
09dc68d9
JB		 884 .legacy_models = {
885 { .family = 4, .model_names =
65eb6b43
PC		 886 {
887 [0] = "486 DX-25/33",
888 [1] = "486 DX-50",
889 [2] = "486 SX",
890 [3] = "486 DX/2",
891 [4] = "486 SL",
892 [5] = "486 SX/2",
893 [7] = "486 DX/2-WB",
894 [8] = "486 DX/4",
1da177e4
LT		 895 [9] = "486 DX/4-WB"
896 }
897 },
09dc68d9 898 { .family = 5, .model_names =
65eb6b43
PC		 899 {
900 [0] = "Pentium 60/66 A-step",
901 [1] = "Pentium 60/66",
1da177e4 902 [2] = "Pentium 75 - 200",
65eb6b43 903 [3] = "OverDrive PODP5V83",
1da177e4 904 [4] = "Pentium MMX",
65eb6b43 905 [7] = "Mobile Pentium 75 - 200",
aece118e
BD		 906 [8] = "Mobile Pentium MMX",
907 [9] = "Quark SoC X1000",
1da177e4
LT		 908 }
909 },
09dc68d9 910 { .family = 6, .model_names =
65eb6b43 911 {
1da177e4 912 [0] = "Pentium Pro A-step",
65eb6b43
PC		 913 [1] = "Pentium Pro",
914 [3] = "Pentium II (Klamath)",
915 [4] = "Pentium II (Deschutes)",
916 [5] = "Pentium II (Deschutes)",
1da177e4 917 [6] = "Mobile Pentium II",
65eb6b43
PC		 918 [7] = "Pentium III (Katmai)",
919 [8] = "Pentium III (Coppermine)",
1da177e4
LT		 920 [10] = "Pentium III (Cascades)",
921 [11] = "Pentium III (Tualatin)",
922 }
923 },
09dc68d9 924 { .family = 15, .model_names =
1da177e4
LT		 925 {
926 [0] = "Pentium 4 (Unknown)",
927 [1] = "Pentium 4 (Willamette)",
928 [2] = "Pentium 4 (Northwood)",
929 [4] = "Pentium 4 (Foster)",
930 [5] = "Pentium 4 (Foster)",
931 }
932 },
933 },
09dc68d9 934 .legacy_cache_size = intel_size_cache,
185f3b9d 935#endif
e0ba94f1 936 .c_detect_tlb = intel_detect_tlb,
03ae5768 937 .c_early_init = early_init_intel,
1da177e4 938 .c_init = init_intel,
b51ef52d 939 .c_bsp_resume = intel_bsp_resume,
10a434fc 940 .c_x86_vendor = X86_VENDOR_INTEL,
1da177e4
LT		 941};
942
10a434fc 943cpu_dev_register(intel_cpu_dev);
1da177e4 944
Linux 6.x block layer and io_uring tree(s)