[linux-2.6-block.git] / arch / x86 / kernel / cpu / cyrix.c

#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/processor-cyrix.h>
#include <asm/processor-flags.h>
#include <asm/timer.h>
#include <asm/pci-direct.h>
#include <asm/tsc.h>

#include "cpu.h"

/*
 * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
 */
static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
{
	unsigned char ccr2, ccr3;
	unsigned long flags;

	/* we test for DEVID by checking whether CCR3 is writable */
	local_irq_save(flags);
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	getCx86(0xc0);   /* dummy to change bus */

	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
		ccr2 = getCx86(CX86_CCR2);
		setCx86(CX86_CCR2, ccr2 ^ 0x04);
		getCx86(0xc0);  /* dummy */

		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
			*dir0 = 0xfd;
		else {                          /* Cx486S A step */
			setCx86(CX86_CCR2, ccr2);
			*dir0 = 0xfe;
		}
	} else {
		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */

		/* read DIR0 and DIR1 CPU registers */
		*dir0 = getCx86(CX86_DIR0);
		*dir1 = getCx86(CX86_DIR1);
	}
	local_irq_restore(flags);
}

/*
 * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
 * order to identify the Cyrix CPU model after we're out of setup.c
 *
 * Actually since bugs.h doesn't even reference this perhaps someone should
 * fix the documentation ???
 */
static unsigned char Cx86_dir0_msb __cpuinitdata = 0;

static char Cx86_model[][9] __cpuinitdata = {
	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	"M II ", "Unknown"
};
static char Cx486_name[][5] __cpuinitdata = {
	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	"SRx2", "DRx2"
};
static char Cx486S_name[][4] __cpuinitdata = {
	"S", "S2", "Se", "S2e"
};
static char Cx486D_name[][4] __cpuinitdata = {
	"DX", "DX2", "?", "?", "?", "DX4"
};
static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
static char cyrix_model_mult1[] __cpuinitdata = "12??43";
static char cyrix_model_mult2[] __cpuinitdata = "12233445";

/*
 * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
 * BIOSes for compatibility with DOS games.  This makes the udelay loop
 * work correctly, and improves performance.
 *
 * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
 */

static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
{
	unsigned long flags;

	if (Cx86_dir0_msb == 3) {
		unsigned char ccr3, ccr5;

		local_irq_save(flags);
		ccr3 = getCx86(CX86_CCR3);
		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
		ccr5 = getCx86(CX86_CCR5);
		if (ccr5 & 2)
			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
		local_irq_restore(flags);

		if (ccr5 & 2) { /* possible wrong calibration done */
			printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
			calibrate_delay();
			c->loops_per_jiffy = loops_per_jiffy;
		}
	}
}


static void __cpuinit set_cx86_reorder(void)
{
	u8 ccr3;

	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */

	/* Load/Store Serialize to mem access disable (=reorder it) */
	setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
	/* set load/store serialize from 1GB to 4GB */
	ccr3 |= 0xe0;
	setCx86(CX86_CCR3, ccr3);
}

static void __cpuinit set_cx86_memwb(void)
{
	printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");

	/* CCR2 bit 2: unlock NW bit */
	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
	/* set 'Not Write-through' */
	write_cr0(read_cr0() | X86_CR0_NW);
	/* CCR2 bit 2: lock NW bit and set WT1 */
	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
}

static void __cpuinit set_cx86_inc(void)
{
	unsigned char ccr3;

	printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
	/* PCR1 -- Performance Control */
	/* Incrementor on, whatever that is */
	setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
	/* PCR0 -- Performance Control */
	/* Incrementor Margin 10 */
	setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
	setCx86(CX86_CCR3, ccr3);	/* disable MAPEN */
}

/*
 *	Configure later MediaGX and/or Geode processor.
 */

static void __cpuinit geode_configure(void)
{
	unsigned long flags;
	u8 ccr3;
	local_irq_save(flags);

	/* Suspend on halt power saving and enable #SUSP pin */
	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);

	ccr3 = getCx86(CX86_CCR3);
	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */


	/* FPU fast, DTE cache, Mem bypass */
	setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */

	set_cx86_memwb();
	set_cx86_reorder();
	set_cx86_inc();

	local_irq_restore(flags);
}


static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
{
	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	char *buf = c->x86_model_id;
	const char *p = NULL;

	/*
	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	 */
	clear_cpu_cap(c, 0*32+31);

	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
	if (test_cpu_cap(c, 1*32+24)) {
		clear_cpu_cap(c, 1*32+24);
		set_cpu_cap(c, X86_FEATURE_CXMMX);
	}

	do_cyrix_devid(&dir0, &dir1);

	check_cx686_slop(c);

	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */

	/* common case step number/rev -- exceptions handled below */
	c->x86_model = (dir1 >> 4) + 1;
	c->x86_mask = dir1 & 0xf;

	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	 * We do the same thing for each generation: we work out
	 * the model, multiplier and stepping.  Black magic included,
	 * to make the silicon step/rev numbers match the printed ones.
	 */

	switch (dir0_msn) {
		unsigned char tmp;

	case 0: /* Cx486SLC/DLC/SRx/DRx */
		p = Cx486_name[dir0_lsn & 7];
		break;

	case 1: /* Cx486S/DX/DX2/DX4 */
		p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
			: Cx486S_name[dir0_lsn & 3];
		break;

	case 2: /* 5x86 */
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		p = Cx86_cb+2;
		break;

	case 3: /* 6x86/6x86L */
		Cx86_cb[1] = ' ';
		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
		if (dir1 > 0x21) { /* 686L */
			Cx86_cb[0] = 'L';
			p = Cx86_cb;
			(c->x86_model)++;
		} else             /* 686 */
			p = Cx86_cb+1;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		/* 6x86's contain this bug */
		c->coma_bug = 1;
		break;

	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
#ifdef CONFIG_PCI
	{
		u32 vendor, device;
		/*
		 * It isn't really a PCI quirk directly, but the cure is the
		 * same. The MediaGX has deep magic SMM stuff that handles the
		 * SB emulation. It throws away the fifo on disable_dma() which
		 * is wrong and ruins the audio.
		 *
		 *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
		 *  causes bad things. According to NatSemi VSA2 has another
		 *  bug to do with 'hlt'. I've not seen any boards using VSA2
		 *  and X doesn't seem to support it either so who cares 8).
		 *  VSA1 we work around however.
		 */

		printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
		isa_dma_bridge_buggy = 2;

		/* We do this before the PCI layer is running. However we
		   are safe here as we know the bridge must be a Cyrix
		   companion and must be present */
		vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
		device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);

		/*
		 *  The 5510/5520 companion chips have a funky PIT.
		 */
		if (vendor == PCI_VENDOR_ID_CYRIX &&
	 (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
			mark_tsc_unstable("cyrix 5510/5520 detected");
	}
#endif
		c->x86_cache_size = 16;	/* Yep 16K integrated cache thats it */

		/* GXm supports extended cpuid levels 'ala' AMD */
		if (c->cpuid_level == 2) {
			/* Enable cxMMX extensions (GX1 Datasheet 54) */
			setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);

			/*
			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
			 * GXlv: 0x6x          GXlv datasheet 54
			 *  ?  : 0x7x
			 * GX1 : 0x8x          GX1  datasheet 56
			 */
			if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
				geode_configure();
			get_model_name(c);  /* get CPU marketing name */
			return;
		} else { /* MediaGX */
			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
			p = Cx86_cb+2;
			c->x86_model = (dir1 & 0x20) ? 1 : 2;
		}
		break;

	case 5: /* 6x86MX/M II */
		if (dir1 > 7) {
			dir0_msn++;  /* M II */
			/* Enable MMX extensions (App note 108) */
			setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
		} else {
			c->coma_bug = 1;      /* 6x86MX, it has the bug. */
		}
		tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
		Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
		p = Cx86_cb+tmp;
		if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
			(c->x86_model)++;
		/* Emulate MTRRs using Cyrix's ARRs. */
		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
		break;

	case 0xf:  /* Cyrix 486 without DEVID registers */
		switch (dir0_lsn) {
		case 0xd:  /* either a 486SLC or DLC w/o DEVID */
			dir0_msn = 0;
			p = Cx486_name[(c->hard_math) ? 1 : 0];
			break;

		case 0xe:  /* a 486S A step */
			dir0_msn = 0;
			p = Cx486S_name[0];
			break;
		}
		break;

	default:  /* unknown (shouldn't happen, we know everyone ;-) */
		dir0_msn = 7;
		break;
	}
	strcpy(buf, Cx86_model[dir0_msn & 7]);
	if (p)
		strcat(buf, p);
	return;
}

/*
 * Handle National Semiconductor branded processors
 */
static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
{
	/*
	 * There may be GX1 processors in the wild that are branded
	 * NSC and not Cyrix.
	 *
	 * This function only handles the GX processor, and kicks every
	 * thing else to the Cyrix init function above - that should
	 * cover any processors that might have been branded differently
	 * after NSC acquired Cyrix.
	 *
	 * If this breaks your GX1 horribly, please e-mail
	 * info-linux@ldcmail.amd.com to tell us.
	 */

	/* Handle the GX (Formally known as the GX2) */

	if (c->x86 == 5 && c->x86_model == 5)
		display_cacheinfo(c);
	else
		init_cyrix(c);
}

/*
 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 * by the fact that they preserve the flags across the division of 5/2.
 * PII and PPro exhibit this behavior too, but they have cpuid available.
 */

/*
 * Perform the Cyrix 5/2 test. A Cyrix won't change
 * the flags, while other 486 chips will.
 */
static inline int test_cyrix_52div(void)
{
	unsigned int test;

	__asm__ __volatile__(
	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
	     "div %b2\n\t"	/* divide 5 by 2 */
	     "lahf"		/* store flags into %ah */
	     : "=a" (test)
	     : "0" (5), "q" (2)
	     : "cc");

	/* AH is 0x02 on Cyrix after the divide.. */
	return (unsigned char) (test >> 8) == 0x02;
}

static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
{
	/* Detect Cyrix with disabled CPUID */
	if (c->x86 == 4 && test_cyrix_52div()) {
		unsigned char dir0, dir1;

		strcpy(c->x86_vendor_id, "CyrixInstead");
		c->x86_vendor = X86_VENDOR_CYRIX;

		/* Actually enable cpuid on the older cyrix */

		/* Retrieve CPU revisions */

		do_cyrix_devid(&dir0, &dir1);

		dir0 >>= 4;

		/* Check it is an affected model */

		if (dir0 == 5 || dir0 == 3) {
			unsigned char ccr3;
			unsigned long flags;
			printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
			local_irq_save(flags);
			ccr3 = getCx86(CX86_CCR3);
			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN  */
			setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);  /* enable cpuid  */
			setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
			local_irq_restore(flags);
		}
	}
}

static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
	.c_vendor	= "Cyrix",
	.c_ident	= { "CyrixInstead" },
	.c_init		= init_cyrix,
	.c_identify	= cyrix_identify,
};

cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev);

static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
	.c_vendor	= "NSC",
	.c_ident	= { "Geode by NSC" },
	.c_init		= init_nsc,
};

cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
	2	#include <linux/bitops.h>
	3	#include <linux/delay.h>
	4	#include <linux/pci.h>
	5	#include <asm/dma.h>
	6	#include <asm/io.h>
f25f64ed	7	#include <asm/processor-cyrix.h>
7ebad705	8	#include <asm/processor-flags.h>
1da177e4	9	#include <asm/timer.h>
120fad72	10	#include <asm/pci-direct.h>
e8edc6e0	11	#include <asm/tsc.h>
1da177e4 LT	12
	13	#include "cpu.h"
	14
	15	/*
	16	* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
	17	*/
5f0f1c16	18	static void __cpuinit do_cyrix_devid(unsigned char dir0, unsigned char dir1)
1da177e4 LT	19	{
	20	unsigned char ccr2, ccr3;
	21	unsigned long flags;
adf85265	22
1da177e4 LT	23	/* we test for DEVID by checking whether CCR3 is writable */
	24	local_irq_save(flags);
	25	ccr3 = getCx86(CX86_CCR3);
	26	setCx86(CX86_CCR3, ccr3 ^ 0x80);
	27	getCx86(0xc0); /* dummy to change bus */
	28
	29	if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
	30	ccr2 = getCx86(CX86_CCR2);
	31	setCx86(CX86_CCR2, ccr2 ^ 0x04);
	32	getCx86(0xc0); /* dummy */
	33
	34	if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
	35	*dir0 = 0xfd;
	36	else { /* Cx486S A step */
	37	setCx86(CX86_CCR2, ccr2);
	38	*dir0 = 0xfe;
	39	}
adf85265	40	} else {
1da177e4 LT	41	setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
	42
	43	/* read DIR0 and DIR1 CPU registers */
	44	*dir0 = getCx86(CX86_DIR0);
	45	*dir1 = getCx86(CX86_DIR1);
	46	}
	47	local_irq_restore(flags);
	48	}
	49
	50	/*
	51	* Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
	52	* order to identify the Cyrix CPU model after we're out of setup.c
	53	*
	54	* Actually since bugs.h doesn't even reference this perhaps someone should
	55	* fix the documentation ???
	56	*/
b4af3f7c	57	static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
1da177e4	58
b4af3f7c	59	static char Cx86_model[][9] __cpuinitdata = {
1da177e4 LT	60	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
	61	"M II ", "Unknown"
	62	};
b4af3f7c	63	static char Cx486_name[][5] __cpuinitdata = {
1da177e4 LT	64	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
	65	"SRx2", "DRx2"
	66	};
b4af3f7c	67	static char Cx486S_name[][4] __cpuinitdata = {
1da177e4 LT	68	"S", "S2", "Se", "S2e"
1da177e4 LT	69	};
b4af3f7c	70	static char Cx486D_name[][4] __cpuinitdata = {
1da177e4 LT	71	"DX", "DX2", "?", "?", "?", "DX4"
1da177e4 LT	72	};
b4af3f7c MD	73	static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
	74	static char cyrix_model_mult1[] __cpuinitdata = "12??43";
	75	static char cyrix_model_mult2[] __cpuinitdata = "12233445";
1da177e4 LT	76
	77	/*
	78	* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
	79	* BIOSes for compatibility with DOS games. This makes the udelay loop
	80	* work correctly, and improves performance.
	81	*
	82	* FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
	83	*/
	84
b4af3f7c	85	static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
1da177e4 LT	86	{
1da177e4 LT	87	unsigned long flags;
adf85265	88
1da177e4 LT	89	if (Cx86_dir0_msb == 3) {
	90	unsigned char ccr3, ccr5;
	91
	92	local_irq_save(flags);
	93	ccr3 = getCx86(CX86_CCR3);
db955170	94	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4 LT	95	ccr5 = getCx86(CX86_CCR5);
	96	if (ccr5 & 2)
	97	setCx86(CX86_CCR5, ccr5 & 0xfd); /* reset SLOP */
	98	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
	99	local_irq_restore(flags);
	100
	101	if (ccr5 & 2) { /* possible wrong calibration done */
	102	printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
	103	calibrate_delay();
	104	c->loops_per_jiffy = loops_per_jiffy;
	105	}
	106	}
	107	}
	108
	109
b4af3f7c	110	static void __cpuinit set_cx86_reorder(void)
1da177e4 LT	111	{
	112	u8 ccr3;
	113
	114	printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
	115	ccr3 = getCx86(CX86_CCR3);
96de0e25	116	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4	117
96de0e25	118	/* Load/Store Serialize to mem access disable (=reorder it) */
1da177e4 LT	119	setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
	120	/* set load/store serialize from 1GB to 4GB */
	121	ccr3 \|= 0xe0;
	122	setCx86(CX86_CCR3, ccr3);
	123	}
	124
b4af3f7c	125	static void __cpuinit set_cx86_memwb(void)
1da177e4	126	{
1da177e4 LT	127	printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
	128
	129	/* CCR2 bit 2: unlock NW bit */
	130	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
	131	/* set 'Not Write-through' */
7ebad705	132	write_cr0(read_cr0() \| X86_CR0_NW);
1da177e4	133	/* CCR2 bit 2: lock NW bit and set WT1 */
adf85265	134	setCx86(CX86_CCR2, getCx86(CX86_CCR2) \| 0x14);
1da177e4 LT	135	}
1da177e4 LT	136
b4af3f7c	137	static void __cpuinit set_cx86_inc(void)
1da177e4 LT	138	{
	139	unsigned char ccr3;
	140
	141	printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
	142
	143	ccr3 = getCx86(CX86_CCR3);
96de0e25	144	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
1da177e4 LT	145	/* PCR1 -- Performance Control */
	146	/* Incrementor on, whatever that is */
	147	setCx86(CX86_PCR1, getCx86(CX86_PCR1) \| 0x02);
	148	/* PCR0 -- Performance Control */
	149	/* Incrementor Margin 10 */
adf85265	150	setCx86(CX86_PCR0, getCx86(CX86_PCR0) \| 0x04);
1da177e4 LT	151	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
	152	}
	153
	154	/*
	155	* Configure later MediaGX and/or Geode processor.
	156	*/
	157
b4af3f7c	158	static void __cpuinit geode_configure(void)
1da177e4 LT	159	{
1da177e4 LT	160	unsigned long flags;
bcde1ebb	161	u8 ccr3;
1da177e4 LT	162	local_irq_save(flags);
	163
	164	/* Suspend on halt power saving and enable #SUSP pin */
	165	setCx86(CX86_CCR2, getCx86(CX86_CCR2) \| 0x88);
	166
	167	ccr3 = getCx86(CX86_CCR3);
bcde1ebb	168	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
adf85265	169
bcde1ebb TY	170
	171	/* FPU fast, DTE cache, Mem bypass */
	172	setCx86(CX86_CCR4, getCx86(CX86_CCR4) \| 0x38);
	173	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
adf85265	174
1da177e4	175	set_cx86_memwb();
adf85265	176	set_cx86_reorder();
1da177e4	177	set_cx86_inc();
adf85265	178
1da177e4 LT	179	local_irq_restore(flags);
	180	}
	181
	182
b4af3f7c	183	static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
1da177e4 LT	184	{
	185	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
	186	char *buf = c->x86_model_id;
	187	const char *p = NULL;
	188
adf85265 PC	189	/*
	190	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
	191	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
	192	*/
1d007cd5	193	clear_cpu_cap(c, 0*32+31);
1da177e4 LT	194
1da177e4 LT	195	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
1d007cd5 IM	196	if (test_cpu_cap(c, 1*32+24)) {
	197	clear_cpu_cap(c, 1*32+24);
	198	set_cpu_cap(c, X86_FEATURE_CXMMX);
1da177e4 LT	199	}
	200
	201	do_cyrix_devid(&dir0, &dir1);
	202
	203	check_cx686_slop(c);
	204
	205	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family" */
	206	dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
	207
	208	/* common case step number/rev -- exceptions handled below */
	209	c->x86_model = (dir1 >> 4) + 1;
	210	c->x86_mask = dir1 & 0xf;
	211
	212	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
	213	* We do the same thing for each generation: we work out
	214	* the model, multiplier and stepping. Black magic included,
	215	* to make the silicon step/rev numbers match the printed ones.
	216	*/
adf85265	217
1da177e4 LT	218	switch (dir0_msn) {
	219	unsigned char tmp;
	220
	221	case 0: /* Cx486SLC/DLC/SRx/DRx */
	222	p = Cx486_name[dir0_lsn & 7];
	223	break;
	224
	225	case 1: /* Cx486S/DX/DX2/DX4 */
	226	p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
	227	: Cx486S_name[dir0_lsn & 3];
	228	break;
	229
	230	case 2: /* 5x86 */
	231	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	232	p = Cx86_cb+2;
	233	break;
	234
	235	case 3: /* 6x86/6x86L */
	236	Cx86_cb[1] = ' ';
	237	Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
	238	if (dir1 > 0x21) { /* 686L */
	239	Cx86_cb[0] = 'L';
	240	p = Cx86_cb;
	241	(c->x86_model)++;
	242	} else /* 686 */
	243	p = Cx86_cb+1;
	244	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	245	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4 LT	246	/* 6x86's contain this bug */
	247	c->coma_bug = 1;
	248	break;
	249
	250	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
	251	#ifdef CONFIG_PCI
120fad72 A	252	{
120fad72 A	253	u32 vendor, device;
adf85265 PC	254	/*
	255	* It isn't really a PCI quirk directly, but the cure is the
	256	* same. The MediaGX has deep magic SMM stuff that handles the
	257	* SB emulation. It throws away the fifo on disable_dma() which
	258	* is wrong and ruins the audio.
	259	*
	260	* Bug2: VSA1 has a wrap bug so that using maximum sized DMA
	261	* causes bad things. According to NatSemi VSA2 has another
	262	* bug to do with 'hlt'. I've not seen any boards using VSA2
	263	* and X doesn't seem to support it either so who cares 8).
	264	* VSA1 we work around however.
	265	*/
1da177e4 LT	266
	267	printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
	268	isa_dma_bridge_buggy = 2;
cefc0113	269
120fad72 A	270	/* We do this before the PCI layer is running. However we
	271	are safe here as we know the bridge must be a Cyrix
	272	companion and must be present */
	273	vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
	274	device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
cefc0113	275
1da177e4 LT	276	/*
1da177e4 LT	277	* The 5510/5520 companion chips have a funky PIT.
adf85265	278	*/
120fad72 A	279	if (vendor == PCI_VENDOR_ID_CYRIX &&
120fad72 A	280	(device == PCI_DEVICE_ID_CYRIX_5510 \|\| device == PCI_DEVICE_ID_CYRIX_5520))
5a90cf20	281	mark_tsc_unstable("cyrix 5510/5520 detected");
120fad72	282	}
cefc0113	283	#endif
adf85265	284	c->x86_cache_size = 16; /* Yep 16K integrated cache thats it */
1da177e4 LT	285
	286	/* GXm supports extended cpuid levels 'ala' AMD */
	287	if (c->cpuid_level == 2) {
	288	/* Enable cxMMX extensions (GX1 Datasheet 54) */
2632f01a	289	setCx86(CX86_CCR7, getCx86(CX86_CCR7) \| 1);
adf85265	290
2632f01a	291	/*
	292	* GXm : 0x30 ... 0x5f GXm datasheet 51
	293	* GXlv: 0x6x GXlv datasheet 54
	294	* ? : 0x7x
	295	* GX1 : 0x8x GX1 datasheet 56
	296	*/
adf85265	297	if ((0x30 <= dir1 && dir1 <= 0x6f) \|\| (0x80 <= dir1 && dir1 <= 0x8f))
1da177e4 LT	298	geode_configure();
	299	get_model_name(c); /* get CPU marketing name */
	300	return;
adf85265	301	} else { /* MediaGX */
1da177e4 LT	302	Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
	303	p = Cx86_cb+2;
	304	c->x86_model = (dir1 & 0x20) ? 1 : 2;
	305	}
	306	break;
	307
adf85265 PC	308	case 5: /* 6x86MX/M II */
adf85265 PC	309	if (dir1 > 7) {
1da177e4 LT	310	dir0_msn++; /* M II */
	311	/* Enable MMX extensions (App note 108) */
	312	setCx86(CX86_CCR7, getCx86(CX86_CCR7)\|1);
adf85265	313	} else {
1da177e4 LT	314	c->coma_bug = 1; /* 6x86MX, it has the bug. */
	315	}
	316	tmp = (!(dir0_lsn & 7) \|\| dir0_lsn & 1) ? 2 : 0;
	317	Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
	318	p = Cx86_cb+tmp;
adf85265	319	if (((dir1 & 0x0f) > 4) \|\| ((dir1 & 0xf0) == 0x20))
1da177e4 LT	320	(c->x86_model)++;
1da177e4 LT	321	/* Emulate MTRRs using Cyrix's ARRs. */
1d007cd5	322	set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
1da177e4 LT	323	break;
	324
	325	case 0xf: /* Cyrix 486 without DEVID registers */
	326	switch (dir0_lsn) {
	327	case 0xd: /* either a 486SLC or DLC w/o DEVID */
	328	dir0_msn = 0;
	329	p = Cx486_name[(c->hard_math) ? 1 : 0];
	330	break;
	331
	332	case 0xe: /* a 486S A step */
	333	dir0_msn = 0;
	334	p = Cx486S_name[0];
	335	break;
	336	}
	337	break;
	338
	339	default: /* unknown (shouldn't happen, we know everyone ;-) */
	340	dir0_msn = 7;
	341	break;
	342	}
	343	strcpy(buf, Cx86_model[dir0_msn & 7]);
adf85265 PC	344	if (p)
adf85265 PC	345	strcat(buf, p);
1da177e4 LT	346	return;
	347	}
	348
f90b8116 JC	349	/*
	350	* Handle National Semiconductor branded processors
	351	*/
b4af3f7c	352	static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
f90b8116	353	{
adf85265 PC	354	/*
adf85265 PC	355	* There may be GX1 processors in the wild that are branded
f90b8116 JC	356	* NSC and not Cyrix.
	357	*
	358	* This function only handles the GX processor, and kicks every
	359	* thing else to the Cyrix init function above - that should
	360	* cover any processors that might have been branded differently
d6e05edc	361	* after NSC acquired Cyrix.
f90b8116 JC	362	*
	363	* If this breaks your GX1 horribly, please e-mail
	364	* info-linux@ldcmail.amd.com to tell us.
	365	*/
	366
	367	/* Handle the GX (Formally known as the GX2) */
	368
	369	if (c->x86 == 5 && c->x86_model == 5)
	370	display_cacheinfo(c);
	371	else
	372	init_cyrix(c);
	373	}
	374
1da177e4 LT	375	/*
	376	* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
	377	* by the fact that they preserve the flags across the division of 5/2.
	378	* PII and PPro exhibit this behavior too, but they have cpuid available.
	379	*/
adf85265	380
1da177e4 LT	381	/*
	382	* Perform the Cyrix 5/2 test. A Cyrix won't change
	383	* the flags, while other 486 chips will.
	384	*/
	385	static inline int test_cyrix_52div(void)
	386	{
	387	unsigned int test;
	388
	389	__asm__ __volatile__(
	390	"sahf\n\t" /* clear flags (%eax = 0x0005) */
	391	"div %b2\n\t" /* divide 5 by 2 */
	392	"lahf" /* store flags into %ah */
	393	: "=a" (test)
	394	: "0" (5), "q" (2)
	395	: "cc");
	396
	397	/* AH is 0x02 on Cyrix after the divide.. */
	398	return (unsigned char) (test >> 8) == 0x02;
	399	}
	400
adf85265	401	static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
1da177e4 LT	402	{
1da177e4 LT	403	/* Detect Cyrix with disabled CPUID */
adf85265	404	if (c->x86 == 4 && test_cyrix_52div()) {
1da177e4	405	unsigned char dir0, dir1;
adf85265	406
1da177e4	407	strcpy(c->x86_vendor_id, "CyrixInstead");
adf85265 PC	408	c->x86_vendor = X86_VENDOR_CYRIX;
	409
	410	/* Actually enable cpuid on the older cyrix */
	411
	412	/* Retrieve CPU revisions */
	413
1da177e4 LT	414	do_cyrix_devid(&dir0, &dir1);
1da177e4 LT	415
adf85265 PC	416	dir0 >>= 4;
adf85265 PC	417
1da177e4	418	/* Check it is an affected model */
adf85265 PC	419
adf85265 PC	420	if (dir0 == 5 \|\| dir0 == 3) {
bcde1ebb	421	unsigned char ccr3;
1da177e4 LT	422	unsigned long flags;
	423	printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
	424	local_irq_save(flags);
	425	ccr3 = getCx86(CX86_CCR3);
bcde1ebb TY	426	setCx86(CX86_CCR3, (ccr3 & 0x0f) \| 0x10); /* enable MAPEN */
	427	setCx86(CX86_CCR4, getCx86(CX86_CCR4) \| 0x80); /* enable cpuid */
	428	setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
1da177e4 LT	429	local_irq_restore(flags);
	430	}
	431	}
1da177e4 LT	432	}
1da177e4 LT	433
95414930	434	static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
1da177e4	435	.c_vendor = "Cyrix",
adf85265	436	.c_ident = { "CyrixInstead" },
1da177e4 LT	437	.c_init = init_cyrix,
	438	.c_identify = cyrix_identify,
	439	};
	440
03ae5768	441	cpu_vendor_dev_register(X86_VENDOR_CYRIX, &cyrix_cpu_dev);
1da177e4	442
95414930	443	static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
1da177e4	444	.c_vendor = "NSC",
adf85265	445	.c_ident = { "Geode by NSC" },
f90b8116	446	.c_init = init_nsc,
1da177e4 LT	447	};
1da177e4 LT	448
03ae5768	449	cpu_vendor_dev_register(X86_VENDOR_NSC, &nsc_cpu_dev);