Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> | |
3 | * | |
4 | * Licensed under the terms of the GNU GPL License version 2. | |
5 | * | |
6 | * Library for common functions for Intel SpeedStep v.1 and v.2 support | |
7 | * | |
8 | * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
32ee8c3e | 12 | #include <linux/module.h> |
1da177e4 LT |
13 | #include <linux/moduleparam.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/cpufreq.h> | |
1da177e4 LT |
16 | #include <linux/slab.h> |
17 | ||
18 | #include <asm/msr.h> | |
199785ea | 19 | #include <asm/tsc.h> |
1da177e4 LT |
20 | #include "speedstep-lib.h" |
21 | ||
bbfebd66 DJ |
22 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \ |
23 | "speedstep-lib", msg) | |
24 | ||
25 | #define PFX "speedstep-lib: " | |
1da177e4 LT |
26 | |
27 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
bbfebd66 | 28 | static int relaxed_check; |
1da177e4 LT |
29 | #else |
30 | #define relaxed_check 0 | |
31 | #endif | |
32 | ||
33 | /********************************************************************* | |
34 | * GET PROCESSOR CORE SPEED IN KHZ * | |
35 | *********************************************************************/ | |
36 | ||
bbfebd66 | 37 | static unsigned int pentium3_get_frequency(unsigned int processor) |
1da177e4 | 38 | { |
bbfebd66 | 39 | /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ |
1da177e4 LT |
40 | struct { |
41 | unsigned int ratio; /* Frequency Multiplier (x10) */ | |
32ee8c3e DJ |
42 | u8 bitmap; /* power on configuration bits |
43 | [27, 25:22] (in MSR 0x2a) */ | |
bbfebd66 | 44 | } msr_decode_mult[] = { |
1da177e4 LT |
45 | { 30, 0x01 }, |
46 | { 35, 0x05 }, | |
47 | { 40, 0x02 }, | |
48 | { 45, 0x06 }, | |
49 | { 50, 0x00 }, | |
50 | { 55, 0x04 }, | |
51 | { 60, 0x0b }, | |
52 | { 65, 0x0f }, | |
53 | { 70, 0x09 }, | |
54 | { 75, 0x0d }, | |
55 | { 80, 0x0a }, | |
56 | { 85, 0x26 }, | |
57 | { 90, 0x20 }, | |
58 | { 100, 0x2b }, | |
bbfebd66 | 59 | { 0, 0xff } /* error or unknown value */ |
1da177e4 LT |
60 | }; |
61 | ||
62 | /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ | |
63 | struct { | |
32ee8c3e DJ |
64 | unsigned int value; /* Front Side Bus speed in MHz */ |
65 | u8 bitmap; /* power on configuration bits [18: 19] | |
66 | (in MSR 0x2a) */ | |
bbfebd66 | 67 | } msr_decode_fsb[] = { |
1da177e4 LT |
68 | { 66, 0x0 }, |
69 | { 100, 0x2 }, | |
70 | { 133, 0x1 }, | |
71 | { 0, 0xff} | |
72 | }; | |
73 | ||
32ee8c3e DJ |
74 | u32 msr_lo, msr_tmp; |
75 | int i = 0, j = 0; | |
1da177e4 LT |
76 | |
77 | /* read MSR 0x2a - we only need the low 32 bits */ | |
78 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
79 | dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); | |
80 | msr_tmp = msr_lo; | |
81 | ||
82 | /* decode the FSB */ | |
83 | msr_tmp &= 0x00c0000; | |
84 | msr_tmp >>= 18; | |
85 | while (msr_tmp != msr_decode_fsb[i].bitmap) { | |
86 | if (msr_decode_fsb[i].bitmap == 0xff) | |
87 | return 0; | |
88 | i++; | |
89 | } | |
90 | ||
91 | /* decode the multiplier */ | |
bbfebd66 | 92 | if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) { |
1da177e4 LT |
93 | dprintk("workaround for early PIIIs\n"); |
94 | msr_lo &= 0x03c00000; | |
95 | } else | |
96 | msr_lo &= 0x0bc00000; | |
97 | msr_lo >>= 22; | |
98 | while (msr_lo != msr_decode_mult[j].bitmap) { | |
99 | if (msr_decode_mult[j].bitmap == 0xff) | |
100 | return 0; | |
101 | j++; | |
102 | } | |
103 | ||
bbfebd66 DJ |
104 | dprintk("speed is %u\n", |
105 | (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100)); | |
1da177e4 | 106 | |
bbfebd66 | 107 | return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100; |
1da177e4 LT |
108 | } |
109 | ||
110 | ||
111 | static unsigned int pentiumM_get_frequency(void) | |
112 | { | |
32ee8c3e | 113 | u32 msr_lo, msr_tmp; |
1da177e4 LT |
114 | |
115 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
116 | dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); | |
117 | ||
118 | /* see table B-2 of 24547212.pdf */ | |
119 | if (msr_lo & 0x00040000) { | |
bbfebd66 DJ |
120 | printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n", |
121 | msr_lo, msr_tmp); | |
1da177e4 LT |
122 | return 0; |
123 | } | |
124 | ||
125 | msr_tmp = (msr_lo >> 22) & 0x1f; | |
bbfebd66 DJ |
126 | dprintk("bits 22-26 are 0x%x, speed is %u\n", |
127 | msr_tmp, (msr_tmp * 100 * 1000)); | |
1da177e4 | 128 | |
bbfebd66 | 129 | return msr_tmp * 100 * 1000; |
1da177e4 LT |
130 | } |
131 | ||
4e74663c DB |
132 | static unsigned int pentium_core_get_frequency(void) |
133 | { | |
134 | u32 fsb = 0; | |
135 | u32 msr_lo, msr_tmp; | |
bbfebd66 | 136 | int ret; |
4e74663c DB |
137 | |
138 | rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp); | |
e11952b9 | 139 | /* see table B-2 of 25366920.pdf */ |
4e74663c DB |
140 | switch (msr_lo & 0x07) { |
141 | case 5: | |
e11952b9 | 142 | fsb = 100000; |
4e74663c DB |
143 | break; |
144 | case 1: | |
e11952b9 | 145 | fsb = 133333; |
4e74663c DB |
146 | break; |
147 | case 3: | |
e11952b9 | 148 | fsb = 166667; |
4e74663c | 149 | break; |
c60e19eb HRK |
150 | case 2: |
151 | fsb = 200000; | |
152 | break; | |
153 | case 0: | |
154 | fsb = 266667; | |
155 | break; | |
156 | case 4: | |
157 | fsb = 333333; | |
158 | break; | |
4e74663c DB |
159 | default: |
160 | printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value"); | |
161 | } | |
162 | ||
163 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
bbfebd66 DJ |
164 | dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", |
165 | msr_lo, msr_tmp); | |
4e74663c DB |
166 | |
167 | msr_tmp = (msr_lo >> 22) & 0x1f; | |
bbfebd66 DJ |
168 | dprintk("bits 22-26 are 0x%x, speed is %u\n", |
169 | msr_tmp, (msr_tmp * fsb)); | |
4e74663c | 170 | |
bbfebd66 DJ |
171 | ret = (msr_tmp * fsb); |
172 | return ret; | |
4e74663c | 173 | } |
e11952b9 | 174 | |
1da177e4 LT |
175 | |
176 | static unsigned int pentium4_get_frequency(void) | |
177 | { | |
178 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
179 | u32 msr_lo, msr_hi, mult; | |
180 | unsigned int fsb = 0; | |
bbfebd66 | 181 | unsigned int ret; |
199785ea MCO |
182 | u8 fsb_code; |
183 | ||
184 | /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency | |
185 | * to System Bus Frequency Ratio Field in the Processor Frequency | |
186 | * Configuration Register of the MSR. Therefore the current | |
187 | * frequency cannot be calculated and has to be measured. | |
188 | */ | |
189 | if (c->x86_model < 2) | |
190 | return cpu_khz; | |
1da177e4 LT |
191 | |
192 | rdmsr(0x2c, msr_lo, msr_hi); | |
193 | ||
194 | dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); | |
195 | ||
32ee8c3e | 196 | /* decode the FSB: see IA-32 Intel (C) Architecture Software |
1da177e4 LT |
197 | * Developer's Manual, Volume 3: System Prgramming Guide, |
198 | * revision #12 in Table B-1: MSRs in the Pentium 4 and | |
199 | * Intel Xeon Processors, on page B-4 and B-5. | |
200 | */ | |
199785ea MCO |
201 | fsb_code = (msr_lo >> 16) & 0x7; |
202 | switch (fsb_code) { | |
203 | case 0: | |
1da177e4 | 204 | fsb = 100 * 1000; |
199785ea MCO |
205 | break; |
206 | case 1: | |
207 | fsb = 13333 * 10; | |
208 | break; | |
209 | case 2: | |
210 | fsb = 200 * 1000; | |
211 | break; | |
1da177e4 LT |
212 | } |
213 | ||
214 | if (!fsb) | |
bbfebd66 DJ |
215 | printk(KERN_DEBUG PFX "couldn't detect FSB speed. " |
216 | "Please send an e-mail to <linux@brodo.de>\n"); | |
1da177e4 LT |
217 | |
218 | /* Multiplier. */ | |
ed9cbcd4 | 219 | mult = msr_lo >> 24; |
1da177e4 | 220 | |
bbfebd66 DJ |
221 | dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", |
222 | fsb, mult, (fsb * mult)); | |
1da177e4 | 223 | |
bbfebd66 DJ |
224 | ret = (fsb * mult); |
225 | return ret; | |
1da177e4 LT |
226 | } |
227 | ||
32ee8c3e | 228 | |
394122ab | 229 | /* Warning: may get called from smp_call_function_single. */ |
bbfebd66 | 230 | unsigned int speedstep_get_frequency(unsigned int processor) |
1da177e4 LT |
231 | { |
232 | switch (processor) { | |
bbfebd66 | 233 | case SPEEDSTEP_CPU_PCORE: |
4e74663c | 234 | return pentium_core_get_frequency(); |
bbfebd66 | 235 | case SPEEDSTEP_CPU_PM: |
1da177e4 | 236 | return pentiumM_get_frequency(); |
bbfebd66 DJ |
237 | case SPEEDSTEP_CPU_P4D: |
238 | case SPEEDSTEP_CPU_P4M: | |
1da177e4 | 239 | return pentium4_get_frequency(); |
bbfebd66 DJ |
240 | case SPEEDSTEP_CPU_PIII_T: |
241 | case SPEEDSTEP_CPU_PIII_C: | |
242 | case SPEEDSTEP_CPU_PIII_C_EARLY: | |
1da177e4 LT |
243 | return pentium3_get_frequency(processor); |
244 | default: | |
245 | return 0; | |
246 | }; | |
247 | return 0; | |
248 | } | |
bbfebd66 | 249 | EXPORT_SYMBOL_GPL(speedstep_get_frequency); |
1da177e4 LT |
250 | |
251 | ||
252 | /********************************************************************* | |
253 | * DETECT SPEEDSTEP-CAPABLE PROCESSOR * | |
254 | *********************************************************************/ | |
255 | ||
bbfebd66 | 256 | unsigned int speedstep_detect_processor(void) |
1da177e4 | 257 | { |
92cb7612 | 258 | struct cpuinfo_x86 *c = &cpu_data(0); |
32ee8c3e | 259 | u32 ebx, msr_lo, msr_hi; |
1da177e4 LT |
260 | |
261 | dprintk("x86: %x, model: %x\n", c->x86, c->x86_model); | |
262 | ||
32ee8c3e | 263 | if ((c->x86_vendor != X86_VENDOR_INTEL) || |
1da177e4 LT |
264 | ((c->x86 != 6) && (c->x86 != 0xF))) |
265 | return 0; | |
266 | ||
267 | if (c->x86 == 0xF) { | |
268 | /* Intel Mobile Pentium 4-M | |
269 | * or Intel Mobile Pentium 4 with 533 MHz FSB */ | |
270 | if (c->x86_model != 2) | |
271 | return 0; | |
272 | ||
273 | ebx = cpuid_ebx(0x00000001); | |
274 | ebx &= 0x000000FF; | |
275 | ||
276 | dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask); | |
277 | ||
278 | switch (c->x86_mask) { | |
32ee8c3e | 279 | case 4: |
1da177e4 | 280 | /* |
32ee8c3e | 281 | * B-stepping [M-P4-M] |
1da177e4 LT |
282 | * sample has ebx = 0x0f, production has 0x0e. |
283 | */ | |
284 | if ((ebx == 0x0e) || (ebx == 0x0f)) | |
bbfebd66 | 285 | return SPEEDSTEP_CPU_P4M; |
1da177e4 | 286 | break; |
32ee8c3e | 287 | case 7: |
1da177e4 LT |
288 | /* |
289 | * C-stepping [M-P4-M] | |
290 | * needs to have ebx=0x0e, else it's a celeron: | |
291 | * cf. 25130917.pdf / page 7, footnote 5 even | |
292 | * though 25072120.pdf / page 7 doesn't say | |
293 | * samples are only of B-stepping... | |
294 | */ | |
295 | if (ebx == 0x0e) | |
bbfebd66 | 296 | return SPEEDSTEP_CPU_P4M; |
1da177e4 LT |
297 | break; |
298 | case 9: | |
299 | /* | |
300 | * D-stepping [M-P4-M or M-P4/533] | |
301 | * | |
302 | * this is totally strange: CPUID 0x0F29 is | |
303 | * used by M-P4-M, M-P4/533 and(!) Celeron CPUs. | |
304 | * The latter need to be sorted out as they don't | |
305 | * support speedstep. | |
306 | * Celerons with CPUID 0x0F29 may have either | |
307 | * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything | |
308 | * specific. | |
309 | * M-P4-Ms may have either ebx=0xe or 0xf [see above] | |
310 | * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] | |
311 | * also, M-P4M HTs have ebx=0x8, too | |
bbfebd66 DJ |
312 | * For now, they are distinguished by the model_id |
313 | * string | |
1da177e4 | 314 | */ |
bbfebd66 DJ |
315 | if ((ebx == 0x0e) || |
316 | (strstr(c->x86_model_id, | |
317 | "Mobile Intel(R) Pentium(R) 4") != NULL)) | |
318 | return SPEEDSTEP_CPU_P4M; | |
1da177e4 LT |
319 | break; |
320 | default: | |
321 | break; | |
322 | } | |
323 | return 0; | |
324 | } | |
325 | ||
326 | switch (c->x86_model) { | |
327 | case 0x0B: /* Intel PIII [Tualatin] */ | |
bbfebd66 DJ |
328 | /* cpuid_ebx(1) is 0x04 for desktop PIII, |
329 | * 0x06 for mobile PIII-M */ | |
1da177e4 LT |
330 | ebx = cpuid_ebx(0x00000001); |
331 | dprintk("ebx is %x\n", ebx); | |
332 | ||
333 | ebx &= 0x000000FF; | |
334 | ||
335 | if (ebx != 0x06) | |
336 | return 0; | |
337 | ||
338 | /* So far all PIII-M processors support SpeedStep. See | |
32ee8c3e | 339 | * Intel's 24540640.pdf of June 2003 |
1da177e4 | 340 | */ |
bbfebd66 | 341 | return SPEEDSTEP_CPU_PIII_T; |
1da177e4 LT |
342 | |
343 | case 0x08: /* Intel PIII [Coppermine] */ | |
344 | ||
345 | /* all mobile PIII Coppermines have FSB 100 MHz | |
346 | * ==> sort out a few desktop PIIIs. */ | |
347 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); | |
bbfebd66 DJ |
348 | dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", |
349 | msr_lo, msr_hi); | |
1da177e4 LT |
350 | msr_lo &= 0x00c0000; |
351 | if (msr_lo != 0x0080000) | |
352 | return 0; | |
353 | ||
354 | /* | |
355 | * If the processor is a mobile version, | |
356 | * platform ID has bit 50 set | |
357 | * it has SpeedStep technology if either | |
358 | * bit 56 or 57 is set | |
359 | */ | |
360 | rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); | |
bbfebd66 DJ |
361 | dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", |
362 | msr_lo, msr_hi); | |
363 | if ((msr_hi & (1<<18)) && | |
364 | (relaxed_check ? 1 : (msr_hi & (3<<24)))) { | |
1da177e4 LT |
365 | if (c->x86_mask == 0x01) { |
366 | dprintk("early PIII version\n"); | |
bbfebd66 | 367 | return SPEEDSTEP_CPU_PIII_C_EARLY; |
1da177e4 | 368 | } else |
bbfebd66 | 369 | return SPEEDSTEP_CPU_PIII_C; |
1da177e4 LT |
370 | } |
371 | ||
372 | default: | |
373 | return 0; | |
374 | } | |
375 | } | |
376 | EXPORT_SYMBOL_GPL(speedstep_detect_processor); | |
377 | ||
378 | ||
379 | /********************************************************************* | |
380 | * DETECT SPEEDSTEP SPEEDS * | |
381 | *********************************************************************/ | |
382 | ||
383 | unsigned int speedstep_get_freqs(unsigned int processor, | |
384 | unsigned int *low_speed, | |
385 | unsigned int *high_speed, | |
1a10760c | 386 | unsigned int *transition_latency, |
1da177e4 LT |
387 | void (*set_state) (unsigned int state)) |
388 | { | |
389 | unsigned int prev_speed; | |
390 | unsigned int ret = 0; | |
391 | unsigned long flags; | |
1a10760c | 392 | struct timeval tv1, tv2; |
1da177e4 LT |
393 | |
394 | if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) | |
395 | return -EINVAL; | |
396 | ||
397 | dprintk("trying to determine both speeds\n"); | |
398 | ||
399 | /* get current speed */ | |
bbfebd66 | 400 | prev_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
401 | if (!prev_speed) |
402 | return -EIO; | |
403 | ||
f94ea640 | 404 | dprintk("previous speed is %u\n", prev_speed); |
1a10760c | 405 | |
1da177e4 LT |
406 | local_irq_save(flags); |
407 | ||
408 | /* switch to low state */ | |
409 | set_state(SPEEDSTEP_LOW); | |
bbfebd66 | 410 | *low_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
411 | if (!*low_speed) { |
412 | ret = -EIO; | |
413 | goto out; | |
414 | } | |
415 | ||
f94ea640 | 416 | dprintk("low speed is %u\n", *low_speed); |
1da177e4 | 417 | |
1a10760c MD |
418 | /* start latency measurement */ |
419 | if (transition_latency) | |
420 | do_gettimeofday(&tv1); | |
421 | ||
1da177e4 LT |
422 | /* switch to high state */ |
423 | set_state(SPEEDSTEP_HIGH); | |
1a10760c MD |
424 | |
425 | /* end latency measurement */ | |
426 | if (transition_latency) | |
427 | do_gettimeofday(&tv2); | |
428 | ||
bbfebd66 | 429 | *high_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
430 | if (!*high_speed) { |
431 | ret = -EIO; | |
432 | goto out; | |
433 | } | |
434 | ||
f94ea640 | 435 | dprintk("high speed is %u\n", *high_speed); |
1da177e4 LT |
436 | |
437 | if (*low_speed == *high_speed) { | |
438 | ret = -ENODEV; | |
439 | goto out; | |
440 | } | |
441 | ||
442 | /* switch to previous state, if necessary */ | |
443 | if (*high_speed != prev_speed) | |
444 | set_state(SPEEDSTEP_LOW); | |
445 | ||
1a10760c MD |
446 | if (transition_latency) { |
447 | *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC + | |
448 | tv2.tv_usec - tv1.tv_usec; | |
449 | dprintk("transition latency is %u uSec\n", *transition_latency); | |
450 | ||
451 | /* convert uSec to nSec and add 20% for safety reasons */ | |
452 | *transition_latency *= 1200; | |
453 | ||
454 | /* check if the latency measurement is too high or too low | |
455 | * and set it to a safe value (500uSec) in that case | |
456 | */ | |
bbfebd66 DJ |
457 | if (*transition_latency > 10000000 || |
458 | *transition_latency < 50000) { | |
459 | printk(KERN_WARNING PFX "frequency transition " | |
460 | "measured seems out of range (%u " | |
461 | "nSec), falling back to a safe one of" | |
462 | "%u nSec.\n", | |
1a10760c MD |
463 | *transition_latency, 500000); |
464 | *transition_latency = 500000; | |
465 | } | |
466 | } | |
467 | ||
32ee8c3e | 468 | out: |
1da177e4 | 469 | local_irq_restore(flags); |
bbfebd66 | 470 | return ret; |
1da177e4 LT |
471 | } |
472 | EXPORT_SYMBOL_GPL(speedstep_get_freqs); | |
473 | ||
474 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
475 | module_param(relaxed_check, int, 0444); | |
bbfebd66 DJ |
476 | MODULE_PARM_DESC(relaxed_check, |
477 | "Don't do all checks for speedstep capability."); | |
1da177e4 LT |
478 | #endif |
479 | ||
bbfebd66 DJ |
480 | MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>"); |
481 | MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); | |
482 | MODULE_LICENSE("GPL"); |