Commit | Line | Data |
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1da177e4 | 1 | /* |
1f729e06 | 2 | * (c) 2003-2006 Advanced Micro Devices, Inc. |
1da177e4 LT |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | */ | |
7 | ||
8 | struct powernow_k8_data { | |
9 | unsigned int cpu; | |
10 | ||
11 | u32 numps; /* number of p-states */ | |
12 | u32 batps; /* number of p-states supported on battery */ | |
c5829cd0 | 13 | u32 max_hw_pstate; /* maximum legal hardware pstate */ |
1da177e4 LT |
14 | |
15 | /* these values are constant when the PSB is used to determine | |
16 | * vid/fid pairings, but are modified during the ->target() call | |
17 | * when ACPI is used */ | |
18 | u32 rvo; /* ramp voltage offset */ | |
19 | u32 irt; /* isochronous relief time */ | |
20 | u32 vidmvs; /* usable value calculated from mvs */ | |
21 | u32 vstable; /* voltage stabilization time, units 20 us */ | |
22 | u32 plllock; /* pll lock time, units 1 us */ | |
841e40b3 | 23 | u32 exttype; /* extended interface = 1 */ |
1da177e4 | 24 | |
c5829cd0 ML |
25 | /* keep track of the current fid / vid or pstate */ |
26 | u32 currvid, currfid, currpstate; | |
1da177e4 LT |
27 | |
28 | /* the powernow_table includes all frequency and vid/fid pairings: | |
29 | * fid are the lower 8 bits of the index, vid are the upper 8 bits. | |
30 | * frequency is in kHz */ | |
31 | struct cpufreq_frequency_table *powernow_table; | |
32 | ||
33 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI | |
34 | /* the acpi table needs to be kept. it's only available if ACPI was | |
35 | * used to determine valid frequency/vid/fid states */ | |
f607e3a0 | 36 | struct acpi_processor_performance acpi_data; |
1da177e4 | 37 | #endif |
1f729e06 DJ |
38 | /* we need to keep track of associated cores, but let cpufreq |
39 | * handle hotplug events - so just point at cpufreq pol->cpus | |
40 | * structure */ | |
41 | cpumask_t *available_cores; | |
1da177e4 LT |
42 | }; |
43 | ||
44 | ||
45 | /* processor's cpuid instruction support */ | |
46 | #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ | |
47 | #define CPUID_XFAM 0x0ff00000 /* extended family */ | |
48 | #define CPUID_XFAM_K8 0 | |
49 | #define CPUID_XMOD 0x000f0000 /* extended model */ | |
6c9cda78 | 50 | #define CPUID_XMOD_REV_MASK 0x000c0000 |
30046e58 | 51 | #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */ |
1da177e4 LT |
52 | #define CPUID_USE_XFAM_XMOD 0x00000f00 |
53 | #define CPUID_GET_MAX_CAPABILITIES 0x80000000 | |
54 | #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 | |
55 | #define P_STATE_TRANSITION_CAPABLE 6 | |
56 | ||
57 | /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ | |
58 | /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ | |
59 | /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ | |
60 | /* the register number is placed in ecx, and the data is returned in edx:eax. */ | |
61 | ||
62 | #define MSR_FIDVID_CTL 0xc0010041 | |
63 | #define MSR_FIDVID_STATUS 0xc0010042 | |
64 | ||
65 | /* Field definitions within the FID VID Low Control MSR : */ | |
66 | #define MSR_C_LO_INIT_FID_VID 0x00010000 | |
841e40b3 DJ |
67 | #define MSR_C_LO_NEW_VID 0x00003f00 |
68 | #define MSR_C_LO_NEW_FID 0x0000003f | |
1da177e4 LT |
69 | #define MSR_C_LO_VID_SHIFT 8 |
70 | ||
71 | /* Field definitions within the FID VID High Control MSR : */ | |
32ee8c3e | 72 | #define MSR_C_HI_STP_GNT_TO 0x000fffff |
1da177e4 LT |
73 | |
74 | /* Field definitions within the FID VID Low Status MSR : */ | |
841e40b3 DJ |
75 | #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ |
76 | #define MSR_S_LO_MAX_RAMP_VID 0x3f000000 | |
1da177e4 LT |
77 | #define MSR_S_LO_MAX_FID 0x003f0000 |
78 | #define MSR_S_LO_START_FID 0x00003f00 | |
79 | #define MSR_S_LO_CURRENT_FID 0x0000003f | |
80 | ||
81 | /* Field definitions within the FID VID High Status MSR : */ | |
841e40b3 DJ |
82 | #define MSR_S_HI_MIN_WORKING_VID 0x3f000000 |
83 | #define MSR_S_HI_MAX_WORKING_VID 0x003f0000 | |
84 | #define MSR_S_HI_START_VID 0x00003f00 | |
85 | #define MSR_S_HI_CURRENT_VID 0x0000003f | |
86 | #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 | |
1da177e4 | 87 | |
1f729e06 DJ |
88 | |
89 | /* Hardware Pstate _PSS and MSR definitions */ | |
90 | #define USE_HW_PSTATE 0x00000080 | |
1f729e06 DJ |
91 | #define HW_PSTATE_MASK 0x00000007 |
92 | #define HW_PSTATE_VALID_MASK 0x80000000 | |
c5829cd0 ML |
93 | #define HW_PSTATE_MAX_MASK 0x000000f0 |
94 | #define HW_PSTATE_MAX_SHIFT 4 | |
1f729e06 DJ |
95 | #define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */ |
96 | #define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */ | |
97 | #define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */ | |
c5829cd0 | 98 | #define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */ |
1f729e06 DJ |
99 | |
100 | /* define the two driver architectures */ | |
101 | #define CPU_OPTERON 0 | |
102 | #define CPU_HW_PSTATE 1 | |
103 | ||
104 | ||
1da177e4 LT |
105 | /* |
106 | * There are restrictions frequencies have to follow: | |
107 | * - only 1 entry in the low fid table ( <=1.4GHz ) | |
108 | * - lowest entry in the high fid table must be >= 2 * the entry in the | |
109 | * low fid table | |
110 | * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry | |
111 | * in the low fid table | |
019a61b9 LM |
112 | * - the parts can only step at <= 200 MHz intervals, odd fid values are |
113 | * supported in revision G and later revisions. | |
1da177e4 LT |
114 | * - lowest frequency must be >= interprocessor hypertransport link speed |
115 | * (only applies to MP systems obviously) | |
116 | */ | |
117 | ||
118 | /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ | |
019a61b9 | 119 | #define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */ |
1da177e4 LT |
120 | #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ |
121 | ||
122 | #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ | |
123 | #define HI_VCOFREQ_TABLE_BOTTOM 1600 | |
124 | ||
125 | #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ | |
126 | ||
127 | #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ | |
841e40b3 | 128 | #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ |
1da177e4 LT |
129 | |
130 | #define MIN_FREQ 800 /* Min and max freqs, per spec */ | |
131 | #define MAX_FREQ 5000 | |
132 | ||
019a61b9 | 133 | #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */ |
841e40b3 DJ |
134 | #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ |
135 | ||
136 | #define VID_OFF 0x3f | |
1da177e4 LT |
137 | |
138 | #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ | |
139 | ||
140 | #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ | |
141 | ||
142 | #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ | |
27b46d76 | 143 | #define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */ |
1da177e4 LT |
144 | |
145 | /* | |
27b46d76 | 146 | * Most values of interest are encoded in a single field of the _PSS |
1da177e4 LT |
147 | * entries: the "control" value. |
148 | */ | |
32ee8c3e | 149 | |
1da177e4 LT |
150 | #define IRT_SHIFT 30 |
151 | #define RVO_SHIFT 28 | |
2bcad935 | 152 | #define EXT_TYPE_SHIFT 27 |
1da177e4 LT |
153 | #define PLL_L_SHIFT 20 |
154 | #define MVS_SHIFT 18 | |
155 | #define VST_SHIFT 11 | |
156 | #define VID_SHIFT 6 | |
157 | #define IRT_MASK 3 | |
158 | #define RVO_MASK 3 | |
2bcad935 | 159 | #define EXT_TYPE_MASK 1 |
1da177e4 LT |
160 | #define PLL_L_MASK 0x7f |
161 | #define MVS_MASK 3 | |
162 | #define VST_MASK 0x7f | |
163 | #define VID_MASK 0x1f | |
6cad647d LM |
164 | #define FID_MASK 0x1f |
165 | #define EXT_VID_MASK 0x3f | |
166 | #define EXT_FID_MASK 0x3f | |
1da177e4 LT |
167 | |
168 | ||
169 | /* | |
170 | * Version 1.4 of the PSB table. This table is constructed by BIOS and is | |
171 | * to tell the OS's power management driver which VIDs and FIDs are | |
172 | * supported by this particular processor. | |
173 | * If the data in the PSB / PST is wrong, then this driver will program the | |
174 | * wrong values into hardware, which is very likely to lead to a crash. | |
175 | */ | |
176 | ||
177 | #define PSB_ID_STRING "AMDK7PNOW!" | |
178 | #define PSB_ID_STRING_LEN 10 | |
179 | ||
180 | #define PSB_VERSION_1_4 0x14 | |
181 | ||
182 | struct psb_s { | |
183 | u8 signature[10]; | |
184 | u8 tableversion; | |
185 | u8 flags1; | |
186 | u16 vstable; | |
187 | u8 flags2; | |
188 | u8 num_tables; | |
189 | u32 cpuid; | |
190 | u8 plllocktime; | |
191 | u8 maxfid; | |
192 | u8 maxvid; | |
193 | u8 numps; | |
194 | }; | |
195 | ||
196 | /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ | |
197 | struct pst_s { | |
198 | u8 fid; | |
199 | u8 vid; | |
200 | }; | |
201 | ||
202 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg) | |
203 | ||
204 | static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid); | |
205 | static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); | |
206 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); | |
207 | ||
208 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); | |
065b807c | 209 | |
b96e80e3 | 210 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI |
1f729e06 DJ |
211 | static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); |
212 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); | |
b96e80e3 | 213 | #endif |
1f729e06 | 214 | |
065b807c DJ |
215 | #ifdef CONFIG_SMP |
216 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) | |
217 | { | |
218 | } | |
219 | #else | |
220 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) | |
221 | { | |
222 | cpu_set(0, cpu_sharedcore_mask[0]); | |
223 | } | |
224 | #endif |