Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
dcd32b6a | 2 | #ifndef ARCH_X86_CPU_H |
dcd32b6a | 3 | #define ARCH_X86_CPU_H |
1da177e4 | 4 | |
ebdb2036 TG |
5 | #include <asm/cpu.h> |
6 | #include <asm/topology.h> | |
7 | ||
8 | #include "topology.h" | |
9 | ||
1da177e4 LT |
10 | /* attempt to consolidate cpu attributes */ |
11 | struct cpu_dev { | |
f2362e6f | 12 | const char *c_vendor; |
1da177e4 LT |
13 | |
14 | /* some have two possibilities for cpuid string */ | |
f2362e6f | 15 | const char *c_ident[2]; |
1da177e4 | 16 | |
f2362e6f | 17 | void (*c_early_init)(struct cpuinfo_x86 *); |
a110b5ec | 18 | void (*c_bsp_init)(struct cpuinfo_x86 *); |
f2362e6f JSR |
19 | void (*c_init)(struct cpuinfo_x86 *); |
20 | void (*c_identify)(struct cpuinfo_x86 *); | |
e0ba94f1 | 21 | void (*c_detect_tlb)(struct cpuinfo_x86 *); |
f2362e6f | 22 | int c_x86_vendor; |
09dc68d9 JB |
23 | #ifdef CONFIG_X86_32 |
24 | /* Optional vendor specific routine to obtain the cache size. */ | |
25 | unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *, | |
26 | unsigned int); | |
27 | ||
28 | /* Family/stepping-based lookup table for model names. */ | |
29 | struct legacy_cpu_model_info { | |
30 | int family; | |
31 | const char *model_names[16]; | |
32 | } legacy_models[5]; | |
33 | #endif | |
1da177e4 LT |
34 | }; |
35 | ||
e0ba94f1 AS |
36 | struct _tlb_table { |
37 | unsigned char descriptor; | |
38 | char tlb_type; | |
39 | unsigned int entries; | |
40 | /* unsigned int ways; */ | |
41 | char info[128]; | |
42 | }; | |
43 | ||
10a434fc | 44 | #define cpu_dev_register(cpu_devX) \ |
02dde8b4 | 45 | static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \ |
33def849 | 46 | __section(".x86_cpu_dev.init") = \ |
10a434fc | 47 | &cpu_devX; |
1da177e4 | 48 | |
02dde8b4 JB |
49 | extern const struct cpu_dev *const __x86_cpu_dev_start[], |
50 | *const __x86_cpu_dev_end[]; | |
03ae5768 | 51 | |
95c5824f PG |
52 | #ifdef CONFIG_CPU_SUP_INTEL |
53 | enum tsx_ctrl_states { | |
54 | TSX_CTRL_ENABLE, | |
55 | TSX_CTRL_DISABLE, | |
29364930 | 56 | TSX_CTRL_RTM_ALWAYS_ABORT, |
95c5824f PG |
57 | TSX_CTRL_NOT_SUPPORTED, |
58 | }; | |
59 | ||
60 | extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state; | |
61 | ||
62 | extern void __init tsx_init(void); | |
400331f8 | 63 | void tsx_ap_init(void); |
0c2f6d04 | 64 | void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c); |
95c5824f PG |
65 | #else |
66 | static inline void tsx_init(void) { } | |
400331f8 | 67 | static inline void tsx_ap_init(void) { } |
0c2f6d04 | 68 | static inline void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { } |
95c5824f PG |
69 | #endif /* CONFIG_CPU_SUP_INTEL */ |
70 | ||
d7caac99 PZ |
71 | extern void init_spectral_chicken(struct cpuinfo_x86 *c); |
72 | ||
c2b9ff24 | 73 | extern void get_cpu_cap(struct cpuinfo_x86 *c); |
405c018a | 74 | extern void get_cpu_address_sizes(struct cpuinfo_x86 *c); |
27c13ece | 75 | extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); |
b5cf8707 | 76 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
807e9bc8 | 77 | extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); |
b5cf8707 | 78 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
d4f7423e | 79 | extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); |
b5cf8707 | 80 | |
415de440 | 81 | extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); |
7d5905dc | 82 | |
f7fb3b2d | 83 | void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id); |
6e290323 TG |
84 | void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c); |
85 | ||
7d5905dc | 86 | unsigned int aperfmperf_get_khz(int cpu); |
7c7077a7 | 87 | void cpu_select_mitigations(void); |
7d5905dc | 88 | |
77243971 | 89 | extern void x86_spec_ctrl_setup_ap(void); |
7e5b3c26 | 90 | extern void update_srbds_msr(void); |
8974eb58 | 91 | extern void update_gds_msr(void); |
77243971 | 92 | |
8cc68c9c BPA |
93 | extern enum spectre_v2_mitigation spectre_v2_enabled; |
94 | ||
95 | static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode) | |
96 | { | |
97 | return mode == SPECTRE_V2_EIBRS || | |
98 | mode == SPECTRE_V2_EIBRS_RETPOLINE || | |
99 | mode == SPECTRE_V2_EIBRS_LFENCE; | |
100 | } | |
ebdb2036 | 101 | |
d059f24a | 102 | #endif /* ARCH_X86_CPU_H */ |