projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| dcd32b6a | 2 | #ifndef ARCH_X86_CPU_H |
| dcd32b6a | 3 | #define ARCH_X86_CPU_H |
| 1da177e4 | 4 | |
| 1da177e4 LT |
5 | /* attempt to consolidate cpu attributes */ |
| 6 | struct cpu_dev { | |
| f2362e6f | 7 | const char *c_vendor; |
| 1da177e4 LT |
8 | |
| 9 | /* some have two possibilities for cpuid string */ | |
| f2362e6f | 10 | const char *c_ident[2]; |
| 1da177e4 | 11 | |
| f2362e6f | 12 | void (*c_early_init)(struct cpuinfo_x86 *); |
| a110b5ec | 13 | void (*c_bsp_init)(struct cpuinfo_x86 *); |
| f2362e6f JSR |
14 | void (*c_init)(struct cpuinfo_x86 *); |
| 15 | void (*c_identify)(struct cpuinfo_x86 *); | |
| e0ba94f1 | 16 | void (*c_detect_tlb)(struct cpuinfo_x86 *); |
| f2362e6f | 17 | int c_x86_vendor; |
| 09dc68d9 JB |
18 | #ifdef CONFIG_X86_32 |
| 19 | /* Optional vendor specific routine to obtain the cache size. */ | |
| 20 | unsigned int (*legacy_cache_size)(struct cpuinfo_x86 *, | |
| 21 | unsigned int); | |
| 22 | ||
| 23 | /* Family/stepping-based lookup table for model names. */ | |
| 24 | struct legacy_cpu_model_info { | |
| 25 | int family; | |
| 26 | const char *model_names[16]; | |
| 27 | } legacy_models[5]; | |
| 28 | #endif | |
| 1da177e4 LT |
29 | }; |
| 30 | ||
| e0ba94f1 AS |
31 | struct _tlb_table { |
| 32 | unsigned char descriptor; | |
| 33 | char tlb_type; | |
| 34 | unsigned int entries; | |
| 35 | /* unsigned int ways; */ | |
| 36 | char info[128]; | |
| 37 | }; | |
| 38 | ||
| 10a434fc | 39 | #define cpu_dev_register(cpu_devX) \ |
| 02dde8b4 | 40 | static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \ |
| 33def849 | 41 | __section(".x86_cpu_dev.init") = \ |
| 10a434fc | 42 | &cpu_devX; |
| 1da177e4 | 43 | |
| 02dde8b4 JB |
44 | extern const struct cpu_dev *const __x86_cpu_dev_start[], |
| 45 | *const __x86_cpu_dev_end[]; | |
| 03ae5768 | 46 | |
| 95c5824f PG |
47 | #ifdef CONFIG_CPU_SUP_INTEL |
| 48 | enum tsx_ctrl_states { | |
| 49 | TSX_CTRL_ENABLE, | |
| 50 | TSX_CTRL_DISABLE, | |
| 29364930 | 51 | TSX_CTRL_RTM_ALWAYS_ABORT, |
| 95c5824f PG |
52 | TSX_CTRL_NOT_SUPPORTED, |
| 53 | }; | |
| 54 | ||
| 55 | extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state; | |
| 56 | ||
| 57 | extern void __init tsx_init(void); | |
| 58 | extern void tsx_enable(void); | |
| 59 | extern void tsx_disable(void); | |
| 29364930 | 60 | extern void tsx_clear_cpuid(void); |
| 95c5824f PG |
61 | #else |
| 62 | static inline void tsx_init(void) { } | |
| 63 | #endif /* CONFIG_CPU_SUP_INTEL */ | |
| 64 | ||
| c2b9ff24 | 65 | extern void get_cpu_cap(struct cpuinfo_x86 *c); |
| 405c018a | 66 | extern void get_cpu_address_sizes(struct cpuinfo_x86 *c); |
| 27c13ece | 67 | extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c); |
| b5cf8707 | 68 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
| 807e9bc8 | 69 | extern void init_intel_cacheinfo(struct cpuinfo_x86 *c); |
| b5cf8707 | 70 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
| d4f7423e | 71 | extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c); |
| b5cf8707 | 72 | |
| 9305bd6c | 73 | extern void detect_num_cpu_cores(struct cpuinfo_x86 *c); |
| 95f3d39c | 74 | extern int detect_extended_topology_early(struct cpuinfo_x86 *c); |
| b5cf8707 | 75 | extern int detect_extended_topology(struct cpuinfo_x86 *c); |
| 545401f4 | 76 | extern int detect_ht_early(struct cpuinfo_x86 *c); |
| b5cf8707 | 77 | extern void detect_ht(struct cpuinfo_x86 *c); |
| 7d5905dc RW |
78 | |
| 79 | unsigned int aperfmperf_get_khz(int cpu); | |
| 80 | ||
| 77243971 | 81 | extern void x86_spec_ctrl_setup_ap(void); |
| 7e5b3c26 | 82 | extern void update_srbds_msr(void); |
| 77243971 | 83 | |
| 286836a7 PG |
84 | extern u64 x86_read_arch_cap_msr(void); |
| 85 | ||
| d059f24a | 86 | #endif /* ARCH_X86_CPU_H */ |