Commit | Line | Data |
---|---|---|
1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
7e00df58 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
1da177e4 LT |
23 | #ifdef CONFIG_X86_LOCAL_APIC |
24 | #include <asm/mpspec.h> | |
25 | #include <asm/apic.h> | |
26 | #include <mach_apic.h> | |
f0fc4aff | 27 | #include <asm/genapic.h> |
1da177e4 LT |
28 | #endif |
29 | ||
f0fc4aff YL |
30 | #include <asm/pda.h> |
31 | #include <asm/pgtable.h> | |
32 | #include <asm/processor.h> | |
33 | #include <asm/desc.h> | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/proto.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/setup.h> | |
38 | ||
1da177e4 LT |
39 | #include "cpu.h" |
40 | ||
0a488a53 YL |
41 | static struct cpu_dev *this_cpu __cpuinitdata; |
42 | ||
63cc8c75 | 43 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
6842ef0e GOC |
44 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
45 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
46 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
47 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
48 | /* |
49 | * Segments used for calling PnP BIOS have byte granularity. | |
50 | * They code segments and data segments have fixed 64k limits, | |
51 | * the transfer segment sizes are set at run time. | |
52 | */ | |
6842ef0e GOC |
53 | /* 32-bit code */ |
54 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
55 | /* 16-bit code */ | |
56 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
57 | /* 16-bit data */ | |
58 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
59 | /* 16-bit data */ | |
60 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
61 | /* 16-bit data */ | |
62 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
63 | /* |
64 | * The APM segments have byte granularity and their bases | |
65 | * are set at run time. All have 64k limits. | |
66 | */ | |
6842ef0e GOC |
67 | /* 32-bit code */ |
68 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 69 | /* 16-bit code */ |
6842ef0e GOC |
70 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
71 | /* data */ | |
72 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 73 | |
6842ef0e GOC |
74 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
75 | [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } }, | |
7a61d35d JF |
76 | } }; |
77 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); | |
ae1ee11b | 78 | |
3bc9b76b | 79 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 80 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 81 | |
0a488a53 YL |
82 | static int __init cachesize_setup(char *str) |
83 | { | |
84 | get_option(&str, &cachesize_override); | |
85 | return 1; | |
86 | } | |
87 | __setup("cachesize=", cachesize_setup); | |
88 | ||
89 | /* | |
90 | * Naming convention should be: <Name> [(<Codename>)] | |
91 | * This table only is used unless init_<vendor>() below doesn't set it; | |
92 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
93 | * | |
94 | */ | |
95 | ||
96 | /* Look up CPU names by table lookup. */ | |
97 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
98 | { | |
99 | struct cpu_model_info *info; | |
100 | ||
101 | if (c->x86_model >= 16) | |
102 | return NULL; /* Range check */ | |
103 | ||
104 | if (!this_cpu) | |
105 | return NULL; | |
106 | ||
107 | info = this_cpu->c_models; | |
108 | ||
109 | while (info && info->family) { | |
110 | if (info->family == c->x86) | |
111 | return info->model_names[c->x86_model]; | |
112 | info++; | |
113 | } | |
114 | return NULL; /* Not found */ | |
115 | } | |
116 | ||
117 | static int __init x86_fxsr_setup(char *s) | |
118 | { | |
119 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
120 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
121 | return 1; | |
122 | } | |
123 | __setup("nofxsr", x86_fxsr_setup); | |
124 | ||
125 | static int __init x86_sep_setup(char *s) | |
126 | { | |
127 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
128 | return 1; | |
129 | } | |
130 | __setup("nosep", x86_sep_setup); | |
131 | ||
132 | /* Standard macro to see if a specific flag is changeable */ | |
133 | static inline int flag_is_changeable_p(u32 flag) | |
134 | { | |
135 | u32 f1, f2; | |
136 | ||
137 | asm("pushfl\n\t" | |
138 | "pushfl\n\t" | |
139 | "popl %0\n\t" | |
140 | "movl %0,%1\n\t" | |
141 | "xorl %2,%0\n\t" | |
142 | "pushl %0\n\t" | |
143 | "popfl\n\t" | |
144 | "pushfl\n\t" | |
145 | "popl %0\n\t" | |
146 | "popfl\n\t" | |
147 | : "=&r" (f1), "=&r" (f2) | |
148 | : "ir" (flag)); | |
149 | ||
150 | return ((f1^f2) & flag) != 0; | |
151 | } | |
152 | ||
153 | /* Probe for the CPUID instruction */ | |
154 | static int __cpuinit have_cpuid_p(void) | |
155 | { | |
156 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
157 | } | |
158 | ||
159 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
160 | { | |
161 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
162 | /* Disable processor serial number */ | |
163 | unsigned long lo, hi; | |
164 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
165 | lo |= 0x200000; | |
166 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
167 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
168 | clear_cpu_cap(c, X86_FEATURE_PN); | |
169 | ||
170 | /* Disabling the serial number may affect the cpuid level */ | |
171 | c->cpuid_level = cpuid_eax(0); | |
172 | } | |
173 | } | |
174 | ||
175 | static int __init x86_serial_nr_setup(char *s) | |
176 | { | |
177 | disable_x86_serial_nr = 0; | |
178 | return 1; | |
179 | } | |
180 | __setup("serialnumber", x86_serial_nr_setup); | |
181 | ||
7d851c8d AK |
182 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
183 | ||
9d31d35b YL |
184 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
185 | * it's on the real one. */ | |
186 | void switch_to_new_gdt(void) | |
187 | { | |
188 | struct desc_ptr gdt_descr; | |
189 | ||
190 | gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id()); | |
191 | gdt_descr.size = GDT_SIZE - 1; | |
192 | load_gdt(&gdt_descr); | |
193 | asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory"); | |
194 | } | |
195 | ||
10a434fc | 196 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 197 | |
34048c9e | 198 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
199 | { |
200 | /* Not much we can do here... */ | |
201 | /* Check if at least it has cpuid */ | |
202 | if (c->cpuid_level == -1) { | |
203 | /* No cpuid. It must be an ancient CPU */ | |
204 | if (c->x86 == 4) | |
205 | strcpy(c->x86_model_id, "486"); | |
206 | else if (c->x86 == 3) | |
207 | strcpy(c->x86_model_id, "386"); | |
208 | } | |
209 | } | |
210 | ||
95414930 | 211 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 212 | .c_init = default_init, |
fe38d855 | 213 | .c_vendor = "Unknown", |
10a434fc | 214 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 215 | }; |
1da177e4 | 216 | |
3bc9b76b | 217 | int __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
218 | { |
219 | unsigned int *v; | |
220 | char *p, *q; | |
221 | ||
3da99c97 | 222 | if (c->extended_cpuid_level < 0x80000004) |
1da177e4 LT |
223 | return 0; |
224 | ||
225 | v = (unsigned int *) c->x86_model_id; | |
226 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
227 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
228 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
229 | c->x86_model_id[48] = 0; | |
230 | ||
231 | /* Intel chips right-justify this string for some dumb reason; | |
232 | undo that brain damage */ | |
233 | p = q = &c->x86_model_id[0]; | |
34048c9e | 234 | while (*p == ' ') |
1da177e4 | 235 | p++; |
34048c9e PC |
236 | if (p != q) { |
237 | while (*p) | |
1da177e4 | 238 | *q++ = *p++; |
34048c9e | 239 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
240 | *q++ = '\0'; /* Zero-pad the rest */ |
241 | } | |
242 | ||
243 | return 1; | |
244 | } | |
245 | ||
3bc9b76b | 246 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 247 | { |
9d31d35b | 248 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 249 | |
3da99c97 | 250 | n = c->extended_cpuid_level; |
1da177e4 LT |
251 | |
252 | if (n >= 0x80000005) { | |
9d31d35b | 253 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 254 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
255 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
256 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
1da177e4 LT |
257 | } |
258 | ||
259 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
260 | return; | |
261 | ||
0a488a53 | 262 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 263 | l2size = ecx >> 16; |
34048c9e | 264 | |
1da177e4 LT |
265 | /* do processor-specific cache resizing */ |
266 | if (this_cpu->c_size_cache) | |
34048c9e | 267 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
268 | |
269 | /* Allow user to override all this if necessary. */ | |
270 | if (cachesize_override != -1) | |
271 | l2size = cachesize_override; | |
272 | ||
34048c9e | 273 | if (l2size == 0) |
1da177e4 LT |
274 | return; /* Again, no L2 cache is possible */ |
275 | ||
276 | c->x86_cache_size = l2size; | |
277 | ||
278 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 279 | l2size, ecx & 0xFF); |
1da177e4 LT |
280 | } |
281 | ||
9d31d35b | 282 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 283 | { |
97e4db7c | 284 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
285 | u32 eax, ebx, ecx, edx; |
286 | int index_msb, core_bits; | |
1da177e4 | 287 | |
0a488a53 | 288 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 289 | return; |
1da177e4 | 290 | |
0a488a53 YL |
291 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
292 | goto out; | |
1da177e4 | 293 | |
0a488a53 | 294 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 295 | |
9d31d35b YL |
296 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
297 | ||
298 | if (smp_num_siblings == 1) { | |
299 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
300 | } else if (smp_num_siblings > 1) { | |
301 | ||
302 | if (smp_num_siblings > NR_CPUS) { | |
303 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", | |
304 | smp_num_siblings); | |
305 | smp_num_siblings = 1; | |
306 | return; | |
307 | } | |
308 | ||
309 | index_msb = get_count_order(smp_num_siblings); | |
310 | c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb); | |
311 | ||
9d31d35b YL |
312 | |
313 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
314 | ||
315 | index_msb = get_count_order(smp_num_siblings); | |
316 | ||
317 | core_bits = get_count_order(c->x86_max_cores); | |
318 | ||
319 | c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) & | |
320 | ((1 << core_bits) - 1); | |
1da177e4 | 321 | } |
1da177e4 | 322 | |
0a488a53 YL |
323 | out: |
324 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
325 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
326 | c->phys_proc_id); | |
327 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
328 | c->cpu_core_id); | |
9d31d35b | 329 | } |
9d31d35b | 330 | #endif |
97e4db7c | 331 | } |
1da177e4 | 332 | |
3da99c97 | 333 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
334 | { |
335 | char *v = c->x86_vendor_id; | |
336 | int i; | |
fe38d855 | 337 | static int printed; |
1da177e4 LT |
338 | |
339 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
340 | if (!cpu_devs[i]) |
341 | break; | |
342 | ||
343 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
344 | (cpu_devs[i]->c_ident[1] && | |
345 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
346 | this_cpu = cpu_devs[i]; | |
347 | c->x86_vendor = this_cpu->c_x86_vendor; | |
348 | return; | |
1da177e4 LT |
349 | } |
350 | } | |
10a434fc | 351 | |
fe38d855 CE |
352 | if (!printed) { |
353 | printed++; | |
354 | printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n"); | |
355 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); | |
356 | } | |
10a434fc | 357 | |
fe38d855 CE |
358 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
359 | this_cpu = &default_cpu; | |
1da177e4 LT |
360 | } |
361 | ||
9d31d35b | 362 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 363 | { |
1da177e4 | 364 | /* Get vendor name */ |
4a148513 HH |
365 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
366 | (unsigned int *)&c->x86_vendor_id[0], | |
367 | (unsigned int *)&c->x86_vendor_id[8], | |
368 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 369 | |
1da177e4 | 370 | c->x86 = 4; |
9d31d35b | 371 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
372 | if (c->cpuid_level >= 0x00000001) { |
373 | u32 junk, tfms, cap0, misc; | |
374 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
375 | c->x86 = (tfms >> 8) & 0xf; |
376 | c->x86_model = (tfms >> 4) & 0xf; | |
377 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 378 | if (c->x86 == 0xf) |
1da177e4 | 379 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 380 | if (c->x86 >= 0x6) |
9d31d35b | 381 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 382 | if (cap0 & (1<<19)) { |
d4387bd3 | 383 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 384 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 385 | } |
1da177e4 | 386 | } |
1da177e4 | 387 | } |
3da99c97 YL |
388 | |
389 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
390 | { |
391 | u32 tfms, xlvl; | |
3da99c97 | 392 | u32 ebx; |
093af8d7 | 393 | |
3da99c97 YL |
394 | /* Intel-defined flags: level 0x00000001 */ |
395 | if (c->cpuid_level >= 0x00000001) { | |
396 | u32 capability, excap; | |
397 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
398 | c->x86_capability[0] = capability; | |
399 | c->x86_capability[4] = excap; | |
400 | } | |
093af8d7 | 401 | |
3da99c97 YL |
402 | /* AMD-defined flags: level 0x80000001 */ |
403 | xlvl = cpuid_eax(0x80000000); | |
404 | c->extended_cpuid_level = xlvl; | |
405 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
406 | if (xlvl >= 0x80000001) { | |
407 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
408 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 409 | } |
093af8d7 | 410 | } |
093af8d7 | 411 | } |
34048c9e PC |
412 | /* |
413 | * Do minimum CPU detection early. | |
414 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
415 | * cache alignment. | |
416 | * The others are not touched to avoid unwanted side effects. | |
417 | * | |
418 | * WARNING: this function is only called on the BP. Don't add code here | |
419 | * that is supposed to run on all CPUs. | |
420 | */ | |
3da99c97 | 421 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 422 | { |
d4387bd3 | 423 | c->x86_clflush_size = 32; |
0a488a53 | 424 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 RR |
425 | |
426 | if (!have_cpuid_p()) | |
427 | return; | |
428 | ||
3da99c97 YL |
429 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
430 | ||
0a488a53 YL |
431 | c->extended_cpuid_level = 0; |
432 | ||
d7cd5611 RR |
433 | cpu_detect(c); |
434 | ||
3da99c97 | 435 | get_cpu_vendor(c); |
2b16a235 | 436 | |
3da99c97 | 437 | get_cpu_cap(c); |
2b16a235 | 438 | |
10a434fc YL |
439 | if (this_cpu->c_early_init) |
440 | this_cpu->c_early_init(c); | |
093af8d7 | 441 | |
3da99c97 | 442 | validate_pat_support(c); |
d7cd5611 RR |
443 | } |
444 | ||
9d31d35b YL |
445 | void __init early_cpu_init(void) |
446 | { | |
10a434fc YL |
447 | struct cpu_dev **cdev; |
448 | int count = 0; | |
449 | ||
450 | printk("KERNEL supported cpus:\n"); | |
451 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
452 | struct cpu_dev *cpudev = *cdev; | |
453 | unsigned int j; | |
9d31d35b | 454 | |
10a434fc YL |
455 | if (count >= X86_VENDOR_NUM) |
456 | break; | |
457 | cpu_devs[count] = cpudev; | |
458 | count++; | |
459 | ||
460 | for (j = 0; j < 2; j++) { | |
461 | if (!cpudev->c_ident[j]) | |
462 | continue; | |
463 | printk(" %s %s\n", cpudev->c_vendor, | |
464 | cpudev->c_ident[j]); | |
465 | } | |
466 | } | |
9d31d35b | 467 | |
9d31d35b | 468 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 RR |
469 | } |
470 | ||
7e00df58 PA |
471 | /* |
472 | * The NOPL instruction is supposed to exist on all CPUs with | |
473 | * family >= 6, unfortunately, that's not true in practice because | |
474 | * of early VIA chips and (more importantly) broken virtualizers that | |
475 | * are not easy to detect. Hence, probe for it based on first | |
476 | * principles. | |
477 | */ | |
478 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
479 | { | |
480 | const u32 nopl_signature = 0x888c53b1; /* Random number */ | |
481 | u32 has_nopl = nopl_signature; | |
482 | ||
483 | clear_cpu_cap(c, X86_FEATURE_NOPL); | |
484 | if (c->x86 >= 6) { | |
485 | asm volatile("\n" | |
486 | "1: .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */ | |
487 | "2:\n" | |
488 | " .section .fixup,\"ax\"\n" | |
489 | "3: xor %0,%0\n" | |
490 | " jmp 2b\n" | |
491 | " .previous\n" | |
492 | _ASM_EXTABLE(1b,3b) | |
493 | : "+a" (has_nopl)); | |
494 | ||
495 | if (has_nopl == nopl_signature) | |
496 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
497 | } | |
498 | } | |
499 | ||
34048c9e | 500 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 501 | { |
3da99c97 YL |
502 | if (!have_cpuid_p()) |
503 | return; | |
1da177e4 | 504 | |
3da99c97 | 505 | c->extended_cpuid_level = 0; |
1d67953f | 506 | |
3da99c97 | 507 | cpu_detect(c); |
1da177e4 | 508 | |
3da99c97 | 509 | get_cpu_vendor(c); |
1da177e4 | 510 | |
3da99c97 | 511 | get_cpu_cap(c); |
1da177e4 | 512 | |
3da99c97 YL |
513 | if (c->cpuid_level >= 0x00000001) { |
514 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
96c52749 | 515 | #ifdef CONFIG_X86_HT |
3da99c97 YL |
516 | c->apicid = phys_pkg_id(c->initial_apicid, 0); |
517 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 518 | #else |
3da99c97 | 519 | c->apicid = c->initial_apicid; |
1e9f28fa | 520 | #endif |
3da99c97 | 521 | } |
1da177e4 | 522 | |
3da99c97 YL |
523 | if (c->extended_cpuid_level >= 0x80000004) |
524 | get_model_name(c); /* Default name */ | |
1da177e4 | 525 | |
3da99c97 YL |
526 | init_scattered_cpuid_features(c); |
527 | detect_nopl(c); | |
1da177e4 | 528 | } |
1da177e4 LT |
529 | |
530 | /* | |
531 | * This does the hard work of actually picking apart the CPU stuff... | |
532 | */ | |
9a250347 | 533 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
534 | { |
535 | int i; | |
536 | ||
537 | c->loops_per_jiffy = loops_per_jiffy; | |
538 | c->x86_cache_size = -1; | |
539 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
540 | c->cpuid_level = -1; /* CPUID not detected */ | |
541 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ | |
542 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
543 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 544 | c->x86_max_cores = 1; |
770d132f | 545 | c->x86_clflush_size = 32; |
1da177e4 LT |
546 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
547 | ||
548 | if (!have_cpuid_p()) { | |
34048c9e PC |
549 | /* |
550 | * First of all, decide if this is a 486 or higher | |
551 | * It's a 486 if we can modify the AC flag | |
552 | */ | |
553 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1da177e4 LT |
554 | c->x86 = 4; |
555 | else | |
556 | c->x86 = 3; | |
557 | } | |
558 | ||
559 | generic_identify(c); | |
560 | ||
3898534d | 561 | if (this_cpu->c_identify) |
1da177e4 LT |
562 | this_cpu->c_identify(c); |
563 | ||
1da177e4 LT |
564 | /* |
565 | * Vendor-specific initialization. In this section we | |
566 | * canonicalize the feature flags, meaning if there are | |
567 | * features a certain CPU supports which CPUID doesn't | |
568 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
569 | * we handle them here. | |
570 | * | |
571 | * At the end of this section, c->x86_capability better | |
572 | * indicate the features this CPU genuinely supports! | |
573 | */ | |
574 | if (this_cpu->c_init) | |
575 | this_cpu->c_init(c); | |
576 | ||
577 | /* Disable the PN if appropriate */ | |
578 | squash_the_stupid_serial_number(c); | |
579 | ||
580 | /* | |
581 | * The vendor-specific functions might have changed features. Now | |
582 | * we do "generic changes." | |
583 | */ | |
584 | ||
1da177e4 | 585 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 586 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
587 | char *p; |
588 | p = table_lookup_model(c); | |
34048c9e | 589 | if (p) |
1da177e4 LT |
590 | strcpy(c->x86_model_id, p); |
591 | else | |
592 | /* Last resort... */ | |
593 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 594 | c->x86, c->x86_model); |
1da177e4 LT |
595 | } |
596 | ||
1da177e4 LT |
597 | /* |
598 | * On SMP, boot_cpu_data holds the common feature set between | |
599 | * all CPUs; so make sure that we indicate which features are | |
600 | * common between the CPUs. The first time this routine gets | |
601 | * executed, c == &boot_cpu_data. | |
602 | */ | |
34048c9e | 603 | if (c != &boot_cpu_data) { |
1da177e4 | 604 | /* AND the already accumulated flags with these */ |
9d31d35b | 605 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
606 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
607 | } | |
608 | ||
7d851c8d AK |
609 | /* Clear all flags overriden by options */ |
610 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 611 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 612 | |
1da177e4 | 613 | /* Init Machine Check Exception if available. */ |
1da177e4 | 614 | mcheck_init(c); |
30d432df AK |
615 | |
616 | select_idle_routine(c); | |
a6c4e076 | 617 | } |
31ab269a | 618 | |
a6c4e076 JF |
619 | void __init identify_boot_cpu(void) |
620 | { | |
621 | identify_cpu(&boot_cpu_data); | |
622 | sysenter_setup(); | |
6fe940d6 | 623 | enable_sep_cpu(); |
a6c4e076 | 624 | } |
3b520b23 | 625 | |
a6c4e076 JF |
626 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
627 | { | |
628 | BUG_ON(c == &boot_cpu_data); | |
629 | identify_cpu(c); | |
630 | enable_sep_cpu(); | |
631 | mtrr_ap_init(); | |
1da177e4 LT |
632 | } |
633 | ||
a0854a46 YL |
634 | struct msr_range { |
635 | unsigned min; | |
636 | unsigned max; | |
637 | }; | |
1da177e4 | 638 | |
a0854a46 YL |
639 | static struct msr_range msr_range_array[] __cpuinitdata = { |
640 | { 0x00000000, 0x00000418}, | |
641 | { 0xc0000000, 0xc000040b}, | |
642 | { 0xc0010000, 0xc0010142}, | |
643 | { 0xc0011000, 0xc001103b}, | |
644 | }; | |
1da177e4 | 645 | |
a0854a46 YL |
646 | static void __cpuinit print_cpu_msr(void) |
647 | { | |
648 | unsigned index; | |
649 | u64 val; | |
650 | int i; | |
651 | unsigned index_min, index_max; | |
652 | ||
653 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
654 | index_min = msr_range_array[i].min; | |
655 | index_max = msr_range_array[i].max; | |
656 | for (index = index_min; index < index_max; index++) { | |
657 | if (rdmsrl_amd_safe(index, &val)) | |
658 | continue; | |
659 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 660 | } |
a0854a46 YL |
661 | } |
662 | } | |
94605eff | 663 | |
a0854a46 YL |
664 | static int show_msr __cpuinitdata; |
665 | static __init int setup_show_msr(char *arg) | |
666 | { | |
667 | int num; | |
3dd9d514 | 668 | |
a0854a46 | 669 | get_option(&arg, &num); |
3dd9d514 | 670 | |
a0854a46 YL |
671 | if (num > 0) |
672 | show_msr = num; | |
673 | return 1; | |
1da177e4 | 674 | } |
a0854a46 | 675 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 676 | |
191679fd AK |
677 | static __init int setup_noclflush(char *arg) |
678 | { | |
679 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
680 | return 1; | |
681 | } | |
682 | __setup("noclflush", setup_noclflush); | |
683 | ||
3bc9b76b | 684 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
685 | { |
686 | char *vendor = NULL; | |
687 | ||
688 | if (c->x86_vendor < X86_VENDOR_NUM) | |
689 | vendor = this_cpu->c_vendor; | |
690 | else if (c->cpuid_level >= 0) | |
691 | vendor = c->x86_vendor_id; | |
692 | ||
693 | if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor))) | |
9d31d35b | 694 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 695 | |
9d31d35b YL |
696 | if (c->x86_model_id[0]) |
697 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 698 | else |
9d31d35b | 699 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 700 | |
34048c9e | 701 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 702 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 703 | else |
9d31d35b | 704 | printk(KERN_CONT "\n"); |
a0854a46 YL |
705 | |
706 | #ifdef CONFIG_SMP | |
707 | if (c->cpu_index < show_msr) | |
708 | print_cpu_msr(); | |
709 | #else | |
710 | if (show_msr) | |
711 | print_cpu_msr(); | |
712 | #endif | |
1da177e4 LT |
713 | } |
714 | ||
ac72e788 AK |
715 | static __init int setup_disablecpuid(char *arg) |
716 | { | |
717 | int bit; | |
718 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
719 | setup_clear_cpu_cap(bit); | |
720 | else | |
721 | return 0; | |
722 | return 1; | |
723 | } | |
724 | __setup("clearcpuid=", setup_disablecpuid); | |
725 | ||
3bc9b76b | 726 | cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE; |
1da177e4 | 727 | |
7c3576d2 | 728 | /* Make sure %fs is initialized properly in idle threads */ |
6b2fb3c6 | 729 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
730 | { |
731 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 732 | regs->fs = __KERNEL_PERCPU; |
f95d47ca JF |
733 | return regs; |
734 | } | |
735 | ||
d2cbcc49 RR |
736 | /* |
737 | * cpu_init() initializes state that is per-CPU. Some data is already | |
738 | * initialized (naturally) in the bootstrap process, such as the GDT | |
739 | * and IDT. We reload them nevertheless, this function acts as a | |
740 | * 'CPU state barrier', nothing should get across. | |
741 | */ | |
742 | void __cpuinit cpu_init(void) | |
9ee79a3d | 743 | { |
d2cbcc49 RR |
744 | int cpu = smp_processor_id(); |
745 | struct task_struct *curr = current; | |
34048c9e | 746 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 747 | struct thread_struct *thread = &curr->thread; |
62111195 JF |
748 | |
749 | if (cpu_test_and_set(cpu, cpu_initialized)) { | |
750 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); | |
751 | for (;;) local_irq_enable(); | |
752 | } | |
753 | ||
754 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
755 | ||
756 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
757 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 758 | |
4d37e7e3 | 759 | load_idt(&idt_descr); |
c5413fbe | 760 | switch_to_new_gdt(); |
1da177e4 | 761 | |
1da177e4 LT |
762 | /* |
763 | * Set up and load the per-CPU TSS and LDT | |
764 | */ | |
765 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
766 | curr->active_mm = &init_mm; |
767 | if (curr->mm) | |
768 | BUG(); | |
769 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 770 | |
faca6227 | 771 | load_sp0(t, thread); |
34048c9e | 772 | set_tss_desc(cpu, t); |
1da177e4 LT |
773 | load_TR_desc(); |
774 | load_LDT(&init_mm.context); | |
775 | ||
22c4e308 | 776 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
777 | /* Set up doublefault TSS pointer in the GDT */ |
778 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 779 | #endif |
1da177e4 | 780 | |
464d1a78 JF |
781 | /* Clear %gs. */ |
782 | asm volatile ("mov %0, %%gs" : : "r" (0)); | |
1da177e4 LT |
783 | |
784 | /* Clear all 6 debug registers: */ | |
4bb0d3ec ZA |
785 | set_debugreg(0, 0); |
786 | set_debugreg(0, 1); | |
787 | set_debugreg(0, 2); | |
788 | set_debugreg(0, 3); | |
789 | set_debugreg(0, 6); | |
790 | set_debugreg(0, 7); | |
1da177e4 LT |
791 | |
792 | /* | |
793 | * Force FPU initialization: | |
794 | */ | |
b359e8a4 SS |
795 | if (cpu_has_xsave) |
796 | current_thread_info()->status = TS_XSAVE; | |
797 | else | |
798 | current_thread_info()->status = 0; | |
1da177e4 LT |
799 | clear_used_math(); |
800 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
801 | |
802 | /* | |
803 | * Boot processor to setup the FP and extended state context info. | |
804 | */ | |
805 | if (!smp_processor_id()) | |
806 | init_thread_xstate(); | |
807 | ||
808 | xsave_init(); | |
1da177e4 | 809 | } |
e1367daf LS |
810 | |
811 | #ifdef CONFIG_HOTPLUG_CPU | |
3bc9b76b | 812 | void __cpuinit cpu_uninit(void) |
e1367daf LS |
813 | { |
814 | int cpu = raw_smp_processor_id(); | |
815 | cpu_clear(cpu, cpu_initialized); | |
816 | ||
817 | /* lazy TLB state */ | |
818 | per_cpu(cpu_tlbstate, cpu).state = 0; | |
819 | per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm; | |
820 | } | |
821 | #endif |