Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
68e21be2 | 10 | #include <linux/sched/mm.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
fec9434a DW |
50 | #include <asm/intel-family.h> |
51 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
52 | |
53 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 54 | #include <asm/uv/uv.h> |
1da177e4 LT |
55 | #endif |
56 | ||
57 | #include "cpu.h" | |
58 | ||
0274f955 GA |
59 | u32 elf_hwcap2 __read_mostly; |
60 | ||
c2d1cec1 | 61 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 62 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
63 | cpumask_var_t cpu_callout_mask; |
64 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
65 | |
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | cpumask_var_t cpu_sibling_setup_mask; | |
68 | ||
2f2f52ba | 69 | /* correctly size the local cpu masks */ |
4369f1fb | 70 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
71 | { |
72 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
73 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
74 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
75 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
76 | } | |
77 | ||
148f9bb8 | 78 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
79 | { |
80 | #ifdef CONFIG_X86_64 | |
27c13ece | 81 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
82 | #else |
83 | /* Not much we can do here... */ | |
84 | /* Check if at least it has cpuid */ | |
85 | if (c->cpuid_level == -1) { | |
86 | /* No cpuid. It must be an ancient CPU */ | |
87 | if (c->x86 == 4) | |
88 | strcpy(c->x86_model_id, "486"); | |
89 | else if (c->x86 == 3) | |
90 | strcpy(c->x86_model_id, "386"); | |
91 | } | |
92 | #endif | |
93 | } | |
94 | ||
148f9bb8 | 95 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
96 | .c_init = default_init, |
97 | .c_vendor = "Unknown", | |
98 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
99 | }; | |
100 | ||
148f9bb8 | 101 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 102 | |
06deef89 | 103 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 104 | #ifdef CONFIG_X86_64 |
06deef89 BG |
105 | /* |
106 | * We need valid kernel segments for data and code in long mode too | |
107 | * IRET will check the segment types kkeil 2000/10/28 | |
108 | * Also sysret mandates a special GDT layout | |
109 | * | |
9766cdbc | 110 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
111 | * Hopefully nobody expects them at a fixed place (Wine?) |
112 | */ | |
1e5de182 AM |
113 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
114 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
115 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
116 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
117 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
118 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 119 | #else |
1e5de182 AM |
120 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
121 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
122 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
123 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
124 | /* |
125 | * Segments used for calling PnP BIOS have byte granularity. | |
126 | * They code segments and data segments have fixed 64k limits, | |
127 | * the transfer segment sizes are set at run time. | |
128 | */ | |
6842ef0e | 129 | /* 32-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 131 | /* 16-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 133 | /* 16-bit data */ |
1e5de182 | 134 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 135 | /* 16-bit data */ |
1e5de182 | 136 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 137 | /* 16-bit data */ |
1e5de182 | 138 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
139 | /* |
140 | * The APM segments have byte granularity and their bases | |
141 | * are set at run time. All have 64k limits. | |
142 | */ | |
6842ef0e | 143 | /* 32-bit code */ |
1e5de182 | 144 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 145 | /* 16-bit code */ |
1e5de182 | 146 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 147 | /* data */ |
72c4d853 | 148 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 149 | |
1e5de182 AM |
150 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
151 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 152 | GDT_STACK_CANARY_INIT |
950ad7ff | 153 | #endif |
06deef89 | 154 | } }; |
7a61d35d | 155 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 156 | |
8c3641e9 | 157 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 158 | { |
8c3641e9 | 159 | /* require an exact match without trailing characters */ |
2cd3949f DH |
160 | if (strlen(s)) |
161 | return 0; | |
0c752a93 | 162 | |
8c3641e9 DH |
163 | /* do not emit a message if the feature is not present */ |
164 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
165 | return 1; | |
6bad06b7 | 166 | |
8c3641e9 DH |
167 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
168 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
169 | return 1; |
170 | } | |
8c3641e9 | 171 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 172 | |
0790c9aa | 173 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 174 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 175 | { |
c7ad5ad2 AL |
176 | /* nopcid doesn't accept parameters */ |
177 | if (s) | |
178 | return -EINVAL; | |
0790c9aa AL |
179 | |
180 | /* do not emit a message if the feature is not present */ | |
181 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 182 | return 0; |
0790c9aa AL |
183 | |
184 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
185 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 186 | return 0; |
0790c9aa | 187 | } |
c7ad5ad2 | 188 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
189 | #endif |
190 | ||
d12a72b8 AL |
191 | static int __init x86_noinvpcid_setup(char *s) |
192 | { | |
193 | /* noinvpcid doesn't accept parameters */ | |
194 | if (s) | |
195 | return -EINVAL; | |
196 | ||
197 | /* do not emit a message if the feature is not present */ | |
198 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
199 | return 0; | |
200 | ||
201 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
202 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
203 | return 0; | |
204 | } | |
205 | early_param("noinvpcid", x86_noinvpcid_setup); | |
206 | ||
ba51dced | 207 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
208 | static int cachesize_override = -1; |
209 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 210 | |
0a488a53 YL |
211 | static int __init cachesize_setup(char *str) |
212 | { | |
213 | get_option(&str, &cachesize_override); | |
214 | return 1; | |
215 | } | |
216 | __setup("cachesize=", cachesize_setup); | |
217 | ||
0a488a53 YL |
218 | static int __init x86_sep_setup(char *s) |
219 | { | |
220 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
221 | return 1; | |
222 | } | |
223 | __setup("nosep", x86_sep_setup); | |
224 | ||
225 | /* Standard macro to see if a specific flag is changeable */ | |
226 | static inline int flag_is_changeable_p(u32 flag) | |
227 | { | |
228 | u32 f1, f2; | |
229 | ||
94f6bac1 KH |
230 | /* |
231 | * Cyrix and IDT cpus allow disabling of CPUID | |
232 | * so the code below may return different results | |
233 | * when it is executed before and after enabling | |
234 | * the CPUID. Add "volatile" to not allow gcc to | |
235 | * optimize the subsequent calls to this function. | |
236 | */ | |
0f3fa48a IM |
237 | asm volatile ("pushfl \n\t" |
238 | "pushfl \n\t" | |
239 | "popl %0 \n\t" | |
240 | "movl %0, %1 \n\t" | |
241 | "xorl %2, %0 \n\t" | |
242 | "pushl %0 \n\t" | |
243 | "popfl \n\t" | |
244 | "pushfl \n\t" | |
245 | "popl %0 \n\t" | |
246 | "popfl \n\t" | |
247 | ||
94f6bac1 KH |
248 | : "=&r" (f1), "=&r" (f2) |
249 | : "ir" (flag)); | |
0a488a53 YL |
250 | |
251 | return ((f1^f2) & flag) != 0; | |
252 | } | |
253 | ||
254 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 255 | int have_cpuid_p(void) |
0a488a53 YL |
256 | { |
257 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
258 | } | |
259 | ||
148f9bb8 | 260 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 261 | { |
0f3fa48a IM |
262 | unsigned long lo, hi; |
263 | ||
264 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
265 | return; | |
266 | ||
267 | /* Disable processor serial number: */ | |
268 | ||
269 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
270 | lo |= 0x200000; | |
271 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
272 | ||
1b74dde7 | 273 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
274 | clear_cpu_cap(c, X86_FEATURE_PN); |
275 | ||
276 | /* Disabling the serial number may affect the cpuid level */ | |
277 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
278 | } |
279 | ||
280 | static int __init x86_serial_nr_setup(char *s) | |
281 | { | |
282 | disable_x86_serial_nr = 0; | |
283 | return 1; | |
284 | } | |
285 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 286 | #else |
102bbe3a YL |
287 | static inline int flag_is_changeable_p(u32 flag) |
288 | { | |
289 | return 1; | |
290 | } | |
102bbe3a YL |
291 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
292 | { | |
293 | } | |
ba51dced | 294 | #endif |
0a488a53 | 295 | |
de5397ad FY |
296 | static __init int setup_disable_smep(char *arg) |
297 | { | |
b2cc2a07 | 298 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
299 | /* Check for things that depend on SMEP being enabled: */ |
300 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
301 | return 1; |
302 | } | |
303 | __setup("nosmep", setup_disable_smep); | |
304 | ||
b2cc2a07 | 305 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 306 | { |
b2cc2a07 | 307 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 308 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
309 | } |
310 | ||
52b6179a PA |
311 | static __init int setup_disable_smap(char *arg) |
312 | { | |
b2cc2a07 | 313 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
314 | return 1; |
315 | } | |
316 | __setup("nosmap", setup_disable_smap); | |
317 | ||
b2cc2a07 PA |
318 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
319 | { | |
581b7f15 | 320 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
321 | |
322 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
323 | BUG_ON(eflags & X86_EFLAGS_AC); |
324 | ||
03bbd596 PA |
325 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
326 | #ifdef CONFIG_X86_SMAP | |
375074cc | 327 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 328 | #else |
375074cc | 329 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
330 | #endif |
331 | } | |
de5397ad FY |
332 | } |
333 | ||
aa35f896 RN |
334 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
335 | { | |
336 | /* Check the boot processor, plus build option for UMIP. */ | |
337 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
338 | goto out; | |
339 | ||
340 | /* Check the current processor's cpuid bits. */ | |
341 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
342 | goto out; | |
343 | ||
344 | cr4_set_bits(X86_CR4_UMIP); | |
345 | ||
770c7755 RN |
346 | pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); |
347 | ||
aa35f896 RN |
348 | return; |
349 | ||
350 | out: | |
351 | /* | |
352 | * Make sure UMIP is disabled in case it was enabled in a | |
353 | * previous boot (e.g., via kexec). | |
354 | */ | |
355 | cr4_clear_bits(X86_CR4_UMIP); | |
356 | } | |
357 | ||
06976945 DH |
358 | /* |
359 | * Protection Keys are not available in 32-bit mode. | |
360 | */ | |
361 | static bool pku_disabled; | |
362 | ||
363 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
364 | { | |
e8df1a95 DH |
365 | /* check the boot processor, plus compile options for PKU: */ |
366 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
367 | return; | |
368 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
369 | if (!cpu_has(c, X86_FEATURE_PKU)) |
370 | return; | |
371 | if (pku_disabled) | |
372 | return; | |
373 | ||
374 | cr4_set_bits(X86_CR4_PKE); | |
375 | /* | |
376 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
377 | * cpuid bit to be set. We need to ensure that we | |
378 | * update that bit in this CPU's "cpu_info". | |
379 | */ | |
380 | get_cpu_cap(c); | |
381 | } | |
382 | ||
383 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
384 | static __init int setup_disable_pku(char *arg) | |
385 | { | |
386 | /* | |
387 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
388 | * runtime checks are against OSPKE so clearing the | |
389 | * bit does nothing. | |
390 | * | |
391 | * This way, we will see "pku" in cpuinfo, but not | |
392 | * "ospke", which is exactly what we want. It shows | |
393 | * that the CPU has PKU, but the OS has not enabled it. | |
394 | * This happens to be exactly how a system would look | |
395 | * if we disabled the config option. | |
396 | */ | |
397 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
398 | pku_disabled = true; | |
399 | return 1; | |
400 | } | |
401 | __setup("nopku", setup_disable_pku); | |
402 | #endif /* CONFIG_X86_64 */ | |
403 | ||
b38b0665 PA |
404 | /* |
405 | * Some CPU features depend on higher CPUID levels, which may not always | |
406 | * be available due to CPUID level capping or broken virtualization | |
407 | * software. Add those features to this table to auto-disable them. | |
408 | */ | |
409 | struct cpuid_dependent_feature { | |
410 | u32 feature; | |
411 | u32 level; | |
412 | }; | |
0f3fa48a | 413 | |
148f9bb8 | 414 | static const struct cpuid_dependent_feature |
b38b0665 PA |
415 | cpuid_dependent_features[] = { |
416 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
417 | { X86_FEATURE_DCA, 0x00000009 }, | |
418 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
419 | { 0, 0 } | |
420 | }; | |
421 | ||
148f9bb8 | 422 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
423 | { |
424 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 425 | |
b38b0665 | 426 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
427 | |
428 | if (!cpu_has(c, df->feature)) | |
429 | continue; | |
b38b0665 PA |
430 | /* |
431 | * Note: cpuid_level is set to -1 if unavailable, but | |
432 | * extended_extended_level is set to 0 if unavailable | |
433 | * and the legitimate extended levels are all negative | |
434 | * when signed; hence the weird messing around with | |
435 | * signs here... | |
436 | */ | |
0f3fa48a | 437 | if (!((s32)df->level < 0 ? |
f6db44df | 438 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
439 | (s32)df->level > (s32)c->cpuid_level)) |
440 | continue; | |
441 | ||
442 | clear_cpu_cap(c, df->feature); | |
443 | if (!warn) | |
444 | continue; | |
445 | ||
1b74dde7 CY |
446 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
447 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 448 | } |
f6db44df | 449 | } |
b38b0665 | 450 | |
102bbe3a YL |
451 | /* |
452 | * Naming convention should be: <Name> [(<Codename>)] | |
453 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
454 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
455 | * isn't used | |
102bbe3a YL |
456 | */ |
457 | ||
458 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 459 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 460 | { |
09dc68d9 JB |
461 | #ifdef CONFIG_X86_32 |
462 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
463 | |
464 | if (c->x86_model >= 16) | |
465 | return NULL; /* Range check */ | |
466 | ||
467 | if (!this_cpu) | |
468 | return NULL; | |
469 | ||
09dc68d9 | 470 | info = this_cpu->legacy_models; |
102bbe3a | 471 | |
09dc68d9 | 472 | while (info->family) { |
102bbe3a YL |
473 | if (info->family == c->x86) |
474 | return info->model_names[c->x86_model]; | |
475 | info++; | |
476 | } | |
09dc68d9 | 477 | #endif |
102bbe3a YL |
478 | return NULL; /* Not found */ |
479 | } | |
480 | ||
6cbd2171 TG |
481 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
482 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 483 | |
11e3a840 JF |
484 | void load_percpu_segment(int cpu) |
485 | { | |
486 | #ifdef CONFIG_X86_32 | |
487 | loadsegment(fs, __KERNEL_PERCPU); | |
488 | #else | |
45e876f7 | 489 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
490 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
491 | #endif | |
60a5317f | 492 | load_stack_canary_segment(); |
11e3a840 JF |
493 | } |
494 | ||
72f5e08d AL |
495 | #ifdef CONFIG_X86_32 |
496 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
497 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
498 | #endif | |
499 | ||
40e7f949 AL |
500 | #ifdef CONFIG_X86_64 |
501 | /* | |
502 | * Special IST stacks which the CPU switches to when it calls | |
503 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
504 | * limit), all of them are 4K, except the debug stack which | |
505 | * is 8K. | |
506 | */ | |
507 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
508 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
509 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
510 | }; | |
45fc8757 | 511 | #endif |
69218e47 | 512 | |
45fc8757 TG |
513 | /* Load the original GDT from the per-cpu structure */ |
514 | void load_direct_gdt(int cpu) | |
515 | { | |
516 | struct desc_ptr gdt_descr; | |
517 | ||
518 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
519 | gdt_descr.size = GDT_SIZE - 1; | |
520 | load_gdt(&gdt_descr); | |
521 | } | |
522 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
523 | ||
69218e47 TG |
524 | /* Load a fixmap remapping of the per-cpu GDT */ |
525 | void load_fixmap_gdt(int cpu) | |
526 | { | |
527 | struct desc_ptr gdt_descr; | |
528 | ||
529 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
530 | gdt_descr.size = GDT_SIZE - 1; | |
531 | load_gdt(&gdt_descr); | |
532 | } | |
45fc8757 | 533 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 534 | |
0f3fa48a IM |
535 | /* |
536 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
537 | * it's on the real one. | |
538 | */ | |
552be871 | 539 | void switch_to_new_gdt(int cpu) |
9d31d35b | 540 | { |
45fc8757 TG |
541 | /* Load the original GDT */ |
542 | load_direct_gdt(cpu); | |
2697fbd5 | 543 | /* Reload the per-cpu base */ |
11e3a840 | 544 | load_percpu_segment(cpu); |
9d31d35b YL |
545 | } |
546 | ||
148f9bb8 | 547 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 548 | |
148f9bb8 | 549 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
550 | { |
551 | unsigned int *v; | |
ee098e1a | 552 | char *p, *q, *s; |
1da177e4 | 553 | |
3da99c97 | 554 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 555 | return; |
1da177e4 | 556 | |
0f3fa48a | 557 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
558 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
559 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
560 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
561 | c->x86_model_id[48] = 0; | |
562 | ||
ee098e1a BP |
563 | /* Trim whitespace */ |
564 | p = q = s = &c->x86_model_id[0]; | |
565 | ||
566 | while (*p == ' ') | |
567 | p++; | |
568 | ||
569 | while (*p) { | |
570 | /* Note the last non-whitespace index */ | |
571 | if (!isspace(*p)) | |
572 | s = q; | |
573 | ||
574 | *q++ = *p++; | |
575 | } | |
576 | ||
577 | *(s + 1) = '\0'; | |
1da177e4 LT |
578 | } |
579 | ||
148f9bb8 | 580 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 581 | { |
9d31d35b | 582 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 583 | |
3da99c97 | 584 | n = c->extended_cpuid_level; |
1da177e4 LT |
585 | |
586 | if (n >= 0x80000005) { | |
9d31d35b | 587 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 588 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
589 | #ifdef CONFIG_X86_64 |
590 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
591 | c->x86_tlbsize = 0; | |
592 | #endif | |
1da177e4 LT |
593 | } |
594 | ||
595 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
596 | return; | |
597 | ||
0a488a53 | 598 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 599 | l2size = ecx >> 16; |
34048c9e | 600 | |
140fc727 YL |
601 | #ifdef CONFIG_X86_64 |
602 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
603 | #else | |
1da177e4 | 604 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
605 | if (this_cpu->legacy_cache_size) |
606 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
607 | |
608 | /* Allow user to override all this if necessary. */ | |
609 | if (cachesize_override != -1) | |
610 | l2size = cachesize_override; | |
611 | ||
34048c9e | 612 | if (l2size == 0) |
1da177e4 | 613 | return; /* Again, no L2 cache is possible */ |
140fc727 | 614 | #endif |
1da177e4 LT |
615 | |
616 | c->x86_cache_size = l2size; | |
1da177e4 LT |
617 | } |
618 | ||
e0ba94f1 AS |
619 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
620 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
621 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
622 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
623 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
624 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 625 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 626 | |
f94fe119 | 627 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
628 | { |
629 | if (this_cpu->c_detect_tlb) | |
630 | this_cpu->c_detect_tlb(c); | |
631 | ||
f94fe119 | 632 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 633 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
634 | tlb_lli_4m[ENTRIES]); |
635 | ||
636 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
637 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
638 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
639 | } |
640 | ||
148f9bb8 | 641 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 642 | { |
c8e56d20 | 643 | #ifdef CONFIG_SMP |
0a488a53 YL |
644 | u32 eax, ebx, ecx, edx; |
645 | int index_msb, core_bits; | |
2eaad1fd | 646 | static bool printed; |
1da177e4 | 647 | |
0a488a53 | 648 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 649 | return; |
1da177e4 | 650 | |
0a488a53 YL |
651 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
652 | goto out; | |
1da177e4 | 653 | |
1cd78776 YL |
654 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
655 | return; | |
1da177e4 | 656 | |
0a488a53 | 657 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 658 | |
9d31d35b YL |
659 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
660 | ||
661 | if (smp_num_siblings == 1) { | |
1b74dde7 | 662 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
663 | goto out; |
664 | } | |
9d31d35b | 665 | |
0f3fa48a IM |
666 | if (smp_num_siblings <= 1) |
667 | goto out; | |
9d31d35b | 668 | |
0f3fa48a IM |
669 | index_msb = get_count_order(smp_num_siblings); |
670 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 671 | |
0f3fa48a | 672 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 673 | |
0f3fa48a | 674 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 675 | |
0f3fa48a | 676 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 677 | |
0f3fa48a IM |
678 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
679 | ((1 << core_bits) - 1); | |
1da177e4 | 680 | |
0a488a53 | 681 | out: |
2eaad1fd | 682 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
683 | pr_info("CPU: Physical Processor ID: %d\n", |
684 | c->phys_proc_id); | |
685 | pr_info("CPU: Processor Core ID: %d\n", | |
686 | c->cpu_core_id); | |
2eaad1fd | 687 | printed = 1; |
9d31d35b | 688 | } |
9d31d35b | 689 | #endif |
97e4db7c | 690 | } |
1da177e4 | 691 | |
148f9bb8 | 692 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
693 | { |
694 | char *v = c->x86_vendor_id; | |
0f3fa48a | 695 | int i; |
1da177e4 LT |
696 | |
697 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
698 | if (!cpu_devs[i]) |
699 | break; | |
700 | ||
701 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
702 | (cpu_devs[i]->c_ident[1] && | |
703 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 704 | |
10a434fc YL |
705 | this_cpu = cpu_devs[i]; |
706 | c->x86_vendor = this_cpu->c_x86_vendor; | |
707 | return; | |
1da177e4 LT |
708 | } |
709 | } | |
10a434fc | 710 | |
1b74dde7 CY |
711 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
712 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 713 | |
fe38d855 CE |
714 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
715 | this_cpu = &default_cpu; | |
1da177e4 LT |
716 | } |
717 | ||
148f9bb8 | 718 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 719 | { |
1da177e4 | 720 | /* Get vendor name */ |
4a148513 HH |
721 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
722 | (unsigned int *)&c->x86_vendor_id[0], | |
723 | (unsigned int *)&c->x86_vendor_id[8], | |
724 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 725 | |
1da177e4 | 726 | c->x86 = 4; |
9d31d35b | 727 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
728 | if (c->cpuid_level >= 0x00000001) { |
729 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 730 | |
1da177e4 | 731 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
732 | c->x86 = x86_family(tfms); |
733 | c->x86_model = x86_model(tfms); | |
b399151c | 734 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 735 | |
d4387bd3 | 736 | if (cap0 & (1<<19)) { |
d4387bd3 | 737 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 738 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 739 | } |
1da177e4 | 740 | } |
1da177e4 | 741 | } |
3da99c97 | 742 | |
8bf1ebca AL |
743 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
744 | { | |
745 | int i; | |
746 | ||
6cbd2171 | 747 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
748 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
749 | c->x86_capability[i] |= cpu_caps_set[i]; | |
750 | } | |
751 | } | |
752 | ||
7fcae111 DW |
753 | static void init_speculation_control(struct cpuinfo_x86 *c) |
754 | { | |
755 | /* | |
756 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
757 | * and they also have a different bit for STIBP support. Also, | |
758 | * a hypervisor might have set the individual AMD bits even on | |
759 | * Intel CPUs, for finer-grained selection of what's available. | |
760 | * | |
761 | * We use the AMD bits in 0x8000_0008 EBX as the generic hardware | |
762 | * features, which are visible in /proc/cpuinfo and used by the | |
763 | * kernel. So set those accordingly from the Intel bits. | |
764 | */ | |
765 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
766 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
767 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
768 | } | |
769 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) | |
770 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
771 | } | |
772 | ||
148f9bb8 | 773 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 774 | { |
39c06df4 | 775 | u32 eax, ebx, ecx, edx; |
093af8d7 | 776 | |
3da99c97 YL |
777 | /* Intel-defined flags: level 0x00000001 */ |
778 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 779 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 780 | |
39c06df4 BP |
781 | c->x86_capability[CPUID_1_ECX] = ecx; |
782 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 783 | } |
093af8d7 | 784 | |
3df8d920 AL |
785 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
786 | if (c->cpuid_level >= 0x00000006) | |
787 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
788 | ||
bdc802dc PA |
789 | /* Additional Intel-defined flags: level 0x00000007 */ |
790 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 791 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 792 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 793 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 794 | c->x86_capability[CPUID_7_EDX] = edx; |
bdc802dc PA |
795 | } |
796 | ||
6229ad27 FY |
797 | /* Extended state features: level 0x0000000d */ |
798 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
799 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
800 | ||
39c06df4 | 801 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
802 | } |
803 | ||
cbc82b17 PWJ |
804 | /* Additional Intel-defined flags: level 0x0000000F */ |
805 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
806 | |
807 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
808 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
809 | c->x86_capability[CPUID_F_0_EDX] = edx; |
810 | ||
cbc82b17 PWJ |
811 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
812 | /* will be overridden if occupancy monitoring exists */ | |
813 | c->x86_cache_max_rmid = ebx; | |
814 | ||
815 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
816 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
817 | c->x86_capability[CPUID_F_1_EDX] = edx; |
818 | ||
33c3cc7a VS |
819 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
820 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
821 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
822 | c->x86_cache_max_rmid = ecx; |
823 | c->x86_cache_occ_scale = ebx; | |
824 | } | |
825 | } else { | |
826 | c->x86_cache_max_rmid = -1; | |
827 | c->x86_cache_occ_scale = -1; | |
828 | } | |
829 | } | |
830 | ||
3da99c97 | 831 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
832 | eax = cpuid_eax(0x80000000); |
833 | c->extended_cpuid_level = eax; | |
834 | ||
835 | if ((eax & 0xffff0000) == 0x80000000) { | |
836 | if (eax >= 0x80000001) { | |
837 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 838 | |
39c06df4 BP |
839 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
840 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 841 | } |
093af8d7 | 842 | } |
093af8d7 | 843 | |
71faad43 YG |
844 | if (c->extended_cpuid_level >= 0x80000007) { |
845 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
846 | ||
847 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
848 | c->x86_power = edx; | |
849 | } | |
850 | ||
5122c890 | 851 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 852 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
853 | |
854 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
855 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 856 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 857 | } |
13c6c532 JB |
858 | #ifdef CONFIG_X86_32 |
859 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
860 | c->x86_phys_bits = 36; | |
5122c890 | 861 | #endif |
e3224234 | 862 | |
2ccd71f1 | 863 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 864 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 865 | |
1dedefd1 | 866 | init_scattered_cpuid_features(c); |
7fcae111 | 867 | init_speculation_control(c); |
60d34501 AL |
868 | |
869 | /* | |
870 | * Clear/Set all flags overridden by options, after probe. | |
871 | * This needs to happen each time we re-probe, which may happen | |
872 | * several times during CPU initialization. | |
873 | */ | |
874 | apply_forced_caps(c); | |
093af8d7 | 875 | } |
1da177e4 | 876 | |
148f9bb8 | 877 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
878 | { |
879 | #ifdef CONFIG_X86_32 | |
880 | int i; | |
881 | ||
882 | /* | |
883 | * First of all, decide if this is a 486 or higher | |
884 | * It's a 486 if we can modify the AC flag | |
885 | */ | |
886 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
887 | c->x86 = 4; | |
888 | else | |
889 | c->x86 = 3; | |
890 | ||
891 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
892 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
893 | c->x86_vendor_id[0] = 0; | |
894 | cpu_devs[i]->c_identify(c); | |
895 | if (c->x86_vendor_id[0]) { | |
896 | get_cpu_vendor(c); | |
897 | break; | |
898 | } | |
899 | } | |
900 | #endif | |
901 | } | |
902 | ||
4bf5d56d | 903 | static const __initconst struct x86_cpu_id cpu_no_speculation[] = { |
fec9434a DW |
904 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, |
905 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, | |
906 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, | |
907 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, | |
908 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, | |
909 | { X86_VENDOR_CENTAUR, 5 }, | |
910 | { X86_VENDOR_INTEL, 5 }, | |
911 | { X86_VENDOR_NSC, 5 }, | |
912 | { X86_VENDOR_ANY, 4 }, | |
913 | {} | |
914 | }; | |
915 | ||
4bf5d56d | 916 | static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { |
fec9434a DW |
917 | { X86_VENDOR_AMD }, |
918 | {} | |
919 | }; | |
920 | ||
921 | static bool __init cpu_vulnerable_to_meltdown(struct cpuinfo_x86 *c) | |
922 | { | |
923 | u64 ia32_cap = 0; | |
924 | ||
925 | if (x86_match_cpu(cpu_no_meltdown)) | |
926 | return false; | |
927 | ||
928 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) | |
929 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
930 | ||
931 | /* Rogue Data Cache Load? No! */ | |
932 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
933 | return false; | |
934 | ||
935 | return true; | |
936 | } | |
937 | ||
34048c9e PC |
938 | /* |
939 | * Do minimum CPU detection early. | |
940 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
941 | * cache alignment. | |
942 | * The others are not touched to avoid unwanted side effects. | |
943 | * | |
a1652bb8 JD |
944 | * WARNING: this function is only called on the boot CPU. Don't add code |
945 | * here that is supposed to run on all CPUs. | |
34048c9e | 946 | */ |
3da99c97 | 947 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 948 | { |
6627d242 YL |
949 | #ifdef CONFIG_X86_64 |
950 | c->x86_clflush_size = 64; | |
13c6c532 JB |
951 | c->x86_phys_bits = 36; |
952 | c->x86_virt_bits = 48; | |
6627d242 | 953 | #else |
d4387bd3 | 954 | c->x86_clflush_size = 32; |
13c6c532 JB |
955 | c->x86_phys_bits = 32; |
956 | c->x86_virt_bits = 32; | |
6627d242 | 957 | #endif |
0a488a53 | 958 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 959 | |
3da99c97 | 960 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 961 | c->extended_cpuid_level = 0; |
d7cd5611 | 962 | |
aef93c8b | 963 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
964 | if (have_cpuid_p()) { |
965 | cpu_detect(c); | |
966 | get_cpu_vendor(c); | |
967 | get_cpu_cap(c); | |
78d1b296 | 968 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 969 | |
05fb3c19 AL |
970 | if (this_cpu->c_early_init) |
971 | this_cpu->c_early_init(c); | |
12cf105c | 972 | |
05fb3c19 AL |
973 | c->cpu_index = 0; |
974 | filter_cpuid_features(c, false); | |
093af8d7 | 975 | |
05fb3c19 AL |
976 | if (this_cpu->c_bsp_init) |
977 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
978 | } else { |
979 | identify_cpu_without_cpuid(c); | |
980 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 981 | } |
c3b83598 BP |
982 | |
983 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 984 | |
fec9434a DW |
985 | if (!x86_match_cpu(cpu_no_speculation)) { |
986 | if (cpu_vulnerable_to_meltdown(c)) | |
987 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); | |
988 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
989 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
990 | } | |
99c6fa25 | 991 | |
db52ef74 | 992 | fpu__init_system(c); |
b8b7abae AL |
993 | |
994 | #ifdef CONFIG_X86_32 | |
995 | /* | |
996 | * Regardless of whether PCID is enumerated, the SDM says | |
997 | * that it can't be enabled in 32-bit mode. | |
998 | */ | |
999 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1000 | #endif | |
d7cd5611 RR |
1001 | } |
1002 | ||
9d31d35b YL |
1003 | void __init early_cpu_init(void) |
1004 | { | |
02dde8b4 | 1005 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1006 | int count = 0; |
1007 | ||
ac23f253 | 1008 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1009 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1010 | #endif |
1011 | ||
10a434fc | 1012 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1013 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1014 | |
10a434fc YL |
1015 | if (count >= X86_VENDOR_NUM) |
1016 | break; | |
1017 | cpu_devs[count] = cpudev; | |
1018 | count++; | |
1019 | ||
ac23f253 | 1020 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1021 | { |
1022 | unsigned int j; | |
1023 | ||
1024 | for (j = 0; j < 2; j++) { | |
1025 | if (!cpudev->c_ident[j]) | |
1026 | continue; | |
1b74dde7 | 1027 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1028 | cpudev->c_ident[j]); |
1029 | } | |
10a434fc | 1030 | } |
0388423d | 1031 | #endif |
10a434fc | 1032 | } |
9d31d35b | 1033 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1034 | } |
093af8d7 | 1035 | |
b6734c35 | 1036 | /* |
366d4a43 BP |
1037 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
1038 | * unfortunately, that's not true in practice because of early VIA | |
1039 | * chips and (more importantly) broken virtualizers that are not easy | |
1040 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1041 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 1042 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 1043 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 1044 | */ |
148f9bb8 | 1045 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 1046 | { |
366d4a43 | 1047 | #ifdef CONFIG_X86_32 |
b6734c35 | 1048 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
1049 | #else |
1050 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 1051 | #endif |
d7cd5611 | 1052 | } |
58a5aac5 | 1053 | |
7a5d6704 AL |
1054 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1055 | { | |
1056 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1057 | /* |
7a5d6704 AL |
1058 | * Empirically, writing zero to a segment selector on AMD does |
1059 | * not clear the base, whereas writing zero to a segment | |
1060 | * selector on Intel does clear the base. Intel's behavior | |
1061 | * allows slightly faster context switches in the common case | |
1062 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1063 | * |
7a5d6704 AL |
1064 | * Since neither vendor documents this anywhere that I can see, |
1065 | * detect it directly instead of hardcoding the choice by | |
1066 | * vendor. | |
1067 | * | |
1068 | * I've designated AMD's behavior as the "bug" because it's | |
1069 | * counterintuitive and less friendly. | |
58a5aac5 | 1070 | */ |
7a5d6704 AL |
1071 | |
1072 | unsigned long old_base, tmp; | |
1073 | rdmsrl(MSR_FS_BASE, old_base); | |
1074 | wrmsrl(MSR_FS_BASE, 1); | |
1075 | loadsegment(fs, 0); | |
1076 | rdmsrl(MSR_FS_BASE, tmp); | |
1077 | if (tmp != 0) | |
1078 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1079 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1080 | #endif |
d7cd5611 RR |
1081 | } |
1082 | ||
148f9bb8 | 1083 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1084 | { |
aef93c8b | 1085 | c->extended_cpuid_level = 0; |
1da177e4 | 1086 | |
3da99c97 | 1087 | if (!have_cpuid_p()) |
aef93c8b | 1088 | identify_cpu_without_cpuid(c); |
1d67953f | 1089 | |
aef93c8b | 1090 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1091 | if (!have_cpuid_p()) |
aef93c8b | 1092 | return; |
1da177e4 | 1093 | |
3da99c97 | 1094 | cpu_detect(c); |
1da177e4 | 1095 | |
3da99c97 | 1096 | get_cpu_vendor(c); |
1da177e4 | 1097 | |
3da99c97 | 1098 | get_cpu_cap(c); |
1da177e4 | 1099 | |
3da99c97 YL |
1100 | if (c->cpuid_level >= 0x00000001) { |
1101 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1102 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1103 | # ifdef CONFIG_SMP |
cb8cc442 | 1104 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1105 | # else |
3da99c97 | 1106 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1107 | # endif |
1108 | #endif | |
b89d3b3e | 1109 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1110 | } |
1da177e4 | 1111 | |
1b05d60d | 1112 | get_model_name(c); /* Default name */ |
1da177e4 | 1113 | |
3da99c97 | 1114 | detect_nopl(c); |
7a5d6704 AL |
1115 | |
1116 | detect_null_seg_behavior(c); | |
0230bb03 AL |
1117 | |
1118 | /* | |
1119 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1120 | * systems that run Linux at CPL > 0 may or may not have the | |
1121 | * issue, but, even if they have the issue, there's absolutely | |
1122 | * nothing we can do about it because we can't use the real IRET | |
1123 | * instruction. | |
1124 | * | |
1125 | * NB: For the time being, only 32-bit kernels support | |
1126 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1127 | * whether to apply espfix using paravirt hooks. If any | |
1128 | * non-paravirt system ever shows up that does *not* have the | |
1129 | * ESPFIX issue, we can change this. | |
1130 | */ | |
1131 | #ifdef CONFIG_X86_32 | |
1132 | # ifdef CONFIG_PARAVIRT | |
1133 | do { | |
1134 | extern void native_iret(void); | |
1135 | if (pv_cpu_ops.iret == native_iret) | |
1136 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1137 | } while (0); | |
1138 | # else | |
1139 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1140 | # endif | |
1141 | #endif | |
1da177e4 | 1142 | } |
1da177e4 | 1143 | |
cbc82b17 PWJ |
1144 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1145 | { | |
1146 | /* | |
1147 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1148 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1149 | * in case CQM bits really aren't there in this CPU. | |
1150 | */ | |
1151 | if (c != &boot_cpu_data) { | |
1152 | boot_cpu_data.x86_cache_max_rmid = | |
1153 | min(boot_cpu_data.x86_cache_max_rmid, | |
1154 | c->x86_cache_max_rmid); | |
1155 | } | |
1156 | } | |
1157 | ||
d49597fd | 1158 | /* |
9d85eb91 TG |
1159 | * Validate that ACPI/mptables have the same information about the |
1160 | * effective APIC id and update the package map. | |
d49597fd | 1161 | */ |
9d85eb91 | 1162 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1163 | { |
1164 | #ifdef CONFIG_SMP | |
9d85eb91 | 1165 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1166 | |
1167 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1168 | |
9d85eb91 TG |
1169 | if (apicid != c->apicid) { |
1170 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1171 | cpu, apicid, c->initial_apicid); |
d49597fd | 1172 | } |
9d85eb91 | 1173 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1174 | #else |
1175 | c->logical_proc_id = 0; | |
1176 | #endif | |
1177 | } | |
1178 | ||
1da177e4 LT |
1179 | /* |
1180 | * This does the hard work of actually picking apart the CPU stuff... | |
1181 | */ | |
148f9bb8 | 1182 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1183 | { |
1184 | int i; | |
1185 | ||
1186 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1187 | c->x86_cache_size = 0; |
1da177e4 | 1188 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1189 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1190 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1191 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1192 | c->x86_max_cores = 1; |
102bbe3a | 1193 | c->x86_coreid_bits = 0; |
79a8b9aa | 1194 | c->cu_id = 0xff; |
11fdd252 | 1195 | #ifdef CONFIG_X86_64 |
102bbe3a | 1196 | c->x86_clflush_size = 64; |
13c6c532 JB |
1197 | c->x86_phys_bits = 36; |
1198 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1199 | #else |
1200 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1201 | c->x86_clflush_size = 32; |
13c6c532 JB |
1202 | c->x86_phys_bits = 32; |
1203 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1204 | #endif |
1205 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1206 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1207 | ||
1da177e4 LT |
1208 | generic_identify(c); |
1209 | ||
3898534d | 1210 | if (this_cpu->c_identify) |
1da177e4 LT |
1211 | this_cpu->c_identify(c); |
1212 | ||
6a6256f9 | 1213 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1214 | apply_forced_caps(c); |
2759c328 | 1215 | |
102bbe3a | 1216 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1217 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1218 | #endif |
1219 | ||
1da177e4 LT |
1220 | /* |
1221 | * Vendor-specific initialization. In this section we | |
1222 | * canonicalize the feature flags, meaning if there are | |
1223 | * features a certain CPU supports which CPUID doesn't | |
1224 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1225 | * we handle them here. | |
1226 | * | |
1227 | * At the end of this section, c->x86_capability better | |
1228 | * indicate the features this CPU genuinely supports! | |
1229 | */ | |
1230 | if (this_cpu->c_init) | |
1231 | this_cpu->c_init(c); | |
1232 | ||
1233 | /* Disable the PN if appropriate */ | |
1234 | squash_the_stupid_serial_number(c); | |
1235 | ||
aa35f896 | 1236 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1237 | setup_smep(c); |
1238 | setup_smap(c); | |
aa35f896 | 1239 | setup_umip(c); |
b2cc2a07 | 1240 | |
1da177e4 | 1241 | /* |
0f3fa48a IM |
1242 | * The vendor-specific functions might have changed features. |
1243 | * Now we do "generic changes." | |
1da177e4 LT |
1244 | */ |
1245 | ||
b38b0665 PA |
1246 | /* Filter out anything that depends on CPUID levels we don't have */ |
1247 | filter_cpuid_features(c, true); | |
1248 | ||
1da177e4 | 1249 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1250 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1251 | const char *p; |
1da177e4 | 1252 | p = table_lookup_model(c); |
34048c9e | 1253 | if (p) |
1da177e4 LT |
1254 | strcpy(c->x86_model_id, p); |
1255 | else | |
1256 | /* Last resort... */ | |
1257 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1258 | c->x86, c->x86_model); |
1da177e4 LT |
1259 | } |
1260 | ||
102bbe3a YL |
1261 | #ifdef CONFIG_X86_64 |
1262 | detect_ht(c); | |
1263 | #endif | |
1264 | ||
49d859d7 | 1265 | x86_init_rdrand(c); |
cbc82b17 | 1266 | x86_init_cache_qos(c); |
06976945 | 1267 | setup_pku(c); |
3e0c3737 YL |
1268 | |
1269 | /* | |
6a6256f9 | 1270 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1271 | * before following smp all cpus cap AND. |
1272 | */ | |
8bf1ebca | 1273 | apply_forced_caps(c); |
3e0c3737 | 1274 | |
1da177e4 LT |
1275 | /* |
1276 | * On SMP, boot_cpu_data holds the common feature set between | |
1277 | * all CPUs; so make sure that we indicate which features are | |
1278 | * common between the CPUs. The first time this routine gets | |
1279 | * executed, c == &boot_cpu_data. | |
1280 | */ | |
34048c9e | 1281 | if (c != &boot_cpu_data) { |
1da177e4 | 1282 | /* AND the already accumulated flags with these */ |
9d31d35b | 1283 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1284 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1285 | |
1286 | /* OR, i.e. replicate the bug flags */ | |
1287 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1288 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1289 | } |
1290 | ||
1291 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1292 | mcheck_cpu_init(c); |
30d432df AK |
1293 | |
1294 | select_idle_routine(c); | |
102bbe3a | 1295 | |
de2d9445 | 1296 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1297 | numa_add_cpu(smp_processor_id()); |
1298 | #endif | |
a6c4e076 | 1299 | } |
31ab269a | 1300 | |
8b6c0ab1 IM |
1301 | /* |
1302 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1303 | * on 32-bit kernels: | |
1304 | */ | |
cfda7bb9 AL |
1305 | #ifdef CONFIG_X86_32 |
1306 | void enable_sep_cpu(void) | |
1307 | { | |
8b6c0ab1 IM |
1308 | struct tss_struct *tss; |
1309 | int cpu; | |
cfda7bb9 | 1310 | |
b3edfda4 BP |
1311 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1312 | return; | |
1313 | ||
8b6c0ab1 | 1314 | cpu = get_cpu(); |
c482feef | 1315 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1316 | |
8b6c0ab1 | 1317 | /* |
cf9328cc AL |
1318 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1319 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1320 | */ |
cfda7bb9 AL |
1321 | |
1322 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1323 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1324 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1325 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1326 | |
cfda7bb9 AL |
1327 | put_cpu(); |
1328 | } | |
e04d645f GC |
1329 | #endif |
1330 | ||
a6c4e076 JF |
1331 | void __init identify_boot_cpu(void) |
1332 | { | |
1333 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1334 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1335 | sysenter_setup(); |
6fe940d6 | 1336 | enable_sep_cpu(); |
102bbe3a | 1337 | #endif |
5b556332 | 1338 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1339 | } |
3b520b23 | 1340 | |
148f9bb8 | 1341 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1342 | { |
1343 | BUG_ON(c == &boot_cpu_data); | |
1344 | identify_cpu(c); | |
102bbe3a | 1345 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1346 | enable_sep_cpu(); |
102bbe3a | 1347 | #endif |
a6c4e076 | 1348 | mtrr_ap_init(); |
9d85eb91 | 1349 | validate_apic_and_package_id(c); |
1da177e4 LT |
1350 | } |
1351 | ||
191679fd AK |
1352 | static __init int setup_noclflush(char *arg) |
1353 | { | |
840d2830 | 1354 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1355 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1356 | return 1; |
1357 | } | |
1358 | __setup("noclflush", setup_noclflush); | |
1359 | ||
148f9bb8 | 1360 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1361 | { |
02dde8b4 | 1362 | const char *vendor = NULL; |
1da177e4 | 1363 | |
0f3fa48a | 1364 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1365 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1366 | } else { |
1367 | if (c->cpuid_level >= 0) | |
1368 | vendor = c->x86_vendor_id; | |
1369 | } | |
1da177e4 | 1370 | |
bd32a8cf | 1371 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1372 | pr_cont("%s ", vendor); |
1da177e4 | 1373 | |
9d31d35b | 1374 | if (c->x86_model_id[0]) |
1b74dde7 | 1375 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1376 | else |
1b74dde7 | 1377 | pr_cont("%d86", c->x86); |
1da177e4 | 1378 | |
1b74dde7 | 1379 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1380 | |
b399151c JZ |
1381 | if (c->x86_stepping || c->cpuid_level >= 0) |
1382 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1383 | else |
1b74dde7 | 1384 | pr_cont(")\n"); |
1da177e4 LT |
1385 | } |
1386 | ||
0c2a3913 AK |
1387 | /* |
1388 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1389 | * But we need to keep a dummy __setup around otherwise it would | |
1390 | * show up as an environment variable for init. | |
1391 | */ | |
1392 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1393 | { |
ac72e788 AK |
1394 | return 1; |
1395 | } | |
0c2a3913 | 1396 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1397 | |
d5494d4f | 1398 | #ifdef CONFIG_X86_64 |
947e76cd | 1399 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1400 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1401 | |
bdf977b3 | 1402 | /* |
a7fcf28d AL |
1403 | * The following percpu variables are hot. Align current_task to |
1404 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1405 | */ |
1406 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1407 | &init_task; | |
1408 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1409 | |
bdf977b3 | 1410 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1411 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1412 | |
277d5b40 | 1413 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1414 | |
c2daa3be PZ |
1415 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1416 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1417 | ||
d5494d4f YL |
1418 | /* May not be marked __init: used by software suspend */ |
1419 | void syscall_init(void) | |
1da177e4 | 1420 | { |
3386bc8a AL |
1421 | extern char _entry_trampoline[]; |
1422 | extern char entry_SYSCALL_64_trampoline[]; | |
1423 | ||
72f5e08d | 1424 | int cpu = smp_processor_id(); |
3386bc8a AL |
1425 | unsigned long SYSCALL64_entry_trampoline = |
1426 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1427 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
72f5e08d | 1428 | |
31ac34ca | 1429 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
8d4b0678 TG |
1430 | if (static_cpu_has(X86_FEATURE_PTI)) |
1431 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1432 | else | |
1433 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
d56fe4bf IM |
1434 | |
1435 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1436 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1437 | /* |
487d1edb DV |
1438 | * This only works on Intel CPUs. |
1439 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1440 | * This does not cause SYSENTER to jump to the wrong location, because | |
1441 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1442 | */ |
1443 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
4fe2d8b1 | 1444 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); |
4c8cd0c5 | 1445 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1446 | #else |
47edb651 | 1447 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1448 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1449 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1450 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1451 | #endif |
03ae5768 | 1452 | |
d5494d4f YL |
1453 | /* Flags to clear on syscall */ |
1454 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1455 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1456 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1457 | } |
62111195 | 1458 | |
d5494d4f YL |
1459 | /* |
1460 | * Copies of the original ist values from the tss are only accessed during | |
1461 | * debugging, no special alignment required. | |
1462 | */ | |
1463 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1464 | ||
228bdaa9 | 1465 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1466 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1467 | |
1468 | int is_debug_stack(unsigned long addr) | |
1469 | { | |
89cbc767 CL |
1470 | return __this_cpu_read(debug_stack_usage) || |
1471 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1472 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1473 | } |
0f46efeb | 1474 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1475 | |
629f4f9d | 1476 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1477 | |
228bdaa9 SR |
1478 | void debug_stack_set_zero(void) |
1479 | { | |
629f4f9d SA |
1480 | this_cpu_inc(debug_idt_ctr); |
1481 | load_current_idt(); | |
228bdaa9 | 1482 | } |
0f46efeb | 1483 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1484 | |
1485 | void debug_stack_reset(void) | |
1486 | { | |
629f4f9d | 1487 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1488 | return; |
629f4f9d SA |
1489 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1490 | load_current_idt(); | |
228bdaa9 | 1491 | } |
0f46efeb | 1492 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1493 | |
0f3fa48a | 1494 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1495 | |
bdf977b3 TH |
1496 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1497 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1498 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1499 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1500 | |
a7fcf28d AL |
1501 | /* |
1502 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1503 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1504 | * top of the kernel stack directly. | |
1505 | */ | |
1506 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1507 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1508 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1509 | ||
60a5317f | 1510 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1511 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1512 | #endif |
d5494d4f | 1513 | |
0f3fa48a | 1514 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1515 | |
9766cdbc JSR |
1516 | /* |
1517 | * Clear all 6 debug registers: | |
1518 | */ | |
1519 | static void clear_all_debug_regs(void) | |
1520 | { | |
1521 | int i; | |
1522 | ||
1523 | for (i = 0; i < 8; i++) { | |
1524 | /* Ignore db4, db5 */ | |
1525 | if ((i == 4) || (i == 5)) | |
1526 | continue; | |
1527 | ||
1528 | set_debugreg(0, i); | |
1529 | } | |
1530 | } | |
c5413fbe | 1531 | |
0bb9fef9 JW |
1532 | #ifdef CONFIG_KGDB |
1533 | /* | |
1534 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1535 | * connection established. | |
1536 | */ | |
1537 | static void dbg_restore_debug_regs(void) | |
1538 | { | |
1539 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1540 | arch_kgdb_ops.correct_hw_break(); | |
1541 | } | |
1542 | #else /* ! CONFIG_KGDB */ | |
1543 | #define dbg_restore_debug_regs() | |
1544 | #endif /* ! CONFIG_KGDB */ | |
1545 | ||
ce4b1b16 IM |
1546 | static void wait_for_master_cpu(int cpu) |
1547 | { | |
1548 | #ifdef CONFIG_SMP | |
1549 | /* | |
1550 | * wait for ACK from master CPU before continuing | |
1551 | * with AP initialization | |
1552 | */ | |
1553 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1554 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1555 | cpu_relax(); | |
1556 | #endif | |
1557 | } | |
1558 | ||
d2cbcc49 RR |
1559 | /* |
1560 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1561 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1562 | * and IDT. We reload them nevertheless, this function acts as a | |
1563 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1564 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1565 | */ |
1ba76586 | 1566 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1567 | |
148f9bb8 | 1568 | void cpu_init(void) |
1ba76586 | 1569 | { |
0fe1e009 | 1570 | struct orig_ist *oist; |
1ba76586 | 1571 | struct task_struct *me; |
0f3fa48a IM |
1572 | struct tss_struct *t; |
1573 | unsigned long v; | |
fb59831b | 1574 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1575 | int i; |
1576 | ||
ce4b1b16 IM |
1577 | wait_for_master_cpu(cpu); |
1578 | ||
1e02ce4c AL |
1579 | /* |
1580 | * Initialize the CR4 shadow before doing anything that could | |
1581 | * try to read it. | |
1582 | */ | |
1583 | cr4_init_shadow(); | |
1584 | ||
777284b6 BP |
1585 | if (cpu) |
1586 | load_ucode_ap(); | |
e6ebf5de | 1587 | |
c482feef | 1588 | t = &per_cpu(cpu_tss_rw, cpu); |
0fe1e009 | 1589 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1590 | |
e7a22c1e | 1591 | #ifdef CONFIG_NUMA |
27fd185f | 1592 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1593 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1594 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1595 | #endif |
1ba76586 YL |
1596 | |
1597 | me = current; | |
1598 | ||
2eaad1fd | 1599 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1600 | |
375074cc | 1601 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1602 | |
1603 | /* | |
1604 | * Initialize the per-CPU GDT with the boot GDT, | |
1605 | * and set up the GDT descriptor: | |
1606 | */ | |
1607 | ||
552be871 | 1608 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1609 | loadsegment(fs, 0); |
1610 | ||
cf910e83 | 1611 | load_current_idt(); |
1ba76586 YL |
1612 | |
1613 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1614 | syscall_init(); | |
1615 | ||
1616 | wrmsrl(MSR_FS_BASE, 0); | |
1617 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1618 | barrier(); | |
1619 | ||
4763ed4d | 1620 | x86_configure_nx(); |
659006bf | 1621 | x2apic_setup(); |
1ba76586 YL |
1622 | |
1623 | /* | |
1624 | * set up and load the per-CPU TSS | |
1625 | */ | |
0fe1e009 | 1626 | if (!oist->ist[0]) { |
40e7f949 | 1627 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1628 | |
1ba76586 | 1629 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1630 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1631 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1632 | (unsigned long)estacks; |
228bdaa9 SR |
1633 | if (v == DEBUG_STACK-1) |
1634 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1635 | } |
1636 | } | |
1637 | ||
7fb983b4 | 1638 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1639 | |
1ba76586 YL |
1640 | /* |
1641 | * <= is required because the CPU will access up to | |
1642 | * 8 bits beyond the end of the IO permission bitmap. | |
1643 | */ | |
1644 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1645 | t->io_bitmap[i] = ~0UL; | |
1646 | ||
f1f10076 | 1647 | mmgrab(&init_mm); |
1ba76586 | 1648 | me->active_mm = &init_mm; |
8c5dfd25 | 1649 | BUG_ON(me->mm); |
72c0098d | 1650 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1651 | enter_lazy_tlb(&init_mm, me); |
1652 | ||
20bb8344 | 1653 | /* |
7f2590a1 AL |
1654 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1655 | * regardless of what task is running. | |
20bb8344 | 1656 | */ |
72f5e08d | 1657 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1658 | load_TR_desc(); |
4fe2d8b1 | 1659 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1660 | |
37868fe1 | 1661 | load_mm_ldt(&init_mm); |
1ba76586 | 1662 | |
0bb9fef9 JW |
1663 | clear_all_debug_regs(); |
1664 | dbg_restore_debug_regs(); | |
1ba76586 | 1665 | |
21c4cd10 | 1666 | fpu__init_cpu(); |
1ba76586 | 1667 | |
1ba76586 YL |
1668 | if (is_uv_system()) |
1669 | uv_cpu_init(); | |
69218e47 | 1670 | |
69218e47 | 1671 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1672 | } |
1673 | ||
1674 | #else | |
1675 | ||
148f9bb8 | 1676 | void cpu_init(void) |
9ee79a3d | 1677 | { |
d2cbcc49 RR |
1678 | int cpu = smp_processor_id(); |
1679 | struct task_struct *curr = current; | |
c482feef | 1680 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1681 | |
ce4b1b16 | 1682 | wait_for_master_cpu(cpu); |
e6ebf5de | 1683 | |
5b2bdbc8 SR |
1684 | /* |
1685 | * Initialize the CR4 shadow before doing anything that could | |
1686 | * try to read it. | |
1687 | */ | |
1688 | cr4_init_shadow(); | |
1689 | ||
ce4b1b16 | 1690 | show_ucode_info_early(); |
62111195 | 1691 | |
1b74dde7 | 1692 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1693 | |
362f924b | 1694 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1695 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1696 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1697 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1698 | |
cf910e83 | 1699 | load_current_idt(); |
552be871 | 1700 | switch_to_new_gdt(cpu); |
1da177e4 | 1701 | |
1da177e4 LT |
1702 | /* |
1703 | * Set up and load the per-CPU TSS and LDT | |
1704 | */ | |
f1f10076 | 1705 | mmgrab(&init_mm); |
62111195 | 1706 | curr->active_mm = &init_mm; |
8c5dfd25 | 1707 | BUG_ON(curr->mm); |
72c0098d | 1708 | initialize_tlbstate_and_flush(); |
62111195 | 1709 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1710 | |
20bb8344 AL |
1711 | /* |
1712 | * Initialize the TSS. Don't bother initializing sp0, as the initial | |
1713 | * task never enters user mode. | |
1714 | */ | |
72f5e08d | 1715 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1716 | load_TR_desc(); |
20bb8344 | 1717 | |
37868fe1 | 1718 | load_mm_ldt(&init_mm); |
1da177e4 | 1719 | |
7fb983b4 | 1720 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1721 | |
22c4e308 | 1722 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1723 | /* Set up doublefault TSS pointer in the GDT */ |
1724 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1725 | #endif |
1da177e4 | 1726 | |
9766cdbc | 1727 | clear_all_debug_regs(); |
0bb9fef9 | 1728 | dbg_restore_debug_regs(); |
1da177e4 | 1729 | |
21c4cd10 | 1730 | fpu__init_cpu(); |
69218e47 | 1731 | |
69218e47 | 1732 | load_fixmap_gdt(cpu); |
1da177e4 | 1733 | } |
1ba76586 | 1734 | #endif |
5700f743 | 1735 | |
b51ef52d LA |
1736 | static void bsp_resume(void) |
1737 | { | |
1738 | if (this_cpu->c_bsp_resume) | |
1739 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1740 | } | |
1741 | ||
1742 | static struct syscore_ops cpu_syscore_ops = { | |
1743 | .resume = bsp_resume, | |
1744 | }; | |
1745 | ||
1746 | static int __init init_cpu_syscore(void) | |
1747 | { | |
1748 | register_syscore_ops(&cpu_syscore_ops); | |
1749 | return 0; | |
1750 | } | |
1751 | core_initcall(init_cpu_syscore); | |
1008c52c BP |
1752 | |
1753 | /* | |
1754 | * The microcode loader calls this upon late microcode load to recheck features, | |
1755 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1756 | * hotplug lock. | |
1757 | */ | |
1758 | void microcode_check(void) | |
1759 | { | |
42ca8082 BP |
1760 | struct cpuinfo_x86 info; |
1761 | ||
1008c52c | 1762 | perf_check_microcode(); |
42ca8082 BP |
1763 | |
1764 | /* Reload CPUID max function as it might've changed. */ | |
1765 | info.cpuid_level = cpuid_eax(0); | |
1766 | ||
1767 | /* | |
1768 | * Copy all capability leafs to pick up the synthetic ones so that | |
1769 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1770 | * get overwritten in get_cpu_cap(). | |
1771 | */ | |
1772 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1773 | ||
1774 | get_cpu_cap(&info); | |
1775 | ||
1776 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1777 | return; | |
1778 | ||
1779 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1780 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 1781 | } |