Commit | Line | Data |
---|---|---|
f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
d288e1cf FY |
40 | #include <asm/microcode.h> |
41 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
42 | |
43 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 44 | #include <asm/uv/uv.h> |
1da177e4 LT |
45 | #endif |
46 | ||
47 | #include "cpu.h" | |
48 | ||
c2d1cec1 | 49 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 50 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
51 | cpumask_var_t cpu_callout_mask; |
52 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
53 | |
54 | /* representing cpus for which sibling maps can be computed */ | |
55 | cpumask_var_t cpu_sibling_setup_mask; | |
56 | ||
2f2f52ba | 57 | /* correctly size the local cpu masks */ |
4369f1fb | 58 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
59 | { |
60 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
62 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
63 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
64 | } | |
65 | ||
148f9bb8 | 66 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
67 | { |
68 | #ifdef CONFIG_X86_64 | |
27c13ece | 69 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
70 | #else |
71 | /* Not much we can do here... */ | |
72 | /* Check if at least it has cpuid */ | |
73 | if (c->cpuid_level == -1) { | |
74 | /* No cpuid. It must be an ancient CPU */ | |
75 | if (c->x86 == 4) | |
76 | strcpy(c->x86_model_id, "486"); | |
77 | else if (c->x86 == 3) | |
78 | strcpy(c->x86_model_id, "386"); | |
79 | } | |
80 | #endif | |
81 | } | |
82 | ||
148f9bb8 | 83 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
84 | .c_init = default_init, |
85 | .c_vendor = "Unknown", | |
86 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
87 | }; | |
88 | ||
148f9bb8 | 89 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 90 | |
06deef89 | 91 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 92 | #ifdef CONFIG_X86_64 |
06deef89 BG |
93 | /* |
94 | * We need valid kernel segments for data and code in long mode too | |
95 | * IRET will check the segment types kkeil 2000/10/28 | |
96 | * Also sysret mandates a special GDT layout | |
97 | * | |
9766cdbc | 98 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
99 | * Hopefully nobody expects them at a fixed place (Wine?) |
100 | */ | |
1e5de182 AM |
101 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
102 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
103 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
105 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
106 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 107 | #else |
1e5de182 AM |
108 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
109 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
110 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
111 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
112 | /* |
113 | * Segments used for calling PnP BIOS have byte granularity. | |
114 | * They code segments and data segments have fixed 64k limits, | |
115 | * the transfer segment sizes are set at run time. | |
116 | */ | |
6842ef0e | 117 | /* 32-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit code */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 125 | /* 16-bit data */ |
1e5de182 | 126 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
127 | /* |
128 | * The APM segments have byte granularity and their bases | |
129 | * are set at run time. All have 64k limits. | |
130 | */ | |
6842ef0e | 131 | /* 32-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 133 | /* 16-bit code */ |
1e5de182 | 134 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 135 | /* data */ |
72c4d853 | 136 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 137 | |
1e5de182 AM |
138 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
139 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 140 | GDT_STACK_CANARY_INIT |
950ad7ff | 141 | #endif |
06deef89 | 142 | } }; |
7a61d35d | 143 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 144 | |
0c752a93 SS |
145 | static int __init x86_xsave_setup(char *s) |
146 | { | |
147 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 148 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
149 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
150 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
151 | return 1; |
152 | } | |
153 | __setup("noxsave", x86_xsave_setup); | |
154 | ||
6bad06b7 SS |
155 | static int __init x86_xsaveopt_setup(char *s) |
156 | { | |
157 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
158 | return 1; | |
159 | } | |
160 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
161 | ||
ba51dced | 162 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
163 | static int cachesize_override = -1; |
164 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 165 | |
0a488a53 YL |
166 | static int __init cachesize_setup(char *str) |
167 | { | |
168 | get_option(&str, &cachesize_override); | |
169 | return 1; | |
170 | } | |
171 | __setup("cachesize=", cachesize_setup); | |
172 | ||
0a488a53 YL |
173 | static int __init x86_fxsr_setup(char *s) |
174 | { | |
175 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
176 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
177 | return 1; | |
178 | } | |
179 | __setup("nofxsr", x86_fxsr_setup); | |
180 | ||
181 | static int __init x86_sep_setup(char *s) | |
182 | { | |
183 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
184 | return 1; | |
185 | } | |
186 | __setup("nosep", x86_sep_setup); | |
187 | ||
188 | /* Standard macro to see if a specific flag is changeable */ | |
189 | static inline int flag_is_changeable_p(u32 flag) | |
190 | { | |
191 | u32 f1, f2; | |
192 | ||
94f6bac1 KH |
193 | /* |
194 | * Cyrix and IDT cpus allow disabling of CPUID | |
195 | * so the code below may return different results | |
196 | * when it is executed before and after enabling | |
197 | * the CPUID. Add "volatile" to not allow gcc to | |
198 | * optimize the subsequent calls to this function. | |
199 | */ | |
0f3fa48a IM |
200 | asm volatile ("pushfl \n\t" |
201 | "pushfl \n\t" | |
202 | "popl %0 \n\t" | |
203 | "movl %0, %1 \n\t" | |
204 | "xorl %2, %0 \n\t" | |
205 | "pushl %0 \n\t" | |
206 | "popfl \n\t" | |
207 | "pushfl \n\t" | |
208 | "popl %0 \n\t" | |
209 | "popfl \n\t" | |
210 | ||
94f6bac1 KH |
211 | : "=&r" (f1), "=&r" (f2) |
212 | : "ir" (flag)); | |
0a488a53 YL |
213 | |
214 | return ((f1^f2) & flag) != 0; | |
215 | } | |
216 | ||
217 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 218 | int have_cpuid_p(void) |
0a488a53 YL |
219 | { |
220 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
221 | } | |
222 | ||
148f9bb8 | 223 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 224 | { |
0f3fa48a IM |
225 | unsigned long lo, hi; |
226 | ||
227 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
228 | return; | |
229 | ||
230 | /* Disable processor serial number: */ | |
231 | ||
232 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
233 | lo |= 0x200000; | |
234 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
235 | ||
236 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
237 | clear_cpu_cap(c, X86_FEATURE_PN); | |
238 | ||
239 | /* Disabling the serial number may affect the cpuid level */ | |
240 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
241 | } |
242 | ||
243 | static int __init x86_serial_nr_setup(char *s) | |
244 | { | |
245 | disable_x86_serial_nr = 0; | |
246 | return 1; | |
247 | } | |
248 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 249 | #else |
102bbe3a YL |
250 | static inline int flag_is_changeable_p(u32 flag) |
251 | { | |
252 | return 1; | |
253 | } | |
102bbe3a YL |
254 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
255 | { | |
256 | } | |
ba51dced | 257 | #endif |
0a488a53 | 258 | |
de5397ad FY |
259 | static __init int setup_disable_smep(char *arg) |
260 | { | |
b2cc2a07 | 261 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
262 | return 1; |
263 | } | |
264 | __setup("nosmep", setup_disable_smep); | |
265 | ||
b2cc2a07 | 266 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 267 | { |
b2cc2a07 PA |
268 | if (cpu_has(c, X86_FEATURE_SMEP)) |
269 | set_in_cr4(X86_CR4_SMEP); | |
de5397ad FY |
270 | } |
271 | ||
52b6179a PA |
272 | static __init int setup_disable_smap(char *arg) |
273 | { | |
b2cc2a07 | 274 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
275 | return 1; |
276 | } | |
277 | __setup("nosmap", setup_disable_smap); | |
278 | ||
b2cc2a07 PA |
279 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
280 | { | |
281 | unsigned long eflags; | |
282 | ||
283 | /* This should have been cleared long ago */ | |
284 | raw_local_save_flags(eflags); | |
285 | BUG_ON(eflags & X86_EFLAGS_AC); | |
286 | ||
287 | if (cpu_has(c, X86_FEATURE_SMAP)) | |
288 | set_in_cr4(X86_CR4_SMAP); | |
de5397ad FY |
289 | } |
290 | ||
b38b0665 PA |
291 | /* |
292 | * Some CPU features depend on higher CPUID levels, which may not always | |
293 | * be available due to CPUID level capping or broken virtualization | |
294 | * software. Add those features to this table to auto-disable them. | |
295 | */ | |
296 | struct cpuid_dependent_feature { | |
297 | u32 feature; | |
298 | u32 level; | |
299 | }; | |
0f3fa48a | 300 | |
148f9bb8 | 301 | static const struct cpuid_dependent_feature |
b38b0665 PA |
302 | cpuid_dependent_features[] = { |
303 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
304 | { X86_FEATURE_DCA, 0x00000009 }, | |
305 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
306 | { 0, 0 } | |
307 | }; | |
308 | ||
148f9bb8 | 309 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
310 | { |
311 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 312 | |
b38b0665 | 313 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
314 | |
315 | if (!cpu_has(c, df->feature)) | |
316 | continue; | |
b38b0665 PA |
317 | /* |
318 | * Note: cpuid_level is set to -1 if unavailable, but | |
319 | * extended_extended_level is set to 0 if unavailable | |
320 | * and the legitimate extended levels are all negative | |
321 | * when signed; hence the weird messing around with | |
322 | * signs here... | |
323 | */ | |
0f3fa48a | 324 | if (!((s32)df->level < 0 ? |
f6db44df | 325 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
326 | (s32)df->level > (s32)c->cpuid_level)) |
327 | continue; | |
328 | ||
329 | clear_cpu_cap(c, df->feature); | |
330 | if (!warn) | |
331 | continue; | |
332 | ||
333 | printk(KERN_WARNING | |
334 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
335 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 336 | } |
f6db44df | 337 | } |
b38b0665 | 338 | |
102bbe3a YL |
339 | /* |
340 | * Naming convention should be: <Name> [(<Codename>)] | |
341 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
342 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
343 | * isn't used | |
102bbe3a YL |
344 | */ |
345 | ||
346 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 347 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 348 | { |
02dde8b4 | 349 | const struct cpu_model_info *info; |
102bbe3a YL |
350 | |
351 | if (c->x86_model >= 16) | |
352 | return NULL; /* Range check */ | |
353 | ||
354 | if (!this_cpu) | |
355 | return NULL; | |
356 | ||
357 | info = this_cpu->c_models; | |
358 | ||
359 | while (info && info->family) { | |
360 | if (info->family == c->x86) | |
361 | return info->model_names[c->x86_model]; | |
362 | info++; | |
363 | } | |
364 | return NULL; /* Not found */ | |
365 | } | |
366 | ||
148f9bb8 PG |
367 | __u32 cpu_caps_cleared[NCAPINTS]; |
368 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 369 | |
11e3a840 JF |
370 | void load_percpu_segment(int cpu) |
371 | { | |
372 | #ifdef CONFIG_X86_32 | |
373 | loadsegment(fs, __KERNEL_PERCPU); | |
374 | #else | |
375 | loadsegment(gs, 0); | |
376 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
377 | #endif | |
60a5317f | 378 | load_stack_canary_segment(); |
11e3a840 JF |
379 | } |
380 | ||
0f3fa48a IM |
381 | /* |
382 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
383 | * it's on the real one. | |
384 | */ | |
552be871 | 385 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
386 | { |
387 | struct desc_ptr gdt_descr; | |
388 | ||
2697fbd5 | 389 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
390 | gdt_descr.size = GDT_SIZE - 1; |
391 | load_gdt(&gdt_descr); | |
2697fbd5 | 392 | /* Reload the per-cpu base */ |
11e3a840 JF |
393 | |
394 | load_percpu_segment(cpu); | |
9d31d35b YL |
395 | } |
396 | ||
148f9bb8 | 397 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 398 | |
148f9bb8 | 399 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
400 | { |
401 | unsigned int *v; | |
402 | char *p, *q; | |
403 | ||
3da99c97 | 404 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 405 | return; |
1da177e4 | 406 | |
0f3fa48a | 407 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
408 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
409 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
410 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
411 | c->x86_model_id[48] = 0; | |
412 | ||
0f3fa48a IM |
413 | /* |
414 | * Intel chips right-justify this string for some dumb reason; | |
415 | * undo that brain damage: | |
416 | */ | |
1da177e4 | 417 | p = q = &c->x86_model_id[0]; |
34048c9e | 418 | while (*p == ' ') |
9766cdbc | 419 | p++; |
34048c9e | 420 | if (p != q) { |
9766cdbc JSR |
421 | while (*p) |
422 | *q++ = *p++; | |
423 | while (q <= &c->x86_model_id[48]) | |
424 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 425 | } |
1da177e4 LT |
426 | } |
427 | ||
148f9bb8 | 428 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 429 | { |
9d31d35b | 430 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 431 | |
3da99c97 | 432 | n = c->extended_cpuid_level; |
1da177e4 LT |
433 | |
434 | if (n >= 0x80000005) { | |
9d31d35b | 435 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 436 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
437 | #ifdef CONFIG_X86_64 |
438 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
439 | c->x86_tlbsize = 0; | |
440 | #endif | |
1da177e4 LT |
441 | } |
442 | ||
443 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
444 | return; | |
445 | ||
0a488a53 | 446 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 447 | l2size = ecx >> 16; |
34048c9e | 448 | |
140fc727 YL |
449 | #ifdef CONFIG_X86_64 |
450 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
451 | #else | |
1da177e4 LT |
452 | /* do processor-specific cache resizing */ |
453 | if (this_cpu->c_size_cache) | |
34048c9e | 454 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
455 | |
456 | /* Allow user to override all this if necessary. */ | |
457 | if (cachesize_override != -1) | |
458 | l2size = cachesize_override; | |
459 | ||
34048c9e | 460 | if (l2size == 0) |
1da177e4 | 461 | return; /* Again, no L2 cache is possible */ |
140fc727 | 462 | #endif |
1da177e4 LT |
463 | |
464 | c->x86_cache_size = l2size; | |
1da177e4 LT |
465 | } |
466 | ||
e0ba94f1 AS |
467 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
468 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
469 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
470 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
471 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
472 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
473 | ||
c4211f42 AS |
474 | /* |
475 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
476 | * with multiple 'invlpg'. It will do this replacement when | |
477 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
478 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
479 | */ | |
480 | s8 __read_mostly tlb_flushall_shift = -1; | |
481 | ||
148f9bb8 | 482 | void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
483 | { |
484 | if (this_cpu->c_detect_tlb) | |
485 | this_cpu->c_detect_tlb(c); | |
486 | ||
487 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ | |
c4211f42 | 488 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ |
a9ad773e | 489 | "tlb_flushall_shift: %d\n", |
e0ba94f1 AS |
490 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
491 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 AS |
492 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
493 | tlb_flushall_shift); | |
e0ba94f1 AS |
494 | } |
495 | ||
148f9bb8 | 496 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 497 | { |
97e4db7c | 498 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
499 | u32 eax, ebx, ecx, edx; |
500 | int index_msb, core_bits; | |
2eaad1fd | 501 | static bool printed; |
1da177e4 | 502 | |
0a488a53 | 503 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 504 | return; |
1da177e4 | 505 | |
0a488a53 YL |
506 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
507 | goto out; | |
1da177e4 | 508 | |
1cd78776 YL |
509 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
510 | return; | |
1da177e4 | 511 | |
0a488a53 | 512 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 513 | |
9d31d35b YL |
514 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
515 | ||
516 | if (smp_num_siblings == 1) { | |
2eaad1fd | 517 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
518 | goto out; |
519 | } | |
9d31d35b | 520 | |
0f3fa48a IM |
521 | if (smp_num_siblings <= 1) |
522 | goto out; | |
9d31d35b | 523 | |
0f3fa48a IM |
524 | index_msb = get_count_order(smp_num_siblings); |
525 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 526 | |
0f3fa48a | 527 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 528 | |
0f3fa48a | 529 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 530 | |
0f3fa48a | 531 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 532 | |
0f3fa48a IM |
533 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
534 | ((1 << core_bits) - 1); | |
1da177e4 | 535 | |
0a488a53 | 536 | out: |
2eaad1fd | 537 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
538 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
539 | c->phys_proc_id); | |
540 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
541 | c->cpu_core_id); | |
2eaad1fd | 542 | printed = 1; |
9d31d35b | 543 | } |
9d31d35b | 544 | #endif |
97e4db7c | 545 | } |
1da177e4 | 546 | |
148f9bb8 | 547 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
548 | { |
549 | char *v = c->x86_vendor_id; | |
0f3fa48a | 550 | int i; |
1da177e4 LT |
551 | |
552 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
553 | if (!cpu_devs[i]) |
554 | break; | |
555 | ||
556 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
557 | (cpu_devs[i]->c_ident[1] && | |
558 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 559 | |
10a434fc YL |
560 | this_cpu = cpu_devs[i]; |
561 | c->x86_vendor = this_cpu->c_x86_vendor; | |
562 | return; | |
1da177e4 LT |
563 | } |
564 | } | |
10a434fc | 565 | |
a9c56953 MK |
566 | printk_once(KERN_ERR |
567 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
568 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 569 | |
fe38d855 CE |
570 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
571 | this_cpu = &default_cpu; | |
1da177e4 LT |
572 | } |
573 | ||
148f9bb8 | 574 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 575 | { |
1da177e4 | 576 | /* Get vendor name */ |
4a148513 HH |
577 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
578 | (unsigned int *)&c->x86_vendor_id[0], | |
579 | (unsigned int *)&c->x86_vendor_id[8], | |
580 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 581 | |
1da177e4 | 582 | c->x86 = 4; |
9d31d35b | 583 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
584 | if (c->cpuid_level >= 0x00000001) { |
585 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 586 | |
1da177e4 | 587 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
588 | c->x86 = (tfms >> 8) & 0xf; |
589 | c->x86_model = (tfms >> 4) & 0xf; | |
590 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 591 | |
f5f786d0 | 592 | if (c->x86 == 0xf) |
1da177e4 | 593 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 594 | if (c->x86 >= 0x6) |
9d31d35b | 595 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 596 | |
d4387bd3 | 597 | if (cap0 & (1<<19)) { |
d4387bd3 | 598 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 599 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 600 | } |
1da177e4 | 601 | } |
1da177e4 | 602 | } |
3da99c97 | 603 | |
148f9bb8 | 604 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
605 | { |
606 | u32 tfms, xlvl; | |
3da99c97 | 607 | u32 ebx; |
093af8d7 | 608 | |
3da99c97 YL |
609 | /* Intel-defined flags: level 0x00000001 */ |
610 | if (c->cpuid_level >= 0x00000001) { | |
611 | u32 capability, excap; | |
0f3fa48a | 612 | |
3da99c97 YL |
613 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
614 | c->x86_capability[0] = capability; | |
615 | c->x86_capability[4] = excap; | |
616 | } | |
093af8d7 | 617 | |
bdc802dc PA |
618 | /* Additional Intel-defined flags: level 0x00000007 */ |
619 | if (c->cpuid_level >= 0x00000007) { | |
620 | u32 eax, ebx, ecx, edx; | |
621 | ||
622 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
623 | ||
2494b030 | 624 | c->x86_capability[9] = ebx; |
bdc802dc PA |
625 | } |
626 | ||
3da99c97 YL |
627 | /* AMD-defined flags: level 0x80000001 */ |
628 | xlvl = cpuid_eax(0x80000000); | |
629 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 630 | |
3da99c97 YL |
631 | if ((xlvl & 0xffff0000) == 0x80000000) { |
632 | if (xlvl >= 0x80000001) { | |
633 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
634 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 635 | } |
093af8d7 | 636 | } |
093af8d7 | 637 | |
5122c890 YL |
638 | if (c->extended_cpuid_level >= 0x80000008) { |
639 | u32 eax = cpuid_eax(0x80000008); | |
640 | ||
641 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
642 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 643 | } |
13c6c532 JB |
644 | #ifdef CONFIG_X86_32 |
645 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
646 | c->x86_phys_bits = 36; | |
5122c890 | 647 | #endif |
e3224234 YL |
648 | |
649 | if (c->extended_cpuid_level >= 0x80000007) | |
650 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 651 | |
1dedefd1 | 652 | init_scattered_cpuid_features(c); |
093af8d7 | 653 | } |
1da177e4 | 654 | |
148f9bb8 | 655 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
656 | { |
657 | #ifdef CONFIG_X86_32 | |
658 | int i; | |
659 | ||
660 | /* | |
661 | * First of all, decide if this is a 486 or higher | |
662 | * It's a 486 if we can modify the AC flag | |
663 | */ | |
664 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
665 | c->x86 = 4; | |
666 | else | |
667 | c->x86 = 3; | |
668 | ||
669 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
670 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
671 | c->x86_vendor_id[0] = 0; | |
672 | cpu_devs[i]->c_identify(c); | |
673 | if (c->x86_vendor_id[0]) { | |
674 | get_cpu_vendor(c); | |
675 | break; | |
676 | } | |
677 | } | |
678 | #endif | |
679 | } | |
680 | ||
34048c9e PC |
681 | /* |
682 | * Do minimum CPU detection early. | |
683 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
684 | * cache alignment. | |
685 | * The others are not touched to avoid unwanted side effects. | |
686 | * | |
687 | * WARNING: this function is only called on the BP. Don't add code here | |
688 | * that is supposed to run on all CPUs. | |
689 | */ | |
3da99c97 | 690 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 691 | { |
6627d242 YL |
692 | #ifdef CONFIG_X86_64 |
693 | c->x86_clflush_size = 64; | |
13c6c532 JB |
694 | c->x86_phys_bits = 36; |
695 | c->x86_virt_bits = 48; | |
6627d242 | 696 | #else |
d4387bd3 | 697 | c->x86_clflush_size = 32; |
13c6c532 JB |
698 | c->x86_phys_bits = 32; |
699 | c->x86_virt_bits = 32; | |
6627d242 | 700 | #endif |
0a488a53 | 701 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 702 | |
3da99c97 | 703 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 704 | c->extended_cpuid_level = 0; |
d7cd5611 | 705 | |
aef93c8b YL |
706 | if (!have_cpuid_p()) |
707 | identify_cpu_without_cpuid(c); | |
708 | ||
709 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
710 | if (!have_cpuid_p()) |
711 | return; | |
712 | ||
713 | cpu_detect(c); | |
3da99c97 | 714 | get_cpu_vendor(c); |
3da99c97 | 715 | get_cpu_cap(c); |
60e019eb | 716 | fpu_detect(c); |
12cf105c | 717 | |
10a434fc YL |
718 | if (this_cpu->c_early_init) |
719 | this_cpu->c_early_init(c); | |
093af8d7 | 720 | |
f6e9456c | 721 | c->cpu_index = 0; |
b38b0665 | 722 | filter_cpuid_features(c, false); |
de5397ad | 723 | |
a110b5ec BP |
724 | if (this_cpu->c_bsp_init) |
725 | this_cpu->c_bsp_init(c); | |
c3b83598 BP |
726 | |
727 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
d7cd5611 RR |
728 | } |
729 | ||
9d31d35b YL |
730 | void __init early_cpu_init(void) |
731 | { | |
02dde8b4 | 732 | const struct cpu_dev *const *cdev; |
10a434fc YL |
733 | int count = 0; |
734 | ||
ac23f253 | 735 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 736 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
737 | #endif |
738 | ||
10a434fc | 739 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 740 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 741 | |
10a434fc YL |
742 | if (count >= X86_VENDOR_NUM) |
743 | break; | |
744 | cpu_devs[count] = cpudev; | |
745 | count++; | |
746 | ||
ac23f253 | 747 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
748 | { |
749 | unsigned int j; | |
750 | ||
751 | for (j = 0; j < 2; j++) { | |
752 | if (!cpudev->c_ident[j]) | |
753 | continue; | |
754 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
755 | cpudev->c_ident[j]); | |
756 | } | |
10a434fc | 757 | } |
0388423d | 758 | #endif |
10a434fc | 759 | } |
9d31d35b | 760 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 761 | } |
093af8d7 | 762 | |
b6734c35 | 763 | /* |
366d4a43 BP |
764 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
765 | * unfortunately, that's not true in practice because of early VIA | |
766 | * chips and (more importantly) broken virtualizers that are not easy | |
767 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
768 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 769 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 770 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 771 | */ |
148f9bb8 | 772 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 773 | { |
366d4a43 | 774 | #ifdef CONFIG_X86_32 |
b6734c35 | 775 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
776 | #else |
777 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
778 | #endif | |
d7cd5611 RR |
779 | } |
780 | ||
148f9bb8 | 781 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 782 | { |
aef93c8b | 783 | c->extended_cpuid_level = 0; |
1da177e4 | 784 | |
3da99c97 | 785 | if (!have_cpuid_p()) |
aef93c8b | 786 | identify_cpu_without_cpuid(c); |
1d67953f | 787 | |
aef93c8b | 788 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 789 | if (!have_cpuid_p()) |
aef93c8b | 790 | return; |
1da177e4 | 791 | |
3da99c97 | 792 | cpu_detect(c); |
1da177e4 | 793 | |
3da99c97 | 794 | get_cpu_vendor(c); |
1da177e4 | 795 | |
3da99c97 | 796 | get_cpu_cap(c); |
1da177e4 | 797 | |
3da99c97 YL |
798 | if (c->cpuid_level >= 0x00000001) { |
799 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
800 | #ifdef CONFIG_X86_32 |
801 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 802 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 803 | # else |
3da99c97 | 804 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
805 | # endif |
806 | #endif | |
b89d3b3e | 807 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 808 | } |
1da177e4 | 809 | |
1b05d60d | 810 | get_model_name(c); /* Default name */ |
1da177e4 | 811 | |
3da99c97 | 812 | detect_nopl(c); |
1da177e4 | 813 | } |
1da177e4 LT |
814 | |
815 | /* | |
816 | * This does the hard work of actually picking apart the CPU stuff... | |
817 | */ | |
148f9bb8 | 818 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
819 | { |
820 | int i; | |
821 | ||
822 | c->loops_per_jiffy = loops_per_jiffy; | |
823 | c->x86_cache_size = -1; | |
824 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
825 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
826 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
827 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 828 | c->x86_max_cores = 1; |
102bbe3a | 829 | c->x86_coreid_bits = 0; |
11fdd252 | 830 | #ifdef CONFIG_X86_64 |
102bbe3a | 831 | c->x86_clflush_size = 64; |
13c6c532 JB |
832 | c->x86_phys_bits = 36; |
833 | c->x86_virt_bits = 48; | |
102bbe3a YL |
834 | #else |
835 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 836 | c->x86_clflush_size = 32; |
13c6c532 JB |
837 | c->x86_phys_bits = 32; |
838 | c->x86_virt_bits = 32; | |
102bbe3a YL |
839 | #endif |
840 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
841 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
842 | ||
1da177e4 LT |
843 | generic_identify(c); |
844 | ||
3898534d | 845 | if (this_cpu->c_identify) |
1da177e4 LT |
846 | this_cpu->c_identify(c); |
847 | ||
2759c328 YL |
848 | /* Clear/Set all flags overriden by options, after probe */ |
849 | for (i = 0; i < NCAPINTS; i++) { | |
850 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
851 | c->x86_capability[i] |= cpu_caps_set[i]; | |
852 | } | |
853 | ||
102bbe3a | 854 | #ifdef CONFIG_X86_64 |
cb8cc442 | 855 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
856 | #endif |
857 | ||
1da177e4 LT |
858 | /* |
859 | * Vendor-specific initialization. In this section we | |
860 | * canonicalize the feature flags, meaning if there are | |
861 | * features a certain CPU supports which CPUID doesn't | |
862 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
863 | * we handle them here. | |
864 | * | |
865 | * At the end of this section, c->x86_capability better | |
866 | * indicate the features this CPU genuinely supports! | |
867 | */ | |
868 | if (this_cpu->c_init) | |
869 | this_cpu->c_init(c); | |
870 | ||
871 | /* Disable the PN if appropriate */ | |
872 | squash_the_stupid_serial_number(c); | |
873 | ||
b2cc2a07 PA |
874 | /* Set up SMEP/SMAP */ |
875 | setup_smep(c); | |
876 | setup_smap(c); | |
877 | ||
1da177e4 | 878 | /* |
0f3fa48a IM |
879 | * The vendor-specific functions might have changed features. |
880 | * Now we do "generic changes." | |
1da177e4 LT |
881 | */ |
882 | ||
b38b0665 PA |
883 | /* Filter out anything that depends on CPUID levels we don't have */ |
884 | filter_cpuid_features(c, true); | |
885 | ||
1da177e4 | 886 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 887 | if (!c->x86_model_id[0]) { |
02dde8b4 | 888 | const char *p; |
1da177e4 | 889 | p = table_lookup_model(c); |
34048c9e | 890 | if (p) |
1da177e4 LT |
891 | strcpy(c->x86_model_id, p); |
892 | else | |
893 | /* Last resort... */ | |
894 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 895 | c->x86, c->x86_model); |
1da177e4 LT |
896 | } |
897 | ||
102bbe3a YL |
898 | #ifdef CONFIG_X86_64 |
899 | detect_ht(c); | |
900 | #endif | |
901 | ||
88b094fb | 902 | init_hypervisor(c); |
49d859d7 | 903 | x86_init_rdrand(c); |
3e0c3737 YL |
904 | |
905 | /* | |
906 | * Clear/Set all flags overriden by options, need do it | |
907 | * before following smp all cpus cap AND. | |
908 | */ | |
909 | for (i = 0; i < NCAPINTS; i++) { | |
910 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
911 | c->x86_capability[i] |= cpu_caps_set[i]; | |
912 | } | |
913 | ||
1da177e4 LT |
914 | /* |
915 | * On SMP, boot_cpu_data holds the common feature set between | |
916 | * all CPUs; so make sure that we indicate which features are | |
917 | * common between the CPUs. The first time this routine gets | |
918 | * executed, c == &boot_cpu_data. | |
919 | */ | |
34048c9e | 920 | if (c != &boot_cpu_data) { |
1da177e4 | 921 | /* AND the already accumulated flags with these */ |
9d31d35b | 922 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 923 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
924 | |
925 | /* OR, i.e. replicate the bug flags */ | |
926 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
927 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
928 | } |
929 | ||
930 | /* Init Machine Check Exception if available. */ | |
5e09954a | 931 | mcheck_cpu_init(c); |
30d432df AK |
932 | |
933 | select_idle_routine(c); | |
102bbe3a | 934 | |
de2d9445 | 935 | #ifdef CONFIG_NUMA |
102bbe3a YL |
936 | numa_add_cpu(smp_processor_id()); |
937 | #endif | |
a6c4e076 | 938 | } |
31ab269a | 939 | |
e04d645f GC |
940 | #ifdef CONFIG_X86_64 |
941 | static void vgetcpu_set_mode(void) | |
942 | { | |
943 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
944 | vgetcpu_mode = VGETCPU_RDTSCP; | |
945 | else | |
946 | vgetcpu_mode = VGETCPU_LSL; | |
947 | } | |
948 | #endif | |
949 | ||
a6c4e076 JF |
950 | void __init identify_boot_cpu(void) |
951 | { | |
952 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 953 | init_amd_e400_c1e_mask(); |
102bbe3a | 954 | #ifdef CONFIG_X86_32 |
a6c4e076 | 955 | sysenter_setup(); |
6fe940d6 | 956 | enable_sep_cpu(); |
e04d645f GC |
957 | #else |
958 | vgetcpu_set_mode(); | |
102bbe3a | 959 | #endif |
5b556332 | 960 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 961 | } |
3b520b23 | 962 | |
148f9bb8 | 963 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
964 | { |
965 | BUG_ON(c == &boot_cpu_data); | |
966 | identify_cpu(c); | |
102bbe3a | 967 | #ifdef CONFIG_X86_32 |
a6c4e076 | 968 | enable_sep_cpu(); |
102bbe3a | 969 | #endif |
a6c4e076 | 970 | mtrr_ap_init(); |
1da177e4 LT |
971 | } |
972 | ||
a0854a46 | 973 | struct msr_range { |
0f3fa48a IM |
974 | unsigned min; |
975 | unsigned max; | |
a0854a46 | 976 | }; |
1da177e4 | 977 | |
148f9bb8 | 978 | static const struct msr_range msr_range_array[] = { |
a0854a46 YL |
979 | { 0x00000000, 0x00000418}, |
980 | { 0xc0000000, 0xc000040b}, | |
981 | { 0xc0010000, 0xc0010142}, | |
982 | { 0xc0011000, 0xc001103b}, | |
983 | }; | |
1da177e4 | 984 | |
148f9bb8 | 985 | static void __print_cpu_msr(void) |
a0854a46 | 986 | { |
0f3fa48a | 987 | unsigned index_min, index_max; |
a0854a46 YL |
988 | unsigned index; |
989 | u64 val; | |
990 | int i; | |
a0854a46 YL |
991 | |
992 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
993 | index_min = msr_range_array[i].min; | |
994 | index_max = msr_range_array[i].max; | |
0f3fa48a | 995 | |
a0854a46 | 996 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 997 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
998 | continue; |
999 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1000 | } |
a0854a46 YL |
1001 | } |
1002 | } | |
94605eff | 1003 | |
148f9bb8 | 1004 | static int show_msr; |
0f3fa48a | 1005 | |
a0854a46 YL |
1006 | static __init int setup_show_msr(char *arg) |
1007 | { | |
1008 | int num; | |
3dd9d514 | 1009 | |
a0854a46 | 1010 | get_option(&arg, &num); |
3dd9d514 | 1011 | |
a0854a46 YL |
1012 | if (num > 0) |
1013 | show_msr = num; | |
1014 | return 1; | |
1da177e4 | 1015 | } |
a0854a46 | 1016 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1017 | |
191679fd AK |
1018 | static __init int setup_noclflush(char *arg) |
1019 | { | |
1020 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1021 | return 1; | |
1022 | } | |
1023 | __setup("noclflush", setup_noclflush); | |
1024 | ||
148f9bb8 | 1025 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1026 | { |
02dde8b4 | 1027 | const char *vendor = NULL; |
1da177e4 | 1028 | |
0f3fa48a | 1029 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1030 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1031 | } else { |
1032 | if (c->cpuid_level >= 0) | |
1033 | vendor = c->x86_vendor_id; | |
1034 | } | |
1da177e4 | 1035 | |
bd32a8cf | 1036 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1037 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1038 | |
9d31d35b | 1039 | if (c->x86_model_id[0]) |
924e101a | 1040 | printk(KERN_CONT "%s", strim(c->x86_model_id)); |
1da177e4 | 1041 | else |
9d31d35b | 1042 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1043 | |
924e101a BP |
1044 | printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model); |
1045 | ||
34048c9e | 1046 | if (c->x86_mask || c->cpuid_level >= 0) |
924e101a | 1047 | printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask); |
1da177e4 | 1048 | else |
924e101a | 1049 | printk(KERN_CONT ")\n"); |
a0854a46 | 1050 | |
0b8b8078 | 1051 | print_cpu_msr(c); |
21c3fcf3 YL |
1052 | } |
1053 | ||
148f9bb8 | 1054 | void print_cpu_msr(struct cpuinfo_x86 *c) |
21c3fcf3 | 1055 | { |
a0854a46 | 1056 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1057 | __print_cpu_msr(); |
1da177e4 LT |
1058 | } |
1059 | ||
ac72e788 AK |
1060 | static __init int setup_disablecpuid(char *arg) |
1061 | { | |
1062 | int bit; | |
0f3fa48a | 1063 | |
ac72e788 AK |
1064 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1065 | setup_clear_cpu_cap(bit); | |
1066 | else | |
1067 | return 0; | |
0f3fa48a | 1068 | |
ac72e788 AK |
1069 | return 1; |
1070 | } | |
1071 | __setup("clearcpuid=", setup_disablecpuid); | |
1072 | ||
d5494d4f | 1073 | #ifdef CONFIG_X86_64 |
9ff80942 | 1074 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
629f4f9d SA |
1075 | struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1, |
1076 | (unsigned long) debug_idt_table }; | |
d5494d4f | 1077 | |
947e76cd BG |
1078 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1079 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1080 | |
bdf977b3 TH |
1081 | /* |
1082 | * The following four percpu variables are hot. Align current_task to | |
1083 | * cacheline size such that all four fall in the same cacheline. | |
1084 | */ | |
1085 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1086 | &init_task; | |
1087 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1088 | |
9af45651 BG |
1089 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1090 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1091 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1092 | ||
bdf977b3 TH |
1093 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1094 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1095 | ||
56895530 | 1096 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1097 | |
7e16838d LT |
1098 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1099 | ||
0f3fa48a IM |
1100 | /* |
1101 | * Special IST stacks which the CPU switches to when it calls | |
1102 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1103 | * limit), all of them are 4K, except the debug stack which | |
1104 | * is 8K. | |
1105 | */ | |
1106 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1107 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1108 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1109 | }; | |
1110 | ||
92d65b23 | 1111 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1112 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1113 | |
d5494d4f YL |
1114 | /* May not be marked __init: used by software suspend */ |
1115 | void syscall_init(void) | |
1da177e4 | 1116 | { |
d5494d4f YL |
1117 | /* |
1118 | * LSTAR and STAR live in a bit strange symbiosis. | |
1119 | * They both write to the same internal register. STAR allows to | |
1120 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1121 | */ | |
1122 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1123 | wrmsrl(MSR_LSTAR, system_call); | |
1124 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1125 | |
d5494d4f YL |
1126 | #ifdef CONFIG_IA32_EMULATION |
1127 | syscall32_cpu_init(); | |
1128 | #endif | |
03ae5768 | 1129 | |
d5494d4f YL |
1130 | /* Flags to clear on syscall */ |
1131 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a PA |
1132 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
1133 | X86_EFLAGS_IOPL|X86_EFLAGS_AC); | |
1da177e4 | 1134 | } |
62111195 | 1135 | |
d5494d4f YL |
1136 | /* |
1137 | * Copies of the original ist values from the tss are only accessed during | |
1138 | * debugging, no special alignment required. | |
1139 | */ | |
1140 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1141 | ||
228bdaa9 | 1142 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1143 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1144 | |
1145 | int is_debug_stack(unsigned long addr) | |
1146 | { | |
42181186 SR |
1147 | return __get_cpu_var(debug_stack_usage) || |
1148 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1149 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1150 | } |
1151 | ||
629f4f9d | 1152 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1153 | |
228bdaa9 SR |
1154 | void debug_stack_set_zero(void) |
1155 | { | |
629f4f9d SA |
1156 | this_cpu_inc(debug_idt_ctr); |
1157 | load_current_idt(); | |
228bdaa9 SR |
1158 | } |
1159 | ||
1160 | void debug_stack_reset(void) | |
1161 | { | |
629f4f9d | 1162 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1163 | return; |
629f4f9d SA |
1164 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1165 | load_current_idt(); | |
228bdaa9 SR |
1166 | } |
1167 | ||
0f3fa48a | 1168 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1169 | |
bdf977b3 TH |
1170 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1171 | EXPORT_PER_CPU_SYMBOL(current_task); | |
27e74da9 | 1172 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1173 | |
60a5317f | 1174 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1175 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1176 | #endif |
d5494d4f | 1177 | |
0f3fa48a | 1178 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1179 | |
9766cdbc JSR |
1180 | /* |
1181 | * Clear all 6 debug registers: | |
1182 | */ | |
1183 | static void clear_all_debug_regs(void) | |
1184 | { | |
1185 | int i; | |
1186 | ||
1187 | for (i = 0; i < 8; i++) { | |
1188 | /* Ignore db4, db5 */ | |
1189 | if ((i == 4) || (i == 5)) | |
1190 | continue; | |
1191 | ||
1192 | set_debugreg(0, i); | |
1193 | } | |
1194 | } | |
c5413fbe | 1195 | |
0bb9fef9 JW |
1196 | #ifdef CONFIG_KGDB |
1197 | /* | |
1198 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1199 | * connection established. | |
1200 | */ | |
1201 | static void dbg_restore_debug_regs(void) | |
1202 | { | |
1203 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1204 | arch_kgdb_ops.correct_hw_break(); | |
1205 | } | |
1206 | #else /* ! CONFIG_KGDB */ | |
1207 | #define dbg_restore_debug_regs() | |
1208 | #endif /* ! CONFIG_KGDB */ | |
1209 | ||
d2cbcc49 RR |
1210 | /* |
1211 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1212 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1213 | * and IDT. We reload them nevertheless, this function acts as a | |
1214 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1215 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1216 | */ |
1ba76586 | 1217 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1218 | |
148f9bb8 | 1219 | void cpu_init(void) |
1ba76586 | 1220 | { |
0fe1e009 | 1221 | struct orig_ist *oist; |
1ba76586 | 1222 | struct task_struct *me; |
0f3fa48a IM |
1223 | struct tss_struct *t; |
1224 | unsigned long v; | |
1225 | int cpu; | |
1ba76586 YL |
1226 | int i; |
1227 | ||
e6ebf5de FY |
1228 | /* |
1229 | * Load microcode on this cpu if a valid microcode is available. | |
1230 | * This is early microcode loading procedure. | |
1231 | */ | |
1232 | load_ucode_ap(); | |
1233 | ||
0f3fa48a IM |
1234 | cpu = stack_smp_processor_id(); |
1235 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1236 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1237 | |
e7a22c1e | 1238 | #ifdef CONFIG_NUMA |
27fd185f | 1239 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1240 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1241 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1242 | #endif |
1ba76586 YL |
1243 | |
1244 | me = current; | |
1245 | ||
c2d1cec1 | 1246 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1247 | panic("CPU#%d already initialized!\n", cpu); |
1248 | ||
2eaad1fd | 1249 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1250 | |
1251 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1252 | ||
1253 | /* | |
1254 | * Initialize the per-CPU GDT with the boot GDT, | |
1255 | * and set up the GDT descriptor: | |
1256 | */ | |
1257 | ||
552be871 | 1258 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1259 | loadsegment(fs, 0); |
1260 | ||
cf910e83 | 1261 | load_current_idt(); |
1ba76586 YL |
1262 | |
1263 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1264 | syscall_init(); | |
1265 | ||
1266 | wrmsrl(MSR_FS_BASE, 0); | |
1267 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1268 | barrier(); | |
1269 | ||
4763ed4d | 1270 | x86_configure_nx(); |
27fd185f | 1271 | enable_x2apic(); |
1ba76586 YL |
1272 | |
1273 | /* | |
1274 | * set up and load the per-CPU TSS | |
1275 | */ | |
0fe1e009 | 1276 | if (!oist->ist[0]) { |
92d65b23 | 1277 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1278 | |
1ba76586 | 1279 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1280 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1281 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1282 | (unsigned long)estacks; |
228bdaa9 SR |
1283 | if (v == DEBUG_STACK-1) |
1284 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1285 | } |
1286 | } | |
1287 | ||
1288 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1289 | |
1ba76586 YL |
1290 | /* |
1291 | * <= is required because the CPU will access up to | |
1292 | * 8 bits beyond the end of the IO permission bitmap. | |
1293 | */ | |
1294 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1295 | t->io_bitmap[i] = ~0UL; | |
1296 | ||
1297 | atomic_inc(&init_mm.mm_count); | |
1298 | me->active_mm = &init_mm; | |
8c5dfd25 | 1299 | BUG_ON(me->mm); |
1ba76586 YL |
1300 | enter_lazy_tlb(&init_mm, me); |
1301 | ||
1302 | load_sp0(t, ¤t->thread); | |
1303 | set_tss_desc(cpu, t); | |
1304 | load_TR_desc(); | |
1305 | load_LDT(&init_mm.context); | |
1306 | ||
0bb9fef9 JW |
1307 | clear_all_debug_regs(); |
1308 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1309 | |
1310 | fpu_init(); | |
1311 | ||
1ba76586 YL |
1312 | if (is_uv_system()) |
1313 | uv_cpu_init(); | |
1314 | } | |
1315 | ||
1316 | #else | |
1317 | ||
148f9bb8 | 1318 | void cpu_init(void) |
9ee79a3d | 1319 | { |
d2cbcc49 RR |
1320 | int cpu = smp_processor_id(); |
1321 | struct task_struct *curr = current; | |
34048c9e | 1322 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1323 | struct thread_struct *thread = &curr->thread; |
62111195 | 1324 | |
e6ebf5de FY |
1325 | show_ucode_info_early(); |
1326 | ||
c2d1cec1 | 1327 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1328 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1329 | for (;;) |
1330 | local_irq_enable(); | |
62111195 JF |
1331 | } |
1332 | ||
1333 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1334 | ||
1335 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1336 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1337 | |
cf910e83 | 1338 | load_current_idt(); |
552be871 | 1339 | switch_to_new_gdt(cpu); |
1da177e4 | 1340 | |
1da177e4 LT |
1341 | /* |
1342 | * Set up and load the per-CPU TSS and LDT | |
1343 | */ | |
1344 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1345 | curr->active_mm = &init_mm; |
8c5dfd25 | 1346 | BUG_ON(curr->mm); |
62111195 | 1347 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1348 | |
faca6227 | 1349 | load_sp0(t, thread); |
34048c9e | 1350 | set_tss_desc(cpu, t); |
1da177e4 LT |
1351 | load_TR_desc(); |
1352 | load_LDT(&init_mm.context); | |
1353 | ||
f9a196b8 TG |
1354 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1355 | ||
22c4e308 | 1356 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1357 | /* Set up doublefault TSS pointer in the GDT */ |
1358 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1359 | #endif |
1da177e4 | 1360 | |
9766cdbc | 1361 | clear_all_debug_regs(); |
0bb9fef9 | 1362 | dbg_restore_debug_regs(); |
1da177e4 | 1363 | |
0e49bf66 | 1364 | fpu_init(); |
1da177e4 | 1365 | } |
1ba76586 | 1366 | #endif |
5700f743 BP |
1367 | |
1368 | #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS | |
1369 | void warn_pre_alternatives(void) | |
1370 | { | |
1371 | WARN(1, "You're using static_cpu_has before alternatives have run!\n"); | |
1372 | } | |
1373 | EXPORT_SYMBOL_GPL(warn_pre_alternatives); | |
1374 | #endif | |
4a90a99c BP |
1375 | |
1376 | inline bool __static_cpu_has_safe(u16 bit) | |
1377 | { | |
1378 | return boot_cpu_has(bit); | |
1379 | } | |
1380 | EXPORT_SYMBOL_GPL(__static_cpu_has_safe); |