Commit | Line | Data |
---|---|---|
2458e53f KS |
1 | /* cpu_feature_enabled() cannot be used this early */ |
2 | #define USE_EARLY_PGTABLE_L5 | |
3 | ||
f0fc4aff | 4 | #include <linux/bootmem.h> |
9766cdbc | 5 | #include <linux/linkage.h> |
f0fc4aff | 6 | #include <linux/bitops.h> |
9766cdbc | 7 | #include <linux/kernel.h> |
186f4360 | 8 | #include <linux/export.h> |
9766cdbc JSR |
9 | #include <linux/percpu.h> |
10 | #include <linux/string.h> | |
ee098e1a | 11 | #include <linux/ctype.h> |
1da177e4 | 12 | #include <linux/delay.h> |
68e21be2 | 13 | #include <linux/sched/mm.h> |
e6017571 | 14 | #include <linux/sched/clock.h> |
9164bb4a | 15 | #include <linux/sched/task.h> |
9766cdbc | 16 | #include <linux/init.h> |
0f46efeb | 17 | #include <linux/kprobes.h> |
9766cdbc | 18 | #include <linux/kgdb.h> |
1da177e4 | 19 | #include <linux/smp.h> |
9766cdbc | 20 | #include <linux/io.h> |
b51ef52d | 21 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
22 | |
23 | #include <asm/stackprotector.h> | |
cdd6c482 | 24 | #include <asm/perf_event.h> |
1da177e4 | 25 | #include <asm/mmu_context.h> |
49d859d7 | 26 | #include <asm/archrandom.h> |
9766cdbc JSR |
27 | #include <asm/hypervisor.h> |
28 | #include <asm/processor.h> | |
1e02ce4c | 29 | #include <asm/tlbflush.h> |
f649e938 | 30 | #include <asm/debugreg.h> |
9766cdbc | 31 | #include <asm/sections.h> |
f40c3300 | 32 | #include <asm/vsyscall.h> |
8bdbd962 AC |
33 | #include <linux/topology.h> |
34 | #include <linux/cpumask.h> | |
9766cdbc | 35 | #include <asm/pgtable.h> |
60063497 | 36 | #include <linux/atomic.h> |
9766cdbc JSR |
37 | #include <asm/proto.h> |
38 | #include <asm/setup.h> | |
39 | #include <asm/apic.h> | |
40 | #include <asm/desc.h> | |
78f7f1e5 | 41 | #include <asm/fpu/internal.h> |
27b07da7 | 42 | #include <asm/mtrr.h> |
0274f955 | 43 | #include <asm/hwcap2.h> |
8bdbd962 | 44 | #include <linux/numa.h> |
9766cdbc | 45 | #include <asm/asm.h> |
0f6ff2bc | 46 | #include <asm/bugs.h> |
9766cdbc | 47 | #include <asm/cpu.h> |
a03a3e28 | 48 | #include <asm/mce.h> |
9766cdbc | 49 | #include <asm/msr.h> |
8d4a4300 | 50 | #include <asm/pat.h> |
d288e1cf FY |
51 | #include <asm/microcode.h> |
52 | #include <asm/microcode_intel.h> | |
fec9434a DW |
53 | #include <asm/intel-family.h> |
54 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
55 | |
56 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 57 | #include <asm/uv/uv.h> |
1da177e4 LT |
58 | #endif |
59 | ||
60 | #include "cpu.h" | |
61 | ||
0274f955 GA |
62 | u32 elf_hwcap2 __read_mostly; |
63 | ||
c2d1cec1 | 64 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 65 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
66 | cpumask_var_t cpu_callout_mask; |
67 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
68 | |
69 | /* representing cpus for which sibling maps can be computed */ | |
70 | cpumask_var_t cpu_sibling_setup_mask; | |
71 | ||
f8b64d08 BP |
72 | /* Number of siblings per CPU package */ |
73 | int smp_num_siblings = 1; | |
74 | EXPORT_SYMBOL(smp_num_siblings); | |
75 | ||
76 | /* Last level cache ID of each logical CPU */ | |
77 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
78 | ||
2f2f52ba | 79 | /* correctly size the local cpu masks */ |
4369f1fb | 80 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
81 | { |
82 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
83 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
84 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
85 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
86 | } | |
87 | ||
148f9bb8 | 88 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
89 | { |
90 | #ifdef CONFIG_X86_64 | |
27c13ece | 91 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
92 | #else |
93 | /* Not much we can do here... */ | |
94 | /* Check if at least it has cpuid */ | |
95 | if (c->cpuid_level == -1) { | |
96 | /* No cpuid. It must be an ancient CPU */ | |
97 | if (c->x86 == 4) | |
98 | strcpy(c->x86_model_id, "486"); | |
99 | else if (c->x86 == 3) | |
100 | strcpy(c->x86_model_id, "386"); | |
101 | } | |
102 | #endif | |
103 | } | |
104 | ||
148f9bb8 | 105 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
106 | .c_init = default_init, |
107 | .c_vendor = "Unknown", | |
108 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
109 | }; | |
110 | ||
148f9bb8 | 111 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 112 | |
06deef89 | 113 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 114 | #ifdef CONFIG_X86_64 |
06deef89 BG |
115 | /* |
116 | * We need valid kernel segments for data and code in long mode too | |
117 | * IRET will check the segment types kkeil 2000/10/28 | |
118 | * Also sysret mandates a special GDT layout | |
119 | * | |
9766cdbc | 120 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
121 | * Hopefully nobody expects them at a fixed place (Wine?) |
122 | */ | |
1e5de182 AM |
123 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
124 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
125 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
126 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
127 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
128 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 129 | #else |
1e5de182 AM |
130 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
131 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
132 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
133 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
134 | /* |
135 | * Segments used for calling PnP BIOS have byte granularity. | |
136 | * They code segments and data segments have fixed 64k limits, | |
137 | * the transfer segment sizes are set at run time. | |
138 | */ | |
6842ef0e | 139 | /* 32-bit code */ |
1e5de182 | 140 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 141 | /* 16-bit code */ |
1e5de182 | 142 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 143 | /* 16-bit data */ |
1e5de182 | 144 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 145 | /* 16-bit data */ |
1e5de182 | 146 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 147 | /* 16-bit data */ |
1e5de182 | 148 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
149 | /* |
150 | * The APM segments have byte granularity and their bases | |
151 | * are set at run time. All have 64k limits. | |
152 | */ | |
6842ef0e | 153 | /* 32-bit code */ |
1e5de182 | 154 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 155 | /* 16-bit code */ |
1e5de182 | 156 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 157 | /* data */ |
72c4d853 | 158 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 159 | |
1e5de182 AM |
160 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
161 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 162 | GDT_STACK_CANARY_INIT |
950ad7ff | 163 | #endif |
06deef89 | 164 | } }; |
7a61d35d | 165 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 166 | |
8c3641e9 | 167 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 168 | { |
8c3641e9 | 169 | /* require an exact match without trailing characters */ |
2cd3949f DH |
170 | if (strlen(s)) |
171 | return 0; | |
0c752a93 | 172 | |
8c3641e9 DH |
173 | /* do not emit a message if the feature is not present */ |
174 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
175 | return 1; | |
6bad06b7 | 176 | |
8c3641e9 DH |
177 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
178 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
179 | return 1; |
180 | } | |
8c3641e9 | 181 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 182 | |
0790c9aa | 183 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 184 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 185 | { |
c7ad5ad2 AL |
186 | /* nopcid doesn't accept parameters */ |
187 | if (s) | |
188 | return -EINVAL; | |
0790c9aa AL |
189 | |
190 | /* do not emit a message if the feature is not present */ | |
191 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 192 | return 0; |
0790c9aa AL |
193 | |
194 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
195 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 196 | return 0; |
0790c9aa | 197 | } |
c7ad5ad2 | 198 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
199 | #endif |
200 | ||
d12a72b8 AL |
201 | static int __init x86_noinvpcid_setup(char *s) |
202 | { | |
203 | /* noinvpcid doesn't accept parameters */ | |
204 | if (s) | |
205 | return -EINVAL; | |
206 | ||
207 | /* do not emit a message if the feature is not present */ | |
208 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
209 | return 0; | |
210 | ||
211 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
212 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
213 | return 0; | |
214 | } | |
215 | early_param("noinvpcid", x86_noinvpcid_setup); | |
216 | ||
ba51dced | 217 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
218 | static int cachesize_override = -1; |
219 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 220 | |
0a488a53 YL |
221 | static int __init cachesize_setup(char *str) |
222 | { | |
223 | get_option(&str, &cachesize_override); | |
224 | return 1; | |
225 | } | |
226 | __setup("cachesize=", cachesize_setup); | |
227 | ||
0a488a53 YL |
228 | static int __init x86_sep_setup(char *s) |
229 | { | |
230 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
231 | return 1; | |
232 | } | |
233 | __setup("nosep", x86_sep_setup); | |
234 | ||
235 | /* Standard macro to see if a specific flag is changeable */ | |
236 | static inline int flag_is_changeable_p(u32 flag) | |
237 | { | |
238 | u32 f1, f2; | |
239 | ||
94f6bac1 KH |
240 | /* |
241 | * Cyrix and IDT cpus allow disabling of CPUID | |
242 | * so the code below may return different results | |
243 | * when it is executed before and after enabling | |
244 | * the CPUID. Add "volatile" to not allow gcc to | |
245 | * optimize the subsequent calls to this function. | |
246 | */ | |
0f3fa48a IM |
247 | asm volatile ("pushfl \n\t" |
248 | "pushfl \n\t" | |
249 | "popl %0 \n\t" | |
250 | "movl %0, %1 \n\t" | |
251 | "xorl %2, %0 \n\t" | |
252 | "pushl %0 \n\t" | |
253 | "popfl \n\t" | |
254 | "pushfl \n\t" | |
255 | "popl %0 \n\t" | |
256 | "popfl \n\t" | |
257 | ||
94f6bac1 KH |
258 | : "=&r" (f1), "=&r" (f2) |
259 | : "ir" (flag)); | |
0a488a53 YL |
260 | |
261 | return ((f1^f2) & flag) != 0; | |
262 | } | |
263 | ||
264 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 265 | int have_cpuid_p(void) |
0a488a53 YL |
266 | { |
267 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
268 | } | |
269 | ||
148f9bb8 | 270 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 271 | { |
0f3fa48a IM |
272 | unsigned long lo, hi; |
273 | ||
274 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
275 | return; | |
276 | ||
277 | /* Disable processor serial number: */ | |
278 | ||
279 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
280 | lo |= 0x200000; | |
281 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
282 | ||
1b74dde7 | 283 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
284 | clear_cpu_cap(c, X86_FEATURE_PN); |
285 | ||
286 | /* Disabling the serial number may affect the cpuid level */ | |
287 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
288 | } |
289 | ||
290 | static int __init x86_serial_nr_setup(char *s) | |
291 | { | |
292 | disable_x86_serial_nr = 0; | |
293 | return 1; | |
294 | } | |
295 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 296 | #else |
102bbe3a YL |
297 | static inline int flag_is_changeable_p(u32 flag) |
298 | { | |
299 | return 1; | |
300 | } | |
102bbe3a YL |
301 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
302 | { | |
303 | } | |
ba51dced | 304 | #endif |
0a488a53 | 305 | |
de5397ad FY |
306 | static __init int setup_disable_smep(char *arg) |
307 | { | |
b2cc2a07 | 308 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
309 | /* Check for things that depend on SMEP being enabled: */ |
310 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
311 | return 1; |
312 | } | |
313 | __setup("nosmep", setup_disable_smep); | |
314 | ||
b2cc2a07 | 315 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 316 | { |
b2cc2a07 | 317 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 318 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
319 | } |
320 | ||
52b6179a PA |
321 | static __init int setup_disable_smap(char *arg) |
322 | { | |
b2cc2a07 | 323 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
324 | return 1; |
325 | } | |
326 | __setup("nosmap", setup_disable_smap); | |
327 | ||
b2cc2a07 PA |
328 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
329 | { | |
581b7f15 | 330 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
331 | |
332 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
333 | BUG_ON(eflags & X86_EFLAGS_AC); |
334 | ||
03bbd596 PA |
335 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
336 | #ifdef CONFIG_X86_SMAP | |
375074cc | 337 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 338 | #else |
375074cc | 339 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
340 | #endif |
341 | } | |
de5397ad FY |
342 | } |
343 | ||
aa35f896 RN |
344 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
345 | { | |
346 | /* Check the boot processor, plus build option for UMIP. */ | |
347 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
348 | goto out; | |
349 | ||
350 | /* Check the current processor's cpuid bits. */ | |
351 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
352 | goto out; | |
353 | ||
354 | cr4_set_bits(X86_CR4_UMIP); | |
355 | ||
770c7755 RN |
356 | pr_info("x86/cpu: Activated the Intel User Mode Instruction Prevention (UMIP) CPU feature\n"); |
357 | ||
aa35f896 RN |
358 | return; |
359 | ||
360 | out: | |
361 | /* | |
362 | * Make sure UMIP is disabled in case it was enabled in a | |
363 | * previous boot (e.g., via kexec). | |
364 | */ | |
365 | cr4_clear_bits(X86_CR4_UMIP); | |
366 | } | |
367 | ||
06976945 DH |
368 | /* |
369 | * Protection Keys are not available in 32-bit mode. | |
370 | */ | |
371 | static bool pku_disabled; | |
372 | ||
373 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
374 | { | |
e8df1a95 DH |
375 | /* check the boot processor, plus compile options for PKU: */ |
376 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
377 | return; | |
378 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
379 | if (!cpu_has(c, X86_FEATURE_PKU)) |
380 | return; | |
381 | if (pku_disabled) | |
382 | return; | |
383 | ||
384 | cr4_set_bits(X86_CR4_PKE); | |
385 | /* | |
386 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
387 | * cpuid bit to be set. We need to ensure that we | |
388 | * update that bit in this CPU's "cpu_info". | |
389 | */ | |
390 | get_cpu_cap(c); | |
391 | } | |
392 | ||
393 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
394 | static __init int setup_disable_pku(char *arg) | |
395 | { | |
396 | /* | |
397 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
398 | * runtime checks are against OSPKE so clearing the | |
399 | * bit does nothing. | |
400 | * | |
401 | * This way, we will see "pku" in cpuinfo, but not | |
402 | * "ospke", which is exactly what we want. It shows | |
403 | * that the CPU has PKU, but the OS has not enabled it. | |
404 | * This happens to be exactly how a system would look | |
405 | * if we disabled the config option. | |
406 | */ | |
407 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
408 | pku_disabled = true; | |
409 | return 1; | |
410 | } | |
411 | __setup("nopku", setup_disable_pku); | |
412 | #endif /* CONFIG_X86_64 */ | |
413 | ||
b38b0665 PA |
414 | /* |
415 | * Some CPU features depend on higher CPUID levels, which may not always | |
416 | * be available due to CPUID level capping or broken virtualization | |
417 | * software. Add those features to this table to auto-disable them. | |
418 | */ | |
419 | struct cpuid_dependent_feature { | |
420 | u32 feature; | |
421 | u32 level; | |
422 | }; | |
0f3fa48a | 423 | |
148f9bb8 | 424 | static const struct cpuid_dependent_feature |
b38b0665 PA |
425 | cpuid_dependent_features[] = { |
426 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
427 | { X86_FEATURE_DCA, 0x00000009 }, | |
428 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
429 | { 0, 0 } | |
430 | }; | |
431 | ||
148f9bb8 | 432 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
433 | { |
434 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 435 | |
b38b0665 | 436 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
437 | |
438 | if (!cpu_has(c, df->feature)) | |
439 | continue; | |
b38b0665 PA |
440 | /* |
441 | * Note: cpuid_level is set to -1 if unavailable, but | |
442 | * extended_extended_level is set to 0 if unavailable | |
443 | * and the legitimate extended levels are all negative | |
444 | * when signed; hence the weird messing around with | |
445 | * signs here... | |
446 | */ | |
0f3fa48a | 447 | if (!((s32)df->level < 0 ? |
f6db44df | 448 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
449 | (s32)df->level > (s32)c->cpuid_level)) |
450 | continue; | |
451 | ||
452 | clear_cpu_cap(c, df->feature); | |
453 | if (!warn) | |
454 | continue; | |
455 | ||
1b74dde7 CY |
456 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
457 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 458 | } |
f6db44df | 459 | } |
b38b0665 | 460 | |
102bbe3a YL |
461 | /* |
462 | * Naming convention should be: <Name> [(<Codename>)] | |
463 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
464 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
465 | * isn't used | |
102bbe3a YL |
466 | */ |
467 | ||
468 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 469 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 470 | { |
09dc68d9 JB |
471 | #ifdef CONFIG_X86_32 |
472 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
473 | |
474 | if (c->x86_model >= 16) | |
475 | return NULL; /* Range check */ | |
476 | ||
477 | if (!this_cpu) | |
478 | return NULL; | |
479 | ||
09dc68d9 | 480 | info = this_cpu->legacy_models; |
102bbe3a | 481 | |
09dc68d9 | 482 | while (info->family) { |
102bbe3a YL |
483 | if (info->family == c->x86) |
484 | return info->model_names[c->x86_model]; | |
485 | info++; | |
486 | } | |
09dc68d9 | 487 | #endif |
102bbe3a YL |
488 | return NULL; /* Not found */ |
489 | } | |
490 | ||
6cbd2171 TG |
491 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
492 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 493 | |
11e3a840 JF |
494 | void load_percpu_segment(int cpu) |
495 | { | |
496 | #ifdef CONFIG_X86_32 | |
497 | loadsegment(fs, __KERNEL_PERCPU); | |
498 | #else | |
45e876f7 | 499 | __loadsegment_simple(gs, 0); |
35060ed6 | 500 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
11e3a840 | 501 | #endif |
60a5317f | 502 | load_stack_canary_segment(); |
11e3a840 JF |
503 | } |
504 | ||
72f5e08d AL |
505 | #ifdef CONFIG_X86_32 |
506 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
507 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
508 | #endif | |
509 | ||
40e7f949 AL |
510 | #ifdef CONFIG_X86_64 |
511 | /* | |
512 | * Special IST stacks which the CPU switches to when it calls | |
513 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
514 | * limit), all of them are 4K, except the debug stack which | |
515 | * is 8K. | |
516 | */ | |
517 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
518 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
519 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
520 | }; | |
45fc8757 | 521 | #endif |
69218e47 | 522 | |
45fc8757 TG |
523 | /* Load the original GDT from the per-cpu structure */ |
524 | void load_direct_gdt(int cpu) | |
525 | { | |
526 | struct desc_ptr gdt_descr; | |
527 | ||
528 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
529 | gdt_descr.size = GDT_SIZE - 1; | |
530 | load_gdt(&gdt_descr); | |
531 | } | |
532 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
533 | ||
69218e47 TG |
534 | /* Load a fixmap remapping of the per-cpu GDT */ |
535 | void load_fixmap_gdt(int cpu) | |
536 | { | |
537 | struct desc_ptr gdt_descr; | |
538 | ||
539 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
540 | gdt_descr.size = GDT_SIZE - 1; | |
541 | load_gdt(&gdt_descr); | |
542 | } | |
45fc8757 | 543 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 544 | |
0f3fa48a IM |
545 | /* |
546 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
547 | * it's on the real one. | |
548 | */ | |
552be871 | 549 | void switch_to_new_gdt(int cpu) |
9d31d35b | 550 | { |
45fc8757 TG |
551 | /* Load the original GDT */ |
552 | load_direct_gdt(cpu); | |
2697fbd5 | 553 | /* Reload the per-cpu base */ |
11e3a840 | 554 | load_percpu_segment(cpu); |
9d31d35b YL |
555 | } |
556 | ||
148f9bb8 | 557 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 558 | |
148f9bb8 | 559 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
560 | { |
561 | unsigned int *v; | |
ee098e1a | 562 | char *p, *q, *s; |
1da177e4 | 563 | |
3da99c97 | 564 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 565 | return; |
1da177e4 | 566 | |
0f3fa48a | 567 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
568 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
569 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
570 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
571 | c->x86_model_id[48] = 0; | |
572 | ||
ee098e1a BP |
573 | /* Trim whitespace */ |
574 | p = q = s = &c->x86_model_id[0]; | |
575 | ||
576 | while (*p == ' ') | |
577 | p++; | |
578 | ||
579 | while (*p) { | |
580 | /* Note the last non-whitespace index */ | |
581 | if (!isspace(*p)) | |
582 | s = q; | |
583 | ||
584 | *q++ = *p++; | |
585 | } | |
586 | ||
587 | *(s + 1) = '\0'; | |
1da177e4 LT |
588 | } |
589 | ||
9305bd6c | 590 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
591 | { |
592 | unsigned int eax, ebx, ecx, edx; | |
593 | ||
9305bd6c | 594 | c->x86_max_cores = 1; |
2cc61be6 | 595 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 596 | return; |
2cc61be6 DW |
597 | |
598 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
599 | if (eax & 0x1f) | |
9305bd6c | 600 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
601 | } |
602 | ||
148f9bb8 | 603 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 604 | { |
9d31d35b | 605 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 606 | |
3da99c97 | 607 | n = c->extended_cpuid_level; |
1da177e4 LT |
608 | |
609 | if (n >= 0x80000005) { | |
9d31d35b | 610 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 611 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
612 | #ifdef CONFIG_X86_64 |
613 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
614 | c->x86_tlbsize = 0; | |
615 | #endif | |
1da177e4 LT |
616 | } |
617 | ||
618 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
619 | return; | |
620 | ||
0a488a53 | 621 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 622 | l2size = ecx >> 16; |
34048c9e | 623 | |
140fc727 YL |
624 | #ifdef CONFIG_X86_64 |
625 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
626 | #else | |
1da177e4 | 627 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
628 | if (this_cpu->legacy_cache_size) |
629 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
630 | |
631 | /* Allow user to override all this if necessary. */ | |
632 | if (cachesize_override != -1) | |
633 | l2size = cachesize_override; | |
634 | ||
34048c9e | 635 | if (l2size == 0) |
1da177e4 | 636 | return; /* Again, no L2 cache is possible */ |
140fc727 | 637 | #endif |
1da177e4 LT |
638 | |
639 | c->x86_cache_size = l2size; | |
1da177e4 LT |
640 | } |
641 | ||
e0ba94f1 AS |
642 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
643 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
644 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
645 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
646 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
647 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 648 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 649 | |
f94fe119 | 650 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
651 | { |
652 | if (this_cpu->c_detect_tlb) | |
653 | this_cpu->c_detect_tlb(c); | |
654 | ||
f94fe119 | 655 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 656 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
657 | tlb_lli_4m[ENTRIES]); |
658 | ||
659 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
660 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
661 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
662 | } |
663 | ||
545401f4 | 664 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 665 | { |
c8e56d20 | 666 | #ifdef CONFIG_SMP |
0a488a53 | 667 | u32 eax, ebx, ecx, edx; |
1da177e4 | 668 | |
0a488a53 | 669 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 670 | return -1; |
1da177e4 | 671 | |
0a488a53 | 672 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 673 | return -1; |
1da177e4 | 674 | |
1cd78776 | 675 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 676 | return -1; |
1da177e4 | 677 | |
0a488a53 | 678 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 679 | |
9d31d35b | 680 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 681 | if (smp_num_siblings == 1) |
1b74dde7 | 682 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
683 | #endif |
684 | return 0; | |
685 | } | |
9d31d35b | 686 | |
545401f4 TG |
687 | void detect_ht(struct cpuinfo_x86 *c) |
688 | { | |
689 | #ifdef CONFIG_SMP | |
690 | int index_msb, core_bits; | |
55e6d279 | 691 | |
545401f4 | 692 | if (detect_ht_early(c) < 0) |
55e6d279 | 693 | return; |
9d31d35b | 694 | |
0f3fa48a IM |
695 | index_msb = get_count_order(smp_num_siblings); |
696 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 697 | |
0f3fa48a | 698 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 699 | |
0f3fa48a | 700 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 701 | |
0f3fa48a | 702 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 703 | |
0f3fa48a IM |
704 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
705 | ((1 << core_bits) - 1); | |
9d31d35b | 706 | #endif |
97e4db7c | 707 | } |
1da177e4 | 708 | |
148f9bb8 | 709 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
710 | { |
711 | char *v = c->x86_vendor_id; | |
0f3fa48a | 712 | int i; |
1da177e4 LT |
713 | |
714 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
715 | if (!cpu_devs[i]) |
716 | break; | |
717 | ||
718 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
719 | (cpu_devs[i]->c_ident[1] && | |
720 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 721 | |
10a434fc YL |
722 | this_cpu = cpu_devs[i]; |
723 | c->x86_vendor = this_cpu->c_x86_vendor; | |
724 | return; | |
1da177e4 LT |
725 | } |
726 | } | |
10a434fc | 727 | |
1b74dde7 CY |
728 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
729 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 730 | |
fe38d855 CE |
731 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
732 | this_cpu = &default_cpu; | |
1da177e4 LT |
733 | } |
734 | ||
148f9bb8 | 735 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 736 | { |
1da177e4 | 737 | /* Get vendor name */ |
4a148513 HH |
738 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
739 | (unsigned int *)&c->x86_vendor_id[0], | |
740 | (unsigned int *)&c->x86_vendor_id[8], | |
741 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 742 | |
1da177e4 | 743 | c->x86 = 4; |
9d31d35b | 744 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
745 | if (c->cpuid_level >= 0x00000001) { |
746 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 747 | |
1da177e4 | 748 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
749 | c->x86 = x86_family(tfms); |
750 | c->x86_model = x86_model(tfms); | |
b399151c | 751 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 752 | |
d4387bd3 | 753 | if (cap0 & (1<<19)) { |
d4387bd3 | 754 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 755 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 756 | } |
1da177e4 | 757 | } |
1da177e4 | 758 | } |
3da99c97 | 759 | |
8bf1ebca AL |
760 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
761 | { | |
762 | int i; | |
763 | ||
6cbd2171 | 764 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
765 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
766 | c->x86_capability[i] |= cpu_caps_set[i]; | |
767 | } | |
768 | } | |
769 | ||
7fcae111 DW |
770 | static void init_speculation_control(struct cpuinfo_x86 *c) |
771 | { | |
772 | /* | |
773 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
774 | * and they also have a different bit for STIBP support. Also, | |
775 | * a hypervisor might have set the individual AMD bits even on | |
776 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
777 | */ |
778 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
779 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
780 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 781 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 782 | } |
e7c587da | 783 | |
7fcae111 DW |
784 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
785 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 786 | |
bc226f07 TL |
787 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
788 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
789 | set_cpu_cap(c, X86_FEATURE_SSBD); |
790 | ||
7eb8956a | 791 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 792 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
793 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
794 | } | |
e7c587da BP |
795 | |
796 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
797 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
798 | ||
7eb8956a | 799 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 800 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
801 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
802 | } | |
6ac2f49e KRW |
803 | |
804 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
805 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
806 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
807 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
808 | } | |
7fcae111 DW |
809 | } |
810 | ||
148f9bb8 | 811 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 812 | { |
39c06df4 | 813 | u32 eax, ebx, ecx, edx; |
093af8d7 | 814 | |
3da99c97 YL |
815 | /* Intel-defined flags: level 0x00000001 */ |
816 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 817 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 818 | |
39c06df4 BP |
819 | c->x86_capability[CPUID_1_ECX] = ecx; |
820 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 821 | } |
093af8d7 | 822 | |
3df8d920 AL |
823 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
824 | if (c->cpuid_level >= 0x00000006) | |
825 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
826 | ||
bdc802dc PA |
827 | /* Additional Intel-defined flags: level 0x00000007 */ |
828 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 829 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 830 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 831 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 832 | c->x86_capability[CPUID_7_EDX] = edx; |
bdc802dc PA |
833 | } |
834 | ||
6229ad27 FY |
835 | /* Extended state features: level 0x0000000d */ |
836 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
837 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
838 | ||
39c06df4 | 839 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
840 | } |
841 | ||
cbc82b17 PWJ |
842 | /* Additional Intel-defined flags: level 0x0000000F */ |
843 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
844 | |
845 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
846 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
847 | c->x86_capability[CPUID_F_0_EDX] = edx; |
848 | ||
cbc82b17 PWJ |
849 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
850 | /* will be overridden if occupancy monitoring exists */ | |
851 | c->x86_cache_max_rmid = ebx; | |
852 | ||
853 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
854 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
855 | c->x86_capability[CPUID_F_1_EDX] = edx; |
856 | ||
33c3cc7a VS |
857 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
858 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
859 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
860 | c->x86_cache_max_rmid = ecx; |
861 | c->x86_cache_occ_scale = ebx; | |
862 | } | |
863 | } else { | |
864 | c->x86_cache_max_rmid = -1; | |
865 | c->x86_cache_occ_scale = -1; | |
866 | } | |
867 | } | |
868 | ||
3da99c97 | 869 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
870 | eax = cpuid_eax(0x80000000); |
871 | c->extended_cpuid_level = eax; | |
872 | ||
873 | if ((eax & 0xffff0000) == 0x80000000) { | |
874 | if (eax >= 0x80000001) { | |
875 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 876 | |
39c06df4 BP |
877 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
878 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 879 | } |
093af8d7 | 880 | } |
093af8d7 | 881 | |
71faad43 YG |
882 | if (c->extended_cpuid_level >= 0x80000007) { |
883 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
884 | ||
885 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
886 | c->x86_power = edx; | |
887 | } | |
888 | ||
c65732e4 TG |
889 | if (c->extended_cpuid_level >= 0x80000008) { |
890 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
891 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
892 | } | |
893 | ||
2ccd71f1 | 894 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 895 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 896 | |
1dedefd1 | 897 | init_scattered_cpuid_features(c); |
7fcae111 | 898 | init_speculation_control(c); |
60d34501 AL |
899 | |
900 | /* | |
901 | * Clear/Set all flags overridden by options, after probe. | |
902 | * This needs to happen each time we re-probe, which may happen | |
903 | * several times during CPU initialization. | |
904 | */ | |
905 | apply_forced_caps(c); | |
093af8d7 | 906 | } |
1da177e4 | 907 | |
405c018a | 908 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
909 | { |
910 | u32 eax, ebx, ecx, edx; | |
911 | ||
912 | if (c->extended_cpuid_level >= 0x80000008) { | |
913 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
914 | ||
915 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
916 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
917 | } |
918 | #ifdef CONFIG_X86_32 | |
919 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
920 | c->x86_phys_bits = 36; | |
921 | #endif | |
cc51e542 | 922 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
923 | } |
924 | ||
148f9bb8 | 925 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
926 | { |
927 | #ifdef CONFIG_X86_32 | |
928 | int i; | |
929 | ||
930 | /* | |
931 | * First of all, decide if this is a 486 or higher | |
932 | * It's a 486 if we can modify the AC flag | |
933 | */ | |
934 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
935 | c->x86 = 4; | |
936 | else | |
937 | c->x86 = 3; | |
938 | ||
939 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
940 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
941 | c->x86_vendor_id[0] = 0; | |
942 | cpu_devs[i]->c_identify(c); | |
943 | if (c->x86_vendor_id[0]) { | |
944 | get_cpu_vendor(c); | |
945 | break; | |
946 | } | |
947 | } | |
948 | #endif | |
949 | } | |
950 | ||
4bf5d56d | 951 | static const __initconst struct x86_cpu_id cpu_no_speculation[] = { |
fec9434a DW |
952 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CEDARVIEW, X86_FEATURE_ANY }, |
953 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_CLOVERVIEW, X86_FEATURE_ANY }, | |
954 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_LINCROFT, X86_FEATURE_ANY }, | |
955 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PENWELL, X86_FEATURE_ANY }, | |
956 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_PINEVIEW, X86_FEATURE_ANY }, | |
957 | { X86_VENDOR_CENTAUR, 5 }, | |
958 | { X86_VENDOR_INTEL, 5 }, | |
959 | { X86_VENDOR_NSC, 5 }, | |
960 | { X86_VENDOR_ANY, 4 }, | |
961 | {} | |
962 | }; | |
963 | ||
4bf5d56d | 964 | static const __initconst struct x86_cpu_id cpu_no_meltdown[] = { |
fec9434a DW |
965 | { X86_VENDOR_AMD }, |
966 | {} | |
967 | }; | |
968 | ||
8ecc4979 | 969 | /* Only list CPUs which speculate but are non susceptible to SSB */ |
c456442c | 970 | static const __initconst struct x86_cpu_id cpu_no_spec_store_bypass[] = { |
c456442c KRW |
971 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, |
972 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
973 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, | |
974 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, | |
975 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_CORE_YONAH }, | |
976 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, | |
977 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, | |
764f3c21 KRW |
978 | { X86_VENDOR_AMD, 0x12, }, |
979 | { X86_VENDOR_AMD, 0x11, }, | |
980 | { X86_VENDOR_AMD, 0x10, }, | |
981 | { X86_VENDOR_AMD, 0xf, }, | |
c456442c KRW |
982 | {} |
983 | }; | |
984 | ||
17dbca11 AK |
985 | static const __initconst struct x86_cpu_id cpu_no_l1tf[] = { |
986 | /* in addition to cpu_no_speculation */ | |
987 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 }, | |
988 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT2 }, | |
989 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT }, | |
990 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MERRIFIELD }, | |
991 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_MOOREFIELD }, | |
992 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT }, | |
993 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON }, | |
994 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GEMINI_LAKE }, | |
995 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNL }, | |
996 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_XEON_PHI_KNM }, | |
997 | {} | |
998 | }; | |
999 | ||
4a28bfe3 | 1000 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) |
fec9434a DW |
1001 | { |
1002 | u64 ia32_cap = 0; | |
1003 | ||
8ecc4979 DB |
1004 | if (x86_match_cpu(cpu_no_speculation)) |
1005 | return; | |
1006 | ||
1007 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1008 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
1009 | ||
77243971 KRW |
1010 | if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) |
1011 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1012 | ||
1013 | if (!x86_match_cpu(cpu_no_spec_store_bypass) && | |
24809860 KRW |
1014 | !(ia32_cap & ARCH_CAP_SSB_NO) && |
1015 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) | |
c456442c KRW |
1016 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1017 | ||
706d5168 SP |
1018 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1019 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1020 | ||
fec9434a | 1021 | if (x86_match_cpu(cpu_no_meltdown)) |
4a28bfe3 | 1022 | return; |
fec9434a | 1023 | |
fec9434a DW |
1024 | /* Rogue Data Cache Load? No! */ |
1025 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1026 | return; |
fec9434a | 1027 | |
4a28bfe3 | 1028 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 AK |
1029 | |
1030 | if (x86_match_cpu(cpu_no_l1tf)) | |
1031 | return; | |
1032 | ||
1033 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1034 | } |
1035 | ||
8990cac6 PT |
1036 | /* |
1037 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1038 | * unfortunately, that's not true in practice because of early VIA | |
1039 | * chips and (more importantly) broken virtualizers that are not easy | |
1040 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1041 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1042 | * unless we can find a reliable way to detect all the broken cases. | |
1043 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1044 | */ | |
9b3661cd | 1045 | static void detect_nopl(void) |
8990cac6 PT |
1046 | { |
1047 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1048 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1049 | #else |
9b3661cd | 1050 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1051 | #endif |
1052 | } | |
1053 | ||
34048c9e PC |
1054 | /* |
1055 | * Do minimum CPU detection early. | |
1056 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1057 | * cache alignment. | |
1058 | * The others are not touched to avoid unwanted side effects. | |
1059 | * | |
a1652bb8 JD |
1060 | * WARNING: this function is only called on the boot CPU. Don't add code |
1061 | * here that is supposed to run on all CPUs. | |
34048c9e | 1062 | */ |
3da99c97 | 1063 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1064 | { |
6627d242 YL |
1065 | #ifdef CONFIG_X86_64 |
1066 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1067 | c->x86_phys_bits = 36; |
1068 | c->x86_virt_bits = 48; | |
6627d242 | 1069 | #else |
d4387bd3 | 1070 | c->x86_clflush_size = 32; |
13c6c532 JB |
1071 | c->x86_phys_bits = 32; |
1072 | c->x86_virt_bits = 32; | |
6627d242 | 1073 | #endif |
0a488a53 | 1074 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1075 | |
3da99c97 | 1076 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 1077 | c->extended_cpuid_level = 0; |
d7cd5611 | 1078 | |
aef93c8b | 1079 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1080 | if (have_cpuid_p()) { |
1081 | cpu_detect(c); | |
1082 | get_cpu_vendor(c); | |
1083 | get_cpu_cap(c); | |
d94a155c | 1084 | get_cpu_address_sizes(c); |
78d1b296 | 1085 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1086 | |
05fb3c19 AL |
1087 | if (this_cpu->c_early_init) |
1088 | this_cpu->c_early_init(c); | |
12cf105c | 1089 | |
05fb3c19 AL |
1090 | c->cpu_index = 0; |
1091 | filter_cpuid_features(c, false); | |
093af8d7 | 1092 | |
05fb3c19 AL |
1093 | if (this_cpu->c_bsp_init) |
1094 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
1095 | } else { |
1096 | identify_cpu_without_cpuid(c); | |
1097 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 1098 | } |
c3b83598 BP |
1099 | |
1100 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1101 | |
4a28bfe3 | 1102 | cpu_set_bug_bits(c); |
99c6fa25 | 1103 | |
db52ef74 | 1104 | fpu__init_system(c); |
b8b7abae AL |
1105 | |
1106 | #ifdef CONFIG_X86_32 | |
1107 | /* | |
1108 | * Regardless of whether PCID is enumerated, the SDM says | |
1109 | * that it can't be enabled in 32-bit mode. | |
1110 | */ | |
1111 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1112 | #endif | |
372fddf7 KS |
1113 | |
1114 | /* | |
1115 | * Later in the boot process pgtable_l5_enabled() relies on | |
1116 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1117 | * enabled by this point we need to clear the feature bit to avoid | |
1118 | * false-positives at the later stage. | |
1119 | * | |
1120 | * pgtable_l5_enabled() can be false here for several reasons: | |
1121 | * - 5-level paging is disabled compile-time; | |
1122 | * - it's 32-bit kernel; | |
1123 | * - machine doesn't support 5-level paging; | |
1124 | * - user specified 'no5lvl' in kernel command line. | |
1125 | */ | |
1126 | if (!pgtable_l5_enabled()) | |
1127 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1128 | |
9b3661cd | 1129 | detect_nopl(); |
d7cd5611 RR |
1130 | } |
1131 | ||
9d31d35b YL |
1132 | void __init early_cpu_init(void) |
1133 | { | |
02dde8b4 | 1134 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1135 | int count = 0; |
1136 | ||
ac23f253 | 1137 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1138 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1139 | #endif |
1140 | ||
10a434fc | 1141 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1142 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1143 | |
10a434fc YL |
1144 | if (count >= X86_VENDOR_NUM) |
1145 | break; | |
1146 | cpu_devs[count] = cpudev; | |
1147 | count++; | |
1148 | ||
ac23f253 | 1149 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1150 | { |
1151 | unsigned int j; | |
1152 | ||
1153 | for (j = 0; j < 2; j++) { | |
1154 | if (!cpudev->c_ident[j]) | |
1155 | continue; | |
1b74dde7 | 1156 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1157 | cpudev->c_ident[j]); |
1158 | } | |
10a434fc | 1159 | } |
0388423d | 1160 | #endif |
10a434fc | 1161 | } |
9d31d35b | 1162 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1163 | } |
093af8d7 | 1164 | |
7a5d6704 AL |
1165 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1166 | { | |
1167 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1168 | /* |
7a5d6704 AL |
1169 | * Empirically, writing zero to a segment selector on AMD does |
1170 | * not clear the base, whereas writing zero to a segment | |
1171 | * selector on Intel does clear the base. Intel's behavior | |
1172 | * allows slightly faster context switches in the common case | |
1173 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1174 | * |
7a5d6704 AL |
1175 | * Since neither vendor documents this anywhere that I can see, |
1176 | * detect it directly instead of hardcoding the choice by | |
1177 | * vendor. | |
1178 | * | |
1179 | * I've designated AMD's behavior as the "bug" because it's | |
1180 | * counterintuitive and less friendly. | |
58a5aac5 | 1181 | */ |
7a5d6704 AL |
1182 | |
1183 | unsigned long old_base, tmp; | |
1184 | rdmsrl(MSR_FS_BASE, old_base); | |
1185 | wrmsrl(MSR_FS_BASE, 1); | |
1186 | loadsegment(fs, 0); | |
1187 | rdmsrl(MSR_FS_BASE, tmp); | |
1188 | if (tmp != 0) | |
1189 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1190 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1191 | #endif |
d7cd5611 RR |
1192 | } |
1193 | ||
148f9bb8 | 1194 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1195 | { |
aef93c8b | 1196 | c->extended_cpuid_level = 0; |
1da177e4 | 1197 | |
3da99c97 | 1198 | if (!have_cpuid_p()) |
aef93c8b | 1199 | identify_cpu_without_cpuid(c); |
1d67953f | 1200 | |
aef93c8b | 1201 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1202 | if (!have_cpuid_p()) |
aef93c8b | 1203 | return; |
1da177e4 | 1204 | |
3da99c97 | 1205 | cpu_detect(c); |
1da177e4 | 1206 | |
3da99c97 | 1207 | get_cpu_vendor(c); |
1da177e4 | 1208 | |
3da99c97 | 1209 | get_cpu_cap(c); |
1da177e4 | 1210 | |
d94a155c KS |
1211 | get_cpu_address_sizes(c); |
1212 | ||
3da99c97 YL |
1213 | if (c->cpuid_level >= 0x00000001) { |
1214 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1215 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1216 | # ifdef CONFIG_SMP |
cb8cc442 | 1217 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1218 | # else |
3da99c97 | 1219 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1220 | # endif |
1221 | #endif | |
b89d3b3e | 1222 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1223 | } |
1da177e4 | 1224 | |
1b05d60d | 1225 | get_model_name(c); /* Default name */ |
1da177e4 | 1226 | |
7a5d6704 | 1227 | detect_null_seg_behavior(c); |
0230bb03 AL |
1228 | |
1229 | /* | |
1230 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1231 | * systems that run Linux at CPL > 0 may or may not have the | |
1232 | * issue, but, even if they have the issue, there's absolutely | |
1233 | * nothing we can do about it because we can't use the real IRET | |
1234 | * instruction. | |
1235 | * | |
1236 | * NB: For the time being, only 32-bit kernels support | |
1237 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1238 | * whether to apply espfix using paravirt hooks. If any | |
1239 | * non-paravirt system ever shows up that does *not* have the | |
1240 | * ESPFIX issue, we can change this. | |
1241 | */ | |
1242 | #ifdef CONFIG_X86_32 | |
1243 | # ifdef CONFIG_PARAVIRT | |
1244 | do { | |
1245 | extern void native_iret(void); | |
1246 | if (pv_cpu_ops.iret == native_iret) | |
1247 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1248 | } while (0); | |
1249 | # else | |
1250 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1251 | # endif | |
1252 | #endif | |
1da177e4 | 1253 | } |
1da177e4 | 1254 | |
cbc82b17 PWJ |
1255 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1256 | { | |
1257 | /* | |
1258 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1259 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1260 | * in case CQM bits really aren't there in this CPU. | |
1261 | */ | |
1262 | if (c != &boot_cpu_data) { | |
1263 | boot_cpu_data.x86_cache_max_rmid = | |
1264 | min(boot_cpu_data.x86_cache_max_rmid, | |
1265 | c->x86_cache_max_rmid); | |
1266 | } | |
1267 | } | |
1268 | ||
d49597fd | 1269 | /* |
9d85eb91 TG |
1270 | * Validate that ACPI/mptables have the same information about the |
1271 | * effective APIC id and update the package map. | |
d49597fd | 1272 | */ |
9d85eb91 | 1273 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1274 | { |
1275 | #ifdef CONFIG_SMP | |
9d85eb91 | 1276 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1277 | |
1278 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1279 | |
9d85eb91 TG |
1280 | if (apicid != c->apicid) { |
1281 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1282 | cpu, apicid, c->initial_apicid); |
d49597fd | 1283 | } |
9d85eb91 | 1284 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1285 | #else |
1286 | c->logical_proc_id = 0; | |
1287 | #endif | |
1288 | } | |
1289 | ||
1da177e4 LT |
1290 | /* |
1291 | * This does the hard work of actually picking apart the CPU stuff... | |
1292 | */ | |
148f9bb8 | 1293 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1294 | { |
1295 | int i; | |
1296 | ||
1297 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1298 | c->x86_cache_size = 0; |
1da177e4 | 1299 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1300 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1301 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1302 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1303 | c->x86_max_cores = 1; |
102bbe3a | 1304 | c->x86_coreid_bits = 0; |
79a8b9aa | 1305 | c->cu_id = 0xff; |
11fdd252 | 1306 | #ifdef CONFIG_X86_64 |
102bbe3a | 1307 | c->x86_clflush_size = 64; |
13c6c532 JB |
1308 | c->x86_phys_bits = 36; |
1309 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1310 | #else |
1311 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1312 | c->x86_clflush_size = 32; |
13c6c532 JB |
1313 | c->x86_phys_bits = 32; |
1314 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1315 | #endif |
1316 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1317 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1318 | ||
1da177e4 LT |
1319 | generic_identify(c); |
1320 | ||
3898534d | 1321 | if (this_cpu->c_identify) |
1da177e4 LT |
1322 | this_cpu->c_identify(c); |
1323 | ||
6a6256f9 | 1324 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1325 | apply_forced_caps(c); |
2759c328 | 1326 | |
102bbe3a | 1327 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1328 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1329 | #endif |
1330 | ||
1da177e4 LT |
1331 | /* |
1332 | * Vendor-specific initialization. In this section we | |
1333 | * canonicalize the feature flags, meaning if there are | |
1334 | * features a certain CPU supports which CPUID doesn't | |
1335 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1336 | * we handle them here. | |
1337 | * | |
1338 | * At the end of this section, c->x86_capability better | |
1339 | * indicate the features this CPU genuinely supports! | |
1340 | */ | |
1341 | if (this_cpu->c_init) | |
1342 | this_cpu->c_init(c); | |
1343 | ||
1344 | /* Disable the PN if appropriate */ | |
1345 | squash_the_stupid_serial_number(c); | |
1346 | ||
aa35f896 | 1347 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1348 | setup_smep(c); |
1349 | setup_smap(c); | |
aa35f896 | 1350 | setup_umip(c); |
b2cc2a07 | 1351 | |
1da177e4 | 1352 | /* |
0f3fa48a IM |
1353 | * The vendor-specific functions might have changed features. |
1354 | * Now we do "generic changes." | |
1da177e4 LT |
1355 | */ |
1356 | ||
b38b0665 PA |
1357 | /* Filter out anything that depends on CPUID levels we don't have */ |
1358 | filter_cpuid_features(c, true); | |
1359 | ||
1da177e4 | 1360 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1361 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1362 | const char *p; |
1da177e4 | 1363 | p = table_lookup_model(c); |
34048c9e | 1364 | if (p) |
1da177e4 LT |
1365 | strcpy(c->x86_model_id, p); |
1366 | else | |
1367 | /* Last resort... */ | |
1368 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1369 | c->x86, c->x86_model); |
1da177e4 LT |
1370 | } |
1371 | ||
102bbe3a YL |
1372 | #ifdef CONFIG_X86_64 |
1373 | detect_ht(c); | |
1374 | #endif | |
1375 | ||
49d859d7 | 1376 | x86_init_rdrand(c); |
cbc82b17 | 1377 | x86_init_cache_qos(c); |
06976945 | 1378 | setup_pku(c); |
3e0c3737 YL |
1379 | |
1380 | /* | |
6a6256f9 | 1381 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1382 | * before following smp all cpus cap AND. |
1383 | */ | |
8bf1ebca | 1384 | apply_forced_caps(c); |
3e0c3737 | 1385 | |
1da177e4 LT |
1386 | /* |
1387 | * On SMP, boot_cpu_data holds the common feature set between | |
1388 | * all CPUs; so make sure that we indicate which features are | |
1389 | * common between the CPUs. The first time this routine gets | |
1390 | * executed, c == &boot_cpu_data. | |
1391 | */ | |
34048c9e | 1392 | if (c != &boot_cpu_data) { |
1da177e4 | 1393 | /* AND the already accumulated flags with these */ |
9d31d35b | 1394 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1395 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1396 | |
1397 | /* OR, i.e. replicate the bug flags */ | |
1398 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1399 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1400 | } |
1401 | ||
1402 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1403 | mcheck_cpu_init(c); |
30d432df AK |
1404 | |
1405 | select_idle_routine(c); | |
102bbe3a | 1406 | |
de2d9445 | 1407 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1408 | numa_add_cpu(smp_processor_id()); |
1409 | #endif | |
a6c4e076 | 1410 | } |
31ab269a | 1411 | |
8b6c0ab1 IM |
1412 | /* |
1413 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1414 | * on 32-bit kernels: | |
1415 | */ | |
cfda7bb9 AL |
1416 | #ifdef CONFIG_X86_32 |
1417 | void enable_sep_cpu(void) | |
1418 | { | |
8b6c0ab1 IM |
1419 | struct tss_struct *tss; |
1420 | int cpu; | |
cfda7bb9 | 1421 | |
b3edfda4 BP |
1422 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1423 | return; | |
1424 | ||
8b6c0ab1 | 1425 | cpu = get_cpu(); |
c482feef | 1426 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1427 | |
8b6c0ab1 | 1428 | /* |
cf9328cc AL |
1429 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1430 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1431 | */ |
cfda7bb9 AL |
1432 | |
1433 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1434 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1435 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1436 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1437 | |
cfda7bb9 AL |
1438 | put_cpu(); |
1439 | } | |
e04d645f GC |
1440 | #endif |
1441 | ||
a6c4e076 JF |
1442 | void __init identify_boot_cpu(void) |
1443 | { | |
1444 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1445 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1446 | sysenter_setup(); |
6fe940d6 | 1447 | enable_sep_cpu(); |
102bbe3a | 1448 | #endif |
5b556332 | 1449 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1450 | } |
3b520b23 | 1451 | |
148f9bb8 | 1452 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1453 | { |
1454 | BUG_ON(c == &boot_cpu_data); | |
1455 | identify_cpu(c); | |
102bbe3a | 1456 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1457 | enable_sep_cpu(); |
102bbe3a | 1458 | #endif |
a6c4e076 | 1459 | mtrr_ap_init(); |
9d85eb91 | 1460 | validate_apic_and_package_id(c); |
77243971 | 1461 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1462 | } |
1463 | ||
191679fd AK |
1464 | static __init int setup_noclflush(char *arg) |
1465 | { | |
840d2830 | 1466 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1467 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1468 | return 1; |
1469 | } | |
1470 | __setup("noclflush", setup_noclflush); | |
1471 | ||
148f9bb8 | 1472 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1473 | { |
02dde8b4 | 1474 | const char *vendor = NULL; |
1da177e4 | 1475 | |
0f3fa48a | 1476 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1477 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1478 | } else { |
1479 | if (c->cpuid_level >= 0) | |
1480 | vendor = c->x86_vendor_id; | |
1481 | } | |
1da177e4 | 1482 | |
bd32a8cf | 1483 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1484 | pr_cont("%s ", vendor); |
1da177e4 | 1485 | |
9d31d35b | 1486 | if (c->x86_model_id[0]) |
1b74dde7 | 1487 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1488 | else |
1b74dde7 | 1489 | pr_cont("%d86", c->x86); |
1da177e4 | 1490 | |
1b74dde7 | 1491 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1492 | |
b399151c JZ |
1493 | if (c->x86_stepping || c->cpuid_level >= 0) |
1494 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1495 | else |
1b74dde7 | 1496 | pr_cont(")\n"); |
1da177e4 LT |
1497 | } |
1498 | ||
0c2a3913 AK |
1499 | /* |
1500 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1501 | * But we need to keep a dummy __setup around otherwise it would | |
1502 | * show up as an environment variable for init. | |
1503 | */ | |
1504 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1505 | { |
ac72e788 AK |
1506 | return 1; |
1507 | } | |
0c2a3913 | 1508 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1509 | |
d5494d4f | 1510 | #ifdef CONFIG_X86_64 |
947e76cd | 1511 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1512 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
35060ed6 | 1513 | EXPORT_PER_CPU_SYMBOL_GPL(irq_stack_union); |
0f3fa48a | 1514 | |
bdf977b3 | 1515 | /* |
a7fcf28d AL |
1516 | * The following percpu variables are hot. Align current_task to |
1517 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1518 | */ |
1519 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1520 | &init_task; | |
1521 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1522 | |
bdf977b3 | 1523 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1524 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1525 | |
277d5b40 | 1526 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1527 | |
c2daa3be PZ |
1528 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1529 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1530 | ||
d5494d4f YL |
1531 | /* May not be marked __init: used by software suspend */ |
1532 | void syscall_init(void) | |
1da177e4 | 1533 | { |
3386bc8a AL |
1534 | extern char _entry_trampoline[]; |
1535 | extern char entry_SYSCALL_64_trampoline[]; | |
1536 | ||
72f5e08d | 1537 | int cpu = smp_processor_id(); |
3386bc8a AL |
1538 | unsigned long SYSCALL64_entry_trampoline = |
1539 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1540 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
72f5e08d | 1541 | |
31ac34ca | 1542 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
8d4b0678 TG |
1543 | if (static_cpu_has(X86_FEATURE_PTI)) |
1544 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1545 | else | |
1546 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
d56fe4bf IM |
1547 | |
1548 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1549 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1550 | /* |
487d1edb DV |
1551 | * This only works on Intel CPUs. |
1552 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1553 | * This does not cause SYSENTER to jump to the wrong location, because | |
1554 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1555 | */ |
1556 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
4fe2d8b1 | 1557 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); |
4c8cd0c5 | 1558 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1559 | #else |
47edb651 | 1560 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1561 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1562 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1563 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1564 | #endif |
03ae5768 | 1565 | |
d5494d4f YL |
1566 | /* Flags to clear on syscall */ |
1567 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1568 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1569 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1570 | } |
62111195 | 1571 | |
d5494d4f YL |
1572 | /* |
1573 | * Copies of the original ist values from the tss are only accessed during | |
1574 | * debugging, no special alignment required. | |
1575 | */ | |
1576 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1577 | ||
228bdaa9 | 1578 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1579 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1580 | |
1581 | int is_debug_stack(unsigned long addr) | |
1582 | { | |
89cbc767 CL |
1583 | return __this_cpu_read(debug_stack_usage) || |
1584 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1585 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1586 | } |
0f46efeb | 1587 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1588 | |
629f4f9d | 1589 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1590 | |
228bdaa9 SR |
1591 | void debug_stack_set_zero(void) |
1592 | { | |
629f4f9d SA |
1593 | this_cpu_inc(debug_idt_ctr); |
1594 | load_current_idt(); | |
228bdaa9 | 1595 | } |
0f46efeb | 1596 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1597 | |
1598 | void debug_stack_reset(void) | |
1599 | { | |
629f4f9d | 1600 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1601 | return; |
629f4f9d SA |
1602 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1603 | load_current_idt(); | |
228bdaa9 | 1604 | } |
0f46efeb | 1605 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1606 | |
0f3fa48a | 1607 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1608 | |
bdf977b3 TH |
1609 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1610 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1611 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1612 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1613 | |
a7fcf28d AL |
1614 | /* |
1615 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1616 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1617 | * top of the kernel stack directly. | |
1618 | */ | |
1619 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1620 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1621 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1622 | ||
050e9baa | 1623 | #ifdef CONFIG_STACKPROTECTOR |
53f82452 | 1624 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1625 | #endif |
d5494d4f | 1626 | |
0f3fa48a | 1627 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1628 | |
9766cdbc JSR |
1629 | /* |
1630 | * Clear all 6 debug registers: | |
1631 | */ | |
1632 | static void clear_all_debug_regs(void) | |
1633 | { | |
1634 | int i; | |
1635 | ||
1636 | for (i = 0; i < 8; i++) { | |
1637 | /* Ignore db4, db5 */ | |
1638 | if ((i == 4) || (i == 5)) | |
1639 | continue; | |
1640 | ||
1641 | set_debugreg(0, i); | |
1642 | } | |
1643 | } | |
c5413fbe | 1644 | |
0bb9fef9 JW |
1645 | #ifdef CONFIG_KGDB |
1646 | /* | |
1647 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1648 | * connection established. | |
1649 | */ | |
1650 | static void dbg_restore_debug_regs(void) | |
1651 | { | |
1652 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1653 | arch_kgdb_ops.correct_hw_break(); | |
1654 | } | |
1655 | #else /* ! CONFIG_KGDB */ | |
1656 | #define dbg_restore_debug_regs() | |
1657 | #endif /* ! CONFIG_KGDB */ | |
1658 | ||
ce4b1b16 IM |
1659 | static void wait_for_master_cpu(int cpu) |
1660 | { | |
1661 | #ifdef CONFIG_SMP | |
1662 | /* | |
1663 | * wait for ACK from master CPU before continuing | |
1664 | * with AP initialization | |
1665 | */ | |
1666 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1667 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1668 | cpu_relax(); | |
1669 | #endif | |
1670 | } | |
1671 | ||
d2cbcc49 RR |
1672 | /* |
1673 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1674 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1675 | * and IDT. We reload them nevertheless, this function acts as a | |
1676 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1677 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1678 | */ |
1ba76586 | 1679 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1680 | |
148f9bb8 | 1681 | void cpu_init(void) |
1ba76586 | 1682 | { |
0fe1e009 | 1683 | struct orig_ist *oist; |
1ba76586 | 1684 | struct task_struct *me; |
0f3fa48a IM |
1685 | struct tss_struct *t; |
1686 | unsigned long v; | |
fb59831b | 1687 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1688 | int i; |
1689 | ||
ce4b1b16 IM |
1690 | wait_for_master_cpu(cpu); |
1691 | ||
1e02ce4c AL |
1692 | /* |
1693 | * Initialize the CR4 shadow before doing anything that could | |
1694 | * try to read it. | |
1695 | */ | |
1696 | cr4_init_shadow(); | |
1697 | ||
777284b6 BP |
1698 | if (cpu) |
1699 | load_ucode_ap(); | |
e6ebf5de | 1700 | |
c482feef | 1701 | t = &per_cpu(cpu_tss_rw, cpu); |
0fe1e009 | 1702 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1703 | |
e7a22c1e | 1704 | #ifdef CONFIG_NUMA |
27fd185f | 1705 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1706 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1707 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1708 | #endif |
1ba76586 YL |
1709 | |
1710 | me = current; | |
1711 | ||
2eaad1fd | 1712 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1713 | |
375074cc | 1714 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1715 | |
1716 | /* | |
1717 | * Initialize the per-CPU GDT with the boot GDT, | |
1718 | * and set up the GDT descriptor: | |
1719 | */ | |
1720 | ||
552be871 | 1721 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1722 | loadsegment(fs, 0); |
1723 | ||
cf910e83 | 1724 | load_current_idt(); |
1ba76586 YL |
1725 | |
1726 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1727 | syscall_init(); | |
1728 | ||
1729 | wrmsrl(MSR_FS_BASE, 0); | |
1730 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1731 | barrier(); | |
1732 | ||
4763ed4d | 1733 | x86_configure_nx(); |
659006bf | 1734 | x2apic_setup(); |
1ba76586 YL |
1735 | |
1736 | /* | |
1737 | * set up and load the per-CPU TSS | |
1738 | */ | |
0fe1e009 | 1739 | if (!oist->ist[0]) { |
40e7f949 | 1740 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1741 | |
1ba76586 | 1742 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1743 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1744 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1745 | (unsigned long)estacks; |
228bdaa9 SR |
1746 | if (v == DEBUG_STACK-1) |
1747 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1748 | } |
1749 | } | |
1750 | ||
7fb983b4 | 1751 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1752 | |
1ba76586 YL |
1753 | /* |
1754 | * <= is required because the CPU will access up to | |
1755 | * 8 bits beyond the end of the IO permission bitmap. | |
1756 | */ | |
1757 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1758 | t->io_bitmap[i] = ~0UL; | |
1759 | ||
f1f10076 | 1760 | mmgrab(&init_mm); |
1ba76586 | 1761 | me->active_mm = &init_mm; |
8c5dfd25 | 1762 | BUG_ON(me->mm); |
72c0098d | 1763 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1764 | enter_lazy_tlb(&init_mm, me); |
1765 | ||
20bb8344 | 1766 | /* |
7f2590a1 AL |
1767 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1768 | * regardless of what task is running. | |
20bb8344 | 1769 | */ |
72f5e08d | 1770 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1771 | load_TR_desc(); |
4fe2d8b1 | 1772 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1773 | |
37868fe1 | 1774 | load_mm_ldt(&init_mm); |
1ba76586 | 1775 | |
0bb9fef9 JW |
1776 | clear_all_debug_regs(); |
1777 | dbg_restore_debug_regs(); | |
1ba76586 | 1778 | |
21c4cd10 | 1779 | fpu__init_cpu(); |
1ba76586 | 1780 | |
1ba76586 YL |
1781 | if (is_uv_system()) |
1782 | uv_cpu_init(); | |
69218e47 | 1783 | |
69218e47 | 1784 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1785 | } |
1786 | ||
1787 | #else | |
1788 | ||
148f9bb8 | 1789 | void cpu_init(void) |
9ee79a3d | 1790 | { |
d2cbcc49 RR |
1791 | int cpu = smp_processor_id(); |
1792 | struct task_struct *curr = current; | |
c482feef | 1793 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1794 | |
ce4b1b16 | 1795 | wait_for_master_cpu(cpu); |
e6ebf5de | 1796 | |
5b2bdbc8 SR |
1797 | /* |
1798 | * Initialize the CR4 shadow before doing anything that could | |
1799 | * try to read it. | |
1800 | */ | |
1801 | cr4_init_shadow(); | |
1802 | ||
ce4b1b16 | 1803 | show_ucode_info_early(); |
62111195 | 1804 | |
1b74dde7 | 1805 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1806 | |
362f924b | 1807 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1808 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1809 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1810 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1811 | |
cf910e83 | 1812 | load_current_idt(); |
552be871 | 1813 | switch_to_new_gdt(cpu); |
1da177e4 | 1814 | |
1da177e4 LT |
1815 | /* |
1816 | * Set up and load the per-CPU TSS and LDT | |
1817 | */ | |
f1f10076 | 1818 | mmgrab(&init_mm); |
62111195 | 1819 | curr->active_mm = &init_mm; |
8c5dfd25 | 1820 | BUG_ON(curr->mm); |
72c0098d | 1821 | initialize_tlbstate_and_flush(); |
62111195 | 1822 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1823 | |
20bb8344 | 1824 | /* |
45d7b255 JR |
1825 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1826 | * regardless of what task is running. | |
20bb8344 | 1827 | */ |
72f5e08d | 1828 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1829 | load_TR_desc(); |
45d7b255 | 1830 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 1831 | |
37868fe1 | 1832 | load_mm_ldt(&init_mm); |
1da177e4 | 1833 | |
7fb983b4 | 1834 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1835 | |
22c4e308 | 1836 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1837 | /* Set up doublefault TSS pointer in the GDT */ |
1838 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1839 | #endif |
1da177e4 | 1840 | |
9766cdbc | 1841 | clear_all_debug_regs(); |
0bb9fef9 | 1842 | dbg_restore_debug_regs(); |
1da177e4 | 1843 | |
21c4cd10 | 1844 | fpu__init_cpu(); |
69218e47 | 1845 | |
69218e47 | 1846 | load_fixmap_gdt(cpu); |
1da177e4 | 1847 | } |
1ba76586 | 1848 | #endif |
5700f743 | 1849 | |
b51ef52d LA |
1850 | static void bsp_resume(void) |
1851 | { | |
1852 | if (this_cpu->c_bsp_resume) | |
1853 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1854 | } | |
1855 | ||
1856 | static struct syscore_ops cpu_syscore_ops = { | |
1857 | .resume = bsp_resume, | |
1858 | }; | |
1859 | ||
1860 | static int __init init_cpu_syscore(void) | |
1861 | { | |
1862 | register_syscore_ops(&cpu_syscore_ops); | |
1863 | return 0; | |
1864 | } | |
1865 | core_initcall(init_cpu_syscore); | |
1008c52c BP |
1866 | |
1867 | /* | |
1868 | * The microcode loader calls this upon late microcode load to recheck features, | |
1869 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1870 | * hotplug lock. | |
1871 | */ | |
1872 | void microcode_check(void) | |
1873 | { | |
42ca8082 BP |
1874 | struct cpuinfo_x86 info; |
1875 | ||
1008c52c | 1876 | perf_check_microcode(); |
42ca8082 BP |
1877 | |
1878 | /* Reload CPUID max function as it might've changed. */ | |
1879 | info.cpuid_level = cpuid_eax(0); | |
1880 | ||
1881 | /* | |
1882 | * Copy all capability leafs to pick up the synthetic ones so that | |
1883 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1884 | * get overwritten in get_cpu_cap(). | |
1885 | */ | |
1886 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1887 | ||
1888 | get_cpu_cap(&info); | |
1889 | ||
1890 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1891 | return; | |
1892 | ||
1893 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1894 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 1895 | } |