Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2458e53f KS |
2 | /* cpu_feature_enabled() cannot be used this early */ |
3 | #define USE_EARLY_PGTABLE_L5 | |
4 | ||
57c8a661 | 5 | #include <linux/memblock.h> |
9766cdbc | 6 | #include <linux/linkage.h> |
f0fc4aff | 7 | #include <linux/bitops.h> |
9766cdbc | 8 | #include <linux/kernel.h> |
186f4360 | 9 | #include <linux/export.h> |
9766cdbc JSR |
10 | #include <linux/percpu.h> |
11 | #include <linux/string.h> | |
ee098e1a | 12 | #include <linux/ctype.h> |
1da177e4 | 13 | #include <linux/delay.h> |
68e21be2 | 14 | #include <linux/sched/mm.h> |
e6017571 | 15 | #include <linux/sched/clock.h> |
9164bb4a | 16 | #include <linux/sched/task.h> |
b47a3698 | 17 | #include <linux/sched/smt.h> |
9766cdbc | 18 | #include <linux/init.h> |
0f46efeb | 19 | #include <linux/kprobes.h> |
9766cdbc | 20 | #include <linux/kgdb.h> |
1da177e4 | 21 | #include <linux/smp.h> |
9766cdbc | 22 | #include <linux/io.h> |
b51ef52d | 23 | #include <linux/syscore_ops.h> |
65fddcfc | 24 | #include <linux/pgtable.h> |
9766cdbc | 25 | |
1ef5423a | 26 | #include <asm/cmdline.h> |
9766cdbc | 27 | #include <asm/stackprotector.h> |
cdd6c482 | 28 | #include <asm/perf_event.h> |
1da177e4 | 29 | #include <asm/mmu_context.h> |
dc4e0021 | 30 | #include <asm/doublefault.h> |
49d859d7 | 31 | #include <asm/archrandom.h> |
9766cdbc JSR |
32 | #include <asm/hypervisor.h> |
33 | #include <asm/processor.h> | |
1e02ce4c | 34 | #include <asm/tlbflush.h> |
f649e938 | 35 | #include <asm/debugreg.h> |
9766cdbc | 36 | #include <asm/sections.h> |
f40c3300 | 37 | #include <asm/vsyscall.h> |
8bdbd962 AC |
38 | #include <linux/topology.h> |
39 | #include <linux/cpumask.h> | |
60063497 | 40 | #include <linux/atomic.h> |
9766cdbc JSR |
41 | #include <asm/proto.h> |
42 | #include <asm/setup.h> | |
43 | #include <asm/apic.h> | |
44 | #include <asm/desc.h> | |
b56d2795 | 45 | #include <asm/fpu/api.h> |
27b07da7 | 46 | #include <asm/mtrr.h> |
0274f955 | 47 | #include <asm/hwcap2.h> |
8bdbd962 | 48 | #include <linux/numa.h> |
0cd39f46 | 49 | #include <asm/numa.h> |
9766cdbc | 50 | #include <asm/asm.h> |
0f6ff2bc | 51 | #include <asm/bugs.h> |
9766cdbc | 52 | #include <asm/cpu.h> |
a03a3e28 | 53 | #include <asm/mce.h> |
9766cdbc | 54 | #include <asm/msr.h> |
eb243d1d | 55 | #include <asm/memtype.h> |
d288e1cf FY |
56 | #include <asm/microcode.h> |
57 | #include <asm/microcode_intel.h> | |
fec9434a DW |
58 | #include <asm/intel-family.h> |
59 | #include <asm/cpu_device_id.h> | |
bdbcdd48 | 60 | #include <asm/uv/uv.h> |
939ef713 | 61 | #include <asm/sigframe.h> |
991625f3 | 62 | #include <asm/traps.h> |
95d33bfa | 63 | #include <asm/sev.h> |
1da177e4 LT |
64 | |
65 | #include "cpu.h" | |
66 | ||
0274f955 GA |
67 | u32 elf_hwcap2 __read_mostly; |
68 | ||
c2d1cec1 | 69 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 70 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
71 | cpumask_var_t cpu_callout_mask; |
72 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
73 | |
74 | /* representing cpus for which sibling maps can be computed */ | |
75 | cpumask_var_t cpu_sibling_setup_mask; | |
76 | ||
f8b64d08 BP |
77 | /* Number of siblings per CPU package */ |
78 | int smp_num_siblings = 1; | |
79 | EXPORT_SYMBOL(smp_num_siblings); | |
80 | ||
81 | /* Last level cache ID of each logical CPU */ | |
82 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
83 | ||
9164d949 KP |
84 | u16 get_llc_id(unsigned int cpu) |
85 | { | |
86 | return per_cpu(cpu_llc_id, cpu); | |
87 | } | |
88 | EXPORT_SYMBOL_GPL(get_llc_id); | |
89 | ||
66558b73 TC |
90 | /* L2 cache ID of each logical CPU */ |
91 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; | |
92 | ||
0dcab41d TL |
93 | static struct ppin_info { |
94 | int feature; | |
95 | int msr_ppin_ctl; | |
822ccfad | 96 | int msr_ppin; |
0dcab41d TL |
97 | } ppin_info[] = { |
98 | [X86_VENDOR_INTEL] = { | |
99 | .feature = X86_FEATURE_INTEL_PPIN, | |
100 | .msr_ppin_ctl = MSR_PPIN_CTL, | |
822ccfad | 101 | .msr_ppin = MSR_PPIN |
0dcab41d TL |
102 | }, |
103 | [X86_VENDOR_AMD] = { | |
104 | .feature = X86_FEATURE_AMD_PPIN, | |
105 | .msr_ppin_ctl = MSR_AMD_PPIN_CTL, | |
822ccfad | 106 | .msr_ppin = MSR_AMD_PPIN |
0dcab41d TL |
107 | }, |
108 | }; | |
109 | ||
110 | static const struct x86_cpu_id ppin_cpuids[] = { | |
111 | X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), | |
00a2f23e | 112 | X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]), |
0dcab41d TL |
113 | |
114 | /* Legacy models without CPUID enumeration */ | |
115 | X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), | |
116 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), | |
117 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), | |
118 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), | |
119 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), | |
120 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), | |
121 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), | |
122 | X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), | |
123 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), | |
124 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), | |
125 | ||
126 | {} | |
127 | }; | |
128 | ||
129 | static void ppin_init(struct cpuinfo_x86 *c) | |
130 | { | |
131 | const struct x86_cpu_id *id; | |
132 | unsigned long long val; | |
133 | struct ppin_info *info; | |
134 | ||
135 | id = x86_match_cpu(ppin_cpuids); | |
136 | if (!id) | |
137 | return; | |
138 | ||
139 | /* | |
140 | * Testing the presence of the MSR is not enough. Need to check | |
141 | * that the PPIN_CTL allows reading of the PPIN. | |
142 | */ | |
143 | info = (struct ppin_info *)id->driver_data; | |
144 | ||
145 | if (rdmsrl_safe(info->msr_ppin_ctl, &val)) | |
146 | goto clear_ppin; | |
147 | ||
148 | if ((val & 3UL) == 1UL) { | |
149 | /* PPIN locked in disabled mode */ | |
150 | goto clear_ppin; | |
151 | } | |
152 | ||
153 | /* If PPIN is disabled, try to enable */ | |
154 | if (!(val & 2UL)) { | |
155 | wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); | |
156 | rdmsrl_safe(info->msr_ppin_ctl, &val); | |
157 | } | |
158 | ||
159 | /* Is the enable bit set? */ | |
160 | if (val & 2UL) { | |
822ccfad | 161 | c->ppin = __rdmsr(info->msr_ppin); |
0dcab41d TL |
162 | set_cpu_cap(c, info->feature); |
163 | return; | |
164 | } | |
165 | ||
166 | clear_ppin: | |
167 | clear_cpu_cap(c, info->feature); | |
168 | } | |
169 | ||
2f2f52ba | 170 | /* correctly size the local cpu masks */ |
4369f1fb | 171 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
172 | { |
173 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
174 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
175 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
176 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
177 | } | |
178 | ||
148f9bb8 | 179 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
180 | { |
181 | #ifdef CONFIG_X86_64 | |
27c13ece | 182 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
183 | #else |
184 | /* Not much we can do here... */ | |
185 | /* Check if at least it has cpuid */ | |
186 | if (c->cpuid_level == -1) { | |
187 | /* No cpuid. It must be an ancient CPU */ | |
188 | if (c->x86 == 4) | |
189 | strcpy(c->x86_model_id, "486"); | |
190 | else if (c->x86 == 3) | |
191 | strcpy(c->x86_model_id, "386"); | |
192 | } | |
193 | #endif | |
194 | } | |
195 | ||
148f9bb8 | 196 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
197 | .c_init = default_init, |
198 | .c_vendor = "Unknown", | |
199 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
200 | }; | |
201 | ||
148f9bb8 | 202 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 203 | |
06deef89 | 204 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 205 | #ifdef CONFIG_X86_64 |
06deef89 BG |
206 | /* |
207 | * We need valid kernel segments for data and code in long mode too | |
208 | * IRET will check the segment types kkeil 2000/10/28 | |
209 | * Also sysret mandates a special GDT layout | |
210 | * | |
9766cdbc | 211 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
212 | * Hopefully nobody expects them at a fixed place (Wine?) |
213 | */ | |
1e5de182 AM |
214 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
215 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
216 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
217 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
218 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
219 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 220 | #else |
1e5de182 AM |
221 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
222 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
223 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
224 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
225 | /* |
226 | * Segments used for calling PnP BIOS have byte granularity. | |
227 | * They code segments and data segments have fixed 64k limits, | |
228 | * the transfer segment sizes are set at run time. | |
229 | */ | |
6842ef0e | 230 | /* 32-bit code */ |
1e5de182 | 231 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 232 | /* 16-bit code */ |
1e5de182 | 233 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 234 | /* 16-bit data */ |
1e5de182 | 235 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 236 | /* 16-bit data */ |
1e5de182 | 237 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 238 | /* 16-bit data */ |
1e5de182 | 239 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
240 | /* |
241 | * The APM segments have byte granularity and their bases | |
242 | * are set at run time. All have 64k limits. | |
243 | */ | |
6842ef0e | 244 | /* 32-bit code */ |
1e5de182 | 245 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 246 | /* 16-bit code */ |
1e5de182 | 247 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 248 | /* data */ |
72c4d853 | 249 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 250 | |
1e5de182 AM |
251 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
252 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
950ad7ff | 253 | #endif |
06deef89 | 254 | } }; |
7a61d35d | 255 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 256 | |
0790c9aa | 257 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 258 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 259 | { |
c7ad5ad2 AL |
260 | /* nopcid doesn't accept parameters */ |
261 | if (s) | |
262 | return -EINVAL; | |
0790c9aa AL |
263 | |
264 | /* do not emit a message if the feature is not present */ | |
265 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 266 | return 0; |
0790c9aa AL |
267 | |
268 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
269 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 270 | return 0; |
0790c9aa | 271 | } |
c7ad5ad2 | 272 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
273 | #endif |
274 | ||
d12a72b8 AL |
275 | static int __init x86_noinvpcid_setup(char *s) |
276 | { | |
277 | /* noinvpcid doesn't accept parameters */ | |
278 | if (s) | |
279 | return -EINVAL; | |
280 | ||
281 | /* do not emit a message if the feature is not present */ | |
282 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
283 | return 0; | |
284 | ||
285 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
286 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
287 | return 0; | |
288 | } | |
289 | early_param("noinvpcid", x86_noinvpcid_setup); | |
290 | ||
ba51dced | 291 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
292 | static int cachesize_override = -1; |
293 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 294 | |
0a488a53 YL |
295 | static int __init cachesize_setup(char *str) |
296 | { | |
297 | get_option(&str, &cachesize_override); | |
298 | return 1; | |
299 | } | |
300 | __setup("cachesize=", cachesize_setup); | |
301 | ||
0a488a53 YL |
302 | /* Standard macro to see if a specific flag is changeable */ |
303 | static inline int flag_is_changeable_p(u32 flag) | |
304 | { | |
305 | u32 f1, f2; | |
306 | ||
94f6bac1 KH |
307 | /* |
308 | * Cyrix and IDT cpus allow disabling of CPUID | |
309 | * so the code below may return different results | |
310 | * when it is executed before and after enabling | |
311 | * the CPUID. Add "volatile" to not allow gcc to | |
312 | * optimize the subsequent calls to this function. | |
313 | */ | |
0f3fa48a IM |
314 | asm volatile ("pushfl \n\t" |
315 | "pushfl \n\t" | |
316 | "popl %0 \n\t" | |
317 | "movl %0, %1 \n\t" | |
318 | "xorl %2, %0 \n\t" | |
319 | "pushl %0 \n\t" | |
320 | "popfl \n\t" | |
321 | "pushfl \n\t" | |
322 | "popl %0 \n\t" | |
323 | "popfl \n\t" | |
324 | ||
94f6bac1 KH |
325 | : "=&r" (f1), "=&r" (f2) |
326 | : "ir" (flag)); | |
0a488a53 YL |
327 | |
328 | return ((f1^f2) & flag) != 0; | |
329 | } | |
330 | ||
331 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 332 | int have_cpuid_p(void) |
0a488a53 YL |
333 | { |
334 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
335 | } | |
336 | ||
148f9bb8 | 337 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 338 | { |
0f3fa48a IM |
339 | unsigned long lo, hi; |
340 | ||
341 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
342 | return; | |
343 | ||
344 | /* Disable processor serial number: */ | |
345 | ||
346 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
347 | lo |= 0x200000; | |
348 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
349 | ||
1b74dde7 | 350 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
351 | clear_cpu_cap(c, X86_FEATURE_PN); |
352 | ||
353 | /* Disabling the serial number may affect the cpuid level */ | |
354 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
355 | } |
356 | ||
357 | static int __init x86_serial_nr_setup(char *s) | |
358 | { | |
359 | disable_x86_serial_nr = 0; | |
360 | return 1; | |
361 | } | |
362 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 363 | #else |
102bbe3a YL |
364 | static inline int flag_is_changeable_p(u32 flag) |
365 | { | |
366 | return 1; | |
367 | } | |
102bbe3a YL |
368 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
369 | { | |
370 | } | |
ba51dced | 371 | #endif |
0a488a53 | 372 | |
b2cc2a07 | 373 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 374 | { |
b2cc2a07 | 375 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 376 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
377 | } |
378 | ||
b2cc2a07 PA |
379 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
380 | { | |
581b7f15 | 381 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
382 | |
383 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
384 | BUG_ON(eflags & X86_EFLAGS_AC); |
385 | ||
dbae0a93 | 386 | if (cpu_has(c, X86_FEATURE_SMAP)) |
375074cc | 387 | cr4_set_bits(X86_CR4_SMAP); |
de5397ad FY |
388 | } |
389 | ||
aa35f896 RN |
390 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
391 | { | |
392 | /* Check the boot processor, plus build option for UMIP. */ | |
393 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
394 | goto out; | |
395 | ||
396 | /* Check the current processor's cpuid bits. */ | |
397 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
398 | goto out; | |
399 | ||
400 | cr4_set_bits(X86_CR4_UMIP); | |
401 | ||
438cbf88 | 402 | pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); |
770c7755 | 403 | |
aa35f896 RN |
404 | return; |
405 | ||
406 | out: | |
407 | /* | |
408 | * Make sure UMIP is disabled in case it was enabled in a | |
409 | * previous boot (e.g., via kexec). | |
410 | */ | |
411 | cr4_clear_bits(X86_CR4_UMIP); | |
412 | } | |
413 | ||
a13b9d0b KC |
414 | /* These bits should not change their value after CPU init is finished. */ |
415 | static const unsigned long cr4_pinned_mask = | |
991625f3 PZ |
416 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | |
417 | X86_CR4_FSGSBASE | X86_CR4_CET; | |
7652ac92 TG |
418 | static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); |
419 | static unsigned long cr4_pinned_bits __ro_after_init; | |
420 | ||
421 | void native_write_cr0(unsigned long val) | |
422 | { | |
423 | unsigned long bits_missing = 0; | |
424 | ||
425 | set_register: | |
aa5cacdc | 426 | asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); |
7652ac92 TG |
427 | |
428 | if (static_branch_likely(&cr_pinning)) { | |
429 | if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { | |
430 | bits_missing = X86_CR0_WP; | |
431 | val |= bits_missing; | |
432 | goto set_register; | |
433 | } | |
434 | /* Warn after we've set the missing bits. */ | |
435 | WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); | |
436 | } | |
437 | } | |
438 | EXPORT_SYMBOL(native_write_cr0); | |
439 | ||
b64dfcde | 440 | void __no_profile native_write_cr4(unsigned long val) |
7652ac92 | 441 | { |
a13b9d0b | 442 | unsigned long bits_changed = 0; |
7652ac92 TG |
443 | |
444 | set_register: | |
aa5cacdc | 445 | asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); |
7652ac92 TG |
446 | |
447 | if (static_branch_likely(&cr_pinning)) { | |
a13b9d0b KC |
448 | if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { |
449 | bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; | |
450 | val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; | |
7652ac92 TG |
451 | goto set_register; |
452 | } | |
a13b9d0b KC |
453 | /* Warn after we've corrected the changed bits. */ |
454 | WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", | |
455 | bits_changed); | |
7652ac92 TG |
456 | } |
457 | } | |
21953ee5 | 458 | #if IS_MODULE(CONFIG_LKDTM) |
d8f0b353 | 459 | EXPORT_SYMBOL_GPL(native_write_cr4); |
21953ee5 | 460 | #endif |
d8f0b353 TG |
461 | |
462 | void cr4_update_irqsoff(unsigned long set, unsigned long clear) | |
463 | { | |
464 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
465 | ||
466 | lockdep_assert_irqs_disabled(); | |
467 | ||
468 | newval = (cr4 & ~clear) | set; | |
469 | if (newval != cr4) { | |
470 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
471 | __write_cr4(newval); | |
472 | } | |
473 | } | |
474 | EXPORT_SYMBOL(cr4_update_irqsoff); | |
475 | ||
476 | /* Read the CR4 shadow. */ | |
477 | unsigned long cr4_read_shadow(void) | |
478 | { | |
479 | return this_cpu_read(cpu_tlbstate.cr4); | |
480 | } | |
481 | EXPORT_SYMBOL_GPL(cr4_read_shadow); | |
7652ac92 TG |
482 | |
483 | void cr4_init(void) | |
484 | { | |
485 | unsigned long cr4 = __read_cr4(); | |
486 | ||
487 | if (boot_cpu_has(X86_FEATURE_PCID)) | |
488 | cr4 |= X86_CR4_PCIDE; | |
489 | if (static_branch_likely(&cr_pinning)) | |
a13b9d0b | 490 | cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; |
7652ac92 TG |
491 | |
492 | __write_cr4(cr4); | |
493 | ||
494 | /* Initialize cr4 shadow for this CPU. */ | |
495 | this_cpu_write(cpu_tlbstate.cr4, cr4); | |
496 | } | |
873d50d5 KC |
497 | |
498 | /* | |
499 | * Once CPU feature detection is finished (and boot params have been | |
500 | * parsed), record any of the sensitive CR bits that are set, and | |
501 | * enable CR pinning. | |
502 | */ | |
503 | static void __init setup_cr_pinning(void) | |
504 | { | |
a13b9d0b | 505 | cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; |
873d50d5 KC |
506 | static_key_enable(&cr_pinning.key); |
507 | } | |
508 | ||
b745cfba | 509 | static __init int x86_nofsgsbase_setup(char *arg) |
dd649bd0 | 510 | { |
b745cfba AL |
511 | /* Require an exact match without trailing characters. */ |
512 | if (strlen(arg)) | |
513 | return 0; | |
514 | ||
515 | /* Do not emit a message if the feature is not present. */ | |
516 | if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) | |
517 | return 1; | |
518 | ||
519 | setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); | |
520 | pr_info("FSGSBASE disabled via kernel command line\n"); | |
dd649bd0 AL |
521 | return 1; |
522 | } | |
b745cfba | 523 | __setup("nofsgsbase", x86_nofsgsbase_setup); |
dd649bd0 | 524 | |
06976945 DH |
525 | /* |
526 | * Protection Keys are not available in 32-bit mode. | |
527 | */ | |
528 | static bool pku_disabled; | |
529 | ||
530 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
531 | { | |
8a1dc55a TG |
532 | if (c == &boot_cpu_data) { |
533 | if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) | |
534 | return; | |
535 | /* | |
536 | * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid | |
537 | * bit to be set. Enforce it. | |
538 | */ | |
539 | setup_force_cpu_cap(X86_FEATURE_OSPKE); | |
a5eff725 | 540 | |
8a1dc55a | 541 | } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { |
06976945 | 542 | return; |
8a1dc55a | 543 | } |
06976945 DH |
544 | |
545 | cr4_set_bits(X86_CR4_PKE); | |
fa8c84b7 TG |
546 | /* Load the default PKRU value */ |
547 | pkru_write_default(); | |
06976945 DH |
548 | } |
549 | ||
550 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
551 | static __init int setup_disable_pku(char *arg) | |
552 | { | |
553 | /* | |
554 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
555 | * runtime checks are against OSPKE so clearing the | |
556 | * bit does nothing. | |
557 | * | |
558 | * This way, we will see "pku" in cpuinfo, but not | |
559 | * "ospke", which is exactly what we want. It shows | |
560 | * that the CPU has PKU, but the OS has not enabled it. | |
561 | * This happens to be exactly how a system would look | |
562 | * if we disabled the config option. | |
563 | */ | |
564 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
565 | pku_disabled = true; | |
566 | return 1; | |
567 | } | |
568 | __setup("nopku", setup_disable_pku); | |
569 | #endif /* CONFIG_X86_64 */ | |
570 | ||
fe379fa4 PZ |
571 | #ifdef CONFIG_X86_KERNEL_IBT |
572 | ||
573 | __noendbr u64 ibt_save(void) | |
574 | { | |
575 | u64 msr = 0; | |
576 | ||
577 | if (cpu_feature_enabled(X86_FEATURE_IBT)) { | |
578 | rdmsrl(MSR_IA32_S_CET, msr); | |
579 | wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); | |
580 | } | |
581 | ||
582 | return msr; | |
583 | } | |
584 | ||
585 | __noendbr void ibt_restore(u64 save) | |
586 | { | |
587 | u64 msr; | |
588 | ||
589 | if (cpu_feature_enabled(X86_FEATURE_IBT)) { | |
590 | rdmsrl(MSR_IA32_S_CET, msr); | |
591 | msr &= ~CET_ENDBR_EN; | |
592 | msr |= (save & CET_ENDBR_EN); | |
593 | wrmsrl(MSR_IA32_S_CET, msr); | |
594 | } | |
595 | } | |
596 | ||
597 | #endif | |
598 | ||
991625f3 PZ |
599 | static __always_inline void setup_cet(struct cpuinfo_x86 *c) |
600 | { | |
601 | u64 msr = CET_ENDBR_EN; | |
602 | ||
603 | if (!HAS_KERNEL_IBT || | |
604 | !cpu_feature_enabled(X86_FEATURE_IBT)) | |
605 | return; | |
606 | ||
607 | wrmsrl(MSR_IA32_S_CET, msr); | |
608 | cr4_set_bits(X86_CR4_CET); | |
609 | ||
610 | if (!ibt_selftest()) { | |
611 | pr_err("IBT selftest: Failed!\n"); | |
612 | setup_clear_cpu_cap(X86_FEATURE_IBT); | |
613 | return; | |
614 | } | |
615 | } | |
616 | ||
af227003 PZ |
617 | __noendbr void cet_disable(void) |
618 | { | |
619 | if (cpu_feature_enabled(X86_FEATURE_IBT)) | |
620 | wrmsrl(MSR_IA32_S_CET, 0); | |
621 | } | |
622 | ||
b38b0665 PA |
623 | /* |
624 | * Some CPU features depend on higher CPUID levels, which may not always | |
625 | * be available due to CPUID level capping or broken virtualization | |
626 | * software. Add those features to this table to auto-disable them. | |
627 | */ | |
628 | struct cpuid_dependent_feature { | |
629 | u32 feature; | |
630 | u32 level; | |
631 | }; | |
0f3fa48a | 632 | |
148f9bb8 | 633 | static const struct cpuid_dependent_feature |
b38b0665 PA |
634 | cpuid_dependent_features[] = { |
635 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
636 | { X86_FEATURE_DCA, 0x00000009 }, | |
637 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
638 | { 0, 0 } | |
639 | }; | |
640 | ||
148f9bb8 | 641 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
642 | { |
643 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 644 | |
b38b0665 | 645 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
646 | |
647 | if (!cpu_has(c, df->feature)) | |
648 | continue; | |
b38b0665 PA |
649 | /* |
650 | * Note: cpuid_level is set to -1 if unavailable, but | |
651 | * extended_extended_level is set to 0 if unavailable | |
652 | * and the legitimate extended levels are all negative | |
653 | * when signed; hence the weird messing around with | |
654 | * signs here... | |
655 | */ | |
0f3fa48a | 656 | if (!((s32)df->level < 0 ? |
f6db44df | 657 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
658 | (s32)df->level > (s32)c->cpuid_level)) |
659 | continue; | |
660 | ||
661 | clear_cpu_cap(c, df->feature); | |
662 | if (!warn) | |
663 | continue; | |
664 | ||
1b74dde7 CY |
665 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
666 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 667 | } |
f6db44df | 668 | } |
b38b0665 | 669 | |
102bbe3a YL |
670 | /* |
671 | * Naming convention should be: <Name> [(<Codename>)] | |
672 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
673 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
674 | * isn't used | |
102bbe3a YL |
675 | */ |
676 | ||
677 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 678 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 679 | { |
09dc68d9 JB |
680 | #ifdef CONFIG_X86_32 |
681 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
682 | |
683 | if (c->x86_model >= 16) | |
684 | return NULL; /* Range check */ | |
685 | ||
686 | if (!this_cpu) | |
687 | return NULL; | |
688 | ||
09dc68d9 | 689 | info = this_cpu->legacy_models; |
102bbe3a | 690 | |
09dc68d9 | 691 | while (info->family) { |
102bbe3a YL |
692 | if (info->family == c->x86) |
693 | return info->model_names[c->x86_model]; | |
694 | info++; | |
695 | } | |
09dc68d9 | 696 | #endif |
102bbe3a YL |
697 | return NULL; /* Not found */ |
698 | } | |
699 | ||
f6a892dd FY |
700 | /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ |
701 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
702 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
7d851c8d | 703 | |
72f5e08d AL |
704 | #ifdef CONFIG_X86_32 |
705 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
706 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
707 | #endif | |
708 | ||
45fc8757 TG |
709 | /* Load the original GDT from the per-cpu structure */ |
710 | void load_direct_gdt(int cpu) | |
711 | { | |
712 | struct desc_ptr gdt_descr; | |
713 | ||
714 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
715 | gdt_descr.size = GDT_SIZE - 1; | |
716 | load_gdt(&gdt_descr); | |
717 | } | |
718 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
719 | ||
69218e47 TG |
720 | /* Load a fixmap remapping of the per-cpu GDT */ |
721 | void load_fixmap_gdt(int cpu) | |
722 | { | |
723 | struct desc_ptr gdt_descr; | |
724 | ||
725 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
726 | gdt_descr.size = GDT_SIZE - 1; | |
727 | load_gdt(&gdt_descr); | |
728 | } | |
45fc8757 | 729 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 730 | |
b5636d45 | 731 | /** |
1f19e2d5 | 732 | * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base |
b5636d45 TG |
733 | * @cpu: The CPU number for which this is invoked |
734 | * | |
1f19e2d5 TG |
735 | * Invoked during early boot to switch from early GDT and early per CPU to |
736 | * the direct GDT and the runtime per CPU area. On 32-bit the percpu base | |
737 | * switch is implicit by loading the direct GDT. On 64bit this requires | |
738 | * to update GSBASE. | |
0f3fa48a | 739 | */ |
1f19e2d5 | 740 | void __init switch_gdt_and_percpu_base(int cpu) |
9d31d35b | 741 | { |
45fc8757 | 742 | load_direct_gdt(cpu); |
b5636d45 TG |
743 | |
744 | #ifdef CONFIG_X86_64 | |
745 | /* | |
746 | * No need to load %gs. It is already correct. | |
747 | * | |
748 | * Writing %gs on 64bit would zero GSBASE which would make any per | |
749 | * CPU operation up to the point of the wrmsrl() fault. | |
750 | * | |
751 | * Set GSBASE to the new offset. Until the wrmsrl() happens the | |
752 | * early mapping is still valid. That means the GSBASE update will | |
753 | * lose any prior per CPU data which was not copied over in | |
754 | * setup_per_cpu_areas(). | |
755 | */ | |
756 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); | |
757 | #else | |
758 | /* | |
759 | * %fs is already set to __KERNEL_PERCPU, but after switching GDT | |
760 | * it is required to load FS again so that the 'hidden' part is | |
761 | * updated from the new GDT. Up to this point the early per CPU | |
762 | * translation is active. Any content of the early per CPU data | |
763 | * which was not copied over in setup_per_cpu_areas() is lost. | |
764 | */ | |
765 | loadsegment(fs, __KERNEL_PERCPU); | |
766 | #endif | |
9d31d35b YL |
767 | } |
768 | ||
148f9bb8 | 769 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 770 | |
148f9bb8 | 771 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
772 | { |
773 | unsigned int *v; | |
ee098e1a | 774 | char *p, *q, *s; |
1da177e4 | 775 | |
3da99c97 | 776 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 777 | return; |
1da177e4 | 778 | |
0f3fa48a | 779 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
780 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
781 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
782 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
783 | c->x86_model_id[48] = 0; | |
784 | ||
ee098e1a BP |
785 | /* Trim whitespace */ |
786 | p = q = s = &c->x86_model_id[0]; | |
787 | ||
788 | while (*p == ' ') | |
789 | p++; | |
790 | ||
791 | while (*p) { | |
792 | /* Note the last non-whitespace index */ | |
793 | if (!isspace(*p)) | |
794 | s = q; | |
795 | ||
796 | *q++ = *p++; | |
797 | } | |
798 | ||
799 | *(s + 1) = '\0'; | |
1da177e4 LT |
800 | } |
801 | ||
9305bd6c | 802 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
803 | { |
804 | unsigned int eax, ebx, ecx, edx; | |
805 | ||
9305bd6c | 806 | c->x86_max_cores = 1; |
2cc61be6 | 807 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 808 | return; |
2cc61be6 DW |
809 | |
810 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
811 | if (eax & 0x1f) | |
9305bd6c | 812 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
813 | } |
814 | ||
148f9bb8 | 815 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 816 | { |
9d31d35b | 817 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 818 | |
3da99c97 | 819 | n = c->extended_cpuid_level; |
1da177e4 LT |
820 | |
821 | if (n >= 0x80000005) { | |
9d31d35b | 822 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 823 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
824 | #ifdef CONFIG_X86_64 |
825 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
826 | c->x86_tlbsize = 0; | |
827 | #endif | |
1da177e4 LT |
828 | } |
829 | ||
830 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
831 | return; | |
832 | ||
0a488a53 | 833 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 834 | l2size = ecx >> 16; |
34048c9e | 835 | |
140fc727 YL |
836 | #ifdef CONFIG_X86_64 |
837 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
838 | #else | |
1da177e4 | 839 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
840 | if (this_cpu->legacy_cache_size) |
841 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
842 | |
843 | /* Allow user to override all this if necessary. */ | |
844 | if (cachesize_override != -1) | |
845 | l2size = cachesize_override; | |
846 | ||
34048c9e | 847 | if (l2size == 0) |
1da177e4 | 848 | return; /* Again, no L2 cache is possible */ |
140fc727 | 849 | #endif |
1da177e4 LT |
850 | |
851 | c->x86_cache_size = l2size; | |
1da177e4 LT |
852 | } |
853 | ||
e0ba94f1 AS |
854 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
855 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
856 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
857 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
858 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
859 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 860 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 861 | |
f94fe119 | 862 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
863 | { |
864 | if (this_cpu->c_detect_tlb) | |
865 | this_cpu->c_detect_tlb(c); | |
866 | ||
f94fe119 | 867 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 868 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
869 | tlb_lli_4m[ENTRIES]); |
870 | ||
871 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
872 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
873 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
874 | } |
875 | ||
545401f4 | 876 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 877 | { |
c8e56d20 | 878 | #ifdef CONFIG_SMP |
0a488a53 | 879 | u32 eax, ebx, ecx, edx; |
1da177e4 | 880 | |
0a488a53 | 881 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 882 | return -1; |
1da177e4 | 883 | |
0a488a53 | 884 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 885 | return -1; |
1da177e4 | 886 | |
1cd78776 | 887 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 888 | return -1; |
1da177e4 | 889 | |
0a488a53 | 890 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 891 | |
9d31d35b | 892 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 893 | if (smp_num_siblings == 1) |
1b74dde7 | 894 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
895 | #endif |
896 | return 0; | |
897 | } | |
9d31d35b | 898 | |
545401f4 TG |
899 | void detect_ht(struct cpuinfo_x86 *c) |
900 | { | |
901 | #ifdef CONFIG_SMP | |
902 | int index_msb, core_bits; | |
55e6d279 | 903 | |
545401f4 | 904 | if (detect_ht_early(c) < 0) |
55e6d279 | 905 | return; |
9d31d35b | 906 | |
0f3fa48a IM |
907 | index_msb = get_count_order(smp_num_siblings); |
908 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 909 | |
0f3fa48a | 910 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 911 | |
0f3fa48a | 912 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 913 | |
0f3fa48a | 914 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 915 | |
0f3fa48a IM |
916 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
917 | ((1 << core_bits) - 1); | |
9d31d35b | 918 | #endif |
97e4db7c | 919 | } |
1da177e4 | 920 | |
148f9bb8 | 921 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
922 | { |
923 | char *v = c->x86_vendor_id; | |
0f3fa48a | 924 | int i; |
1da177e4 LT |
925 | |
926 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
927 | if (!cpu_devs[i]) |
928 | break; | |
929 | ||
930 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
931 | (cpu_devs[i]->c_ident[1] && | |
932 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 933 | |
10a434fc YL |
934 | this_cpu = cpu_devs[i]; |
935 | c->x86_vendor = this_cpu->c_x86_vendor; | |
936 | return; | |
1da177e4 LT |
937 | } |
938 | } | |
10a434fc | 939 | |
1b74dde7 CY |
940 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
941 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 942 | |
fe38d855 CE |
943 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
944 | this_cpu = &default_cpu; | |
1da177e4 LT |
945 | } |
946 | ||
148f9bb8 | 947 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 948 | { |
1da177e4 | 949 | /* Get vendor name */ |
4a148513 HH |
950 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
951 | (unsigned int *)&c->x86_vendor_id[0], | |
952 | (unsigned int *)&c->x86_vendor_id[8], | |
953 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 954 | |
1da177e4 | 955 | c->x86 = 4; |
9d31d35b | 956 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
957 | if (c->cpuid_level >= 0x00000001) { |
958 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 959 | |
1da177e4 | 960 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
961 | c->x86 = x86_family(tfms); |
962 | c->x86_model = x86_model(tfms); | |
b399151c | 963 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 964 | |
d4387bd3 | 965 | if (cap0 & (1<<19)) { |
d4387bd3 | 966 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 967 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 968 | } |
1da177e4 | 969 | } |
1da177e4 | 970 | } |
3da99c97 | 971 | |
8bf1ebca AL |
972 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
973 | { | |
974 | int i; | |
975 | ||
6cbd2171 | 976 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
977 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
978 | c->x86_capability[i] |= cpu_caps_set[i]; | |
979 | } | |
980 | } | |
981 | ||
7fcae111 DW |
982 | static void init_speculation_control(struct cpuinfo_x86 *c) |
983 | { | |
984 | /* | |
985 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
986 | * and they also have a different bit for STIBP support. Also, | |
987 | * a hypervisor might have set the individual AMD bits even on | |
988 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
989 | */ |
990 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
991 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
992 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 993 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 994 | } |
e7c587da | 995 | |
7fcae111 DW |
996 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
997 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 998 | |
bc226f07 TL |
999 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
1000 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
1001 | set_cpu_cap(c, X86_FEATURE_SSBD); |
1002 | ||
7eb8956a | 1003 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 1004 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
1005 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
1006 | } | |
e7c587da BP |
1007 | |
1008 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
1009 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
1010 | ||
7eb8956a | 1011 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 1012 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
1013 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
1014 | } | |
6ac2f49e KRW |
1015 | |
1016 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
1017 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
1018 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
1019 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
1020 | } | |
7fcae111 DW |
1021 | } |
1022 | ||
148f9bb8 | 1023 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 1024 | { |
39c06df4 | 1025 | u32 eax, ebx, ecx, edx; |
093af8d7 | 1026 | |
3da99c97 YL |
1027 | /* Intel-defined flags: level 0x00000001 */ |
1028 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 1029 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 1030 | |
39c06df4 BP |
1031 | c->x86_capability[CPUID_1_ECX] = ecx; |
1032 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 1033 | } |
093af8d7 | 1034 | |
3df8d920 AL |
1035 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
1036 | if (c->cpuid_level >= 0x00000006) | |
1037 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
1038 | ||
bdc802dc PA |
1039 | /* Additional Intel-defined flags: level 0x00000007 */ |
1040 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 1041 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 1042 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 1043 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 1044 | c->x86_capability[CPUID_7_EDX] = edx; |
b302e4b1 FY |
1045 | |
1046 | /* Check valid sub-leaf index before accessing it */ | |
1047 | if (eax >= 1) { | |
1048 | cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); | |
1049 | c->x86_capability[CPUID_7_1_EAX] = eax; | |
1050 | } | |
bdc802dc PA |
1051 | } |
1052 | ||
6229ad27 FY |
1053 | /* Extended state features: level 0x0000000d */ |
1054 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
1055 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
1056 | ||
39c06df4 | 1057 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
1058 | } |
1059 | ||
3da99c97 | 1060 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
1061 | eax = cpuid_eax(0x80000000); |
1062 | c->extended_cpuid_level = eax; | |
1063 | ||
1064 | if ((eax & 0xffff0000) == 0x80000000) { | |
1065 | if (eax >= 0x80000001) { | |
1066 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 1067 | |
39c06df4 BP |
1068 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
1069 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 1070 | } |
093af8d7 | 1071 | } |
093af8d7 | 1072 | |
71faad43 YG |
1073 | if (c->extended_cpuid_level >= 0x80000007) { |
1074 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
1075 | ||
1076 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
1077 | c->x86_power = edx; | |
1078 | } | |
1079 | ||
c65732e4 TG |
1080 | if (c->extended_cpuid_level >= 0x80000008) { |
1081 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
1082 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
1083 | } | |
1084 | ||
2ccd71f1 | 1085 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 1086 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 1087 | |
fb35d30f SC |
1088 | if (c->extended_cpuid_level >= 0x8000001f) |
1089 | c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); | |
1090 | ||
1dedefd1 | 1091 | init_scattered_cpuid_features(c); |
7fcae111 | 1092 | init_speculation_control(c); |
60d34501 AL |
1093 | |
1094 | /* | |
1095 | * Clear/Set all flags overridden by options, after probe. | |
1096 | * This needs to happen each time we re-probe, which may happen | |
1097 | * several times during CPU initialization. | |
1098 | */ | |
1099 | apply_forced_caps(c); | |
093af8d7 | 1100 | } |
1da177e4 | 1101 | |
405c018a | 1102 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
1103 | { |
1104 | u32 eax, ebx, ecx, edx; | |
1105 | ||
1106 | if (c->extended_cpuid_level >= 0x80000008) { | |
1107 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
1108 | ||
1109 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
1110 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
1111 | } |
1112 | #ifdef CONFIG_X86_32 | |
1113 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
1114 | c->x86_phys_bits = 36; | |
1115 | #endif | |
cc51e542 | 1116 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
1117 | } |
1118 | ||
148f9bb8 | 1119 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
1120 | { |
1121 | #ifdef CONFIG_X86_32 | |
1122 | int i; | |
1123 | ||
1124 | /* | |
1125 | * First of all, decide if this is a 486 or higher | |
1126 | * It's a 486 if we can modify the AC flag | |
1127 | */ | |
1128 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1129 | c->x86 = 4; | |
1130 | else | |
1131 | c->x86 = 3; | |
1132 | ||
1133 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
1134 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
1135 | c->x86_vendor_id[0] = 0; | |
1136 | cpu_devs[i]->c_identify(c); | |
1137 | if (c->x86_vendor_id[0]) { | |
1138 | get_cpu_vendor(c); | |
1139 | break; | |
1140 | } | |
1141 | } | |
1142 | #endif | |
1143 | } | |
1144 | ||
db4d30fb VT |
1145 | #define NO_SPECULATION BIT(0) |
1146 | #define NO_MELTDOWN BIT(1) | |
1147 | #define NO_SSB BIT(2) | |
1148 | #define NO_L1TF BIT(3) | |
1149 | #define NO_MDS BIT(4) | |
1150 | #define MSBDS_ONLY BIT(5) | |
1151 | #define NO_SWAPGS BIT(6) | |
1152 | #define NO_ITLB_MULTIHIT BIT(7) | |
1e41a766 | 1153 | #define NO_SPECTRE_V2 BIT(8) |
7df54884 PG |
1154 | #define NO_MMIO BIT(9) |
1155 | #define NO_EIBRS_PBRSB BIT(10) | |
36ad3513 | 1156 | |
f6d502fc TG |
1157 | #define VULNWL(vendor, family, model, whitelist) \ |
1158 | X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) | |
36ad3513 TG |
1159 | |
1160 | #define VULNWL_INTEL(model, whitelist) \ | |
1161 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
1162 | ||
1163 | #define VULNWL_AMD(family, whitelist) \ | |
1164 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
1165 | ||
1166 | #define VULNWL_HYGON(family, whitelist) \ | |
1167 | VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) | |
1168 | ||
1169 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
1170 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
1171 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1172 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1173 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
639475d4 MDSV |
1174 | VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), |
1175 | VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), | |
36ad3513 | 1176 | |
ed5194c2 | 1177 | /* Intel Family 6 */ |
7df54884 PG |
1178 | VULNWL_INTEL(TIGERLAKE, NO_MMIO), |
1179 | VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), | |
1180 | VULNWL_INTEL(ALDERLAKE, NO_MMIO), | |
1181 | VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), | |
1182 | ||
db4d30fb VT |
1183 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), |
1184 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1185 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1186 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1187 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1188 | ||
1189 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1190 | VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1191 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1192 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1193 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1194 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 TG |
1195 | |
1196 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
1197 | ||
db4d30fb VT |
1198 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1199 | VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 | 1200 | |
7df54884 PG |
1201 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), |
1202 | VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), | |
1203 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), | |
f36cf386 TG |
1204 | |
1205 | /* | |
1206 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
1207 | * being documented as such in the APM). But according to AMD, %gs is | |
1208 | * updated non-speculatively, and the issuing of %gs-relative memory | |
1209 | * operands will be blocked until the %gs update completes, which is | |
1210 | * good enough for our purposes. | |
1211 | */ | |
ed5194c2 | 1212 | |
2b129932 DS |
1213 | VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), |
1214 | VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), | |
1215 | VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), | |
cad14885 | 1216 | |
ed5194c2 | 1217 | /* AMD Family 0xf - 0x12 */ |
7df54884 PG |
1218 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), |
1219 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), | |
1220 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), | |
1221 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), | |
36ad3513 TG |
1222 | |
1223 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
7df54884 PG |
1224 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), |
1225 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO), | |
1e41a766 TW |
1226 | |
1227 | /* Zhaoxin Family 7 */ | |
7df54884 PG |
1228 | VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), |
1229 | VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO), | |
fec9434a DW |
1230 | {} |
1231 | }; | |
1232 | ||
6b80b59b AC |
1233 | #define VULNBL(vendor, family, model, blacklist) \ |
1234 | X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) | |
1235 | ||
7e5b3c26 MG |
1236 | #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ |
1237 | X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ | |
1238 | INTEL_FAM6_##model, steppings, \ | |
1239 | X86_FEATURE_ANY, issues) | |
1240 | ||
6b80b59b AC |
1241 | #define VULNBL_AMD(family, blacklist) \ |
1242 | VULNBL(AMD, family, X86_MODEL_ANY, blacklist) | |
1243 | ||
1244 | #define VULNBL_HYGON(family, blacklist) \ | |
1245 | VULNBL(HYGON, family, X86_MODEL_ANY, blacklist) | |
1246 | ||
7e5b3c26 | 1247 | #define SRBDS BIT(0) |
51802186 PG |
1248 | /* CPU is affected by X86_BUG_MMIO_STALE_DATA */ |
1249 | #define MMIO BIT(1) | |
a992b8a4 PG |
1250 | /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */ |
1251 | #define MMIO_SBDS BIT(2) | |
6b80b59b AC |
1252 | /* CPU is affected by RETbleed, speculating where you would not expect it */ |
1253 | #define RETBLEED BIT(3) | |
7e5b3c26 MG |
1254 | |
1255 | static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { | |
1256 | VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), | |
1257 | VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), | |
1258 | VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), | |
1259 | VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), | |
7a05bc95 PZ |
1260 | VULNBL_INTEL_STEPPINGS(HASWELL_X, X86_STEPPING_ANY, MMIO), |
1261 | VULNBL_INTEL_STEPPINGS(BROADWELL_D, X86_STEPPING_ANY, MMIO), | |
7e5b3c26 | 1262 | VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), |
51802186 | 1263 | VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), |
7e5b3c26 | 1264 | VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), |
7a05bc95 PZ |
1265 | VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), |
1266 | VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), | |
1267 | VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), | |
1268 | VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), | |
1269 | VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), | |
f54d4537 | 1270 | VULNBL_INTEL_STEPPINGS(CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED), |
7a05bc95 PZ |
1271 | VULNBL_INTEL_STEPPINGS(ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), |
1272 | VULNBL_INTEL_STEPPINGS(ICELAKE_D, X86_STEPPING_ANY, MMIO), | |
1273 | VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), | |
1274 | VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), | |
6ad0ad2b | 1275 | VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED), |
7a05bc95 PZ |
1276 | VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), |
1277 | VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), | |
1278 | VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), | |
1279 | VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), | |
51802186 | 1280 | VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO), |
7a05bc95 | 1281 | VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), |
6b80b59b AC |
1282 | |
1283 | VULNBL_AMD(0x15, RETBLEED), | |
1284 | VULNBL_AMD(0x16, RETBLEED), | |
1285 | VULNBL_AMD(0x17, RETBLEED), | |
1286 | VULNBL_HYGON(0x18, RETBLEED), | |
7e5b3c26 MG |
1287 | {} |
1288 | }; | |
1289 | ||
93920f61 | 1290 | static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) |
36ad3513 | 1291 | { |
93920f61 | 1292 | const struct x86_cpu_id *m = x86_match_cpu(table); |
c456442c | 1293 | |
36ad3513 TG |
1294 | return m && !!(m->driver_data & which); |
1295 | } | |
17dbca11 | 1296 | |
286836a7 | 1297 | u64 x86_read_arch_cap_msr(void) |
fec9434a DW |
1298 | { |
1299 | u64 ia32_cap = 0; | |
1300 | ||
286836a7 PG |
1301 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1302 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1303 | ||
1304 | return ia32_cap; | |
1305 | } | |
1306 | ||
51802186 PG |
1307 | static bool arch_cap_mmio_immune(u64 ia32_cap) |
1308 | { | |
1309 | return (ia32_cap & ARCH_CAP_FBSDP_NO && | |
1310 | ia32_cap & ARCH_CAP_PSDP_NO && | |
1311 | ia32_cap & ARCH_CAP_SBDR_SSDP_NO); | |
1312 | } | |
1313 | ||
286836a7 PG |
1314 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) |
1315 | { | |
1316 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
1317 | ||
db4d30fb | 1318 | /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ |
93920f61 MG |
1319 | if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && |
1320 | !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) | |
db4d30fb VT |
1321 | setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); |
1322 | ||
93920f61 | 1323 | if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) |
8ecc4979 DB |
1324 | return; |
1325 | ||
1326 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1e41a766 | 1327 | |
93920f61 | 1328 | if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) |
1e41a766 | 1329 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); |
8ecc4979 | 1330 | |
93920f61 MG |
1331 | if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && |
1332 | !(ia32_cap & ARCH_CAP_SSB_NO) && | |
24809860 | 1333 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c456442c KRW |
1334 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1335 | ||
706d5168 SP |
1336 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1337 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1338 | ||
93920f61 MG |
1339 | if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && |
1340 | !(ia32_cap & ARCH_CAP_MDS_NO)) { | |
ed5194c2 | 1341 | setup_force_cpu_bug(X86_BUG_MDS); |
93920f61 | 1342 | if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) |
e261f209 TG |
1343 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); |
1344 | } | |
ed5194c2 | 1345 | |
93920f61 | 1346 | if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) |
f36cf386 TG |
1347 | setup_force_cpu_bug(X86_BUG_SWAPGS); |
1348 | ||
1b42f017 PG |
1349 | /* |
1350 | * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: | |
1351 | * - TSX is supported or | |
1352 | * - TSX_CTRL is present | |
1353 | * | |
1354 | * TSX_CTRL check is needed for cases when TSX could be disabled before | |
1355 | * the kernel boot e.g. kexec. | |
1356 | * TSX_CTRL check alone is not sufficient for cases when the microcode | |
1357 | * update is not present or running as guest that don't get TSX_CTRL. | |
1358 | */ | |
1359 | if (!(ia32_cap & ARCH_CAP_TAA_NO) && | |
1360 | (cpu_has(c, X86_FEATURE_RTM) || | |
1361 | (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) | |
1362 | setup_force_cpu_bug(X86_BUG_TAA); | |
1363 | ||
7e5b3c26 MG |
1364 | /* |
1365 | * SRBDS affects CPUs which support RDRAND or RDSEED and are listed | |
1366 | * in the vulnerability blacklist. | |
a992b8a4 PG |
1367 | * |
1368 | * Some of the implications and mitigation of Shared Buffers Data | |
1369 | * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as | |
1370 | * SRBDS. | |
7e5b3c26 MG |
1371 | */ |
1372 | if ((cpu_has(c, X86_FEATURE_RDRAND) || | |
1373 | cpu_has(c, X86_FEATURE_RDSEED)) && | |
a992b8a4 | 1374 | cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS)) |
7e5b3c26 MG |
1375 | setup_force_cpu_bug(X86_BUG_SRBDS); |
1376 | ||
51802186 PG |
1377 | /* |
1378 | * Processor MMIO Stale Data bug enumeration | |
1379 | * | |
1380 | * Affected CPU list is generally enough to enumerate the vulnerability, | |
1381 | * but for virtualization case check for ARCH_CAP MSR bits also, VMM may | |
1382 | * not want the guest to enumerate the bug. | |
7df54884 PG |
1383 | * |
1384 | * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist, | |
1385 | * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits. | |
51802186 | 1386 | */ |
7df54884 PG |
1387 | if (!arch_cap_mmio_immune(ia32_cap)) { |
1388 | if (cpu_matches(cpu_vuln_blacklist, MMIO)) | |
1389 | setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA); | |
1390 | else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO)) | |
1391 | setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN); | |
1392 | } | |
51802186 | 1393 | |
26aae8cc AC |
1394 | if (!cpu_has(c, X86_FEATURE_BTC_NO)) { |
1395 | if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA)) | |
1396 | setup_force_cpu_bug(X86_BUG_RETBLEED); | |
1397 | } | |
6b80b59b | 1398 | |
2b129932 DS |
1399 | if (cpu_has(c, X86_FEATURE_IBRS_ENHANCED) && |
1400 | !cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) && | |
1401 | !(ia32_cap & ARCH_CAP_PBRSB_NO)) | |
1402 | setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); | |
1403 | ||
93920f61 | 1404 | if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) |
4a28bfe3 | 1405 | return; |
fec9434a | 1406 | |
fec9434a DW |
1407 | /* Rogue Data Cache Load? No! */ |
1408 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1409 | return; |
fec9434a | 1410 | |
4a28bfe3 | 1411 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 | 1412 | |
93920f61 | 1413 | if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) |
17dbca11 AK |
1414 | return; |
1415 | ||
1416 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1417 | } |
1418 | ||
8990cac6 PT |
1419 | /* |
1420 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1421 | * unfortunately, that's not true in practice because of early VIA | |
1422 | * chips and (more importantly) broken virtualizers that are not easy | |
1423 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1424 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1425 | * unless we can find a reliable way to detect all the broken cases. | |
1426 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1427 | */ | |
9b3661cd | 1428 | static void detect_nopl(void) |
8990cac6 PT |
1429 | { |
1430 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1431 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1432 | #else |
9b3661cd | 1433 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1434 | #endif |
1435 | } | |
1436 | ||
1ef5423a MH |
1437 | /* |
1438 | * We parse cpu parameters early because fpu__init_system() is executed | |
1439 | * before parse_early_param(). | |
1440 | */ | |
1441 | static void __init cpu_parse_early_param(void) | |
1442 | { | |
1443 | char arg[128]; | |
1625c833 BP |
1444 | char *argptr = arg, *opt; |
1445 | int arglen, taint = 0; | |
1ef5423a MH |
1446 | |
1447 | #ifdef CONFIG_X86_32 | |
1448 | if (cmdline_find_option_bool(boot_command_line, "no387")) | |
1449 | #ifdef CONFIG_MATH_EMULATION | |
1450 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
1451 | #else | |
1452 | pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); | |
1453 | #endif | |
1454 | ||
1455 | if (cmdline_find_option_bool(boot_command_line, "nofxsr")) | |
1456 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
1457 | #endif | |
1458 | ||
1459 | if (cmdline_find_option_bool(boot_command_line, "noxsave")) | |
1460 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
1461 | ||
1462 | if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) | |
1463 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
1464 | ||
1465 | if (cmdline_find_option_bool(boot_command_line, "noxsaves")) | |
1466 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
1467 | ||
1468 | arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); | |
1469 | if (arglen <= 0) | |
1470 | return; | |
1471 | ||
1472 | pr_info("Clearing CPUID bits:"); | |
1ef5423a | 1473 | |
1625c833 BP |
1474 | while (argptr) { |
1475 | bool found __maybe_unused = false; | |
1476 | unsigned int bit; | |
1ef5423a | 1477 | |
1625c833 BP |
1478 | opt = strsep(&argptr, ","); |
1479 | ||
1480 | /* | |
1481 | * Handle naked numbers first for feature flags which don't | |
1482 | * have names. | |
1483 | */ | |
1484 | if (!kstrtouint(opt, 10, &bit)) { | |
1485 | if (bit < NCAPINTS * 32) { | |
1486 | ||
1487 | #ifdef CONFIG_X86_FEATURE_NAMES | |
1488 | /* empty-string, i.e., ""-defined feature flags */ | |
1489 | if (!x86_cap_flags[bit]) | |
1490 | pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit)); | |
1491 | else | |
1492 | #endif | |
1493 | pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); | |
1494 | ||
1495 | setup_clear_cpu_cap(bit); | |
1496 | taint++; | |
1497 | } | |
1498 | /* | |
1499 | * The assumption is that there are no feature names with only | |
1500 | * numbers in the name thus go to the next argument. | |
1501 | */ | |
1502 | continue; | |
1503 | } | |
1504 | ||
1505 | #ifdef CONFIG_X86_FEATURE_NAMES | |
1506 | for (bit = 0; bit < 32 * NCAPINTS; bit++) { | |
1507 | if (!x86_cap_flag(bit)) | |
1508 | continue; | |
1ef5423a | 1509 | |
1625c833 BP |
1510 | if (strcmp(x86_cap_flag(bit), opt)) |
1511 | continue; | |
1512 | ||
1513 | pr_cont(" %s", opt); | |
1ef5423a | 1514 | setup_clear_cpu_cap(bit); |
1625c833 BP |
1515 | taint++; |
1516 | found = true; | |
1517 | break; | |
1ef5423a | 1518 | } |
1625c833 BP |
1519 | |
1520 | if (!found) | |
1521 | pr_cont(" (unknown: %s)", opt); | |
1522 | #endif | |
1523 | } | |
1ef5423a | 1524 | pr_cont("\n"); |
1625c833 BP |
1525 | |
1526 | if (taint) | |
1527 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
1ef5423a MH |
1528 | } |
1529 | ||
34048c9e PC |
1530 | /* |
1531 | * Do minimum CPU detection early. | |
1532 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1533 | * cache alignment. | |
1534 | * The others are not touched to avoid unwanted side effects. | |
1535 | * | |
a1652bb8 JD |
1536 | * WARNING: this function is only called on the boot CPU. Don't add code |
1537 | * here that is supposed to run on all CPUs. | |
34048c9e | 1538 | */ |
3da99c97 | 1539 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1540 | { |
6627d242 YL |
1541 | #ifdef CONFIG_X86_64 |
1542 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1543 | c->x86_phys_bits = 36; |
1544 | c->x86_virt_bits = 48; | |
6627d242 | 1545 | #else |
d4387bd3 | 1546 | c->x86_clflush_size = 32; |
13c6c532 JB |
1547 | c->x86_phys_bits = 32; |
1548 | c->x86_virt_bits = 32; | |
6627d242 | 1549 | #endif |
0a488a53 | 1550 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1551 | |
0e96f31e | 1552 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
0a488a53 | 1553 | c->extended_cpuid_level = 0; |
d7cd5611 | 1554 | |
2893cc8f MW |
1555 | if (!have_cpuid_p()) |
1556 | identify_cpu_without_cpuid(c); | |
1557 | ||
aef93c8b | 1558 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1559 | if (have_cpuid_p()) { |
1560 | cpu_detect(c); | |
1561 | get_cpu_vendor(c); | |
1562 | get_cpu_cap(c); | |
d94a155c | 1563 | get_cpu_address_sizes(c); |
78d1b296 | 1564 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
1ef5423a | 1565 | cpu_parse_early_param(); |
d7cd5611 | 1566 | |
05fb3c19 AL |
1567 | if (this_cpu->c_early_init) |
1568 | this_cpu->c_early_init(c); | |
12cf105c | 1569 | |
05fb3c19 AL |
1570 | c->cpu_index = 0; |
1571 | filter_cpuid_features(c, false); | |
093af8d7 | 1572 | |
05fb3c19 AL |
1573 | if (this_cpu->c_bsp_init) |
1574 | this_cpu->c_bsp_init(c); | |
78d1b296 | 1575 | } else { |
78d1b296 | 1576 | setup_clear_cpu_cap(X86_FEATURE_CPUID); |
05fb3c19 | 1577 | } |
c3b83598 BP |
1578 | |
1579 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1580 | |
4a28bfe3 | 1581 | cpu_set_bug_bits(c); |
99c6fa25 | 1582 | |
ebb1064e | 1583 | sld_setup(c); |
6650cdd9 | 1584 | |
db52ef74 | 1585 | fpu__init_system(c); |
b8b7abae | 1586 | |
939ef713 CB |
1587 | init_sigframe_size(); |
1588 | ||
b8b7abae AL |
1589 | #ifdef CONFIG_X86_32 |
1590 | /* | |
1591 | * Regardless of whether PCID is enumerated, the SDM says | |
1592 | * that it can't be enabled in 32-bit mode. | |
1593 | */ | |
1594 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1595 | #endif | |
372fddf7 KS |
1596 | |
1597 | /* | |
1598 | * Later in the boot process pgtable_l5_enabled() relies on | |
1599 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1600 | * enabled by this point we need to clear the feature bit to avoid | |
1601 | * false-positives at the later stage. | |
1602 | * | |
1603 | * pgtable_l5_enabled() can be false here for several reasons: | |
1604 | * - 5-level paging is disabled compile-time; | |
1605 | * - it's 32-bit kernel; | |
1606 | * - machine doesn't support 5-level paging; | |
1607 | * - user specified 'no5lvl' in kernel command line. | |
1608 | */ | |
1609 | if (!pgtable_l5_enabled()) | |
1610 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1611 | |
9b3661cd | 1612 | detect_nopl(); |
d7cd5611 RR |
1613 | } |
1614 | ||
9d31d35b YL |
1615 | void __init early_cpu_init(void) |
1616 | { | |
02dde8b4 | 1617 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1618 | int count = 0; |
1619 | ||
ac23f253 | 1620 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1621 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1622 | #endif |
1623 | ||
10a434fc | 1624 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1625 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1626 | |
10a434fc YL |
1627 | if (count >= X86_VENDOR_NUM) |
1628 | break; | |
1629 | cpu_devs[count] = cpudev; | |
1630 | count++; | |
1631 | ||
ac23f253 | 1632 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1633 | { |
1634 | unsigned int j; | |
1635 | ||
1636 | for (j = 0; j < 2; j++) { | |
1637 | if (!cpudev->c_ident[j]) | |
1638 | continue; | |
1b74dde7 | 1639 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1640 | cpudev->c_ident[j]); |
1641 | } | |
10a434fc | 1642 | } |
0388423d | 1643 | #endif |
10a434fc | 1644 | } |
9d31d35b | 1645 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1646 | } |
093af8d7 | 1647 | |
415de440 | 1648 | static bool detect_null_seg_behavior(void) |
7a5d6704 | 1649 | { |
58a5aac5 | 1650 | /* |
7a5d6704 AL |
1651 | * Empirically, writing zero to a segment selector on AMD does |
1652 | * not clear the base, whereas writing zero to a segment | |
1653 | * selector on Intel does clear the base. Intel's behavior | |
1654 | * allows slightly faster context switches in the common case | |
1655 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1656 | * |
7a5d6704 | 1657 | * Since neither vendor documents this anywhere that I can see, |
d9f6e12f | 1658 | * detect it directly instead of hard-coding the choice by |
7a5d6704 AL |
1659 | * vendor. |
1660 | * | |
1661 | * I've designated AMD's behavior as the "bug" because it's | |
1662 | * counterintuitive and less friendly. | |
58a5aac5 | 1663 | */ |
7a5d6704 AL |
1664 | |
1665 | unsigned long old_base, tmp; | |
1666 | rdmsrl(MSR_FS_BASE, old_base); | |
1667 | wrmsrl(MSR_FS_BASE, 1); | |
1668 | loadsegment(fs, 0); | |
1669 | rdmsrl(MSR_FS_BASE, tmp); | |
7a5d6704 | 1670 | wrmsrl(MSR_FS_BASE, old_base); |
415de440 JM |
1671 | return tmp == 0; |
1672 | } | |
1673 | ||
1674 | void check_null_seg_clears_base(struct cpuinfo_x86 *c) | |
1675 | { | |
1676 | /* BUG_NULL_SEG is only relevant with 64bit userspace */ | |
1677 | if (!IS_ENABLED(CONFIG_X86_64)) | |
1678 | return; | |
1679 | ||
1680 | /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ | |
1681 | if (c->extended_cpuid_level >= 0x80000021 && | |
1682 | cpuid_eax(0x80000021) & BIT(6)) | |
1683 | return; | |
1684 | ||
1685 | /* | |
1686 | * CPUID bit above wasn't set. If this kernel is still running | |
1687 | * as a HV guest, then the HV has decided not to advertize | |
1688 | * that CPUID bit for whatever reason. For example, one | |
1689 | * member of the migration pool might be vulnerable. Which | |
1690 | * means, the bug is present: set the BUG flag and return. | |
1691 | */ | |
1692 | if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { | |
1693 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1694 | return; | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * Zen2 CPUs also have this behaviour, but no CPUID bit. | |
1699 | * 0x18 is the respective family for Hygon. | |
1700 | */ | |
1701 | if ((c->x86 == 0x17 || c->x86 == 0x18) && | |
1702 | detect_null_seg_behavior()) | |
1703 | return; | |
1704 | ||
1705 | /* All the remaining ones are affected */ | |
1706 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
d7cd5611 RR |
1707 | } |
1708 | ||
148f9bb8 | 1709 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1710 | { |
aef93c8b | 1711 | c->extended_cpuid_level = 0; |
1da177e4 | 1712 | |
3da99c97 | 1713 | if (!have_cpuid_p()) |
aef93c8b | 1714 | identify_cpu_without_cpuid(c); |
1d67953f | 1715 | |
aef93c8b | 1716 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1717 | if (!have_cpuid_p()) |
aef93c8b | 1718 | return; |
1da177e4 | 1719 | |
3da99c97 | 1720 | cpu_detect(c); |
1da177e4 | 1721 | |
3da99c97 | 1722 | get_cpu_vendor(c); |
1da177e4 | 1723 | |
3da99c97 | 1724 | get_cpu_cap(c); |
1da177e4 | 1725 | |
d94a155c KS |
1726 | get_cpu_address_sizes(c); |
1727 | ||
3da99c97 YL |
1728 | if (c->cpuid_level >= 0x00000001) { |
1729 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1730 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1731 | # ifdef CONFIG_SMP |
cb8cc442 | 1732 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1733 | # else |
3da99c97 | 1734 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1735 | # endif |
1736 | #endif | |
b89d3b3e | 1737 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1738 | } |
1da177e4 | 1739 | |
1b05d60d | 1740 | get_model_name(c); /* Default name */ |
1da177e4 | 1741 | |
0230bb03 AL |
1742 | /* |
1743 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1744 | * systems that run Linux at CPL > 0 may or may not have the | |
1745 | * issue, but, even if they have the issue, there's absolutely | |
1746 | * nothing we can do about it because we can't use the real IRET | |
1747 | * instruction. | |
1748 | * | |
1749 | * NB: For the time being, only 32-bit kernels support | |
1750 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1751 | * whether to apply espfix using paravirt hooks. If any | |
1752 | * non-paravirt system ever shows up that does *not* have the | |
1753 | * ESPFIX issue, we can change this. | |
1754 | */ | |
1755 | #ifdef CONFIG_X86_32 | |
0230bb03 | 1756 | set_cpu_bug(c, X86_BUG_ESPFIX); |
0230bb03 | 1757 | #endif |
1da177e4 | 1758 | } |
1da177e4 | 1759 | |
d49597fd | 1760 | /* |
9d85eb91 TG |
1761 | * Validate that ACPI/mptables have the same information about the |
1762 | * effective APIC id and update the package map. | |
d49597fd | 1763 | */ |
9d85eb91 | 1764 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1765 | { |
1766 | #ifdef CONFIG_SMP | |
9d85eb91 | 1767 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1768 | |
1769 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1770 | |
9d85eb91 TG |
1771 | if (apicid != c->apicid) { |
1772 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1773 | cpu, apicid, c->initial_apicid); |
d49597fd | 1774 | } |
9d85eb91 | 1775 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
212bf4fd | 1776 | BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); |
d49597fd TG |
1777 | #else |
1778 | c->logical_proc_id = 0; | |
1779 | #endif | |
1780 | } | |
1781 | ||
1da177e4 LT |
1782 | /* |
1783 | * This does the hard work of actually picking apart the CPU stuff... | |
1784 | */ | |
148f9bb8 | 1785 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1786 | { |
1787 | int i; | |
1788 | ||
1789 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1790 | c->x86_cache_size = 0; |
1da177e4 | 1791 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1792 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1793 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1794 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1795 | c->x86_max_cores = 1; |
102bbe3a | 1796 | c->x86_coreid_bits = 0; |
79a8b9aa | 1797 | c->cu_id = 0xff; |
11fdd252 | 1798 | #ifdef CONFIG_X86_64 |
102bbe3a | 1799 | c->x86_clflush_size = 64; |
13c6c532 JB |
1800 | c->x86_phys_bits = 36; |
1801 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1802 | #else |
1803 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1804 | c->x86_clflush_size = 32; |
13c6c532 JB |
1805 | c->x86_phys_bits = 32; |
1806 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1807 | #endif |
1808 | c->x86_cache_alignment = c->x86_clflush_size; | |
0e96f31e | 1809 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
b47ce1fe SC |
1810 | #ifdef CONFIG_X86_VMX_FEATURE_NAMES |
1811 | memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); | |
1812 | #endif | |
1da177e4 | 1813 | |
1da177e4 LT |
1814 | generic_identify(c); |
1815 | ||
3898534d | 1816 | if (this_cpu->c_identify) |
1da177e4 LT |
1817 | this_cpu->c_identify(c); |
1818 | ||
6a6256f9 | 1819 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1820 | apply_forced_caps(c); |
2759c328 | 1821 | |
102bbe3a | 1822 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1823 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1824 | #endif |
1825 | ||
1da177e4 LT |
1826 | /* |
1827 | * Vendor-specific initialization. In this section we | |
1828 | * canonicalize the feature flags, meaning if there are | |
1829 | * features a certain CPU supports which CPUID doesn't | |
1830 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1831 | * we handle them here. | |
1832 | * | |
1833 | * At the end of this section, c->x86_capability better | |
1834 | * indicate the features this CPU genuinely supports! | |
1835 | */ | |
1836 | if (this_cpu->c_init) | |
1837 | this_cpu->c_init(c); | |
1838 | ||
1839 | /* Disable the PN if appropriate */ | |
1840 | squash_the_stupid_serial_number(c); | |
1841 | ||
aa35f896 | 1842 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1843 | setup_smep(c); |
1844 | setup_smap(c); | |
aa35f896 | 1845 | setup_umip(c); |
b2cc2a07 | 1846 | |
dd649bd0 | 1847 | /* Enable FSGSBASE instructions if available. */ |
742c45c3 | 1848 | if (cpu_has(c, X86_FEATURE_FSGSBASE)) { |
b745cfba | 1849 | cr4_set_bits(X86_CR4_FSGSBASE); |
742c45c3 AK |
1850 | elf_hwcap2 |= HWCAP2_FSGSBASE; |
1851 | } | |
dd649bd0 | 1852 | |
1da177e4 | 1853 | /* |
0f3fa48a IM |
1854 | * The vendor-specific functions might have changed features. |
1855 | * Now we do "generic changes." | |
1da177e4 LT |
1856 | */ |
1857 | ||
b38b0665 PA |
1858 | /* Filter out anything that depends on CPUID levels we don't have */ |
1859 | filter_cpuid_features(c, true); | |
1860 | ||
1da177e4 | 1861 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1862 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1863 | const char *p; |
1da177e4 | 1864 | p = table_lookup_model(c); |
34048c9e | 1865 | if (p) |
1da177e4 LT |
1866 | strcpy(c->x86_model_id, p); |
1867 | else | |
1868 | /* Last resort... */ | |
1869 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1870 | c->x86, c->x86_model); |
1da177e4 LT |
1871 | } |
1872 | ||
102bbe3a YL |
1873 | #ifdef CONFIG_X86_64 |
1874 | detect_ht(c); | |
1875 | #endif | |
1876 | ||
49d859d7 | 1877 | x86_init_rdrand(c); |
06976945 | 1878 | setup_pku(c); |
991625f3 | 1879 | setup_cet(c); |
3e0c3737 YL |
1880 | |
1881 | /* | |
6a6256f9 | 1882 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1883 | * before following smp all cpus cap AND. |
1884 | */ | |
8bf1ebca | 1885 | apply_forced_caps(c); |
3e0c3737 | 1886 | |
1da177e4 LT |
1887 | /* |
1888 | * On SMP, boot_cpu_data holds the common feature set between | |
1889 | * all CPUs; so make sure that we indicate which features are | |
1890 | * common between the CPUs. The first time this routine gets | |
1891 | * executed, c == &boot_cpu_data. | |
1892 | */ | |
34048c9e | 1893 | if (c != &boot_cpu_data) { |
1da177e4 | 1894 | /* AND the already accumulated flags with these */ |
9d31d35b | 1895 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1896 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1897 | |
1898 | /* OR, i.e. replicate the bug flags */ | |
1899 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1900 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1901 | } |
1902 | ||
0dcab41d TL |
1903 | ppin_init(c); |
1904 | ||
1da177e4 | 1905 | /* Init Machine Check Exception if available. */ |
5e09954a | 1906 | mcheck_cpu_init(c); |
30d432df AK |
1907 | |
1908 | select_idle_routine(c); | |
102bbe3a | 1909 | |
de2d9445 | 1910 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1911 | numa_add_cpu(smp_processor_id()); |
1912 | #endif | |
a6c4e076 | 1913 | } |
31ab269a | 1914 | |
8b6c0ab1 IM |
1915 | /* |
1916 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1917 | * on 32-bit kernels: | |
1918 | */ | |
cfda7bb9 AL |
1919 | #ifdef CONFIG_X86_32 |
1920 | void enable_sep_cpu(void) | |
1921 | { | |
8b6c0ab1 IM |
1922 | struct tss_struct *tss; |
1923 | int cpu; | |
cfda7bb9 | 1924 | |
b3edfda4 BP |
1925 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1926 | return; | |
1927 | ||
8b6c0ab1 | 1928 | cpu = get_cpu(); |
c482feef | 1929 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1930 | |
8b6c0ab1 | 1931 | /* |
cf9328cc AL |
1932 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1933 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1934 | */ |
cfda7bb9 AL |
1935 | |
1936 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1937 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1938 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1939 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1940 | |
cfda7bb9 AL |
1941 | put_cpu(); |
1942 | } | |
e04d645f GC |
1943 | #endif |
1944 | ||
a6c4e076 JF |
1945 | void __init identify_boot_cpu(void) |
1946 | { | |
1947 | identify_cpu(&boot_cpu_data); | |
991625f3 PZ |
1948 | if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) |
1949 | pr_info("CET detected: Indirect Branch Tracking enabled\n"); | |
102bbe3a | 1950 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1951 | sysenter_setup(); |
6fe940d6 | 1952 | enable_sep_cpu(); |
102bbe3a | 1953 | #endif |
5b556332 | 1954 | cpu_detect_tlb(&boot_cpu_data); |
873d50d5 | 1955 | setup_cr_pinning(); |
95c5824f PG |
1956 | |
1957 | tsx_init(); | |
a6c4e076 | 1958 | } |
3b520b23 | 1959 | |
148f9bb8 | 1960 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1961 | { |
1962 | BUG_ON(c == &boot_cpu_data); | |
1963 | identify_cpu(c); | |
102bbe3a | 1964 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1965 | enable_sep_cpu(); |
102bbe3a | 1966 | #endif |
a6c4e076 | 1967 | mtrr_ap_init(); |
9d85eb91 | 1968 | validate_apic_and_package_id(c); |
77243971 | 1969 | x86_spec_ctrl_setup_ap(); |
7e5b3c26 | 1970 | update_srbds_msr(); |
400331f8 PG |
1971 | |
1972 | tsx_ap_init(); | |
1da177e4 LT |
1973 | } |
1974 | ||
148f9bb8 | 1975 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1976 | { |
02dde8b4 | 1977 | const char *vendor = NULL; |
1da177e4 | 1978 | |
0f3fa48a | 1979 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1980 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1981 | } else { |
1982 | if (c->cpuid_level >= 0) | |
1983 | vendor = c->x86_vendor_id; | |
1984 | } | |
1da177e4 | 1985 | |
bd32a8cf | 1986 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1987 | pr_cont("%s ", vendor); |
1da177e4 | 1988 | |
9d31d35b | 1989 | if (c->x86_model_id[0]) |
1b74dde7 | 1990 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1991 | else |
1b74dde7 | 1992 | pr_cont("%d86", c->x86); |
1da177e4 | 1993 | |
1b74dde7 | 1994 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1995 | |
b399151c JZ |
1996 | if (c->x86_stepping || c->cpuid_level >= 0) |
1997 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1998 | else |
1b74dde7 | 1999 | pr_cont(")\n"); |
1da177e4 LT |
2000 | } |
2001 | ||
0c2a3913 | 2002 | /* |
ce38f038 TG |
2003 | * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy |
2004 | * function prevents it from becoming an environment variable for init. | |
0c2a3913 AK |
2005 | */ |
2006 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 2007 | { |
ac72e788 AK |
2008 | return 1; |
2009 | } | |
0c2a3913 | 2010 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 2011 | |
d5494d4f | 2012 | #ifdef CONFIG_X86_64 |
e6401c13 AL |
2013 | DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, |
2014 | fixed_percpu_data) __aligned(PAGE_SIZE) __visible; | |
2015 | EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); | |
0f3fa48a | 2016 | |
bdf977b3 | 2017 | /* |
a7fcf28d AL |
2018 | * The following percpu variables are hot. Align current_task to |
2019 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
2020 | */ |
2021 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
2022 | &init_task; | |
2023 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 2024 | |
951c2a51 | 2025 | DEFINE_PER_CPU(void *, hardirq_stack_ptr); |
e7f89001 | 2026 | DEFINE_PER_CPU(bool, hardirq_stack_inuse); |
d5494d4f | 2027 | |
c2daa3be PZ |
2028 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
2029 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
2030 | ||
1591584e LJ |
2031 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; |
2032 | ||
9c7e2634 AK |
2033 | static void wrmsrl_cstar(unsigned long val) |
2034 | { | |
2035 | /* | |
2036 | * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR | |
2037 | * is so far ignored by the CPU, but raises a #VE trap in a TDX | |
2038 | * guest. Avoid the pointless write on all Intel CPUs. | |
2039 | */ | |
2040 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
2041 | wrmsrl(MSR_CSTAR, val); | |
2042 | } | |
2043 | ||
d5494d4f YL |
2044 | /* May not be marked __init: used by software suspend */ |
2045 | void syscall_init(void) | |
1da177e4 | 2046 | { |
31ac34ca | 2047 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
bf904d27 | 2048 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
2049 | |
2050 | #ifdef CONFIG_IA32_EMULATION | |
9c7e2634 | 2051 | wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 2052 | /* |
487d1edb DV |
2053 | * This only works on Intel CPUs. |
2054 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
2055 | * This does not cause SYSENTER to jump to the wrong location, because | |
2056 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
2057 | */ |
2058 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
8e6b65a1 | 2059 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, |
2060 | (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); | |
4c8cd0c5 | 2061 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 2062 | #else |
9c7e2634 | 2063 | wrmsrl_cstar((unsigned long)ignore_sysret); |
6b51311c | 2064 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
2065 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
2066 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 2067 | #endif |
03ae5768 | 2068 | |
6de4ac1d PAI |
2069 | /* |
2070 | * Flags to clear on syscall; clear as much as possible | |
2071 | * to minimize user space-kernel interference. | |
2072 | */ | |
d5494d4f | 2073 | wrmsrl(MSR_SYSCALL_MASK, |
6de4ac1d PAI |
2074 | X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| |
2075 | X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| | |
2076 | X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| | |
2077 | X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| | |
2078 | X86_EFLAGS_AC|X86_EFLAGS_ID); | |
1da177e4 | 2079 | } |
62111195 | 2080 | |
0f3fa48a | 2081 | #else /* CONFIG_X86_64 */ |
d5494d4f | 2082 | |
bdf977b3 TH |
2083 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
2084 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
2085 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
2086 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 2087 | |
a7fcf28d AL |
2088 | /* |
2089 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
2090 | * the top of the kernel stack. Use an extra percpu variable to track the | |
2091 | * top of the kernel stack directly. | |
2092 | */ | |
2093 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
2094 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
2095 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
2096 | ||
050e9baa | 2097 | #ifdef CONFIG_STACKPROTECTOR |
3fb0fdb3 AL |
2098 | DEFINE_PER_CPU(unsigned long, __stack_chk_guard); |
2099 | EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); | |
60a5317f | 2100 | #endif |
d5494d4f | 2101 | |
0f3fa48a | 2102 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 2103 | |
9766cdbc JSR |
2104 | /* |
2105 | * Clear all 6 debug registers: | |
2106 | */ | |
2107 | static void clear_all_debug_regs(void) | |
2108 | { | |
2109 | int i; | |
2110 | ||
2111 | for (i = 0; i < 8; i++) { | |
2112 | /* Ignore db4, db5 */ | |
2113 | if ((i == 4) || (i == 5)) | |
2114 | continue; | |
2115 | ||
2116 | set_debugreg(0, i); | |
2117 | } | |
2118 | } | |
c5413fbe | 2119 | |
0bb9fef9 JW |
2120 | #ifdef CONFIG_KGDB |
2121 | /* | |
2122 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
2123 | * connection established. | |
2124 | */ | |
2125 | static void dbg_restore_debug_regs(void) | |
2126 | { | |
2127 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
2128 | arch_kgdb_ops.correct_hw_break(); | |
2129 | } | |
2130 | #else /* ! CONFIG_KGDB */ | |
2131 | #define dbg_restore_debug_regs() | |
2132 | #endif /* ! CONFIG_KGDB */ | |
2133 | ||
ce4b1b16 IM |
2134 | static void wait_for_master_cpu(int cpu) |
2135 | { | |
2136 | #ifdef CONFIG_SMP | |
2137 | /* | |
2138 | * wait for ACK from master CPU before continuing | |
2139 | * with AP initialization | |
2140 | */ | |
2141 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
2142 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
2143 | cpu_relax(); | |
2144 | #endif | |
2145 | } | |
2146 | ||
b2e2ba57 | 2147 | #ifdef CONFIG_X86_64 |
505b7899 | 2148 | static inline void setup_getcpu(int cpu) |
b2e2ba57 | 2149 | { |
22245bdf | 2150 | unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); |
b2e2ba57 CB |
2151 | struct desc_struct d = { }; |
2152 | ||
b6b4fbd9 | 2153 | if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) |
fc48a6d1 | 2154 | wrmsr(MSR_TSC_AUX, cpudata, 0); |
b2e2ba57 CB |
2155 | |
2156 | /* Store CPU and node number in limit. */ | |
2157 | d.limit0 = cpudata; | |
2158 | d.limit1 = cpudata >> 16; | |
2159 | ||
2160 | d.type = 5; /* RO data, expand down, accessed */ | |
2161 | d.dpl = 3; /* Visible to user code */ | |
2162 | d.s = 1; /* Not a system segment */ | |
2163 | d.p = 1; /* Present */ | |
2164 | d.d = 1; /* 32-bit */ | |
2165 | ||
22245bdf | 2166 | write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); |
b2e2ba57 | 2167 | } |
505b7899 TG |
2168 | |
2169 | static inline void ucode_cpu_init(int cpu) | |
2170 | { | |
2171 | if (cpu) | |
2172 | load_ucode_ap(); | |
2173 | } | |
2174 | ||
2175 | static inline void tss_setup_ist(struct tss_struct *tss) | |
2176 | { | |
2177 | /* Set up the per-CPU TSS IST stacks */ | |
2178 | tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); | |
2179 | tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); | |
2180 | tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); | |
2181 | tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); | |
02772fb9 JR |
2182 | /* Only mapped when SEV-ES is active */ |
2183 | tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); | |
505b7899 TG |
2184 | } |
2185 | ||
505b7899 TG |
2186 | #else /* CONFIG_X86_64 */ |
2187 | ||
2188 | static inline void setup_getcpu(int cpu) { } | |
2189 | ||
2190 | static inline void ucode_cpu_init(int cpu) | |
2191 | { | |
2192 | show_ucode_info_early(); | |
2193 | } | |
2194 | ||
2195 | static inline void tss_setup_ist(struct tss_struct *tss) { } | |
2196 | ||
505b7899 | 2197 | #endif /* !CONFIG_X86_64 */ |
b2e2ba57 | 2198 | |
111e7b15 TG |
2199 | static inline void tss_setup_io_bitmap(struct tss_struct *tss) |
2200 | { | |
2201 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; | |
2202 | ||
2203 | #ifdef CONFIG_X86_IOPL_IOPERM | |
2204 | tss->io_bitmap.prev_max = 0; | |
2205 | tss->io_bitmap.prev_sequence = 0; | |
2206 | memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); | |
2207 | /* | |
2208 | * Invalidate the extra array entry past the end of the all | |
2209 | * permission bitmap as required by the hardware. | |
2210 | */ | |
2211 | tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; | |
b2e2ba57 | 2212 | #endif |
111e7b15 | 2213 | } |
b2e2ba57 | 2214 | |
520d0308 JR |
2215 | /* |
2216 | * Setup everything needed to handle exceptions from the IDT, including the IST | |
2217 | * exceptions which use paranoid_entry(). | |
2218 | */ | |
2219 | void cpu_init_exception_handling(void) | |
2220 | { | |
2221 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); | |
2222 | int cpu = raw_smp_processor_id(); | |
2223 | ||
2224 | /* paranoid_entry() gets the CPU number from the GDT */ | |
2225 | setup_getcpu(cpu); | |
2226 | ||
2227 | /* IST vectors need TSS to be set up. */ | |
2228 | tss_setup_ist(tss); | |
2229 | tss_setup_io_bitmap(tss); | |
2230 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); | |
2231 | ||
2232 | load_TR_desc(); | |
2233 | ||
95d33bfa BS |
2234 | /* GHCB needs to be setup to handle #VC. */ |
2235 | setup_ghcb(); | |
2236 | ||
520d0308 JR |
2237 | /* Finally load the IDT */ |
2238 | load_current_idt(); | |
2239 | } | |
2240 | ||
d2cbcc49 RR |
2241 | /* |
2242 | * cpu_init() initializes state that is per-CPU. Some data is already | |
b1efd0ff BP |
2243 | * initialized (naturally) in the bootstrap process, such as the GDT. We |
2244 | * reload it nevertheless, this function acts as a 'CPU state barrier', | |
2245 | * nothing should get across. | |
d2cbcc49 | 2246 | */ |
148f9bb8 | 2247 | void cpu_init(void) |
1ba76586 | 2248 | { |
505b7899 | 2249 | struct task_struct *cur = current; |
f6ef7322 | 2250 | int cpu = raw_smp_processor_id(); |
1ba76586 | 2251 | |
ce4b1b16 IM |
2252 | wait_for_master_cpu(cpu); |
2253 | ||
505b7899 | 2254 | ucode_cpu_init(cpu); |
0f3fa48a | 2255 | |
e7a22c1e | 2256 | #ifdef CONFIG_NUMA |
27fd185f | 2257 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
2258 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
2259 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 2260 | #endif |
2eaad1fd | 2261 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 2262 | |
505b7899 TG |
2263 | if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || |
2264 | boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) | |
2265 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1ba76586 | 2266 | |
505b7899 TG |
2267 | if (IS_ENABLED(CONFIG_X86_64)) { |
2268 | loadsegment(fs, 0); | |
2269 | memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
2270 | syscall_init(); | |
1ba76586 | 2271 | |
505b7899 TG |
2272 | wrmsrl(MSR_FS_BASE, 0); |
2273 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
2274 | barrier(); | |
1ba76586 | 2275 | |
505b7899 | 2276 | x2apic_setup(); |
1ba76586 YL |
2277 | } |
2278 | ||
f1f10076 | 2279 | mmgrab(&init_mm); |
505b7899 TG |
2280 | cur->active_mm = &init_mm; |
2281 | BUG_ON(cur->mm); | |
72c0098d | 2282 | initialize_tlbstate_and_flush(); |
505b7899 | 2283 | enter_lazy_tlb(&init_mm, cur); |
1ba76586 | 2284 | |
505b7899 TG |
2285 | /* |
2286 | * sp0 points to the entry trampoline stack regardless of what task | |
2287 | * is running. | |
2288 | */ | |
4fe2d8b1 | 2289 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 2290 | |
37868fe1 | 2291 | load_mm_ldt(&init_mm); |
1ba76586 | 2292 | |
0bb9fef9 JW |
2293 | clear_all_debug_regs(); |
2294 | dbg_restore_debug_regs(); | |
1ba76586 | 2295 | |
dc4e0021 | 2296 | doublefault_init_cpu_tss(); |
505b7899 | 2297 | |
21c4cd10 | 2298 | fpu__init_cpu(); |
1ba76586 | 2299 | |
1ba76586 YL |
2300 | if (is_uv_system()) |
2301 | uv_cpu_init(); | |
69218e47 | 2302 | |
69218e47 | 2303 | load_fixmap_gdt(cpu); |
1ba76586 YL |
2304 | } |
2305 | ||
b1efd0ff BP |
2306 | #ifdef CONFIG_SMP |
2307 | void cpu_init_secondary(void) | |
2308 | { | |
2309 | /* | |
2310 | * Relies on the BP having set-up the IDT tables, which are loaded | |
2311 | * on this CPU in cpu_init_exception_handling(). | |
2312 | */ | |
2313 | cpu_init_exception_handling(); | |
2314 | cpu_init(); | |
2315 | } | |
2316 | #endif | |
2317 | ||
a77a94f8 | 2318 | #ifdef CONFIG_MICROCODE_LATE_LOADING |
1008c52c BP |
2319 | /* |
2320 | * The microcode loader calls this upon late microcode load to recheck features, | |
2321 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
2322 | * hotplug lock. | |
2323 | */ | |
2324 | void microcode_check(void) | |
2325 | { | |
42ca8082 BP |
2326 | struct cpuinfo_x86 info; |
2327 | ||
1008c52c | 2328 | perf_check_microcode(); |
42ca8082 BP |
2329 | |
2330 | /* Reload CPUID max function as it might've changed. */ | |
2331 | info.cpuid_level = cpuid_eax(0); | |
2332 | ||
2333 | /* | |
2334 | * Copy all capability leafs to pick up the synthetic ones so that | |
2335 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
2336 | * get overwritten in get_cpu_cap(). | |
2337 | */ | |
2338 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
2339 | ||
2340 | get_cpu_cap(&info); | |
2341 | ||
2342 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
2343 | return; | |
2344 | ||
2345 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
2346 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 2347 | } |
a77a94f8 | 2348 | #endif |
9c92374b TG |
2349 | |
2350 | /* | |
2351 | * Invoked from core CPU hotplug code after hotplug operations | |
2352 | */ | |
2353 | void arch_smt_update(void) | |
2354 | { | |
2355 | /* Handle the speculative execution misfeatures */ | |
2356 | cpu_bugs_smt_update(); | |
6a1cb5f5 TG |
2357 | /* Check whether IPI broadcasting can be enabled */ |
2358 | apic_smt_update(); | |
9c92374b | 2359 | } |