Commit | Line | Data |
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1da177e4 | 1 | #include <linux/init.h> |
f0fc4aff YL |
2 | #include <linux/kernel.h> |
3 | #include <linux/sched.h> | |
1da177e4 | 4 | #include <linux/string.h> |
f0fc4aff YL |
5 | #include <linux/bootmem.h> |
6 | #include <linux/bitops.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/kgdb.h> | |
9 | #include <linux/topology.h> | |
1da177e4 LT |
10 | #include <linux/delay.h> |
11 | #include <linux/smp.h> | |
1da177e4 | 12 | #include <linux/percpu.h> |
1da177e4 LT |
13 | #include <asm/i387.h> |
14 | #include <asm/msr.h> | |
15 | #include <asm/io.h> | |
f0fc4aff | 16 | #include <asm/linkage.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
27b07da7 | 18 | #include <asm/mtrr.h> |
a03a3e28 | 19 | #include <asm/mce.h> |
8d4a4300 | 20 | #include <asm/pat.h> |
b6734c35 | 21 | #include <asm/asm.h> |
f0fc4aff | 22 | #include <asm/numa.h> |
b342797c | 23 | #include <asm/smp.h> |
f472cdba | 24 | #include <asm/cpu.h> |
06879033 | 25 | #include <asm/cpumask.h> |
7b6aa335 | 26 | #include <asm/apic.h> |
e641f5f5 IM |
27 | |
28 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 29 | #include <asm/uv/uv.h> |
1da177e4 LT |
30 | #endif |
31 | ||
f0fc4aff YL |
32 | #include <asm/pgtable.h> |
33 | #include <asm/processor.h> | |
34 | #include <asm/desc.h> | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/proto.h> | |
37 | #include <asm/sections.h> | |
38 | #include <asm/setup.h> | |
88b094fb | 39 | #include <asm/hypervisor.h> |
60a5317f | 40 | #include <asm/stackprotector.h> |
f0fc4aff | 41 | |
1da177e4 LT |
42 | #include "cpu.h" |
43 | ||
c2d1cec1 MT |
44 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
45 | cpumask_var_t cpu_callin_mask; | |
46 | cpumask_var_t cpu_callout_mask; | |
47 | cpumask_var_t cpu_initialized_mask; | |
48 | ||
49 | /* representing cpus for which sibling maps can be computed */ | |
50 | cpumask_var_t cpu_sibling_setup_mask; | |
51 | ||
2f2f52ba | 52 | /* correctly size the local cpu masks */ |
4369f1fb | 53 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
54 | { |
55 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
56 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
57 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
58 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
59 | } | |
60 | ||
0a488a53 YL |
61 | static struct cpu_dev *this_cpu __cpuinitdata; |
62 | ||
06deef89 | 63 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 64 | #ifdef CONFIG_X86_64 |
06deef89 BG |
65 | /* |
66 | * We need valid kernel segments for data and code in long mode too | |
67 | * IRET will check the segment types kkeil 2000/10/28 | |
68 | * Also sysret mandates a special GDT layout | |
69 | * | |
70 | * The TLS descriptors are currently at a different place compared to i386. | |
71 | * Hopefully nobody expects them at a fixed place (Wine?) | |
72 | */ | |
950ad7ff YL |
73 | [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } }, |
74 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } }, | |
75 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } }, | |
76 | [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } }, | |
77 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } }, | |
78 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } }, | |
950ad7ff | 79 | #else |
6842ef0e GOC |
80 | [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } }, |
81 | [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } }, | |
82 | [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } }, | |
83 | [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } }, | |
bf504672 RR |
84 | /* |
85 | * Segments used for calling PnP BIOS have byte granularity. | |
86 | * They code segments and data segments have fixed 64k limits, | |
87 | * the transfer segment sizes are set at run time. | |
88 | */ | |
6842ef0e GOC |
89 | /* 32-bit code */ |
90 | [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } }, | |
91 | /* 16-bit code */ | |
92 | [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } }, | |
93 | /* 16-bit data */ | |
94 | [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } }, | |
95 | /* 16-bit data */ | |
96 | [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } }, | |
97 | /* 16-bit data */ | |
98 | [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } }, | |
bf504672 RR |
99 | /* |
100 | * The APM segments have byte granularity and their bases | |
101 | * are set at run time. All have 64k limits. | |
102 | */ | |
6842ef0e GOC |
103 | /* 32-bit code */ |
104 | [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } }, | |
bf504672 | 105 | /* 16-bit code */ |
6842ef0e GOC |
106 | [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } }, |
107 | /* data */ | |
108 | [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } }, | |
bf504672 | 109 | |
6842ef0e | 110 | [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } }, |
0dd76d73 | 111 | [GDT_ENTRY_PERCPU] = { { { 0x0000ffff, 0x00cf9200 } } }, |
60a5317f | 112 | GDT_STACK_CANARY_INIT |
950ad7ff | 113 | #endif |
06deef89 | 114 | } }; |
7a61d35d | 115 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 116 | |
ba51dced | 117 | #ifdef CONFIG_X86_32 |
3bc9b76b | 118 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 119 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 120 | |
0a488a53 YL |
121 | static int __init cachesize_setup(char *str) |
122 | { | |
123 | get_option(&str, &cachesize_override); | |
124 | return 1; | |
125 | } | |
126 | __setup("cachesize=", cachesize_setup); | |
127 | ||
0a488a53 YL |
128 | static int __init x86_fxsr_setup(char *s) |
129 | { | |
130 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
131 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
132 | return 1; | |
133 | } | |
134 | __setup("nofxsr", x86_fxsr_setup); | |
135 | ||
136 | static int __init x86_sep_setup(char *s) | |
137 | { | |
138 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
139 | return 1; | |
140 | } | |
141 | __setup("nosep", x86_sep_setup); | |
142 | ||
143 | /* Standard macro to see if a specific flag is changeable */ | |
144 | static inline int flag_is_changeable_p(u32 flag) | |
145 | { | |
146 | u32 f1, f2; | |
147 | ||
94f6bac1 KH |
148 | /* |
149 | * Cyrix and IDT cpus allow disabling of CPUID | |
150 | * so the code below may return different results | |
151 | * when it is executed before and after enabling | |
152 | * the CPUID. Add "volatile" to not allow gcc to | |
153 | * optimize the subsequent calls to this function. | |
154 | */ | |
155 | asm volatile ("pushfl\n\t" | |
156 | "pushfl\n\t" | |
157 | "popl %0\n\t" | |
158 | "movl %0,%1\n\t" | |
159 | "xorl %2,%0\n\t" | |
160 | "pushl %0\n\t" | |
161 | "popfl\n\t" | |
162 | "pushfl\n\t" | |
163 | "popl %0\n\t" | |
164 | "popfl\n\t" | |
165 | : "=&r" (f1), "=&r" (f2) | |
166 | : "ir" (flag)); | |
0a488a53 YL |
167 | |
168 | return ((f1^f2) & flag) != 0; | |
169 | } | |
170 | ||
171 | /* Probe for the CPUID instruction */ | |
172 | static int __cpuinit have_cpuid_p(void) | |
173 | { | |
174 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
175 | } | |
176 | ||
177 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
178 | { | |
179 | if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) { | |
180 | /* Disable processor serial number */ | |
181 | unsigned long lo, hi; | |
182 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
183 | lo |= 0x200000; | |
184 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
185 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
186 | clear_cpu_cap(c, X86_FEATURE_PN); | |
187 | ||
188 | /* Disabling the serial number may affect the cpuid level */ | |
189 | c->cpuid_level = cpuid_eax(0); | |
190 | } | |
191 | } | |
192 | ||
193 | static int __init x86_serial_nr_setup(char *s) | |
194 | { | |
195 | disable_x86_serial_nr = 0; | |
196 | return 1; | |
197 | } | |
198 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 199 | #else |
102bbe3a YL |
200 | static inline int flag_is_changeable_p(u32 flag) |
201 | { | |
202 | return 1; | |
203 | } | |
ba51dced YL |
204 | /* Probe for the CPUID instruction */ |
205 | static inline int have_cpuid_p(void) | |
206 | { | |
207 | return 1; | |
208 | } | |
102bbe3a YL |
209 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
210 | { | |
211 | } | |
ba51dced | 212 | #endif |
0a488a53 | 213 | |
b38b0665 PA |
214 | /* |
215 | * Some CPU features depend on higher CPUID levels, which may not always | |
216 | * be available due to CPUID level capping or broken virtualization | |
217 | * software. Add those features to this table to auto-disable them. | |
218 | */ | |
219 | struct cpuid_dependent_feature { | |
220 | u32 feature; | |
221 | u32 level; | |
222 | }; | |
223 | static const struct cpuid_dependent_feature __cpuinitconst | |
224 | cpuid_dependent_features[] = { | |
225 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
226 | { X86_FEATURE_DCA, 0x00000009 }, | |
227 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
228 | { 0, 0 } | |
229 | }; | |
230 | ||
231 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
232 | { | |
233 | const struct cpuid_dependent_feature *df; | |
234 | for (df = cpuid_dependent_features; df->feature; df++) { | |
235 | /* | |
236 | * Note: cpuid_level is set to -1 if unavailable, but | |
237 | * extended_extended_level is set to 0 if unavailable | |
238 | * and the legitimate extended levels are all negative | |
239 | * when signed; hence the weird messing around with | |
240 | * signs here... | |
241 | */ | |
242 | if (cpu_has(c, df->feature) && | |
f6db44df YL |
243 | ((s32)df->level < 0 ? |
244 | (u32)df->level > (u32)c->extended_cpuid_level : | |
245 | (s32)df->level > (s32)c->cpuid_level)) { | |
b38b0665 PA |
246 | clear_cpu_cap(c, df->feature); |
247 | if (warn) | |
248 | printk(KERN_WARNING | |
249 | "CPU: CPU feature %s disabled " | |
250 | "due to lack of CPUID level 0x%x\n", | |
251 | x86_cap_flags[df->feature], | |
252 | df->level); | |
253 | } | |
254 | } | |
f6db44df | 255 | } |
b38b0665 | 256 | |
102bbe3a YL |
257 | /* |
258 | * Naming convention should be: <Name> [(<Codename>)] | |
259 | * This table only is used unless init_<vendor>() below doesn't set it; | |
260 | * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used | |
261 | * | |
262 | */ | |
263 | ||
264 | /* Look up CPU names by table lookup. */ | |
265 | static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c) | |
266 | { | |
267 | struct cpu_model_info *info; | |
268 | ||
269 | if (c->x86_model >= 16) | |
270 | return NULL; /* Range check */ | |
271 | ||
272 | if (!this_cpu) | |
273 | return NULL; | |
274 | ||
275 | info = this_cpu->c_models; | |
276 | ||
277 | while (info && info->family) { | |
278 | if (info->family == c->x86) | |
279 | return info->model_names[c->x86_model]; | |
280 | info++; | |
281 | } | |
282 | return NULL; /* Not found */ | |
283 | } | |
284 | ||
7d851c8d AK |
285 | __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata; |
286 | ||
11e3a840 JF |
287 | void load_percpu_segment(int cpu) |
288 | { | |
289 | #ifdef CONFIG_X86_32 | |
290 | loadsegment(fs, __KERNEL_PERCPU); | |
291 | #else | |
292 | loadsegment(gs, 0); | |
293 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
294 | #endif | |
60a5317f | 295 | load_stack_canary_segment(); |
11e3a840 JF |
296 | } |
297 | ||
9d31d35b YL |
298 | /* Current gdt points %fs at the "master" per-cpu area: after this, |
299 | * it's on the real one. */ | |
552be871 | 300 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
301 | { |
302 | struct desc_ptr gdt_descr; | |
303 | ||
2697fbd5 | 304 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
305 | gdt_descr.size = GDT_SIZE - 1; |
306 | load_gdt(&gdt_descr); | |
2697fbd5 | 307 | /* Reload the per-cpu base */ |
11e3a840 JF |
308 | |
309 | load_percpu_segment(cpu); | |
9d31d35b YL |
310 | } |
311 | ||
10a434fc | 312 | static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 313 | |
34048c9e | 314 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
1da177e4 | 315 | { |
b9e67f00 YL |
316 | #ifdef CONFIG_X86_64 |
317 | display_cacheinfo(c); | |
318 | #else | |
1da177e4 LT |
319 | /* Not much we can do here... */ |
320 | /* Check if at least it has cpuid */ | |
321 | if (c->cpuid_level == -1) { | |
322 | /* No cpuid. It must be an ancient CPU */ | |
323 | if (c->x86 == 4) | |
324 | strcpy(c->x86_model_id, "486"); | |
325 | else if (c->x86 == 3) | |
326 | strcpy(c->x86_model_id, "386"); | |
327 | } | |
b9e67f00 | 328 | #endif |
1da177e4 LT |
329 | } |
330 | ||
95414930 | 331 | static struct cpu_dev __cpuinitdata default_cpu = { |
1da177e4 | 332 | .c_init = default_init, |
fe38d855 | 333 | .c_vendor = "Unknown", |
10a434fc | 334 | .c_x86_vendor = X86_VENDOR_UNKNOWN, |
1da177e4 | 335 | }; |
1da177e4 | 336 | |
1b05d60d | 337 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
338 | { |
339 | unsigned int *v; | |
340 | char *p, *q; | |
341 | ||
3da99c97 | 342 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 343 | return; |
1da177e4 LT |
344 | |
345 | v = (unsigned int *) c->x86_model_id; | |
346 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); | |
347 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
348 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
349 | c->x86_model_id[48] = 0; | |
350 | ||
351 | /* Intel chips right-justify this string for some dumb reason; | |
352 | undo that brain damage */ | |
353 | p = q = &c->x86_model_id[0]; | |
34048c9e | 354 | while (*p == ' ') |
1da177e4 | 355 | p++; |
34048c9e PC |
356 | if (p != q) { |
357 | while (*p) | |
1da177e4 | 358 | *q++ = *p++; |
34048c9e | 359 | while (q <= &c->x86_model_id[48]) |
1da177e4 LT |
360 | *q++ = '\0'; /* Zero-pad the rest */ |
361 | } | |
1da177e4 LT |
362 | } |
363 | ||
3bc9b76b | 364 | void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c) |
1da177e4 | 365 | { |
9d31d35b | 366 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 367 | |
3da99c97 | 368 | n = c->extended_cpuid_level; |
1da177e4 LT |
369 | |
370 | if (n >= 0x80000005) { | |
9d31d35b | 371 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 372 | printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", |
9d31d35b YL |
373 | edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); |
374 | c->x86_cache_size = (ecx>>24) + (edx>>24); | |
140fc727 YL |
375 | #ifdef CONFIG_X86_64 |
376 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
377 | c->x86_tlbsize = 0; | |
378 | #endif | |
1da177e4 LT |
379 | } |
380 | ||
381 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
382 | return; | |
383 | ||
0a488a53 | 384 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 385 | l2size = ecx >> 16; |
34048c9e | 386 | |
140fc727 YL |
387 | #ifdef CONFIG_X86_64 |
388 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
389 | #else | |
1da177e4 LT |
390 | /* do processor-specific cache resizing */ |
391 | if (this_cpu->c_size_cache) | |
34048c9e | 392 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
393 | |
394 | /* Allow user to override all this if necessary. */ | |
395 | if (cachesize_override != -1) | |
396 | l2size = cachesize_override; | |
397 | ||
34048c9e | 398 | if (l2size == 0) |
1da177e4 | 399 | return; /* Again, no L2 cache is possible */ |
140fc727 | 400 | #endif |
1da177e4 LT |
401 | |
402 | c->x86_cache_size = l2size; | |
403 | ||
404 | printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n", | |
0a488a53 | 405 | l2size, ecx & 0xFF); |
1da177e4 LT |
406 | } |
407 | ||
9d31d35b | 408 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 409 | { |
97e4db7c | 410 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
411 | u32 eax, ebx, ecx, edx; |
412 | int index_msb, core_bits; | |
1da177e4 | 413 | |
0a488a53 | 414 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 415 | return; |
1da177e4 | 416 | |
0a488a53 YL |
417 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
418 | goto out; | |
1da177e4 | 419 | |
1cd78776 YL |
420 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
421 | return; | |
1da177e4 | 422 | |
0a488a53 | 423 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 424 | |
9d31d35b YL |
425 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
426 | ||
427 | if (smp_num_siblings == 1) { | |
428 | printk(KERN_INFO "CPU: Hyper-Threading is disabled\n"); | |
429 | } else if (smp_num_siblings > 1) { | |
430 | ||
9628937d | 431 | if (smp_num_siblings > nr_cpu_ids) { |
9d31d35b YL |
432 | printk(KERN_WARNING "CPU: Unsupported number of siblings %d", |
433 | smp_num_siblings); | |
434 | smp_num_siblings = 1; | |
435 | return; | |
436 | } | |
437 | ||
438 | index_msb = get_count_order(smp_num_siblings); | |
cb8cc442 | 439 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); |
9d31d35b YL |
440 | |
441 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; | |
442 | ||
443 | index_msb = get_count_order(smp_num_siblings); | |
444 | ||
445 | core_bits = get_count_order(c->x86_max_cores); | |
446 | ||
cb8cc442 | 447 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
1cd78776 | 448 | ((1 << core_bits) - 1); |
1da177e4 | 449 | } |
1da177e4 | 450 | |
0a488a53 YL |
451 | out: |
452 | if ((c->x86_max_cores * smp_num_siblings) > 1) { | |
453 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", | |
454 | c->phys_proc_id); | |
455 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
456 | c->cpu_core_id); | |
9d31d35b | 457 | } |
9d31d35b | 458 | #endif |
97e4db7c | 459 | } |
1da177e4 | 460 | |
3da99c97 | 461 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
462 | { |
463 | char *v = c->x86_vendor_id; | |
464 | int i; | |
fe38d855 | 465 | static int printed; |
1da177e4 LT |
466 | |
467 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
468 | if (!cpu_devs[i]) |
469 | break; | |
470 | ||
471 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
472 | (cpu_devs[i]->c_ident[1] && | |
473 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
474 | this_cpu = cpu_devs[i]; | |
475 | c->x86_vendor = this_cpu->c_x86_vendor; | |
476 | return; | |
1da177e4 LT |
477 | } |
478 | } | |
10a434fc | 479 | |
fe38d855 CE |
480 | if (!printed) { |
481 | printed++; | |
43603c8d | 482 | printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v); |
fe38d855 CE |
483 | printk(KERN_ERR "CPU: Your system may be unstable.\n"); |
484 | } | |
10a434fc | 485 | |
fe38d855 CE |
486 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
487 | this_cpu = &default_cpu; | |
1da177e4 LT |
488 | } |
489 | ||
9d31d35b | 490 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 491 | { |
1da177e4 | 492 | /* Get vendor name */ |
4a148513 HH |
493 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
494 | (unsigned int *)&c->x86_vendor_id[0], | |
495 | (unsigned int *)&c->x86_vendor_id[8], | |
496 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 497 | |
1da177e4 | 498 | c->x86 = 4; |
9d31d35b | 499 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
500 | if (c->cpuid_level >= 0x00000001) { |
501 | u32 junk, tfms, cap0, misc; | |
502 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); | |
9d31d35b YL |
503 | c->x86 = (tfms >> 8) & 0xf; |
504 | c->x86_model = (tfms >> 4) & 0xf; | |
505 | c->x86_mask = tfms & 0xf; | |
f5f786d0 | 506 | if (c->x86 == 0xf) |
1da177e4 | 507 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 508 | if (c->x86 >= 0x6) |
9d31d35b | 509 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
d4387bd3 | 510 | if (cap0 & (1<<19)) { |
d4387bd3 | 511 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 512 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 513 | } |
1da177e4 | 514 | } |
1da177e4 | 515 | } |
3da99c97 YL |
516 | |
517 | static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) | |
093af8d7 YL |
518 | { |
519 | u32 tfms, xlvl; | |
3da99c97 | 520 | u32 ebx; |
093af8d7 | 521 | |
3da99c97 YL |
522 | /* Intel-defined flags: level 0x00000001 */ |
523 | if (c->cpuid_level >= 0x00000001) { | |
524 | u32 capability, excap; | |
525 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); | |
526 | c->x86_capability[0] = capability; | |
527 | c->x86_capability[4] = excap; | |
528 | } | |
093af8d7 | 529 | |
3da99c97 YL |
530 | /* AMD-defined flags: level 0x80000001 */ |
531 | xlvl = cpuid_eax(0x80000000); | |
532 | c->extended_cpuid_level = xlvl; | |
533 | if ((xlvl & 0xffff0000) == 0x80000000) { | |
534 | if (xlvl >= 0x80000001) { | |
535 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
536 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 537 | } |
093af8d7 | 538 | } |
093af8d7 | 539 | |
5122c890 | 540 | #ifdef CONFIG_X86_64 |
5122c890 YL |
541 | if (c->extended_cpuid_level >= 0x80000008) { |
542 | u32 eax = cpuid_eax(0x80000008); | |
543 | ||
544 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
545 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 546 | } |
5122c890 | 547 | #endif |
e3224234 YL |
548 | |
549 | if (c->extended_cpuid_level >= 0x80000007) | |
550 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 YL |
551 | |
552 | } | |
1da177e4 | 553 | |
aef93c8b YL |
554 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
555 | { | |
556 | #ifdef CONFIG_X86_32 | |
557 | int i; | |
558 | ||
559 | /* | |
560 | * First of all, decide if this is a 486 or higher | |
561 | * It's a 486 if we can modify the AC flag | |
562 | */ | |
563 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
564 | c->x86 = 4; | |
565 | else | |
566 | c->x86 = 3; | |
567 | ||
568 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
569 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
570 | c->x86_vendor_id[0] = 0; | |
571 | cpu_devs[i]->c_identify(c); | |
572 | if (c->x86_vendor_id[0]) { | |
573 | get_cpu_vendor(c); | |
574 | break; | |
575 | } | |
576 | } | |
577 | #endif | |
578 | } | |
579 | ||
34048c9e PC |
580 | /* |
581 | * Do minimum CPU detection early. | |
582 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
583 | * cache alignment. | |
584 | * The others are not touched to avoid unwanted side effects. | |
585 | * | |
586 | * WARNING: this function is only called on the BP. Don't add code here | |
587 | * that is supposed to run on all CPUs. | |
588 | */ | |
3da99c97 | 589 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 590 | { |
6627d242 YL |
591 | #ifdef CONFIG_X86_64 |
592 | c->x86_clflush_size = 64; | |
593 | #else | |
d4387bd3 | 594 | c->x86_clflush_size = 32; |
6627d242 | 595 | #endif |
0a488a53 | 596 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 597 | |
3da99c97 | 598 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 599 | c->extended_cpuid_level = 0; |
d7cd5611 | 600 | |
aef93c8b YL |
601 | if (!have_cpuid_p()) |
602 | identify_cpu_without_cpuid(c); | |
603 | ||
604 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
605 | if (!have_cpuid_p()) |
606 | return; | |
607 | ||
608 | cpu_detect(c); | |
609 | ||
3da99c97 | 610 | get_cpu_vendor(c); |
2b16a235 | 611 | |
3da99c97 | 612 | get_cpu_cap(c); |
12cf105c | 613 | |
10a434fc YL |
614 | if (this_cpu->c_early_init) |
615 | this_cpu->c_early_init(c); | |
093af8d7 | 616 | |
1c4acdb4 | 617 | #ifdef CONFIG_SMP |
bfcb4c1b | 618 | c->cpu_index = boot_cpu_id; |
1c4acdb4 | 619 | #endif |
b38b0665 | 620 | filter_cpuid_features(c, false); |
d7cd5611 RR |
621 | } |
622 | ||
9d31d35b YL |
623 | void __init early_cpu_init(void) |
624 | { | |
10a434fc YL |
625 | struct cpu_dev **cdev; |
626 | int count = 0; | |
627 | ||
628 | printk("KERNEL supported cpus:\n"); | |
629 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { | |
630 | struct cpu_dev *cpudev = *cdev; | |
631 | unsigned int j; | |
9d31d35b | 632 | |
10a434fc YL |
633 | if (count >= X86_VENDOR_NUM) |
634 | break; | |
635 | cpu_devs[count] = cpudev; | |
636 | count++; | |
637 | ||
638 | for (j = 0; j < 2; j++) { | |
639 | if (!cpudev->c_ident[j]) | |
640 | continue; | |
641 | printk(" %s %s\n", cpudev->c_vendor, | |
642 | cpudev->c_ident[j]); | |
643 | } | |
644 | } | |
9d31d35b | 645 | |
9d31d35b | 646 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 647 | } |
093af8d7 | 648 | |
b6734c35 PA |
649 | /* |
650 | * The NOPL instruction is supposed to exist on all CPUs with | |
ba0593bf | 651 | * family >= 6; unfortunately, that's not true in practice because |
b6734c35 | 652 | * of early VIA chips and (more importantly) broken virtualizers that |
ba0593bf PA |
653 | * are not easy to detect. In the latter case it doesn't even *fail* |
654 | * reliably, so probing for it doesn't even work. Disable it completely | |
655 | * unless we can find a reliable way to detect all the broken cases. | |
b6734c35 PA |
656 | */ |
657 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
658 | { | |
b6734c35 | 659 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
d7cd5611 RR |
660 | } |
661 | ||
34048c9e | 662 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 663 | { |
aef93c8b | 664 | c->extended_cpuid_level = 0; |
1da177e4 | 665 | |
3da99c97 | 666 | if (!have_cpuid_p()) |
aef93c8b | 667 | identify_cpu_without_cpuid(c); |
1d67953f | 668 | |
aef93c8b | 669 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 670 | if (!have_cpuid_p()) |
aef93c8b | 671 | return; |
1da177e4 | 672 | |
3da99c97 | 673 | cpu_detect(c); |
1da177e4 | 674 | |
3da99c97 | 675 | get_cpu_vendor(c); |
1da177e4 | 676 | |
3da99c97 | 677 | get_cpu_cap(c); |
1da177e4 | 678 | |
3da99c97 YL |
679 | if (c->cpuid_level >= 0x00000001) { |
680 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
681 | #ifdef CONFIG_X86_32 |
682 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 683 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 684 | # else |
3da99c97 | 685 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
686 | # endif |
687 | #endif | |
1da177e4 | 688 | |
b89d3b3e YL |
689 | #ifdef CONFIG_X86_HT |
690 | c->phys_proc_id = c->initial_apicid; | |
1e9f28fa | 691 | #endif |
3da99c97 | 692 | } |
1da177e4 | 693 | |
1b05d60d | 694 | get_model_name(c); /* Default name */ |
1da177e4 | 695 | |
3da99c97 YL |
696 | init_scattered_cpuid_features(c); |
697 | detect_nopl(c); | |
1da177e4 | 698 | } |
1da177e4 LT |
699 | |
700 | /* | |
701 | * This does the hard work of actually picking apart the CPU stuff... | |
702 | */ | |
9a250347 | 703 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
704 | { |
705 | int i; | |
706 | ||
707 | c->loops_per_jiffy = loops_per_jiffy; | |
708 | c->x86_cache_size = -1; | |
709 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
710 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
711 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
712 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 713 | c->x86_max_cores = 1; |
102bbe3a | 714 | c->x86_coreid_bits = 0; |
11fdd252 | 715 | #ifdef CONFIG_X86_64 |
102bbe3a YL |
716 | c->x86_clflush_size = 64; |
717 | #else | |
718 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 719 | c->x86_clflush_size = 32; |
102bbe3a YL |
720 | #endif |
721 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
722 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
723 | ||
1da177e4 LT |
724 | generic_identify(c); |
725 | ||
3898534d | 726 | if (this_cpu->c_identify) |
1da177e4 LT |
727 | this_cpu->c_identify(c); |
728 | ||
102bbe3a | 729 | #ifdef CONFIG_X86_64 |
cb8cc442 | 730 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
731 | #endif |
732 | ||
1da177e4 LT |
733 | /* |
734 | * Vendor-specific initialization. In this section we | |
735 | * canonicalize the feature flags, meaning if there are | |
736 | * features a certain CPU supports which CPUID doesn't | |
737 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
738 | * we handle them here. | |
739 | * | |
740 | * At the end of this section, c->x86_capability better | |
741 | * indicate the features this CPU genuinely supports! | |
742 | */ | |
743 | if (this_cpu->c_init) | |
744 | this_cpu->c_init(c); | |
745 | ||
746 | /* Disable the PN if appropriate */ | |
747 | squash_the_stupid_serial_number(c); | |
748 | ||
749 | /* | |
750 | * The vendor-specific functions might have changed features. Now | |
751 | * we do "generic changes." | |
752 | */ | |
753 | ||
b38b0665 PA |
754 | /* Filter out anything that depends on CPUID levels we don't have */ |
755 | filter_cpuid_features(c, true); | |
756 | ||
1da177e4 | 757 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 758 | if (!c->x86_model_id[0]) { |
1da177e4 LT |
759 | char *p; |
760 | p = table_lookup_model(c); | |
34048c9e | 761 | if (p) |
1da177e4 LT |
762 | strcpy(c->x86_model_id, p); |
763 | else | |
764 | /* Last resort... */ | |
765 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 766 | c->x86, c->x86_model); |
1da177e4 LT |
767 | } |
768 | ||
102bbe3a YL |
769 | #ifdef CONFIG_X86_64 |
770 | detect_ht(c); | |
771 | #endif | |
772 | ||
88b094fb | 773 | init_hypervisor(c); |
1da177e4 LT |
774 | /* |
775 | * On SMP, boot_cpu_data holds the common feature set between | |
776 | * all CPUs; so make sure that we indicate which features are | |
777 | * common between the CPUs. The first time this routine gets | |
778 | * executed, c == &boot_cpu_data. | |
779 | */ | |
34048c9e | 780 | if (c != &boot_cpu_data) { |
1da177e4 | 781 | /* AND the already accumulated flags with these */ |
9d31d35b | 782 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
783 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
784 | } | |
785 | ||
7d851c8d AK |
786 | /* Clear all flags overriden by options */ |
787 | for (i = 0; i < NCAPINTS; i++) | |
12c247a6 | 788 | c->x86_capability[i] &= ~cleared_cpu_caps[i]; |
7d851c8d | 789 | |
102bbe3a | 790 | #ifdef CONFIG_X86_MCE |
1da177e4 | 791 | /* Init Machine Check Exception if available. */ |
1da177e4 | 792 | mcheck_init(c); |
102bbe3a | 793 | #endif |
30d432df AK |
794 | |
795 | select_idle_routine(c); | |
102bbe3a YL |
796 | |
797 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64) | |
798 | numa_add_cpu(smp_processor_id()); | |
799 | #endif | |
a6c4e076 | 800 | } |
31ab269a | 801 | |
e04d645f GC |
802 | #ifdef CONFIG_X86_64 |
803 | static void vgetcpu_set_mode(void) | |
804 | { | |
805 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
806 | vgetcpu_mode = VGETCPU_RDTSCP; | |
807 | else | |
808 | vgetcpu_mode = VGETCPU_LSL; | |
809 | } | |
810 | #endif | |
811 | ||
a6c4e076 JF |
812 | void __init identify_boot_cpu(void) |
813 | { | |
814 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 815 | #ifdef CONFIG_X86_32 |
a6c4e076 | 816 | sysenter_setup(); |
6fe940d6 | 817 | enable_sep_cpu(); |
e04d645f GC |
818 | #else |
819 | vgetcpu_set_mode(); | |
102bbe3a | 820 | #endif |
a6c4e076 | 821 | } |
3b520b23 | 822 | |
a6c4e076 JF |
823 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
824 | { | |
825 | BUG_ON(c == &boot_cpu_data); | |
826 | identify_cpu(c); | |
102bbe3a | 827 | #ifdef CONFIG_X86_32 |
a6c4e076 | 828 | enable_sep_cpu(); |
102bbe3a | 829 | #endif |
a6c4e076 | 830 | mtrr_ap_init(); |
1da177e4 LT |
831 | } |
832 | ||
a0854a46 YL |
833 | struct msr_range { |
834 | unsigned min; | |
835 | unsigned max; | |
836 | }; | |
1da177e4 | 837 | |
a0854a46 YL |
838 | static struct msr_range msr_range_array[] __cpuinitdata = { |
839 | { 0x00000000, 0x00000418}, | |
840 | { 0xc0000000, 0xc000040b}, | |
841 | { 0xc0010000, 0xc0010142}, | |
842 | { 0xc0011000, 0xc001103b}, | |
843 | }; | |
1da177e4 | 844 | |
a0854a46 YL |
845 | static void __cpuinit print_cpu_msr(void) |
846 | { | |
847 | unsigned index; | |
848 | u64 val; | |
849 | int i; | |
850 | unsigned index_min, index_max; | |
851 | ||
852 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
853 | index_min = msr_range_array[i].min; | |
854 | index_max = msr_range_array[i].max; | |
855 | for (index = index_min; index < index_max; index++) { | |
856 | if (rdmsrl_amd_safe(index, &val)) | |
857 | continue; | |
858 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 859 | } |
a0854a46 YL |
860 | } |
861 | } | |
94605eff | 862 | |
a0854a46 YL |
863 | static int show_msr __cpuinitdata; |
864 | static __init int setup_show_msr(char *arg) | |
865 | { | |
866 | int num; | |
3dd9d514 | 867 | |
a0854a46 | 868 | get_option(&arg, &num); |
3dd9d514 | 869 | |
a0854a46 YL |
870 | if (num > 0) |
871 | show_msr = num; | |
872 | return 1; | |
1da177e4 | 873 | } |
a0854a46 | 874 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 875 | |
191679fd AK |
876 | static __init int setup_noclflush(char *arg) |
877 | { | |
878 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
879 | return 1; | |
880 | } | |
881 | __setup("noclflush", setup_noclflush); | |
882 | ||
3bc9b76b | 883 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 LT |
884 | { |
885 | char *vendor = NULL; | |
886 | ||
887 | if (c->x86_vendor < X86_VENDOR_NUM) | |
888 | vendor = this_cpu->c_vendor; | |
889 | else if (c->cpuid_level >= 0) | |
890 | vendor = c->x86_vendor_id; | |
891 | ||
bd32a8cf | 892 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 893 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 894 | |
9d31d35b YL |
895 | if (c->x86_model_id[0]) |
896 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 897 | else |
9d31d35b | 898 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 899 | |
34048c9e | 900 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 901 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 902 | else |
9d31d35b | 903 | printk(KERN_CONT "\n"); |
a0854a46 YL |
904 | |
905 | #ifdef CONFIG_SMP | |
906 | if (c->cpu_index < show_msr) | |
907 | print_cpu_msr(); | |
908 | #else | |
909 | if (show_msr) | |
910 | print_cpu_msr(); | |
911 | #endif | |
1da177e4 LT |
912 | } |
913 | ||
ac72e788 AK |
914 | static __init int setup_disablecpuid(char *arg) |
915 | { | |
916 | int bit; | |
917 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) | |
918 | setup_clear_cpu_cap(bit); | |
919 | else | |
920 | return 0; | |
921 | return 1; | |
922 | } | |
923 | __setup("clearcpuid=", setup_disablecpuid); | |
924 | ||
d5494d4f | 925 | #ifdef CONFIG_X86_64 |
d5494d4f YL |
926 | struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; |
927 | ||
947e76cd BG |
928 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
929 | irq_stack_union) __aligned(PAGE_SIZE); | |
26f80bd6 | 930 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
2add8e23 | 931 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; |
d5494d4f | 932 | |
9af45651 BG |
933 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
934 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
935 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
d5494d4f | 936 | |
56895530 | 937 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 938 | |
92d65b23 BG |
939 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
940 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]) | |
941 | __aligned(PAGE_SIZE); | |
d5494d4f YL |
942 | |
943 | extern asmlinkage void ignore_sysret(void); | |
944 | ||
945 | /* May not be marked __init: used by software suspend */ | |
946 | void syscall_init(void) | |
1da177e4 | 947 | { |
d5494d4f YL |
948 | /* |
949 | * LSTAR and STAR live in a bit strange symbiosis. | |
950 | * They both write to the same internal register. STAR allows to | |
951 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
952 | */ | |
953 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
954 | wrmsrl(MSR_LSTAR, system_call); | |
955 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 956 | |
d5494d4f YL |
957 | #ifdef CONFIG_IA32_EMULATION |
958 | syscall32_cpu_init(); | |
959 | #endif | |
03ae5768 | 960 | |
d5494d4f YL |
961 | /* Flags to clear on syscall */ |
962 | wrmsrl(MSR_SYSCALL_MASK, | |
963 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL); | |
1da177e4 | 964 | } |
62111195 | 965 | |
d5494d4f YL |
966 | unsigned long kernel_eflags; |
967 | ||
968 | /* | |
969 | * Copies of the original ist values from the tss are only accessed during | |
970 | * debugging, no special alignment required. | |
971 | */ | |
972 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
973 | ||
60a5317f | 974 | #else /* x86_64 */ |
d5494d4f | 975 | |
60a5317f TH |
976 | #ifdef CONFIG_CC_STACKPROTECTOR |
977 | DEFINE_PER_CPU(unsigned long, stack_canary); | |
978 | #endif | |
d5494d4f | 979 | |
60a5317f | 980 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 981 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
982 | { |
983 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 984 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 985 | regs->gs = __KERNEL_STACK_CANARY; |
f95d47ca JF |
986 | return regs; |
987 | } | |
60a5317f | 988 | #endif /* x86_64 */ |
c5413fbe | 989 | |
d2cbcc49 RR |
990 | /* |
991 | * cpu_init() initializes state that is per-CPU. Some data is already | |
992 | * initialized (naturally) in the bootstrap process, such as the GDT | |
993 | * and IDT. We reload them nevertheless, this function acts as a | |
994 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 995 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 996 | */ |
1ba76586 YL |
997 | #ifdef CONFIG_X86_64 |
998 | void __cpuinit cpu_init(void) | |
999 | { | |
1000 | int cpu = stack_smp_processor_id(); | |
1001 | struct tss_struct *t = &per_cpu(init_tss, cpu); | |
1002 | struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu); | |
1003 | unsigned long v; | |
1ba76586 YL |
1004 | struct task_struct *me; |
1005 | int i; | |
1006 | ||
e7a22c1e BG |
1007 | #ifdef CONFIG_NUMA |
1008 | if (cpu != 0 && percpu_read(node_number) == 0 && | |
1009 | cpu_to_node(cpu) != NUMA_NO_NODE) | |
1010 | percpu_write(node_number, cpu_to_node(cpu)); | |
1011 | #endif | |
1ba76586 YL |
1012 | |
1013 | me = current; | |
1014 | ||
c2d1cec1 | 1015 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1016 | panic("CPU#%d already initialized!\n", cpu); |
1017 | ||
1018 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1019 | ||
1020 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1021 | ||
1022 | /* | |
1023 | * Initialize the per-CPU GDT with the boot GDT, | |
1024 | * and set up the GDT descriptor: | |
1025 | */ | |
1026 | ||
552be871 | 1027 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1028 | loadsegment(fs, 0); |
1029 | ||
1ba76586 YL |
1030 | load_idt((const struct desc_ptr *)&idt_descr); |
1031 | ||
1032 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1033 | syscall_init(); | |
1034 | ||
1035 | wrmsrl(MSR_FS_BASE, 0); | |
1036 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1037 | barrier(); | |
1038 | ||
1039 | check_efer(); | |
06cd9a7d | 1040 | if (cpu != 0) |
1ba76586 YL |
1041 | enable_x2apic(); |
1042 | ||
1043 | /* | |
1044 | * set up and load the per-CPU TSS | |
1045 | */ | |
1046 | if (!orig_ist->ist[0]) { | |
92d65b23 BG |
1047 | static const unsigned int sizes[N_EXCEPTION_STACKS] = { |
1048 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1049 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1ba76586 | 1050 | }; |
92d65b23 | 1051 | char *estacks = per_cpu(exception_stacks, cpu); |
1ba76586 | 1052 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
92d65b23 | 1053 | estacks += sizes[v]; |
1ba76586 YL |
1054 | orig_ist->ist[v] = t->x86_tss.ist[v] = |
1055 | (unsigned long)estacks; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
1060 | /* | |
1061 | * <= is required because the CPU will access up to | |
1062 | * 8 bits beyond the end of the IO permission bitmap. | |
1063 | */ | |
1064 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1065 | t->io_bitmap[i] = ~0UL; | |
1066 | ||
1067 | atomic_inc(&init_mm.mm_count); | |
1068 | me->active_mm = &init_mm; | |
1069 | if (me->mm) | |
1070 | BUG(); | |
1071 | enter_lazy_tlb(&init_mm, me); | |
1072 | ||
1073 | load_sp0(t, ¤t->thread); | |
1074 | set_tss_desc(cpu, t); | |
1075 | load_TR_desc(); | |
1076 | load_LDT(&init_mm.context); | |
1077 | ||
1078 | #ifdef CONFIG_KGDB | |
1079 | /* | |
1080 | * If the kgdb is connected no debug regs should be altered. This | |
1081 | * is only applicable when KGDB and a KGDB I/O module are built | |
1082 | * into the kernel and you are using early debugging with | |
1083 | * kgdbwait. KGDB will control the kernel HW breakpoint registers. | |
1084 | */ | |
1085 | if (kgdb_connected && arch_kgdb_ops.correct_hw_break) | |
1086 | arch_kgdb_ops.correct_hw_break(); | |
8f6d86dc | 1087 | else |
1ba76586 | 1088 | #endif |
8f6d86dc PZ |
1089 | { |
1090 | /* | |
1091 | * Clear all 6 debug registers: | |
1092 | */ | |
1093 | set_debugreg(0UL, 0); | |
1094 | set_debugreg(0UL, 1); | |
1095 | set_debugreg(0UL, 2); | |
1096 | set_debugreg(0UL, 3); | |
1097 | set_debugreg(0UL, 6); | |
1098 | set_debugreg(0UL, 7); | |
1ba76586 | 1099 | } |
1ba76586 YL |
1100 | |
1101 | fpu_init(); | |
1102 | ||
1103 | raw_local_save_flags(kernel_eflags); | |
1104 | ||
1105 | if (is_uv_system()) | |
1106 | uv_cpu_init(); | |
1107 | } | |
1108 | ||
1109 | #else | |
1110 | ||
d2cbcc49 | 1111 | void __cpuinit cpu_init(void) |
9ee79a3d | 1112 | { |
d2cbcc49 RR |
1113 | int cpu = smp_processor_id(); |
1114 | struct task_struct *curr = current; | |
34048c9e | 1115 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1116 | struct thread_struct *thread = &curr->thread; |
62111195 | 1117 | |
c2d1cec1 | 1118 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 JF |
1119 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
1120 | for (;;) local_irq_enable(); | |
1121 | } | |
1122 | ||
1123 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1124 | ||
1125 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1126 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1127 | |
4d37e7e3 | 1128 | load_idt(&idt_descr); |
552be871 | 1129 | switch_to_new_gdt(cpu); |
1da177e4 | 1130 | |
1da177e4 LT |
1131 | /* |
1132 | * Set up and load the per-CPU TSS and LDT | |
1133 | */ | |
1134 | atomic_inc(&init_mm.mm_count); | |
62111195 JF |
1135 | curr->active_mm = &init_mm; |
1136 | if (curr->mm) | |
1137 | BUG(); | |
1138 | enter_lazy_tlb(&init_mm, curr); | |
1da177e4 | 1139 | |
faca6227 | 1140 | load_sp0(t, thread); |
34048c9e | 1141 | set_tss_desc(cpu, t); |
1da177e4 LT |
1142 | load_TR_desc(); |
1143 | load_LDT(&init_mm.context); | |
1144 | ||
22c4e308 | 1145 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1146 | /* Set up doublefault TSS pointer in the GDT */ |
1147 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1148 | #endif |
1da177e4 | 1149 | |
1da177e4 | 1150 | /* Clear all 6 debug registers: */ |
4bb0d3ec ZA |
1151 | set_debugreg(0, 0); |
1152 | set_debugreg(0, 1); | |
1153 | set_debugreg(0, 2); | |
1154 | set_debugreg(0, 3); | |
1155 | set_debugreg(0, 6); | |
1156 | set_debugreg(0, 7); | |
1da177e4 LT |
1157 | |
1158 | /* | |
1159 | * Force FPU initialization: | |
1160 | */ | |
b359e8a4 SS |
1161 | if (cpu_has_xsave) |
1162 | current_thread_info()->status = TS_XSAVE; | |
1163 | else | |
1164 | current_thread_info()->status = 0; | |
1da177e4 LT |
1165 | clear_used_math(); |
1166 | mxcsr_feature_mask_init(); | |
dc1e35c6 SS |
1167 | |
1168 | /* | |
1169 | * Boot processor to setup the FP and extended state context info. | |
1170 | */ | |
b3572e36 | 1171 | if (smp_processor_id() == boot_cpu_id) |
dc1e35c6 SS |
1172 | init_thread_xstate(); |
1173 | ||
1174 | xsave_init(); | |
1da177e4 | 1175 | } |
e1367daf | 1176 | |
1ba76586 YL |
1177 | |
1178 | #endif |