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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
24 | #include <asm/msr.h> |
25 | #include <asm/paravirt.h> | |
26 | #include <asm/alternative.h> | |
62a67e12 | 27 | #include <asm/pgtable.h> |
d1163651 | 28 | #include <asm/set_memory.h> |
c995efd5 | 29 | #include <asm/intel-family.h> |
1353ebb4 | 30 | |
da285121 | 31 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 32 | static void __init ssb_select_mitigation(void); |
da285121 | 33 | |
1b86883c KRW |
34 | /* |
35 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
36 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
37 | */ | |
885f82bf | 38 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 39 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 40 | |
1115a859 KRW |
41 | /* |
42 | * The vendor and possibly platform specific bits which can be modified in | |
43 | * x86_spec_ctrl_base. | |
44 | */ | |
45 | static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS; | |
46 | ||
764f3c21 KRW |
47 | /* |
48 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 49 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
50 | */ |
51 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 52 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 53 | |
1353ebb4 JF |
54 | void __init check_bugs(void) |
55 | { | |
56 | identify_boot_cpu(); | |
55a36b65 | 57 | |
62a67e12 BP |
58 | if (!IS_ENABLED(CONFIG_SMP)) { |
59 | pr_info("CPU: "); | |
60 | print_cpu_info(&boot_cpu_data); | |
61 | } | |
62 | ||
1b86883c KRW |
63 | /* |
64 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
65 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
66 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 67 | */ |
7eb8956a | 68 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
69 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
70 | ||
da285121 DW |
71 | /* Select the proper spectre mitigation before patching alternatives */ |
72 | spectre_v2_select_mitigation(); | |
73 | ||
24f7fc83 KRW |
74 | /* |
75 | * Select proper mitigation for any exposure to the Speculative Store | |
76 | * Bypass vulnerability. | |
77 | */ | |
78 | ssb_select_mitigation(); | |
79 | ||
62a67e12 | 80 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
81 | /* |
82 | * Check whether we are able to run this kernel safely on SMP. | |
83 | * | |
84 | * - i386 is no longer supported. | |
85 | * - In order to run on anything without a TSC, we need to be | |
86 | * compiled for a i486. | |
87 | */ | |
88 | if (boot_cpu_data.x86 < 4) | |
89 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
90 | ||
bfe4bb15 MV |
91 | init_utsname()->machine[1] = |
92 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 93 | alternative_instructions(); |
304bceda | 94 | |
4d164092 | 95 | fpu__init_check_bugs(); |
62a67e12 BP |
96 | #else /* CONFIG_X86_64 */ |
97 | alternative_instructions(); | |
98 | ||
99 | /* | |
100 | * Make sure the first 2MB area is not mapped by huge pages | |
101 | * There are typically fixed size MTRRs in there and overlapping | |
102 | * MTRRs into large pages causes slow downs. | |
103 | * | |
104 | * Right now we don't do that with gbpages because there seems | |
105 | * very little benefit for that case. | |
106 | */ | |
107 | if (!direct_gbpages) | |
108 | set_memory_4k((unsigned long)__va(0), 1); | |
109 | #endif | |
1353ebb4 | 110 | } |
61dc0f55 | 111 | |
da285121 DW |
112 | /* The kernel command line selection */ |
113 | enum spectre_v2_mitigation_cmd { | |
114 | SPECTRE_V2_CMD_NONE, | |
115 | SPECTRE_V2_CMD_AUTO, | |
116 | SPECTRE_V2_CMD_FORCE, | |
117 | SPECTRE_V2_CMD_RETPOLINE, | |
118 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
119 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
120 | }; | |
121 | ||
122 | static const char *spectre_v2_strings[] = { | |
123 | [SPECTRE_V2_NONE] = "Vulnerable", | |
124 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
125 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
126 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
127 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
128 | }; | |
129 | ||
130 | #undef pr_fmt | |
55fa19d3 | 131 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 132 | |
f9544b2b KC |
133 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
134 | SPECTRE_V2_NONE; | |
caf7501a | 135 | |
1b86883c KRW |
136 | void x86_spec_ctrl_set(u64 val) |
137 | { | |
1115a859 | 138 | if (val & x86_spec_ctrl_mask) |
1b86883c KRW |
139 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); |
140 | else | |
141 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); | |
142 | } | |
143 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); | |
144 | ||
cc69b349 BP |
145 | void |
146 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 147 | { |
cc69b349 BP |
148 | struct thread_info *ti = current_thread_info(); |
149 | u64 msr, host = x86_spec_ctrl_base; | |
885f82bf | 150 | |
7eb8956a | 151 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 BP |
152 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
153 | /* SSBD controlled in MSR_SPEC_CTRL */ | |
154 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) | |
155 | host |= ssbd_tif_to_spec_ctrl(ti->flags); | |
156 | ||
157 | if (host != guest_spec_ctrl) { | |
158 | msr = setguest ? guest_spec_ctrl : host; | |
159 | wrmsrl(MSR_IA32_SPEC_CTRL, msr); | |
160 | } | |
161 | } | |
5cf68754 | 162 | } |
cc69b349 | 163 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 164 | |
9f65fb29 | 165 | static void x86_amd_ssb_disable(void) |
764f3c21 | 166 | { |
9f65fb29 | 167 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 168 | |
11fb0683 TL |
169 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
170 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
171 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
172 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
173 | } | |
174 | ||
caf7501a | 175 | #ifdef RETPOLINE |
e383095c TG |
176 | static bool spectre_v2_bad_module; |
177 | ||
caf7501a AK |
178 | bool retpoline_module_ok(bool has_retpoline) |
179 | { | |
180 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
181 | return true; | |
182 | ||
e698dcdf | 183 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
184 | spectre_v2_bad_module = true; |
185 | return false; | |
186 | } | |
e383095c TG |
187 | |
188 | static inline const char *spectre_v2_module_string(void) | |
189 | { | |
190 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
191 | } | |
192 | #else | |
193 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 194 | #endif |
da285121 DW |
195 | |
196 | static void __init spec2_print_if_insecure(const char *reason) | |
197 | { | |
198 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 199 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
200 | } |
201 | ||
202 | static void __init spec2_print_if_secure(const char *reason) | |
203 | { | |
204 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 205 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
206 | } |
207 | ||
208 | static inline bool retp_compiler(void) | |
209 | { | |
210 | return __is_defined(RETPOLINE); | |
211 | } | |
212 | ||
213 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
214 | { | |
215 | int len = strlen(opt); | |
216 | ||
217 | return len == arglen && !strncmp(arg, opt, len); | |
218 | } | |
219 | ||
9005c683 KA |
220 | static const struct { |
221 | const char *option; | |
222 | enum spectre_v2_mitigation_cmd cmd; | |
223 | bool secure; | |
224 | } mitigation_options[] = { | |
225 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
226 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
227 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
228 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
229 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
230 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
231 | }; | |
232 | ||
da285121 DW |
233 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
234 | { | |
235 | char arg[20]; | |
9005c683 KA |
236 | int ret, i; |
237 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
238 | ||
239 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
240 | return SPECTRE_V2_CMD_NONE; | |
241 | else { | |
21e433bd | 242 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
243 | if (ret < 0) |
244 | return SPECTRE_V2_CMD_AUTO; | |
245 | ||
246 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
247 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
248 | continue; | |
249 | cmd = mitigation_options[i].cmd; | |
250 | break; | |
251 | } | |
252 | ||
253 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 254 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
255 | return SPECTRE_V2_CMD_AUTO; |
256 | } | |
257 | } | |
258 | ||
9005c683 KA |
259 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
260 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
261 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
262 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 263 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 264 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
265 | } |
266 | ||
267 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
268 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
269 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
270 | return SPECTRE_V2_CMD_AUTO; | |
271 | } | |
272 | ||
273 | if (mitigation_options[i].secure) | |
274 | spec2_print_if_secure(mitigation_options[i].option); | |
275 | else | |
276 | spec2_print_if_insecure(mitigation_options[i].option); | |
277 | ||
278 | return cmd; | |
da285121 DW |
279 | } |
280 | ||
c995efd5 DW |
281 | /* Check for Skylake-like CPUs (for RSB handling) */ |
282 | static bool __init is_skylake_era(void) | |
283 | { | |
284 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
285 | boot_cpu_data.x86 == 6) { | |
286 | switch (boot_cpu_data.x86_model) { | |
287 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
288 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
289 | case INTEL_FAM6_SKYLAKE_X: | |
290 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
291 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
292 | return true; | |
293 | } | |
294 | } | |
295 | return false; | |
296 | } | |
297 | ||
da285121 DW |
298 | static void __init spectre_v2_select_mitigation(void) |
299 | { | |
300 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
301 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
302 | ||
303 | /* | |
304 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
305 | * then nothing to do. | |
306 | */ | |
307 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
308 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
309 | return; | |
310 | ||
311 | switch (cmd) { | |
312 | case SPECTRE_V2_CMD_NONE: | |
313 | return; | |
314 | ||
315 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 316 | case SPECTRE_V2_CMD_AUTO: |
9471eee9 DL |
317 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
318 | goto retpoline_auto; | |
319 | break; | |
da285121 DW |
320 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
321 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
322 | goto retpoline_amd; | |
323 | break; | |
324 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
325 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
326 | goto retpoline_generic; | |
327 | break; | |
328 | case SPECTRE_V2_CMD_RETPOLINE: | |
329 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
330 | goto retpoline_auto; | |
331 | break; | |
332 | } | |
21e433bd | 333 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
334 | return; |
335 | ||
336 | retpoline_auto: | |
337 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
338 | retpoline_amd: | |
339 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 340 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
341 | goto retpoline_generic; |
342 | } | |
343 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
344 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
345 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
346 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
347 | } else { | |
348 | retpoline_generic: | |
349 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
350 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
351 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
352 | } | |
353 | ||
354 | spectre_v2_enabled = mode; | |
355 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
356 | |
357 | /* | |
21e433bd | 358 | * If neither SMEP nor PTI are available, there is a risk of |
c995efd5 DW |
359 | * hitting userspace addresses in the RSB after a context switch |
360 | * from a shallow call stack to a deeper one. To prevent this fill | |
361 | * the entire RSB, even when using IBRS. | |
362 | * | |
363 | * Skylake era CPUs have a separate issue with *underflow* of the | |
364 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
365 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
366 | * or deactivated in favour of retpolines the RSB fill on context | |
367 | * switch is required. | |
368 | */ | |
369 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
370 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
371 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
21e433bd | 372 | pr_info("Spectre v2 mitigation: Filling RSB on context switch\n"); |
c995efd5 | 373 | } |
20ffa1ca DW |
374 | |
375 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
376 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
377 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 378 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 379 | } |
dd84441a DW |
380 | |
381 | /* | |
382 | * Retpoline means the kernel is safe because it has no indirect | |
383 | * branches. But firmware isn't, so use IBRS to protect that. | |
384 | */ | |
385 | if (boot_cpu_has(X86_FEATURE_IBRS)) { | |
386 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); | |
387 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
388 | } | |
da285121 DW |
389 | } |
390 | ||
24f7fc83 KRW |
391 | #undef pr_fmt |
392 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
393 | ||
f9544b2b | 394 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
395 | |
396 | /* The kernel command line selection */ | |
397 | enum ssb_mitigation_cmd { | |
398 | SPEC_STORE_BYPASS_CMD_NONE, | |
399 | SPEC_STORE_BYPASS_CMD_AUTO, | |
400 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 401 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 402 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
403 | }; |
404 | ||
405 | static const char *ssb_strings[] = { | |
406 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 407 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
408 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
409 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
410 | }; |
411 | ||
412 | static const struct { | |
413 | const char *option; | |
414 | enum ssb_mitigation_cmd cmd; | |
415 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
416 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
417 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
418 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
419 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
420 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
421 | }; |
422 | ||
423 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
424 | { | |
425 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
426 | char arg[20]; | |
427 | int ret, i; | |
428 | ||
429 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
430 | return SPEC_STORE_BYPASS_CMD_NONE; | |
431 | } else { | |
432 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
433 | arg, sizeof(arg)); | |
434 | if (ret < 0) | |
435 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
436 | ||
437 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
438 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
439 | continue; | |
440 | ||
441 | cmd = ssb_mitigation_options[i].cmd; | |
442 | break; | |
443 | } | |
444 | ||
445 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
446 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
447 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
448 | } | |
449 | } | |
450 | ||
451 | return cmd; | |
452 | } | |
453 | ||
d66d8ff3 | 454 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
455 | { |
456 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
457 | enum ssb_mitigation_cmd cmd; | |
458 | ||
9f65fb29 | 459 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
460 | return mode; |
461 | ||
462 | cmd = ssb_parse_cmdline(); | |
463 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
464 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
465 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
466 | return mode; | |
467 | ||
468 | switch (cmd) { | |
469 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
470 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
471 | /* | |
472 | * Choose prctl+seccomp as the default mode if seccomp is | |
473 | * enabled. | |
474 | */ | |
475 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
476 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
477 | else | |
478 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 479 | break; |
24f7fc83 KRW |
480 | case SPEC_STORE_BYPASS_CMD_ON: |
481 | mode = SPEC_STORE_BYPASS_DISABLE; | |
482 | break; | |
a73ec77e TG |
483 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
484 | mode = SPEC_STORE_BYPASS_PRCTL; | |
485 | break; | |
24f7fc83 KRW |
486 | case SPEC_STORE_BYPASS_CMD_NONE: |
487 | break; | |
488 | } | |
489 | ||
77243971 KRW |
490 | /* |
491 | * We have three CPU feature flags that are in play here: | |
492 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 493 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
494 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
495 | */ | |
a73ec77e | 496 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 497 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 KRW |
498 | /* |
499 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses | |
500 | * a completely different MSR and bit dependent on family. | |
501 | */ | |
502 | switch (boot_cpu_data.x86_vendor) { | |
503 | case X86_VENDOR_INTEL: | |
9f65fb29 KRW |
504 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
505 | x86_spec_ctrl_mask &= ~SPEC_CTRL_SSBD; | |
506 | x86_spec_ctrl_set(SPEC_CTRL_SSBD); | |
77243971 KRW |
507 | break; |
508 | case X86_VENDOR_AMD: | |
9f65fb29 | 509 | x86_amd_ssb_disable(); |
77243971 KRW |
510 | break; |
511 | } | |
512 | } | |
513 | ||
24f7fc83 KRW |
514 | return mode; |
515 | } | |
516 | ||
ffed645e | 517 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
518 | { |
519 | ssb_mode = __ssb_select_mitigation(); | |
520 | ||
521 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
522 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
523 | } | |
524 | ||
da285121 | 525 | #undef pr_fmt |
f21b53b2 | 526 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 527 | |
7bbf1373 | 528 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 529 | { |
356e4bff | 530 | bool update; |
a73ec77e | 531 | |
f21b53b2 KC |
532 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
533 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
534 | return -ENXIO; |
535 | ||
356e4bff TG |
536 | switch (ctrl) { |
537 | case PR_SPEC_ENABLE: | |
538 | /* If speculation is force disabled, enable is not allowed */ | |
539 | if (task_spec_ssb_force_disable(task)) | |
540 | return -EPERM; | |
541 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 542 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
543 | break; |
544 | case PR_SPEC_DISABLE: | |
545 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 546 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
547 | break; |
548 | case PR_SPEC_FORCE_DISABLE: | |
549 | task_set_spec_ssb_disable(task); | |
550 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 551 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
552 | break; |
553 | default: | |
554 | return -ERANGE; | |
555 | } | |
a73ec77e | 556 | |
7bbf1373 KC |
557 | /* |
558 | * If being set on non-current task, delay setting the CPU | |
559 | * mitigation until it is next scheduled. | |
560 | */ | |
356e4bff | 561 | if (task == current && update) |
0270be3e | 562 | speculative_store_bypass_update_current(); |
a73ec77e TG |
563 | |
564 | return 0; | |
565 | } | |
566 | ||
8bf37d8c TG |
567 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
568 | unsigned long ctrl) | |
569 | { | |
570 | switch (which) { | |
571 | case PR_SPEC_STORE_BYPASS: | |
572 | return ssb_prctl_set(task, ctrl); | |
573 | default: | |
574 | return -ENODEV; | |
575 | } | |
576 | } | |
577 | ||
578 | #ifdef CONFIG_SECCOMP | |
579 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
580 | { | |
f21b53b2 KC |
581 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
582 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
583 | } |
584 | #endif | |
585 | ||
7bbf1373 | 586 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
587 | { |
588 | switch (ssb_mode) { | |
589 | case SPEC_STORE_BYPASS_DISABLE: | |
590 | return PR_SPEC_DISABLE; | |
f21b53b2 | 591 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 592 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
593 | if (task_spec_ssb_force_disable(task)) |
594 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
595 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
596 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
597 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
598 | default: | |
599 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
600 | return PR_SPEC_ENABLE; | |
601 | return PR_SPEC_NOT_AFFECTED; | |
602 | } | |
603 | } | |
604 | ||
7bbf1373 | 605 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
606 | { |
607 | switch (which) { | |
608 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 609 | return ssb_prctl_get(task); |
a73ec77e TG |
610 | default: |
611 | return -ENODEV; | |
612 | } | |
613 | } | |
614 | ||
77243971 KRW |
615 | void x86_spec_ctrl_setup_ap(void) |
616 | { | |
7eb8956a | 617 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1115a859 | 618 | x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask); |
764f3c21 KRW |
619 | |
620 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 621 | x86_amd_ssb_disable(); |
77243971 KRW |
622 | } |
623 | ||
61dc0f55 | 624 | #ifdef CONFIG_SYSFS |
d1059518 | 625 | |
7bb4d366 | 626 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 627 | char *buf, unsigned int bug) |
61dc0f55 | 628 | { |
d1059518 | 629 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 630 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
631 | |
632 | switch (bug) { | |
633 | case X86_BUG_CPU_MELTDOWN: | |
634 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
635 | return sprintf(buf, "Mitigation: PTI\n"); | |
636 | ||
637 | break; | |
638 | ||
639 | case X86_BUG_SPECTRE_V1: | |
640 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
641 | ||
642 | case X86_BUG_SPECTRE_V2: | |
643 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
644 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
645 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
646 | spectre_v2_module_string()); | |
647 | ||
24f7fc83 KRW |
648 | case X86_BUG_SPEC_STORE_BYPASS: |
649 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
650 | ||
d1059518 KRW |
651 | default: |
652 | break; | |
653 | } | |
654 | ||
61dc0f55 TG |
655 | return sprintf(buf, "Vulnerable\n"); |
656 | } | |
657 | ||
d1059518 KRW |
658 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
659 | { | |
660 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
661 | } | |
662 | ||
21e433bd | 663 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 664 | { |
d1059518 | 665 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
666 | } |
667 | ||
21e433bd | 668 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 669 | { |
d1059518 | 670 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 671 | } |
c456442c KRW |
672 | |
673 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
674 | { | |
675 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
676 | } | |
61dc0f55 | 677 | #endif |