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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
caf7501a | 14 | #include <linux/module.h> |
a73ec77e TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
da285121 | 17 | |
28a27752 | 18 | #include <asm/spec-ctrl.h> |
da285121 | 19 | #include <asm/cmdline.h> |
91eb1b79 | 20 | #include <asm/bugs.h> |
1353ebb4 | 21 | #include <asm/processor.h> |
7ebad705 | 22 | #include <asm/processor-flags.h> |
952f07ec | 23 | #include <asm/fpu/internal.h> |
1353ebb4 | 24 | #include <asm/msr.h> |
72c6d2db | 25 | #include <asm/vmx.h> |
1353ebb4 JF |
26 | #include <asm/paravirt.h> |
27 | #include <asm/alternative.h> | |
62a67e12 | 28 | #include <asm/pgtable.h> |
d1163651 | 29 | #include <asm/set_memory.h> |
c995efd5 | 30 | #include <asm/intel-family.h> |
17dbca11 | 31 | #include <asm/e820/api.h> |
6cb2b08f | 32 | #include <asm/hypervisor.h> |
1353ebb4 | 33 | |
da285121 | 34 | static void __init spectre_v2_select_mitigation(void); |
24f7fc83 | 35 | static void __init ssb_select_mitigation(void); |
17dbca11 | 36 | static void __init l1tf_select_mitigation(void); |
da285121 | 37 | |
1b86883c KRW |
38 | /* |
39 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
40 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
41 | */ | |
885f82bf | 42 | u64 __ro_after_init x86_spec_ctrl_base; |
fa8ac498 | 43 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
1b86883c | 44 | |
1115a859 KRW |
45 | /* |
46 | * The vendor and possibly platform specific bits which can be modified in | |
47 | * x86_spec_ctrl_base. | |
48 | */ | |
be6fcb54 | 49 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
1115a859 | 50 | |
764f3c21 KRW |
51 | /* |
52 | * AMD specific MSR info for Speculative Store Bypass control. | |
9f65fb29 | 53 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
764f3c21 KRW |
54 | */ |
55 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
9f65fb29 | 56 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 57 | |
1353ebb4 JF |
58 | void __init check_bugs(void) |
59 | { | |
60 | identify_boot_cpu(); | |
55a36b65 | 61 | |
fee0aede TG |
62 | /* |
63 | * identify_boot_cpu() initialized SMT support information, let the | |
64 | * core code know. | |
65 | */ | |
bc2d8d26 | 66 | cpu_smt_check_topology_early(); |
fee0aede | 67 | |
62a67e12 BP |
68 | if (!IS_ENABLED(CONFIG_SMP)) { |
69 | pr_info("CPU: "); | |
70 | print_cpu_info(&boot_cpu_data); | |
71 | } | |
72 | ||
1b86883c KRW |
73 | /* |
74 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
764f3c21 KRW |
75 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
76 | * init code as it is not enumerated and depends on the family. | |
1b86883c | 77 | */ |
7eb8956a | 78 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
1b86883c KRW |
79 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
80 | ||
be6fcb54 TG |
81 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
82 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
83 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
84 | ||
da285121 DW |
85 | /* Select the proper spectre mitigation before patching alternatives */ |
86 | spectre_v2_select_mitigation(); | |
87 | ||
24f7fc83 KRW |
88 | /* |
89 | * Select proper mitigation for any exposure to the Speculative Store | |
90 | * Bypass vulnerability. | |
91 | */ | |
92 | ssb_select_mitigation(); | |
93 | ||
17dbca11 AK |
94 | l1tf_select_mitigation(); |
95 | ||
62a67e12 | 96 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
97 | /* |
98 | * Check whether we are able to run this kernel safely on SMP. | |
99 | * | |
100 | * - i386 is no longer supported. | |
101 | * - In order to run on anything without a TSC, we need to be | |
102 | * compiled for a i486. | |
103 | */ | |
104 | if (boot_cpu_data.x86 < 4) | |
105 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
106 | ||
bfe4bb15 MV |
107 | init_utsname()->machine[1] = |
108 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 109 | alternative_instructions(); |
304bceda | 110 | |
4d164092 | 111 | fpu__init_check_bugs(); |
62a67e12 BP |
112 | #else /* CONFIG_X86_64 */ |
113 | alternative_instructions(); | |
114 | ||
115 | /* | |
116 | * Make sure the first 2MB area is not mapped by huge pages | |
117 | * There are typically fixed size MTRRs in there and overlapping | |
118 | * MTRRs into large pages causes slow downs. | |
119 | * | |
120 | * Right now we don't do that with gbpages because there seems | |
121 | * very little benefit for that case. | |
122 | */ | |
123 | if (!direct_gbpages) | |
124 | set_memory_4k((unsigned long)__va(0), 1); | |
125 | #endif | |
1353ebb4 | 126 | } |
61dc0f55 | 127 | |
da285121 DW |
128 | /* The kernel command line selection */ |
129 | enum spectre_v2_mitigation_cmd { | |
130 | SPECTRE_V2_CMD_NONE, | |
131 | SPECTRE_V2_CMD_AUTO, | |
132 | SPECTRE_V2_CMD_FORCE, | |
133 | SPECTRE_V2_CMD_RETPOLINE, | |
134 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
135 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
136 | }; | |
137 | ||
138 | static const char *spectre_v2_strings[] = { | |
139 | [SPECTRE_V2_NONE] = "Vulnerable", | |
140 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
141 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
142 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
143 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
706d5168 | 144 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", |
da285121 DW |
145 | }; |
146 | ||
147 | #undef pr_fmt | |
55fa19d3 | 148 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
da285121 | 149 | |
f9544b2b KC |
150 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = |
151 | SPECTRE_V2_NONE; | |
caf7501a | 152 | |
cc69b349 BP |
153 | void |
154 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
5cf68754 | 155 | { |
be6fcb54 | 156 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
cc69b349 | 157 | struct thread_info *ti = current_thread_info(); |
885f82bf | 158 | |
7eb8956a | 159 | /* Is MSR_SPEC_CTRL implemented ? */ |
cc69b349 | 160 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
be6fcb54 TG |
161 | /* |
162 | * Restrict guest_spec_ctrl to supported values. Clear the | |
163 | * modifiable bits in the host base value and or the | |
164 | * modifiable bits from the guest value. | |
165 | */ | |
166 | guestval = hostval & ~x86_spec_ctrl_mask; | |
167 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
168 | ||
cc69b349 | 169 | /* SSBD controlled in MSR_SPEC_CTRL */ |
612bc3b3 TL |
170 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
171 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
be6fcb54 | 172 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
cc69b349 | 173 | |
be6fcb54 TG |
174 | if (hostval != guestval) { |
175 | msrval = setguest ? guestval : hostval; | |
176 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
cc69b349 BP |
177 | } |
178 | } | |
47c61b39 TG |
179 | |
180 | /* | |
181 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
182 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
183 | */ | |
184 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
185 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
186 | return; | |
187 | ||
188 | /* | |
189 | * If the host has SSBD mitigation enabled, force it in the host's | |
190 | * virtual MSR value. If its not permanently enabled, evaluate | |
191 | * current's TIF_SSBD thread flag. | |
192 | */ | |
193 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
194 | hostval = SPEC_CTRL_SSBD; | |
195 | else | |
196 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
197 | ||
198 | /* Sanitize the guest value */ | |
199 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
200 | ||
201 | if (hostval != guestval) { | |
202 | unsigned long tif; | |
203 | ||
204 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
205 | ssbd_spec_ctrl_to_tif(hostval); | |
206 | ||
207 | speculative_store_bypass_update(tif); | |
208 | } | |
5cf68754 | 209 | } |
cc69b349 | 210 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
5cf68754 | 211 | |
9f65fb29 | 212 | static void x86_amd_ssb_disable(void) |
764f3c21 | 213 | { |
9f65fb29 | 214 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
764f3c21 | 215 | |
11fb0683 TL |
216 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
217 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
218 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
764f3c21 KRW |
219 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
220 | } | |
221 | ||
caf7501a | 222 | #ifdef RETPOLINE |
e383095c TG |
223 | static bool spectre_v2_bad_module; |
224 | ||
caf7501a AK |
225 | bool retpoline_module_ok(bool has_retpoline) |
226 | { | |
227 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
228 | return true; | |
229 | ||
e698dcdf | 230 | pr_err("System may be vulnerable to spectre v2\n"); |
caf7501a AK |
231 | spectre_v2_bad_module = true; |
232 | return false; | |
233 | } | |
e383095c TG |
234 | |
235 | static inline const char *spectre_v2_module_string(void) | |
236 | { | |
237 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
238 | } | |
239 | #else | |
240 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
caf7501a | 241 | #endif |
da285121 DW |
242 | |
243 | static void __init spec2_print_if_insecure(const char *reason) | |
244 | { | |
245 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 246 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
247 | } |
248 | ||
249 | static void __init spec2_print_if_secure(const char *reason) | |
250 | { | |
251 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
9005c683 | 252 | pr_info("%s selected on command line.\n", reason); |
da285121 DW |
253 | } |
254 | ||
255 | static inline bool retp_compiler(void) | |
256 | { | |
257 | return __is_defined(RETPOLINE); | |
258 | } | |
259 | ||
260 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
261 | { | |
262 | int len = strlen(opt); | |
263 | ||
264 | return len == arglen && !strncmp(arg, opt, len); | |
265 | } | |
266 | ||
9005c683 KA |
267 | static const struct { |
268 | const char *option; | |
269 | enum spectre_v2_mitigation_cmd cmd; | |
270 | bool secure; | |
271 | } mitigation_options[] = { | |
272 | { "off", SPECTRE_V2_CMD_NONE, false }, | |
273 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
274 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
275 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
276 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
277 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
278 | }; | |
279 | ||
da285121 DW |
280 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
281 | { | |
282 | char arg[20]; | |
9005c683 KA |
283 | int ret, i; |
284 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; | |
285 | ||
286 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
287 | return SPECTRE_V2_CMD_NONE; | |
288 | else { | |
21e433bd | 289 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
9005c683 KA |
290 | if (ret < 0) |
291 | return SPECTRE_V2_CMD_AUTO; | |
292 | ||
293 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
294 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
295 | continue; | |
296 | cmd = mitigation_options[i].cmd; | |
297 | break; | |
298 | } | |
299 | ||
300 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
9de29eac | 301 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); |
da285121 DW |
302 | return SPECTRE_V2_CMD_AUTO; |
303 | } | |
304 | } | |
305 | ||
9005c683 KA |
306 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
307 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
308 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
309 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
21e433bd | 310 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 311 | return SPECTRE_V2_CMD_AUTO; |
9005c683 KA |
312 | } |
313 | ||
314 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
315 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
316 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
317 | return SPECTRE_V2_CMD_AUTO; | |
318 | } | |
319 | ||
320 | if (mitigation_options[i].secure) | |
321 | spec2_print_if_secure(mitigation_options[i].option); | |
322 | else | |
323 | spec2_print_if_insecure(mitigation_options[i].option); | |
324 | ||
325 | return cmd; | |
da285121 DW |
326 | } |
327 | ||
328 | static void __init spectre_v2_select_mitigation(void) | |
329 | { | |
330 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
331 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
332 | ||
333 | /* | |
334 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
335 | * then nothing to do. | |
336 | */ | |
337 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
338 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
339 | return; | |
340 | ||
341 | switch (cmd) { | |
342 | case SPECTRE_V2_CMD_NONE: | |
343 | return; | |
344 | ||
345 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 346 | case SPECTRE_V2_CMD_AUTO: |
706d5168 SP |
347 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
348 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
349 | /* Force it so VMEXIT will restore correctly */ | |
350 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
351 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
352 | goto specv2_set_mode; | |
353 | } | |
9471eee9 DL |
354 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
355 | goto retpoline_auto; | |
356 | break; | |
da285121 DW |
357 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
358 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
359 | goto retpoline_amd; | |
360 | break; | |
361 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
362 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
363 | goto retpoline_generic; | |
364 | break; | |
365 | case SPECTRE_V2_CMD_RETPOLINE: | |
366 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
367 | goto retpoline_auto; | |
368 | break; | |
369 | } | |
21e433bd | 370 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
371 | return; |
372 | ||
373 | retpoline_auto: | |
374 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
375 | retpoline_amd: | |
376 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
21e433bd | 377 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
378 | goto retpoline_generic; |
379 | } | |
380 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
381 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
382 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
383 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
384 | } else { | |
385 | retpoline_generic: | |
386 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
387 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
388 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
389 | } | |
390 | ||
706d5168 | 391 | specv2_set_mode: |
da285121 DW |
392 | spectre_v2_enabled = mode; |
393 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
394 | |
395 | /* | |
fdf82a78 JK |
396 | * If spectre v2 protection has been enabled, unconditionally fill |
397 | * RSB during a context switch; this protects against two independent | |
398 | * issues: | |
c995efd5 | 399 | * |
fdf82a78 JK |
400 | * - RSB underflow (and switch to BTB) on Skylake+ |
401 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 402 | */ |
fdf82a78 JK |
403 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
404 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
20ffa1ca DW |
405 | |
406 | /* Initialize Indirect Branch Prediction Barrier if supported */ | |
2961298e DW |
407 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
408 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
21e433bd | 409 | pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n"); |
20ffa1ca | 410 | } |
dd84441a DW |
411 | |
412 | /* | |
413 | * Retpoline means the kernel is safe because it has no indirect | |
706d5168 SP |
414 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
415 | * speculation around firmware calls only when Enhanced IBRS isn't | |
416 | * supported. | |
417 | * | |
418 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
419 | * the user might select retpoline on the kernel command line and if | |
420 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
421 | * enable IBRS around firmware calls. | |
dd84441a | 422 | */ |
706d5168 | 423 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
dd84441a DW |
424 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
425 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
426 | } | |
da285121 DW |
427 | } |
428 | ||
24f7fc83 KRW |
429 | #undef pr_fmt |
430 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
431 | ||
f9544b2b | 432 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
24f7fc83 KRW |
433 | |
434 | /* The kernel command line selection */ | |
435 | enum ssb_mitigation_cmd { | |
436 | SPEC_STORE_BYPASS_CMD_NONE, | |
437 | SPEC_STORE_BYPASS_CMD_AUTO, | |
438 | SPEC_STORE_BYPASS_CMD_ON, | |
a73ec77e | 439 | SPEC_STORE_BYPASS_CMD_PRCTL, |
f21b53b2 | 440 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
24f7fc83 KRW |
441 | }; |
442 | ||
443 | static const char *ssb_strings[] = { | |
444 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
a73ec77e | 445 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
f21b53b2 KC |
446 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
447 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
24f7fc83 KRW |
448 | }; |
449 | ||
450 | static const struct { | |
451 | const char *option; | |
452 | enum ssb_mitigation_cmd cmd; | |
453 | } ssb_mitigation_options[] = { | |
f21b53b2 KC |
454 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
455 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
456 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
457 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
458 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
24f7fc83 KRW |
459 | }; |
460 | ||
461 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
462 | { | |
463 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
464 | char arg[20]; | |
465 | int ret, i; | |
466 | ||
467 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
468 | return SPEC_STORE_BYPASS_CMD_NONE; | |
469 | } else { | |
470 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
471 | arg, sizeof(arg)); | |
472 | if (ret < 0) | |
473 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
474 | ||
475 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
476 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
477 | continue; | |
478 | ||
479 | cmd = ssb_mitigation_options[i].cmd; | |
480 | break; | |
481 | } | |
482 | ||
483 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
484 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
485 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
486 | } | |
487 | } | |
488 | ||
489 | return cmd; | |
490 | } | |
491 | ||
d66d8ff3 | 492 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
24f7fc83 KRW |
493 | { |
494 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
495 | enum ssb_mitigation_cmd cmd; | |
496 | ||
9f65fb29 | 497 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
24f7fc83 KRW |
498 | return mode; |
499 | ||
500 | cmd = ssb_parse_cmdline(); | |
501 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
502 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
503 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
504 | return mode; | |
505 | ||
506 | switch (cmd) { | |
507 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
f21b53b2 KC |
508 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
509 | /* | |
510 | * Choose prctl+seccomp as the default mode if seccomp is | |
511 | * enabled. | |
512 | */ | |
513 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
514 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
515 | else | |
516 | mode = SPEC_STORE_BYPASS_PRCTL; | |
a73ec77e | 517 | break; |
24f7fc83 KRW |
518 | case SPEC_STORE_BYPASS_CMD_ON: |
519 | mode = SPEC_STORE_BYPASS_DISABLE; | |
520 | break; | |
a73ec77e TG |
521 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
522 | mode = SPEC_STORE_BYPASS_PRCTL; | |
523 | break; | |
24f7fc83 KRW |
524 | case SPEC_STORE_BYPASS_CMD_NONE: |
525 | break; | |
526 | } | |
527 | ||
77243971 KRW |
528 | /* |
529 | * We have three CPU feature flags that are in play here: | |
530 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
9f65fb29 | 531 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
77243971 KRW |
532 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
533 | */ | |
a73ec77e | 534 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
24f7fc83 | 535 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
77243971 | 536 | /* |
6ac2f49e KRW |
537 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
538 | * use a completely different MSR and bit dependent on family. | |
77243971 | 539 | */ |
612bc3b3 TL |
540 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
541 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
108fab4b | 542 | x86_amd_ssb_disable(); |
612bc3b3 | 543 | } else { |
9f65fb29 | 544 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
be6fcb54 | 545 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
4b59bdb5 | 546 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
77243971 KRW |
547 | } |
548 | } | |
549 | ||
24f7fc83 KRW |
550 | return mode; |
551 | } | |
552 | ||
ffed645e | 553 | static void ssb_select_mitigation(void) |
24f7fc83 KRW |
554 | { |
555 | ssb_mode = __ssb_select_mitigation(); | |
556 | ||
557 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
558 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
559 | } | |
560 | ||
da285121 | 561 | #undef pr_fmt |
f21b53b2 | 562 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 563 | |
7bbf1373 | 564 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) |
a73ec77e | 565 | { |
356e4bff | 566 | bool update; |
a73ec77e | 567 | |
f21b53b2 KC |
568 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
569 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
a73ec77e TG |
570 | return -ENXIO; |
571 | ||
356e4bff TG |
572 | switch (ctrl) { |
573 | case PR_SPEC_ENABLE: | |
574 | /* If speculation is force disabled, enable is not allowed */ | |
575 | if (task_spec_ssb_force_disable(task)) | |
576 | return -EPERM; | |
577 | task_clear_spec_ssb_disable(task); | |
9f65fb29 | 578 | update = test_and_clear_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
579 | break; |
580 | case PR_SPEC_DISABLE: | |
581 | task_set_spec_ssb_disable(task); | |
9f65fb29 | 582 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
583 | break; |
584 | case PR_SPEC_FORCE_DISABLE: | |
585 | task_set_spec_ssb_disable(task); | |
586 | task_set_spec_ssb_force_disable(task); | |
9f65fb29 | 587 | update = !test_and_set_tsk_thread_flag(task, TIF_SSBD); |
356e4bff TG |
588 | break; |
589 | default: | |
590 | return -ERANGE; | |
591 | } | |
a73ec77e | 592 | |
7bbf1373 KC |
593 | /* |
594 | * If being set on non-current task, delay setting the CPU | |
595 | * mitigation until it is next scheduled. | |
596 | */ | |
356e4bff | 597 | if (task == current && update) |
0270be3e | 598 | speculative_store_bypass_update_current(); |
a73ec77e TG |
599 | |
600 | return 0; | |
601 | } | |
602 | ||
8bf37d8c TG |
603 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
604 | unsigned long ctrl) | |
605 | { | |
606 | switch (which) { | |
607 | case PR_SPEC_STORE_BYPASS: | |
608 | return ssb_prctl_set(task, ctrl); | |
609 | default: | |
610 | return -ENODEV; | |
611 | } | |
612 | } | |
613 | ||
614 | #ifdef CONFIG_SECCOMP | |
615 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
616 | { | |
f21b53b2 KC |
617 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
618 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
8bf37d8c TG |
619 | } |
620 | #endif | |
621 | ||
7bbf1373 | 622 | static int ssb_prctl_get(struct task_struct *task) |
a73ec77e TG |
623 | { |
624 | switch (ssb_mode) { | |
625 | case SPEC_STORE_BYPASS_DISABLE: | |
626 | return PR_SPEC_DISABLE; | |
f21b53b2 | 627 | case SPEC_STORE_BYPASS_SECCOMP: |
a73ec77e | 628 | case SPEC_STORE_BYPASS_PRCTL: |
356e4bff TG |
629 | if (task_spec_ssb_force_disable(task)) |
630 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
631 | if (task_spec_ssb_disable(task)) | |
a73ec77e TG |
632 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
633 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
634 | default: | |
635 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
636 | return PR_SPEC_ENABLE; | |
637 | return PR_SPEC_NOT_AFFECTED; | |
638 | } | |
639 | } | |
640 | ||
7bbf1373 | 641 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
a73ec77e TG |
642 | { |
643 | switch (which) { | |
644 | case PR_SPEC_STORE_BYPASS: | |
7bbf1373 | 645 | return ssb_prctl_get(task); |
a73ec77e TG |
646 | default: |
647 | return -ENODEV; | |
648 | } | |
649 | } | |
650 | ||
77243971 KRW |
651 | void x86_spec_ctrl_setup_ap(void) |
652 | { | |
7eb8956a | 653 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
4b59bdb5 | 654 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
764f3c21 KRW |
655 | |
656 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
9f65fb29 | 657 | x86_amd_ssb_disable(); |
77243971 KRW |
658 | } |
659 | ||
56563f53 KRW |
660 | #undef pr_fmt |
661 | #define pr_fmt(fmt) "L1TF: " fmt | |
72c6d2db | 662 | |
d90a7a0e JK |
663 | /* Default mitigation for L1TF-affected CPUs */ |
664 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
72c6d2db | 665 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
d90a7a0e | 666 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
1eb46908 | 667 | #endif |
895ae47f | 668 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
72c6d2db | 669 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
72c6d2db | 670 | |
cc51e542 AK |
671 | /* |
672 | * These CPUs all support 44bits physical address space internally in the | |
673 | * cache but CPUID can report a smaller number of physical address bits. | |
674 | * | |
675 | * The L1TF mitigation uses the top most address bit for the inversion of | |
676 | * non present PTEs. When the installed memory reaches into the top most | |
677 | * address bit due to memory holes, which has been observed on machines | |
678 | * which report 36bits physical address bits and have 32G RAM installed, | |
679 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
680 | * This is a false positive because the mitigation is still possible due to | |
681 | * the fact that the cache uses 44bit internally. Use the cache bits | |
682 | * instead of the reported physical bits and adjust them on the affected | |
683 | * machines to 44bit if the reported bits are less than 44. | |
684 | */ | |
685 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
686 | { | |
687 | if (c->x86 != 6) | |
688 | return; | |
689 | ||
690 | switch (c->x86_model) { | |
691 | case INTEL_FAM6_NEHALEM: | |
692 | case INTEL_FAM6_WESTMERE: | |
693 | case INTEL_FAM6_SANDYBRIDGE: | |
694 | case INTEL_FAM6_IVYBRIDGE: | |
695 | case INTEL_FAM6_HASWELL_CORE: | |
696 | case INTEL_FAM6_HASWELL_ULT: | |
697 | case INTEL_FAM6_HASWELL_GT3E: | |
698 | case INTEL_FAM6_BROADWELL_CORE: | |
699 | case INTEL_FAM6_BROADWELL_GT3E: | |
700 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
701 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
702 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
703 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
704 | if (c->x86_cache_bits < 44) | |
705 | c->x86_cache_bits = 44; | |
706 | break; | |
707 | } | |
708 | } | |
709 | ||
56563f53 KRW |
710 | static void __init l1tf_select_mitigation(void) |
711 | { | |
712 | u64 half_pa; | |
713 | ||
714 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
715 | return; | |
716 | ||
cc51e542 AK |
717 | override_cache_bits(&boot_cpu_data); |
718 | ||
d90a7a0e JK |
719 | switch (l1tf_mitigation) { |
720 | case L1TF_MITIGATION_OFF: | |
721 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
722 | case L1TF_MITIGATION_FLUSH: | |
723 | break; | |
724 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
725 | case L1TF_MITIGATION_FULL: | |
726 | cpu_smt_disable(false); | |
727 | break; | |
728 | case L1TF_MITIGATION_FULL_FORCE: | |
729 | cpu_smt_disable(true); | |
730 | break; | |
731 | } | |
732 | ||
56563f53 KRW |
733 | #if CONFIG_PGTABLE_LEVELS == 2 |
734 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
735 | return; | |
736 | #endif | |
737 | ||
56563f53 KRW |
738 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
739 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
740 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
6a012288 VB |
741 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
742 | half_pa); | |
743 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
744 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n"); | |
56563f53 KRW |
745 | return; |
746 | } | |
747 | ||
748 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
749 | } | |
d90a7a0e JK |
750 | |
751 | static int __init l1tf_cmdline(char *str) | |
752 | { | |
753 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
754 | return 0; | |
755 | ||
756 | if (!str) | |
757 | return -EINVAL; | |
758 | ||
759 | if (!strcmp(str, "off")) | |
760 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
761 | else if (!strcmp(str, "flush,nowarn")) | |
762 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
763 | else if (!strcmp(str, "flush")) | |
764 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
765 | else if (!strcmp(str, "flush,nosmt")) | |
766 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
767 | else if (!strcmp(str, "full")) | |
768 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
769 | else if (!strcmp(str, "full,force")) | |
770 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
771 | ||
772 | return 0; | |
773 | } | |
774 | early_param("l1tf", l1tf_cmdline); | |
775 | ||
56563f53 KRW |
776 | #undef pr_fmt |
777 | ||
61dc0f55 | 778 | #ifdef CONFIG_SYSFS |
d1059518 | 779 | |
72c6d2db TG |
780 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
781 | ||
782 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
783 | static const char *l1tf_vmx_states[] = { | |
a7b9020b TG |
784 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
785 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
786 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
787 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
788 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
8e0b2b91 | 789 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
72c6d2db TG |
790 | }; |
791 | ||
792 | static ssize_t l1tf_show_state(char *buf) | |
793 | { | |
794 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
795 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
796 | ||
ea156d19 PB |
797 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
798 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
799 | cpu_smt_control == CPU_SMT_ENABLED)) | |
800 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, | |
801 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
802 | ||
803 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
804 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
805 | cpu_smt_control == CPU_SMT_ENABLED ? "vulnerable" : "disabled"); | |
72c6d2db TG |
806 | } |
807 | #else | |
808 | static ssize_t l1tf_show_state(char *buf) | |
809 | { | |
810 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
811 | } | |
812 | #endif | |
813 | ||
7bb4d366 | 814 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
ffed645e | 815 | char *buf, unsigned int bug) |
61dc0f55 | 816 | { |
d1059518 | 817 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 818 | return sprintf(buf, "Not affected\n"); |
d1059518 KRW |
819 | |
820 | switch (bug) { | |
821 | case X86_BUG_CPU_MELTDOWN: | |
822 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
823 | return sprintf(buf, "Mitigation: PTI\n"); | |
824 | ||
6cb2b08f JK |
825 | if (hypervisor_is_type(X86_HYPER_XEN_PV)) |
826 | return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n"); | |
827 | ||
d1059518 KRW |
828 | break; |
829 | ||
830 | case X86_BUG_SPECTRE_V1: | |
831 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | |
832 | ||
833 | case X86_BUG_SPECTRE_V2: | |
834 | return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | |
835 | boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "", | |
836 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", | |
837 | spectre_v2_module_string()); | |
838 | ||
24f7fc83 KRW |
839 | case X86_BUG_SPEC_STORE_BYPASS: |
840 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
841 | ||
17dbca11 AK |
842 | case X86_BUG_L1TF: |
843 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
72c6d2db | 844 | return l1tf_show_state(buf); |
17dbca11 | 845 | break; |
d1059518 KRW |
846 | default: |
847 | break; | |
848 | } | |
849 | ||
61dc0f55 TG |
850 | return sprintf(buf, "Vulnerable\n"); |
851 | } | |
852 | ||
d1059518 KRW |
853 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
854 | { | |
855 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
856 | } | |
857 | ||
21e433bd | 858 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 859 | { |
d1059518 | 860 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
861 | } |
862 | ||
21e433bd | 863 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 864 | { |
d1059518 | 865 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 866 | } |
c456442c KRW |
867 | |
868 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
869 | { | |
870 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
871 | } | |
17dbca11 AK |
872 | |
873 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
874 | { | |
875 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
876 | } | |
61dc0f55 | 877 | #endif |