Commit | Line | Data |
---|---|---|
69c60c88 | 1 | #include <linux/export.h> |
1da177e4 | 2 | #include <linux/bitops.h> |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
c98fdeaa | 7 | #include <linux/sched.h> |
4e26d11f | 8 | #include <linux/random.h> |
1da177e4 | 9 | #include <asm/processor.h> |
d3f7eae1 | 10 | #include <asm/apic.h> |
1f442d70 | 11 | #include <asm/cpu.h> |
26bfa5f8 | 12 | #include <asm/smp.h> |
42937e81 | 13 | #include <asm/pci-direct.h> |
b466bdb6 | 14 | #include <asm/delay.h> |
1da177e4 | 15 | |
8d71a2ea | 16 | #ifdef CONFIG_X86_64 |
8d71a2ea YL |
17 | # include <asm/mmconfig.h> |
18 | # include <asm/cacheflush.h> | |
19 | #endif | |
20 | ||
1da177e4 LT |
21 | #include "cpu.h" |
22 | ||
cc2749e4 AG |
23 | /* |
24 | * nodes_per_socket: Stores the number of nodes per socket. | |
25 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX | |
26 | * Node Identifiers[10:8] | |
27 | */ | |
28 | static u32 nodes_per_socket = 1; | |
29 | ||
2c929ce6 BP |
30 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
31 | { | |
2c929ce6 BP |
32 | u32 gprs[8] = { 0 }; |
33 | int err; | |
34 | ||
682469a5 BP |
35 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
36 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
37 | |
38 | gprs[1] = msr; | |
39 | gprs[7] = 0x9c5a203a; | |
40 | ||
41 | err = rdmsr_safe_regs(gprs); | |
42 | ||
43 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
44 | ||
45 | return err; | |
46 | } | |
47 | ||
48 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
49 | { | |
2c929ce6 BP |
50 | u32 gprs[8] = { 0 }; |
51 | ||
682469a5 BP |
52 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
53 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
54 | |
55 | gprs[0] = (u32)val; | |
56 | gprs[1] = msr; | |
57 | gprs[2] = val >> 32; | |
58 | gprs[7] = 0x9c5a203a; | |
59 | ||
60 | return wrmsr_safe_regs(gprs); | |
61 | } | |
62 | ||
1da177e4 LT |
63 | /* |
64 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
65 | * misexecution of code under Linux. Owners of such processors should | |
66 | * contact AMD for precise details and a CPU swap. | |
67 | * | |
68 | * See http://www.multimania.com/poulot/k6bug.html | |
d7de8649 AH |
69 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
70 | * (Publication # 21266 Issue Date: August 1998) | |
1da177e4 LT |
71 | * |
72 | * The following test is erm.. interesting. AMD neglected to up | |
73 | * the chip setting when fixing the bug but they also tweaked some | |
74 | * performance at the same time.. | |
75 | */ | |
fb87a298 | 76 | |
277d5b40 | 77 | extern __visible void vide(void); |
de642faf JP |
78 | __asm__(".globl vide\n" |
79 | ".type vide, @function\n" | |
80 | ".align 4\n" | |
81 | "vide: ret\n"); | |
1da177e4 | 82 | |
148f9bb8 | 83 | static void init_amd_k5(struct cpuinfo_x86 *c) |
11fdd252 | 84 | { |
26bfa5f8 | 85 | #ifdef CONFIG_X86_32 |
11fdd252 YL |
86 | /* |
87 | * General Systems BIOSen alias the cpu frequency registers | |
6a6256f9 | 88 | * of the Elan at 0x000df000. Unfortunately, one of the Linux |
11fdd252 YL |
89 | * drivers subsequently pokes it, and changes the CPU speed. |
90 | * Workaround : Remove the unneeded alias. | |
91 | */ | |
92 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
93 | #define CBAR_ENB (0x80000000) | |
94 | #define CBAR_KEY (0X000000CB) | |
95 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
96 | if (inl(CBAR) & CBAR_ENB) |
97 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 | 98 | } |
26bfa5f8 | 99 | #endif |
11fdd252 YL |
100 | } |
101 | ||
148f9bb8 | 102 | static void init_amd_k6(struct cpuinfo_x86 *c) |
11fdd252 | 103 | { |
26bfa5f8 | 104 | #ifdef CONFIG_X86_32 |
11fdd252 | 105 | u32 l, h; |
46a84132 | 106 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
11fdd252 YL |
107 | |
108 | if (c->x86_model < 6) { | |
109 | /* Based on AMD doc 20734R - June 2000 */ | |
110 | if (c->x86_model == 0) { | |
111 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
112 | set_cpu_cap(c, X86_FEATURE_PGE); | |
113 | } | |
114 | return; | |
115 | } | |
116 | ||
117 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
118 | const int K6_BUG_LOOP = 1000000; | |
119 | int n; | |
120 | void (*f_vide)(void); | |
37963666 | 121 | u64 d, d2; |
11fdd252 | 122 | |
1b74dde7 | 123 | pr_info("AMD K6 stepping B detected - "); |
11fdd252 YL |
124 | |
125 | /* | |
126 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
127 | * calls at the same time. | |
128 | */ | |
129 | ||
130 | n = K6_BUG_LOOP; | |
131 | f_vide = vide; | |
4ea1636b | 132 | d = rdtsc(); |
11fdd252 YL |
133 | while (n--) |
134 | f_vide(); | |
4ea1636b | 135 | d2 = rdtsc(); |
11fdd252 YL |
136 | d = d2-d; |
137 | ||
138 | if (d > 20*K6_BUG_LOOP) | |
1b74dde7 | 139 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); |
11fdd252 | 140 | else |
1b74dde7 | 141 | pr_cont("probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
142 | } |
143 | ||
144 | /* K6 with old style WHCR */ | |
145 | if (c->x86_model < 8 || | |
146 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
147 | /* We can only write allocate on the low 508Mb */ | |
148 | if (mbytes > 508) | |
149 | mbytes = 508; | |
150 | ||
151 | rdmsr(MSR_K6_WHCR, l, h); | |
152 | if ((l&0x0000FFFF) == 0) { | |
153 | unsigned long flags; | |
154 | l = (1<<0)|((mbytes/4)<<1); | |
155 | local_irq_save(flags); | |
156 | wbinvd(); | |
157 | wrmsr(MSR_K6_WHCR, l, h); | |
158 | local_irq_restore(flags); | |
1b74dde7 | 159 | pr_info("Enabling old style K6 write allocation for %d Mb\n", |
11fdd252 YL |
160 | mbytes); |
161 | } | |
162 | return; | |
163 | } | |
164 | ||
165 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
166 | c->x86_model == 9 || c->x86_model == 13) { | |
167 | /* The more serious chips .. */ | |
168 | ||
169 | if (mbytes > 4092) | |
170 | mbytes = 4092; | |
171 | ||
172 | rdmsr(MSR_K6_WHCR, l, h); | |
173 | if ((l&0xFFFF0000) == 0) { | |
174 | unsigned long flags; | |
175 | l = ((mbytes>>2)<<22)|(1<<16); | |
176 | local_irq_save(flags); | |
177 | wbinvd(); | |
178 | wrmsr(MSR_K6_WHCR, l, h); | |
179 | local_irq_restore(flags); | |
1b74dde7 | 180 | pr_info("Enabling new style K6 write allocation for %d Mb\n", |
11fdd252 YL |
181 | mbytes); |
182 | } | |
183 | ||
184 | return; | |
185 | } | |
186 | ||
187 | if (c->x86_model == 10) { | |
188 | /* AMD Geode LX is model 10 */ | |
189 | /* placeholder for any needed mods */ | |
190 | return; | |
191 | } | |
26bfa5f8 | 192 | #endif |
11fdd252 YL |
193 | } |
194 | ||
26bfa5f8 | 195 | static void init_amd_k7(struct cpuinfo_x86 *c) |
1f442d70 | 196 | { |
26bfa5f8 BP |
197 | #ifdef CONFIG_X86_32 |
198 | u32 l, h; | |
199 | ||
200 | /* | |
201 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
202 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
203 | * If the BIOS didn't enable it already, enable it here. | |
204 | */ | |
205 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
206 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
1b74dde7 | 207 | pr_info("Enabling disabled K7/SSE Support.\n"); |
26bfa5f8 BP |
208 | msr_clear_bit(MSR_K7_HWCR, 15); |
209 | set_cpu_cap(c, X86_FEATURE_XMM); | |
210 | } | |
211 | } | |
212 | ||
213 | /* | |
214 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
215 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
216 | * As per AMD technical note 27212 0.2 | |
217 | */ | |
218 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
219 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
220 | if ((l & 0xfff00000) != 0x20000000) { | |
1b74dde7 CY |
221 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
222 | l, ((l & 0x000fffff)|0x20000000)); | |
26bfa5f8 BP |
223 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
224 | } | |
225 | } | |
226 | ||
227 | set_cpu_cap(c, X86_FEATURE_K7); | |
228 | ||
1f442d70 | 229 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 230 | if (!c->cpu_index) |
1f442d70 YL |
231 | return; |
232 | ||
233 | /* | |
234 | * Certain Athlons might work (for various values of 'work') in SMP | |
235 | * but they are not certified as MP capable. | |
236 | */ | |
237 | /* Athlon 660/661 is valid. */ | |
238 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
239 | (c->x86_mask == 1))) | |
1077c932 | 240 | return; |
1f442d70 YL |
241 | |
242 | /* Duron 670 is valid */ | |
243 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
1077c932 | 244 | return; |
1f442d70 YL |
245 | |
246 | /* | |
247 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
248 | * bit. It's worth noting that the A5 stepping (662) of some | |
249 | * Athlon XP's have the MP bit set. | |
250 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
251 | * more. | |
252 | */ | |
253 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
254 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
255 | (c->x86_model > 7)) | |
26bfa5f8 | 256 | if (cpu_has(c, X86_FEATURE_MP)) |
1077c932 | 257 | return; |
1f442d70 YL |
258 | |
259 | /* If we get here, not a certified SMP capable AMD system. */ | |
260 | ||
261 | /* | |
262 | * Don't taint if we are running SMP kernel on a single non-MP | |
263 | * approved Athlon | |
264 | */ | |
265 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 266 | " processors is not suitable for SMP.\n"); |
8c90487c | 267 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
6c62aa4a | 268 | #endif |
26bfa5f8 | 269 | } |
6c62aa4a | 270 | |
645a7919 | 271 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
272 | /* |
273 | * To workaround broken NUMA config. Read the comment in | |
274 | * srat_detect_node(). | |
275 | */ | |
148f9bb8 | 276 | static int nearby_node(int apicid) |
6c62aa4a YL |
277 | { |
278 | int i, node; | |
279 | ||
280 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 281 | node = __apicid_to_node[i]; |
6c62aa4a YL |
282 | if (node != NUMA_NO_NODE && node_online(node)) |
283 | return node; | |
284 | } | |
285 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 286 | node = __apicid_to_node[i]; |
6c62aa4a YL |
287 | if (node != NUMA_NO_NODE && node_online(node)) |
288 | return node; | |
289 | } | |
290 | return first_node(node_online_map); /* Shouldn't happen */ | |
291 | } | |
292 | #endif | |
11fdd252 | 293 | |
4a376ec3 | 294 | /* |
23588c38 AH |
295 | * Fixup core topology information for |
296 | * (1) AMD multi-node processors | |
297 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 298 | * (2) AMD processors supporting compute units |
4a376ec3 | 299 | */ |
c8e56d20 | 300 | #ifdef CONFIG_SMP |
148f9bb8 | 301 | static void amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 302 | { |
23588c38 | 303 | u8 node_id; |
4a376ec3 AH |
304 | int cpu = smp_processor_id(); |
305 | ||
23588c38 | 306 | /* get information required for multi-node processors */ |
362f924b | 307 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
6057b4d3 AH |
308 | u32 eax, ebx, ecx, edx; |
309 | ||
310 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); | |
6057b4d3 AH |
311 | node_id = ecx & 7; |
312 | ||
313 | /* get compute unit information */ | |
314 | smp_num_siblings = ((ebx >> 8) & 3) + 1; | |
ee6825c8 | 315 | c->x86_max_cores /= smp_num_siblings; |
8196dab4 | 316 | c->cpu_core_id = ebx & 0xff; |
23588c38 | 317 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
318 | u64 value; |
319 | ||
23588c38 | 320 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
23588c38 AH |
321 | node_id = value & 7; |
322 | } else | |
4a376ec3 AH |
323 | return; |
324 | ||
23588c38 | 325 | /* fixup multi-node processor information */ |
cc2749e4 | 326 | if (nodes_per_socket > 1) { |
d518573d | 327 | u32 cus_per_node; |
6057b4d3 | 328 | |
23588c38 | 329 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
ee6825c8 | 330 | cus_per_node = c->x86_max_cores / nodes_per_socket; |
9d260ebc | 331 | |
23588c38 AH |
332 | /* store NodeID, use llc_shared_map to store sibling info */ |
333 | per_cpu(cpu_llc_id, cpu) = node_id; | |
4a376ec3 | 334 | |
9e81509e | 335 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
8196dab4 | 336 | c->cpu_core_id %= cus_per_node; |
23588c38 | 337 | } |
4a376ec3 AH |
338 | } |
339 | #endif | |
340 | ||
11fdd252 | 341 | /* |
aa5e5dc2 | 342 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
11fdd252 YL |
343 | * Assumes number of cores is a power of two. |
344 | */ | |
148f9bb8 | 345 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
11fdd252 | 346 | { |
c8e56d20 | 347 | #ifdef CONFIG_SMP |
11fdd252 | 348 | unsigned bits; |
99bd0c0f | 349 | int cpu = smp_processor_id(); |
11fdd252 YL |
350 | |
351 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
352 | /* Low order bits define the core id (index of core in socket) */ |
353 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
354 | /* Convert the initial APIC ID into the socket ID */ | |
355 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
356 | /* use socket ID also for last level cache */ |
357 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 358 | amd_get_topology(c); |
3849e91f AG |
359 | |
360 | /* | |
361 | * Fix percpu cpu_llc_id here as LLC topology is different | |
362 | * for Fam17h systems. | |
363 | */ | |
364 | if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) | |
365 | return; | |
366 | ||
b0b6e868 | 367 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; |
11fdd252 YL |
368 | #endif |
369 | } | |
370 | ||
8b84c8df | 371 | u16 amd_get_nb_id(int cpu) |
6a812691 | 372 | { |
8b84c8df | 373 | u16 id = 0; |
6a812691 AH |
374 | #ifdef CONFIG_SMP |
375 | id = per_cpu(cpu_llc_id, cpu); | |
376 | #endif | |
377 | return id; | |
378 | } | |
379 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
380 | ||
cc2749e4 AG |
381 | u32 amd_get_nodes_per_socket(void) |
382 | { | |
383 | return nodes_per_socket; | |
384 | } | |
385 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); | |
386 | ||
148f9bb8 | 387 | static void srat_detect_node(struct cpuinfo_x86 *c) |
6c62aa4a | 388 | { |
645a7919 | 389 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
390 | int cpu = smp_processor_id(); |
391 | int node; | |
0d96b9ff | 392 | unsigned apicid = c->apicid; |
6c62aa4a | 393 | |
bbc9e2f4 TH |
394 | node = numa_cpu_node(cpu); |
395 | if (node == NUMA_NO_NODE) | |
396 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 397 | |
64be4c1c | 398 | /* |
68894632 AH |
399 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
400 | * platform-specific handler needs to be called to fixup some | |
401 | * IDs of the CPU. | |
64be4c1c | 402 | */ |
68894632 | 403 | if (x86_cpuinit.fixup_cpu_id) |
64be4c1c DB |
404 | x86_cpuinit.fixup_cpu_id(c, node); |
405 | ||
6c62aa4a | 406 | if (!node_online(node)) { |
bbc9e2f4 TH |
407 | /* |
408 | * Two possibilities here: | |
409 | * | |
410 | * - The CPU is missing memory and no node was created. In | |
411 | * that case try picking one from a nearby CPU. | |
412 | * | |
413 | * - The APIC IDs differ from the HyperTransport node IDs | |
414 | * which the K8 northbridge parsing fills in. Assume | |
415 | * they are all increased by a constant offset, but in | |
416 | * the same order as the HT nodeids. If that doesn't | |
417 | * result in a usable node fall back to the path for the | |
418 | * previous case. | |
419 | * | |
420 | * This workaround operates directly on the mapping between | |
421 | * APIC ID and NUMA node, assuming certain relationship | |
422 | * between APIC ID, HT node ID and NUMA topology. As going | |
423 | * through CPU mapping may alter the outcome, directly | |
424 | * access __apicid_to_node[]. | |
425 | */ | |
6c62aa4a YL |
426 | int ht_nodeid = c->initial_apicid; |
427 | ||
7030a7e9 | 428 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
bbc9e2f4 | 429 | node = __apicid_to_node[ht_nodeid]; |
6c62aa4a YL |
430 | /* Pick a nearby node */ |
431 | if (!node_online(node)) | |
432 | node = nearby_node(apicid); | |
433 | } | |
434 | numa_set_node(cpu, node); | |
6c62aa4a YL |
435 | #endif |
436 | } | |
437 | ||
148f9bb8 | 438 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
11fdd252 | 439 | { |
c8e56d20 | 440 | #ifdef CONFIG_SMP |
11fdd252 YL |
441 | unsigned bits, ecx; |
442 | ||
443 | /* Multi core CPU? */ | |
444 | if (c->extended_cpuid_level < 0x80000008) | |
445 | return; | |
446 | ||
447 | ecx = cpuid_ecx(0x80000008); | |
448 | ||
449 | c->x86_max_cores = (ecx & 0xff) + 1; | |
450 | ||
451 | /* CPU telling us the core id bits shift? */ | |
452 | bits = (ecx >> 12) & 0xF; | |
453 | ||
454 | /* Otherwise recompute */ | |
455 | if (bits == 0) { | |
456 | while ((1 << bits) < c->x86_max_cores) | |
457 | bits++; | |
458 | } | |
459 | ||
460 | c->x86_coreid_bits = bits; | |
461 | #endif | |
462 | } | |
463 | ||
148f9bb8 | 464 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
8fa8b035 | 465 | { |
26bfa5f8 BP |
466 | |
467 | #ifdef CONFIG_X86_64 | |
468 | if (c->x86 >= 0xf) { | |
469 | unsigned long long tseg; | |
470 | ||
471 | /* | |
472 | * Split up direct mapping around the TSEG SMM area. | |
473 | * Don't do it for gbpages because there seems very little | |
474 | * benefit in doing so. | |
475 | */ | |
476 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
477 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
478 | ||
1b74dde7 | 479 | pr_debug("tseg: %010llx\n", tseg); |
26bfa5f8 BP |
480 | if (pfn_range_is_mapped(pfn, pfn + 1)) |
481 | set_memory_4k((unsigned long)__va(tseg), 1); | |
482 | } | |
483 | } | |
484 | #endif | |
485 | ||
8fa8b035 BP |
486 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
487 | ||
488 | if (c->x86 > 0x10 || | |
489 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
490 | u64 val; | |
491 | ||
492 | rdmsrl(MSR_K7_HWCR, val); | |
493 | if (!(val & BIT(24))) | |
1b74dde7 | 494 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); |
8fa8b035 BP |
495 | } |
496 | } | |
497 | ||
498 | if (c->x86 == 0x15) { | |
499 | unsigned long upperbit; | |
500 | u32 cpuid, assoc; | |
501 | ||
502 | cpuid = cpuid_edx(0x80000005); | |
503 | assoc = cpuid >> 16 & 0xff; | |
504 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
505 | ||
506 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
507 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
4e26d11f HMG |
508 | |
509 | /* A random value per boot for bit slice [12:upper_bit) */ | |
510 | va_align.bits = get_random_int() & va_align.mask; | |
8fa8b035 | 511 | } |
b466bdb6 HR |
512 | |
513 | if (cpu_has(c, X86_FEATURE_MWAITX)) | |
514 | use_mwaitx_delay(); | |
8dfeae0d HR |
515 | |
516 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
517 | u32 ecx; | |
518 | ||
519 | ecx = cpuid_ecx(0x8000001e); | |
520 | nodes_per_socket = ((ecx >> 8) & 7) + 1; | |
521 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { | |
522 | u64 value; | |
523 | ||
524 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
525 | nodes_per_socket = ((value >> 3) & 7) + 1; | |
526 | } | |
8fa8b035 BP |
527 | } |
528 | ||
148f9bb8 | 529 | static void early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 530 | { |
11fdd252 YL |
531 | early_init_amd_mc(c); |
532 | ||
40fb1715 VP |
533 | /* |
534 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
535 | * with P/T states and does not stop in deep C-states | |
536 | */ | |
537 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 538 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 | 539 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
c98fdeaa | 540 | if (!check_tsc_unstable()) |
35af99e6 | 541 | set_sched_clock_stable(); |
40fb1715 | 542 | } |
5fef55fd | 543 | |
01fe03ff HR |
544 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ |
545 | if (c->x86_power & BIT(12)) | |
546 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); | |
547 | ||
6c62aa4a YL |
548 | #ifdef CONFIG_X86_64 |
549 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
550 | #else | |
5fef55fd | 551 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
552 | if (c->x86 == 5) |
553 | if (c->x86_model == 13 || c->x86_model == 9 || | |
554 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
555 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
556 | #endif | |
42937e81 | 557 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
b9d16a2a AG |
558 | /* |
559 | * ApicID can always be treated as an 8-bit value for AMD APIC versions | |
560 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we | |
561 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families | |
562 | * after 16h. | |
563 | */ | |
425d8c2f BP |
564 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
565 | if (c->x86 > 0x16) | |
42937e81 | 566 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
425d8c2f BP |
567 | else if (c->x86 >= 0xf) { |
568 | /* check CPU config space for extended APIC ID */ | |
569 | unsigned int val; | |
570 | ||
571 | val = read_pci_config(0, 24, 0, 0x68); | |
572 | if ((val >> 17 & 0x3) == 0x3) | |
573 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
574 | } | |
42937e81 AH |
575 | } |
576 | #endif | |
3b564968 | 577 | |
c1118b36 PB |
578 | /* |
579 | * This is only needed to tell the kernel whether to use VMCALL | |
580 | * and VMMCALL. VMMCALL is never executed except under virt, so | |
581 | * we can set it unconditionally. | |
582 | */ | |
583 | set_cpu_cap(c, X86_FEATURE_VMMCALL); | |
584 | ||
3b564968 | 585 | /* F16h erratum 793, CVE-2013-6885 */ |
8f86a737 BP |
586 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
587 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
2b16a235 AK |
588 | } |
589 | ||
e6ee94d5 | 590 | static const int amd_erratum_383[]; |
7d7dc116 | 591 | static const int amd_erratum_400[]; |
8c6b79bb | 592 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); |
e6ee94d5 | 593 | |
26bfa5f8 BP |
594 | static void init_amd_k8(struct cpuinfo_x86 *c) |
595 | { | |
596 | u32 level; | |
597 | u64 value; | |
598 | ||
599 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
600 | level = cpuid_eax(1); | |
601 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
602 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
603 | ||
604 | /* | |
605 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
606 | * (model = 0x14) and later actually support it. | |
607 | * (AMD Erratum #110, docId: 25759). | |
608 | */ | |
609 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
610 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
611 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
612 | value &= ~BIT_64(32); | |
613 | wrmsrl_amd_safe(0xc001100d, value); | |
614 | } | |
615 | } | |
616 | ||
617 | if (!c->x86_model_id[0]) | |
618 | strcpy(c->x86_model_id, "Hammer"); | |
6f9b63a0 BP |
619 | |
620 | #ifdef CONFIG_SMP | |
621 | /* | |
622 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
623 | * bit 6 of msr C001_0015 | |
624 | * | |
625 | * Errata 63 for SH-B3 steppings | |
626 | * Errata 122 for all steppings (F+ have it disabled by default) | |
627 | */ | |
628 | msr_set_bit(MSR_K7_HWCR, 6); | |
629 | #endif | |
96e5d28a | 630 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); |
26bfa5f8 BP |
631 | } |
632 | ||
633 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
634 | { | |
635 | #ifdef CONFIG_X86_64 | |
636 | /* do this for boot cpu */ | |
637 | if (c == &boot_cpu_data) | |
638 | check_enable_amd_mmconf_dmi(); | |
639 | ||
640 | fam10h_check_enable_mmcfg(); | |
641 | #endif | |
642 | ||
643 | /* | |
644 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
645 | * is always needed when GART is enabled, even in a kernel which has no | |
646 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
647 | * If it doesn't, we do it here as suggested by the BKDG. | |
648 | * | |
649 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
650 | */ | |
651 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
652 | ||
653 | /* | |
654 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
655 | * it to be converted to CD memtype. This may result in performance | |
656 | * degradation for certain nested-paging guests. Prevent this conversion | |
657 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
658 | * | |
659 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
660 | * guests on older kvm hosts. | |
661 | */ | |
662 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
663 | ||
664 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
665 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
666 | } | |
667 | ||
d1992996 EC |
668 | #define MSR_AMD64_DE_CFG 0xC0011029 |
669 | ||
670 | static void init_amd_ln(struct cpuinfo_x86 *c) | |
671 | { | |
672 | /* | |
673 | * Apply erratum 665 fix unconditionally so machines without a BIOS | |
674 | * fix work. | |
675 | */ | |
676 | msr_set_bit(MSR_AMD64_DE_CFG, 31); | |
677 | } | |
678 | ||
26bfa5f8 BP |
679 | static void init_amd_bd(struct cpuinfo_x86 *c) |
680 | { | |
681 | u64 value; | |
682 | ||
683 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
96685a55 | 684 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && |
26bfa5f8 BP |
685 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
686 | ||
687 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
688 | rdmsrl(0xc0011005, value); | |
689 | if (value & BIT_64(54)) { | |
690 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
96685a55 | 691 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); |
26bfa5f8 BP |
692 | } |
693 | } | |
694 | } | |
695 | ||
696 | /* | |
697 | * The way access filter has a performance penalty on some workloads. | |
698 | * Disable it on the affected CPUs. | |
699 | */ | |
700 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
ae8b7875 | 701 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { |
26bfa5f8 | 702 | value |= 0x1E; |
ae8b7875 | 703 | wrmsrl_safe(MSR_F15H_IC_CFG, value); |
26bfa5f8 BP |
704 | } |
705 | } | |
706 | } | |
707 | ||
148f9bb8 | 708 | static void init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 709 | { |
8e8da023 | 710 | u32 dummy; |
7d318d77 | 711 | |
2b16a235 AK |
712 | early_init_amd(c); |
713 | ||
fb87a298 PC |
714 | /* |
715 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 716 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 717 | */ |
16282a8e | 718 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 719 | |
12d8a961 | 720 | if (c->x86 >= 0x10) |
6c62aa4a | 721 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
722 | |
723 | /* get apicid instead of initial apic id from cpuid */ | |
724 | c->apicid = hard_smp_processor_id(); | |
11fdd252 YL |
725 | |
726 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
727 | if (c->x86 < 6) | |
728 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
26bfa5f8 BP |
729 | |
730 | switch (c->x86) { | |
731 | case 4: init_amd_k5(c); break; | |
732 | case 5: init_amd_k6(c); break; | |
733 | case 6: init_amd_k7(c); break; | |
734 | case 0xf: init_amd_k8(c); break; | |
735 | case 0x10: init_amd_gh(c); break; | |
d1992996 | 736 | case 0x12: init_amd_ln(c); break; |
26bfa5f8 BP |
737 | case 0x15: init_amd_bd(c); break; |
738 | } | |
11fdd252 | 739 | |
6c62aa4a | 740 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 741 | if (c->x86 >= 6) |
9b13a93d | 742 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
1da177e4 | 743 | |
27c13ece | 744 | cpu_detect_cache_sizes(c); |
3dd9d514 | 745 | |
11fdd252 | 746 | /* Multi core CPU? */ |
6c62aa4a | 747 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 748 | amd_detect_cmp(c); |
6c62aa4a YL |
749 | srat_detect_node(c); |
750 | } | |
faee9a5d | 751 | |
6c62aa4a | 752 | #ifdef CONFIG_X86_32 |
11fdd252 | 753 | detect_ht(c); |
6c62aa4a | 754 | #endif |
39b3a791 | 755 | |
04a15418 | 756 | init_amd_cacheinfo(c); |
3556ddfa | 757 | |
12d8a961 | 758 | if (c->x86 >= 0xf) |
11fdd252 | 759 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 760 | |
054efb64 | 761 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
11fdd252 | 762 | /* MFENCE stops RDTSC speculation */ |
16282a8e | 763 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 764 | } |
6c62aa4a | 765 | |
e9cdd343 BO |
766 | /* |
767 | * Family 0x12 and above processors have APIC timer | |
768 | * running in deep C states. | |
769 | */ | |
770 | if (c->x86 > 0x11) | |
b87cf80a | 771 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d | 772 | |
8c6b79bb | 773 | if (cpu_has_amd_erratum(c, amd_erratum_400)) |
7d7dc116 BP |
774 | set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); |
775 | ||
8e8da023 | 776 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
a930dc45 BP |
777 | |
778 | /* 3DNow or LM implies PREFETCHW */ | |
779 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) | |
780 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) | |
781 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); | |
61f01dd9 AL |
782 | |
783 | /* AMD CPUs don't reset SS attributes on SYSRET */ | |
784 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); | |
1da177e4 LT |
785 | } |
786 | ||
6c62aa4a | 787 | #ifdef CONFIG_X86_32 |
148f9bb8 | 788 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
789 | { |
790 | /* AMD errata T13 (order #21922) */ | |
791 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
792 | /* Duron Rev A0 */ |
793 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 794 | size = 64; |
8bdbd962 | 795 | /* Tbird rev A1/A2 */ |
1da177e4 | 796 | if (c->x86_model == 4 && |
8bdbd962 | 797 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
798 | size = 256; |
799 | } | |
800 | return size; | |
801 | } | |
6c62aa4a | 802 | #endif |
1da177e4 | 803 | |
148f9bb8 | 804 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
b46882e4 BP |
805 | { |
806 | u32 ebx, eax, ecx, edx; | |
807 | u16 mask = 0xfff; | |
808 | ||
809 | if (c->x86 < 0xf) | |
810 | return; | |
811 | ||
812 | if (c->extended_cpuid_level < 0x80000006) | |
813 | return; | |
814 | ||
815 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
816 | ||
817 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
818 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
819 | ||
820 | /* | |
821 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
822 | * characteristics from the CPUID function 0x80000005 instead. | |
823 | */ | |
824 | if (c->x86 == 0xf) { | |
825 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
826 | mask = 0xff; | |
827 | } | |
828 | ||
829 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
d1393367 BP |
830 | if (!((eax >> 16) & mask)) |
831 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
832 | else | |
b46882e4 | 833 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
b46882e4 BP |
834 | |
835 | /* a 4M entry uses two 2M entries */ | |
836 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
837 | ||
838 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
839 | if (!(eax & mask)) { | |
840 | /* Erratum 658 */ | |
841 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
842 | tlb_lli_2m[ENTRIES] = 1024; | |
843 | } else { | |
844 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
845 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
846 | } | |
847 | } else | |
848 | tlb_lli_2m[ENTRIES] = eax & mask; | |
849 | ||
850 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
851 | } | |
852 | ||
148f9bb8 | 853 | static const struct cpu_dev amd_cpu_dev = { |
1da177e4 | 854 | .c_vendor = "AMD", |
fb87a298 | 855 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 856 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
857 | .legacy_models = { |
858 | { .family = 4, .model_names = | |
1da177e4 LT |
859 | { |
860 | [3] = "486 DX/2", | |
861 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
862 | [8] = "486 DX/4", |
863 | [9] = "486 DX/4-WB", | |
1da177e4 | 864 | [14] = "Am5x86-WT", |
fb87a298 | 865 | [15] = "Am5x86-WB" |
1da177e4 LT |
866 | } |
867 | }, | |
868 | }, | |
09dc68d9 | 869 | .legacy_cache_size = amd_size_cache, |
6c62aa4a | 870 | #endif |
03ae5768 | 871 | .c_early_init = early_init_amd, |
b46882e4 | 872 | .c_detect_tlb = cpu_detect_tlb_amd, |
8fa8b035 | 873 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 874 | .c_init = init_amd, |
10a434fc | 875 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
876 | }; |
877 | ||
10a434fc | 878 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
879 | |
880 | /* | |
881 | * AMD errata checking | |
882 | * | |
883 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
884 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
885 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
886 | * variable number of family-specific model-stepping ranges created by | |
7d7dc116 | 887 | * AMD_MODEL_RANGE(). |
d78d671d HR |
888 | * |
889 | * Example: | |
890 | * | |
891 | * const int amd_erratum_319[] = | |
892 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
893 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
894 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
895 | */ | |
896 | ||
7d7dc116 BP |
897 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
898 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
899 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
900 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
901 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
902 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
903 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
904 | ||
905 | static const int amd_erratum_400[] = | |
328935e6 | 906 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 HR |
907 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
908 | ||
e6ee94d5 | 909 | static const int amd_erratum_383[] = |
1be85a6d | 910 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
9d8888c2 | 911 | |
8c6b79bb TK |
912 | |
913 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
d78d671d | 914 | { |
d78d671d HR |
915 | int osvw_id = *erratum++; |
916 | u32 range; | |
917 | u32 ms; | |
918 | ||
d78d671d HR |
919 | if (osvw_id >= 0 && osvw_id < 65536 && |
920 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
921 | u64 osvw_len; | |
922 | ||
923 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
924 | if (osvw_id < osvw_len) { | |
925 | u64 osvw_bits; | |
926 | ||
927 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
928 | osvw_bits); | |
929 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
930 | } | |
931 | } | |
932 | ||
933 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 934 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
935 | while ((range = *erratum++)) |
936 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
937 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
938 | (ms <= AMD_MODEL_RANGE_END(range))) | |
939 | return true; | |
940 | ||
941 | return false; | |
942 | } | |
d6d55f0b JS |
943 | |
944 | void set_dr_addr_mask(unsigned long mask, int dr) | |
945 | { | |
362f924b | 946 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) |
d6d55f0b JS |
947 | return; |
948 | ||
949 | switch (dr) { | |
950 | case 0: | |
951 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); | |
952 | break; | |
953 | case 1: | |
954 | case 2: | |
955 | case 3: | |
956 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); | |
957 | break; | |
958 | default: | |
959 | break; | |
960 | } | |
961 | } |