Commit | Line | Data |
---|---|---|
69c60c88 | 1 | #include <linux/export.h> |
1da177e4 | 2 | #include <linux/bitops.h> |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
c98fdeaa | 7 | #include <linux/sched.h> |
1da177e4 | 8 | #include <asm/processor.h> |
d3f7eae1 | 9 | #include <asm/apic.h> |
1f442d70 | 10 | #include <asm/cpu.h> |
26bfa5f8 | 11 | #include <asm/smp.h> |
42937e81 | 12 | #include <asm/pci-direct.h> |
1da177e4 | 13 | |
8d71a2ea | 14 | #ifdef CONFIG_X86_64 |
8d71a2ea YL |
15 | # include <asm/mmconfig.h> |
16 | # include <asm/cacheflush.h> | |
17 | #endif | |
18 | ||
1da177e4 LT |
19 | #include "cpu.h" |
20 | ||
2c929ce6 BP |
21 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
22 | { | |
2c929ce6 BP |
23 | u32 gprs[8] = { 0 }; |
24 | int err; | |
25 | ||
682469a5 BP |
26 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
27 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
28 | |
29 | gprs[1] = msr; | |
30 | gprs[7] = 0x9c5a203a; | |
31 | ||
32 | err = rdmsr_safe_regs(gprs); | |
33 | ||
34 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
35 | ||
36 | return err; | |
37 | } | |
38 | ||
39 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
40 | { | |
2c929ce6 BP |
41 | u32 gprs[8] = { 0 }; |
42 | ||
682469a5 BP |
43 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
44 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
45 | |
46 | gprs[0] = (u32)val; | |
47 | gprs[1] = msr; | |
48 | gprs[2] = val >> 32; | |
49 | gprs[7] = 0x9c5a203a; | |
50 | ||
51 | return wrmsr_safe_regs(gprs); | |
52 | } | |
53 | ||
1da177e4 LT |
54 | /* |
55 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
56 | * misexecution of code under Linux. Owners of such processors should | |
57 | * contact AMD for precise details and a CPU swap. | |
58 | * | |
59 | * See http://www.multimania.com/poulot/k6bug.html | |
d7de8649 AH |
60 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
61 | * (Publication # 21266 Issue Date: August 1998) | |
1da177e4 LT |
62 | * |
63 | * The following test is erm.. interesting. AMD neglected to up | |
64 | * the chip setting when fixing the bug but they also tweaked some | |
65 | * performance at the same time.. | |
66 | */ | |
fb87a298 | 67 | |
277d5b40 AK |
68 | extern __visible void vide(void); |
69 | __asm__(".globl vide\n\t.align 4\nvide: ret"); | |
1da177e4 | 70 | |
148f9bb8 | 71 | static void init_amd_k5(struct cpuinfo_x86 *c) |
11fdd252 | 72 | { |
26bfa5f8 | 73 | #ifdef CONFIG_X86_32 |
11fdd252 YL |
74 | /* |
75 | * General Systems BIOSen alias the cpu frequency registers | |
76 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux | |
77 | * drivers subsequently pokes it, and changes the CPU speed. | |
78 | * Workaround : Remove the unneeded alias. | |
79 | */ | |
80 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
81 | #define CBAR_ENB (0x80000000) | |
82 | #define CBAR_KEY (0X000000CB) | |
83 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
84 | if (inl(CBAR) & CBAR_ENB) |
85 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 | 86 | } |
26bfa5f8 | 87 | #endif |
11fdd252 YL |
88 | } |
89 | ||
148f9bb8 | 90 | static void init_amd_k6(struct cpuinfo_x86 *c) |
11fdd252 | 91 | { |
26bfa5f8 | 92 | #ifdef CONFIG_X86_32 |
11fdd252 | 93 | u32 l, h; |
46a84132 | 94 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
11fdd252 YL |
95 | |
96 | if (c->x86_model < 6) { | |
97 | /* Based on AMD doc 20734R - June 2000 */ | |
98 | if (c->x86_model == 0) { | |
99 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
100 | set_cpu_cap(c, X86_FEATURE_PGE); | |
101 | } | |
102 | return; | |
103 | } | |
104 | ||
105 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
106 | const int K6_BUG_LOOP = 1000000; | |
107 | int n; | |
108 | void (*f_vide)(void); | |
109 | unsigned long d, d2; | |
110 | ||
111 | printk(KERN_INFO "AMD K6 stepping B detected - "); | |
112 | ||
113 | /* | |
114 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
115 | * calls at the same time. | |
116 | */ | |
117 | ||
118 | n = K6_BUG_LOOP; | |
119 | f_vide = vide; | |
120 | rdtscl(d); | |
121 | while (n--) | |
122 | f_vide(); | |
123 | rdtscl(d2); | |
124 | d = d2-d; | |
125 | ||
126 | if (d > 20*K6_BUG_LOOP) | |
8bdbd962 AC |
127 | printk(KERN_CONT |
128 | "system stability may be impaired when more than 32 MB are used.\n"); | |
11fdd252 | 129 | else |
8bdbd962 | 130 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
131 | } |
132 | ||
133 | /* K6 with old style WHCR */ | |
134 | if (c->x86_model < 8 || | |
135 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
136 | /* We can only write allocate on the low 508Mb */ | |
137 | if (mbytes > 508) | |
138 | mbytes = 508; | |
139 | ||
140 | rdmsr(MSR_K6_WHCR, l, h); | |
141 | if ((l&0x0000FFFF) == 0) { | |
142 | unsigned long flags; | |
143 | l = (1<<0)|((mbytes/4)<<1); | |
144 | local_irq_save(flags); | |
145 | wbinvd(); | |
146 | wrmsr(MSR_K6_WHCR, l, h); | |
147 | local_irq_restore(flags); | |
148 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", | |
149 | mbytes); | |
150 | } | |
151 | return; | |
152 | } | |
153 | ||
154 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
155 | c->x86_model == 9 || c->x86_model == 13) { | |
156 | /* The more serious chips .. */ | |
157 | ||
158 | if (mbytes > 4092) | |
159 | mbytes = 4092; | |
160 | ||
161 | rdmsr(MSR_K6_WHCR, l, h); | |
162 | if ((l&0xFFFF0000) == 0) { | |
163 | unsigned long flags; | |
164 | l = ((mbytes>>2)<<22)|(1<<16); | |
165 | local_irq_save(flags); | |
166 | wbinvd(); | |
167 | wrmsr(MSR_K6_WHCR, l, h); | |
168 | local_irq_restore(flags); | |
169 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", | |
170 | mbytes); | |
171 | } | |
172 | ||
173 | return; | |
174 | } | |
175 | ||
176 | if (c->x86_model == 10) { | |
177 | /* AMD Geode LX is model 10 */ | |
178 | /* placeholder for any needed mods */ | |
179 | return; | |
180 | } | |
26bfa5f8 | 181 | #endif |
11fdd252 YL |
182 | } |
183 | ||
26bfa5f8 | 184 | static void init_amd_k7(struct cpuinfo_x86 *c) |
1f442d70 | 185 | { |
26bfa5f8 BP |
186 | #ifdef CONFIG_X86_32 |
187 | u32 l, h; | |
188 | ||
189 | /* | |
190 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
191 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
192 | * If the BIOS didn't enable it already, enable it here. | |
193 | */ | |
194 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
195 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
196 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); | |
197 | msr_clear_bit(MSR_K7_HWCR, 15); | |
198 | set_cpu_cap(c, X86_FEATURE_XMM); | |
199 | } | |
200 | } | |
201 | ||
202 | /* | |
203 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
204 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
205 | * As per AMD technical note 27212 0.2 | |
206 | */ | |
207 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
208 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
209 | if ((l & 0xfff00000) != 0x20000000) { | |
210 | printk(KERN_INFO | |
211 | "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", | |
212 | l, ((l & 0x000fffff)|0x20000000)); | |
213 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); | |
214 | } | |
215 | } | |
216 | ||
217 | set_cpu_cap(c, X86_FEATURE_K7); | |
218 | ||
1f442d70 | 219 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 220 | if (!c->cpu_index) |
1f442d70 YL |
221 | return; |
222 | ||
223 | /* | |
224 | * Certain Athlons might work (for various values of 'work') in SMP | |
225 | * but they are not certified as MP capable. | |
226 | */ | |
227 | /* Athlon 660/661 is valid. */ | |
228 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
229 | (c->x86_mask == 1))) | |
1077c932 | 230 | return; |
1f442d70 YL |
231 | |
232 | /* Duron 670 is valid */ | |
233 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
1077c932 | 234 | return; |
1f442d70 YL |
235 | |
236 | /* | |
237 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
238 | * bit. It's worth noting that the A5 stepping (662) of some | |
239 | * Athlon XP's have the MP bit set. | |
240 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
241 | * more. | |
242 | */ | |
243 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
244 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
245 | (c->x86_model > 7)) | |
26bfa5f8 | 246 | if (cpu_has(c, X86_FEATURE_MP)) |
1077c932 | 247 | return; |
1f442d70 YL |
248 | |
249 | /* If we get here, not a certified SMP capable AMD system. */ | |
250 | ||
251 | /* | |
252 | * Don't taint if we are running SMP kernel on a single non-MP | |
253 | * approved Athlon | |
254 | */ | |
255 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 256 | " processors is not suitable for SMP.\n"); |
8c90487c | 257 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
6c62aa4a | 258 | #endif |
26bfa5f8 | 259 | } |
6c62aa4a | 260 | |
645a7919 | 261 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
262 | /* |
263 | * To workaround broken NUMA config. Read the comment in | |
264 | * srat_detect_node(). | |
265 | */ | |
148f9bb8 | 266 | static int nearby_node(int apicid) |
6c62aa4a YL |
267 | { |
268 | int i, node; | |
269 | ||
270 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 271 | node = __apicid_to_node[i]; |
6c62aa4a YL |
272 | if (node != NUMA_NO_NODE && node_online(node)) |
273 | return node; | |
274 | } | |
275 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 276 | node = __apicid_to_node[i]; |
6c62aa4a YL |
277 | if (node != NUMA_NO_NODE && node_online(node)) |
278 | return node; | |
279 | } | |
280 | return first_node(node_online_map); /* Shouldn't happen */ | |
281 | } | |
282 | #endif | |
11fdd252 | 283 | |
4a376ec3 | 284 | /* |
23588c38 AH |
285 | * Fixup core topology information for |
286 | * (1) AMD multi-node processors | |
287 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 288 | * (2) AMD processors supporting compute units |
4a376ec3 AH |
289 | */ |
290 | #ifdef CONFIG_X86_HT | |
148f9bb8 | 291 | static void amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 292 | { |
9e81509e | 293 | u32 nodes, cores_per_cu = 1; |
23588c38 | 294 | u8 node_id; |
4a376ec3 AH |
295 | int cpu = smp_processor_id(); |
296 | ||
23588c38 | 297 | /* get information required for multi-node processors */ |
193f3fcb | 298 | if (cpu_has_topoext) { |
6057b4d3 AH |
299 | u32 eax, ebx, ecx, edx; |
300 | ||
301 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); | |
302 | nodes = ((ecx >> 8) & 7) + 1; | |
303 | node_id = ecx & 7; | |
304 | ||
305 | /* get compute unit information */ | |
306 | smp_num_siblings = ((ebx >> 8) & 3) + 1; | |
307 | c->compute_unit_id = ebx & 0xff; | |
9e81509e | 308 | cores_per_cu += ((ebx >> 8) & 3); |
23588c38 | 309 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
310 | u64 value; |
311 | ||
23588c38 AH |
312 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
313 | nodes = ((value >> 3) & 7) + 1; | |
314 | node_id = value & 7; | |
315 | } else | |
4a376ec3 AH |
316 | return; |
317 | ||
23588c38 AH |
318 | /* fixup multi-node processor information */ |
319 | if (nodes > 1) { | |
6057b4d3 | 320 | u32 cores_per_node; |
d518573d | 321 | u32 cus_per_node; |
6057b4d3 | 322 | |
23588c38 AH |
323 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
324 | cores_per_node = c->x86_max_cores / nodes; | |
d518573d | 325 | cus_per_node = cores_per_node / cores_per_cu; |
9d260ebc | 326 | |
23588c38 AH |
327 | /* store NodeID, use llc_shared_map to store sibling info */ |
328 | per_cpu(cpu_llc_id, cpu) = node_id; | |
4a376ec3 | 329 | |
9e81509e | 330 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
d518573d AH |
331 | c->cpu_core_id %= cores_per_node; |
332 | c->compute_unit_id %= cus_per_node; | |
23588c38 | 333 | } |
4a376ec3 AH |
334 | } |
335 | #endif | |
336 | ||
11fdd252 | 337 | /* |
aa5e5dc2 | 338 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
11fdd252 YL |
339 | * Assumes number of cores is a power of two. |
340 | */ | |
148f9bb8 | 341 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
11fdd252 YL |
342 | { |
343 | #ifdef CONFIG_X86_HT | |
344 | unsigned bits; | |
99bd0c0f | 345 | int cpu = smp_processor_id(); |
11fdd252 YL |
346 | |
347 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
348 | /* Low order bits define the core id (index of core in socket) */ |
349 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
350 | /* Convert the initial APIC ID into the socket ID */ | |
351 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
352 | /* use socket ID also for last level cache */ |
353 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 354 | amd_get_topology(c); |
11fdd252 YL |
355 | #endif |
356 | } | |
357 | ||
8b84c8df | 358 | u16 amd_get_nb_id(int cpu) |
6a812691 | 359 | { |
8b84c8df | 360 | u16 id = 0; |
6a812691 AH |
361 | #ifdef CONFIG_SMP |
362 | id = per_cpu(cpu_llc_id, cpu); | |
363 | #endif | |
364 | return id; | |
365 | } | |
366 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
367 | ||
148f9bb8 | 368 | static void srat_detect_node(struct cpuinfo_x86 *c) |
6c62aa4a | 369 | { |
645a7919 | 370 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
371 | int cpu = smp_processor_id(); |
372 | int node; | |
0d96b9ff | 373 | unsigned apicid = c->apicid; |
6c62aa4a | 374 | |
bbc9e2f4 TH |
375 | node = numa_cpu_node(cpu); |
376 | if (node == NUMA_NO_NODE) | |
377 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 378 | |
64be4c1c | 379 | /* |
68894632 AH |
380 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
381 | * platform-specific handler needs to be called to fixup some | |
382 | * IDs of the CPU. | |
64be4c1c | 383 | */ |
68894632 | 384 | if (x86_cpuinit.fixup_cpu_id) |
64be4c1c DB |
385 | x86_cpuinit.fixup_cpu_id(c, node); |
386 | ||
6c62aa4a | 387 | if (!node_online(node)) { |
bbc9e2f4 TH |
388 | /* |
389 | * Two possibilities here: | |
390 | * | |
391 | * - The CPU is missing memory and no node was created. In | |
392 | * that case try picking one from a nearby CPU. | |
393 | * | |
394 | * - The APIC IDs differ from the HyperTransport node IDs | |
395 | * which the K8 northbridge parsing fills in. Assume | |
396 | * they are all increased by a constant offset, but in | |
397 | * the same order as the HT nodeids. If that doesn't | |
398 | * result in a usable node fall back to the path for the | |
399 | * previous case. | |
400 | * | |
401 | * This workaround operates directly on the mapping between | |
402 | * APIC ID and NUMA node, assuming certain relationship | |
403 | * between APIC ID, HT node ID and NUMA topology. As going | |
404 | * through CPU mapping may alter the outcome, directly | |
405 | * access __apicid_to_node[]. | |
406 | */ | |
6c62aa4a YL |
407 | int ht_nodeid = c->initial_apicid; |
408 | ||
409 | if (ht_nodeid >= 0 && | |
bbc9e2f4 TH |
410 | __apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
411 | node = __apicid_to_node[ht_nodeid]; | |
6c62aa4a YL |
412 | /* Pick a nearby node */ |
413 | if (!node_online(node)) | |
414 | node = nearby_node(apicid); | |
415 | } | |
416 | numa_set_node(cpu, node); | |
6c62aa4a YL |
417 | #endif |
418 | } | |
419 | ||
148f9bb8 | 420 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
11fdd252 YL |
421 | { |
422 | #ifdef CONFIG_X86_HT | |
423 | unsigned bits, ecx; | |
424 | ||
425 | /* Multi core CPU? */ | |
426 | if (c->extended_cpuid_level < 0x80000008) | |
427 | return; | |
428 | ||
429 | ecx = cpuid_ecx(0x80000008); | |
430 | ||
431 | c->x86_max_cores = (ecx & 0xff) + 1; | |
432 | ||
433 | /* CPU telling us the core id bits shift? */ | |
434 | bits = (ecx >> 12) & 0xF; | |
435 | ||
436 | /* Otherwise recompute */ | |
437 | if (bits == 0) { | |
438 | while ((1 << bits) < c->x86_max_cores) | |
439 | bits++; | |
440 | } | |
441 | ||
442 | c->x86_coreid_bits = bits; | |
443 | #endif | |
444 | } | |
445 | ||
148f9bb8 | 446 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
8fa8b035 | 447 | { |
26bfa5f8 BP |
448 | |
449 | #ifdef CONFIG_X86_64 | |
450 | if (c->x86 >= 0xf) { | |
451 | unsigned long long tseg; | |
452 | ||
453 | /* | |
454 | * Split up direct mapping around the TSEG SMM area. | |
455 | * Don't do it for gbpages because there seems very little | |
456 | * benefit in doing so. | |
457 | */ | |
458 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
459 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
460 | ||
461 | printk(KERN_DEBUG "tseg: %010llx\n", tseg); | |
462 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
463 | set_memory_4k((unsigned long)__va(tseg), 1); | |
464 | } | |
465 | } | |
466 | #endif | |
467 | ||
8fa8b035 BP |
468 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
469 | ||
470 | if (c->x86 > 0x10 || | |
471 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
472 | u64 val; | |
473 | ||
474 | rdmsrl(MSR_K7_HWCR, val); | |
475 | if (!(val & BIT(24))) | |
476 | printk(KERN_WARNING FW_BUG "TSC doesn't count " | |
477 | "with P0 frequency!\n"); | |
478 | } | |
479 | } | |
480 | ||
481 | if (c->x86 == 0x15) { | |
482 | unsigned long upperbit; | |
483 | u32 cpuid, assoc; | |
484 | ||
485 | cpuid = cpuid_edx(0x80000005); | |
486 | assoc = cpuid >> 16 & 0xff; | |
487 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
488 | ||
489 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
490 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
491 | } | |
492 | } | |
493 | ||
148f9bb8 | 494 | static void early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 495 | { |
11fdd252 YL |
496 | early_init_amd_mc(c); |
497 | ||
40fb1715 VP |
498 | /* |
499 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
500 | * with P/T states and does not stop in deep C-states | |
501 | */ | |
502 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 503 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 | 504 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
c98fdeaa | 505 | if (!check_tsc_unstable()) |
35af99e6 | 506 | set_sched_clock_stable(); |
40fb1715 | 507 | } |
5fef55fd | 508 | |
6c62aa4a YL |
509 | #ifdef CONFIG_X86_64 |
510 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
511 | #else | |
5fef55fd | 512 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
513 | if (c->x86 == 5) |
514 | if (c->x86_model == 13 || c->x86_model == 9 || | |
515 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
516 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
517 | #endif | |
42937e81 AH |
518 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
519 | /* check CPU config space for extended APIC ID */ | |
2cb07860 | 520 | if (cpu_has_apic && c->x86 >= 0xf) { |
42937e81 AH |
521 | unsigned int val; |
522 | val = read_pci_config(0, 24, 0, 0x68); | |
523 | if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18))) | |
524 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
525 | } | |
526 | #endif | |
3b564968 BP |
527 | |
528 | /* F16h erratum 793, CVE-2013-6885 */ | |
8f86a737 BP |
529 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
530 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
2b16a235 AK |
531 | } |
532 | ||
e6ee94d5 | 533 | static const int amd_erratum_383[]; |
7d7dc116 | 534 | static const int amd_erratum_400[]; |
8c6b79bb | 535 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); |
e6ee94d5 | 536 | |
26bfa5f8 BP |
537 | static void init_amd_k8(struct cpuinfo_x86 *c) |
538 | { | |
539 | u32 level; | |
540 | u64 value; | |
541 | ||
542 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
543 | level = cpuid_eax(1); | |
544 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
545 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
546 | ||
547 | /* | |
548 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
549 | * (model = 0x14) and later actually support it. | |
550 | * (AMD Erratum #110, docId: 25759). | |
551 | */ | |
552 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
553 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
554 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
555 | value &= ~BIT_64(32); | |
556 | wrmsrl_amd_safe(0xc001100d, value); | |
557 | } | |
558 | } | |
559 | ||
560 | if (!c->x86_model_id[0]) | |
561 | strcpy(c->x86_model_id, "Hammer"); | |
562 | } | |
563 | ||
564 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
565 | { | |
566 | #ifdef CONFIG_X86_64 | |
567 | /* do this for boot cpu */ | |
568 | if (c == &boot_cpu_data) | |
569 | check_enable_amd_mmconf_dmi(); | |
570 | ||
571 | fam10h_check_enable_mmcfg(); | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
576 | * is always needed when GART is enabled, even in a kernel which has no | |
577 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
578 | * If it doesn't, we do it here as suggested by the BKDG. | |
579 | * | |
580 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
581 | */ | |
582 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
583 | ||
584 | /* | |
585 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
586 | * it to be converted to CD memtype. This may result in performance | |
587 | * degradation for certain nested-paging guests. Prevent this conversion | |
588 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
589 | * | |
590 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
591 | * guests on older kvm hosts. | |
592 | */ | |
593 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
594 | ||
595 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
596 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
597 | } | |
598 | ||
599 | static void init_amd_bd(struct cpuinfo_x86 *c) | |
600 | { | |
601 | u64 value; | |
602 | ||
603 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
604 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) && | |
605 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { | |
606 | ||
607 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
608 | rdmsrl(0xc0011005, value); | |
609 | if (value & BIT_64(54)) { | |
610 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
611 | pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); | |
612 | } | |
613 | } | |
614 | } | |
615 | ||
616 | /* | |
617 | * The way access filter has a performance penalty on some workloads. | |
618 | * Disable it on the affected CPUs. | |
619 | */ | |
620 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
621 | if (!rdmsrl_safe(0xc0011021, &value) && !(value & 0x1E)) { | |
622 | value |= 0x1E; | |
623 | wrmsrl_safe(0xc0011021, value); | |
624 | } | |
625 | } | |
626 | } | |
627 | ||
148f9bb8 | 628 | static void init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 629 | { |
8e8da023 | 630 | u32 dummy; |
7d318d77 | 631 | |
6bf08a8d | 632 | #ifdef CONFIG_SMP |
fb87a298 PC |
633 | /* |
634 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
7d318d77 AK |
635 | * bit 6 of msr C001_0015 |
636 | * | |
637 | * Errata 63 for SH-B3 steppings | |
638 | * Errata 122 for all steppings (F+ have it disabled by default) | |
639 | */ | |
8f86a737 BP |
640 | if (c->x86 == 0xf) |
641 | msr_set_bit(MSR_K7_HWCR, 6); | |
7d318d77 AK |
642 | #endif |
643 | ||
2b16a235 AK |
644 | early_init_amd(c); |
645 | ||
fb87a298 PC |
646 | /* |
647 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 648 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 649 | */ |
16282a8e | 650 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 651 | |
12d8a961 | 652 | if (c->x86 >= 0x10) |
6c62aa4a | 653 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
654 | |
655 | /* get apicid instead of initial apic id from cpuid */ | |
656 | c->apicid = hard_smp_processor_id(); | |
11fdd252 YL |
657 | |
658 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
659 | if (c->x86 < 6) | |
660 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
26bfa5f8 BP |
661 | |
662 | switch (c->x86) { | |
663 | case 4: init_amd_k5(c); break; | |
664 | case 5: init_amd_k6(c); break; | |
665 | case 6: init_amd_k7(c); break; | |
666 | case 0xf: init_amd_k8(c); break; | |
667 | case 0x10: init_amd_gh(c); break; | |
668 | case 0x15: init_amd_bd(c); break; | |
669 | } | |
11fdd252 | 670 | |
6c62aa4a | 671 | /* Enable workaround for FXSAVE leak */ |
18bd057b | 672 | if (c->x86 >= 6) |
9b13a93d | 673 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
1da177e4 | 674 | |
27c13ece | 675 | cpu_detect_cache_sizes(c); |
3dd9d514 | 676 | |
11fdd252 | 677 | /* Multi core CPU? */ |
6c62aa4a | 678 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 679 | amd_detect_cmp(c); |
6c62aa4a YL |
680 | srat_detect_node(c); |
681 | } | |
faee9a5d | 682 | |
6c62aa4a | 683 | #ifdef CONFIG_X86_32 |
11fdd252 | 684 | detect_ht(c); |
6c62aa4a | 685 | #endif |
39b3a791 | 686 | |
04a15418 | 687 | init_amd_cacheinfo(c); |
3556ddfa | 688 | |
12d8a961 | 689 | if (c->x86 >= 0xf) |
11fdd252 | 690 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 691 | |
11fdd252 YL |
692 | if (cpu_has_xmm2) { |
693 | /* MFENCE stops RDTSC speculation */ | |
16282a8e | 694 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); |
11fdd252 | 695 | } |
6c62aa4a | 696 | |
e9cdd343 BO |
697 | /* |
698 | * Family 0x12 and above processors have APIC timer | |
699 | * running in deep C states. | |
700 | */ | |
701 | if (c->x86 > 0x11) | |
b87cf80a | 702 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d | 703 | |
8c6b79bb | 704 | if (cpu_has_amd_erratum(c, amd_erratum_400)) |
7d7dc116 BP |
705 | set_cpu_bug(c, X86_BUG_AMD_APIC_C1E); |
706 | ||
8e8da023 | 707 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
1da177e4 LT |
708 | } |
709 | ||
6c62aa4a | 710 | #ifdef CONFIG_X86_32 |
148f9bb8 | 711 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
712 | { |
713 | /* AMD errata T13 (order #21922) */ | |
714 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
715 | /* Duron Rev A0 */ |
716 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 717 | size = 64; |
8bdbd962 | 718 | /* Tbird rev A1/A2 */ |
1da177e4 | 719 | if (c->x86_model == 4 && |
8bdbd962 | 720 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
721 | size = 256; |
722 | } | |
723 | return size; | |
724 | } | |
6c62aa4a | 725 | #endif |
1da177e4 | 726 | |
148f9bb8 | 727 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
b46882e4 BP |
728 | { |
729 | u32 ebx, eax, ecx, edx; | |
730 | u16 mask = 0xfff; | |
731 | ||
732 | if (c->x86 < 0xf) | |
733 | return; | |
734 | ||
735 | if (c->extended_cpuid_level < 0x80000006) | |
736 | return; | |
737 | ||
738 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
739 | ||
740 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
741 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
742 | ||
743 | /* | |
744 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
745 | * characteristics from the CPUID function 0x80000005 instead. | |
746 | */ | |
747 | if (c->x86 == 0xf) { | |
748 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
749 | mask = 0xff; | |
750 | } | |
751 | ||
752 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
d1393367 BP |
753 | if (!((eax >> 16) & mask)) |
754 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
755 | else | |
b46882e4 | 756 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
b46882e4 BP |
757 | |
758 | /* a 4M entry uses two 2M entries */ | |
759 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
760 | ||
761 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
762 | if (!(eax & mask)) { | |
763 | /* Erratum 658 */ | |
764 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
765 | tlb_lli_2m[ENTRIES] = 1024; | |
766 | } else { | |
767 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
768 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
769 | } | |
770 | } else | |
771 | tlb_lli_2m[ENTRIES] = eax & mask; | |
772 | ||
773 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
774 | } | |
775 | ||
148f9bb8 | 776 | static const struct cpu_dev amd_cpu_dev = { |
1da177e4 | 777 | .c_vendor = "AMD", |
fb87a298 | 778 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 779 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
780 | .legacy_models = { |
781 | { .family = 4, .model_names = | |
1da177e4 LT |
782 | { |
783 | [3] = "486 DX/2", | |
784 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
785 | [8] = "486 DX/4", |
786 | [9] = "486 DX/4-WB", | |
1da177e4 | 787 | [14] = "Am5x86-WT", |
fb87a298 | 788 | [15] = "Am5x86-WB" |
1da177e4 LT |
789 | } |
790 | }, | |
791 | }, | |
09dc68d9 | 792 | .legacy_cache_size = amd_size_cache, |
6c62aa4a | 793 | #endif |
03ae5768 | 794 | .c_early_init = early_init_amd, |
b46882e4 | 795 | .c_detect_tlb = cpu_detect_tlb_amd, |
8fa8b035 | 796 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 797 | .c_init = init_amd, |
10a434fc | 798 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
799 | }; |
800 | ||
10a434fc | 801 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
802 | |
803 | /* | |
804 | * AMD errata checking | |
805 | * | |
806 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
807 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
808 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
809 | * variable number of family-specific model-stepping ranges created by | |
7d7dc116 | 810 | * AMD_MODEL_RANGE(). |
d78d671d HR |
811 | * |
812 | * Example: | |
813 | * | |
814 | * const int amd_erratum_319[] = | |
815 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
816 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
817 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
818 | */ | |
819 | ||
7d7dc116 BP |
820 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
821 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
822 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
823 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
824 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
825 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
826 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
827 | ||
828 | static const int amd_erratum_400[] = | |
328935e6 | 829 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 HR |
830 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
831 | ||
e6ee94d5 | 832 | static const int amd_erratum_383[] = |
1be85a6d | 833 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
9d8888c2 | 834 | |
8c6b79bb TK |
835 | |
836 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
d78d671d | 837 | { |
d78d671d HR |
838 | int osvw_id = *erratum++; |
839 | u32 range; | |
840 | u32 ms; | |
841 | ||
d78d671d HR |
842 | if (osvw_id >= 0 && osvw_id < 65536 && |
843 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
844 | u64 osvw_len; | |
845 | ||
846 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
847 | if (osvw_id < osvw_len) { | |
848 | u64 osvw_bits; | |
849 | ||
850 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
851 | osvw_bits); | |
852 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
853 | } | |
854 | } | |
855 | ||
856 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 857 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
858 | while ((range = *erratum++)) |
859 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
860 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
861 | (ms <= AMD_MODEL_RANGE_END(range))) | |
862 | return true; | |
863 | ||
864 | return false; | |
865 | } |