x86: fold apic_ops into genapic
[linux-2.6-block.git] / arch / x86 / kernel / bigsmp_32.c
CommitLineData
637cba02 1/*
1da177e4
LT
2 * APIC driver for "bigsmp" XAPIC machines with more than 8 virtual CPUs.
3 * Drives the local APIC in "clustered mode".
4 */
5#define APIC_DEFINITION 1
1da177e4
LT
6#include <linux/threads.h>
7#include <linux/cpumask.h>
8#include <asm/mpspec.h>
9#include <asm/genapic.h>
10#include <asm/fixmap.h>
11#include <asm/apicdef.h>
43f39890 12#include <asm/ipi.h>
1da177e4 13#include <linux/kernel.h>
1da177e4
LT
14#include <linux/init.h>
15#include <linux/dmi.h>
4696ca5b 16#include <linux/smp.h>
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17
18
19static inline unsigned bigsmp_get_apic_id(unsigned long x)
20{
21 return (x >> 24) & 0xFF;
22}
23
24#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
25
26static inline int bigsmp_apic_id_registered(void)
27{
28 return 1;
29}
30
31static inline const cpumask_t *bigsmp_target_cpus(void)
32{
33#ifdef CONFIG_SMP
34 return &cpu_online_map;
35#else
36 return &cpumask_of_cpu(0);
37#endif
38}
39
40#define APIC_DFR_VALUE (APIC_DFR_FLAT)
41
42static inline unsigned long
43bigsmp_check_apicid_used(physid_mask_t bitmap, int apicid)
44{
45 return 0;
46}
47
48static inline unsigned long bigsmp_check_apicid_present(int bit)
49{
50 return 1;
51}
52
53static inline unsigned long calculate_ldr(int cpu)
54{
55 unsigned long val, id;
56 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
57 id = xapic_phys_to_log_apicid(cpu);
58 val |= SET_APIC_LOGICAL_ID(id);
59 return val;
60}
61
62/*
63 * Set up the logical destination ID.
64 *
65 * Intel recommends to set DFR, LDR and TPR before enabling
66 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
67 * document number 292116). So here it goes...
68 */
69static inline void bigsmp_init_apic_ldr(void)
70{
71 unsigned long val;
72 int cpu = smp_processor_id();
73
74 apic_write(APIC_DFR, APIC_DFR_VALUE);
75 val = calculate_ldr(cpu);
76 apic_write(APIC_LDR, val);
77}
78
79static inline void bigsmp_setup_apic_routing(void)
80{
81 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
82 "Physflat", nr_ioapics);
83}
84
85static inline int bigsmp_apicid_to_node(int logical_apicid)
86{
87 return apicid_2_node[hard_smp_processor_id()];
88}
89
90static inline int bigsmp_cpu_present_to_apicid(int mps_cpu)
91{
92 if (mps_cpu < nr_cpu_ids)
93 return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
94
95 return BAD_APICID;
96}
97
98static inline physid_mask_t bigsmp_apicid_to_cpu_present(int phys_apicid)
99{
100 return physid_mask_of_physid(phys_apicid);
101}
102
103extern u8 cpu_2_logical_apicid[];
104/* Mapping from cpu number to logical apicid */
105static inline int bigsmp_cpu_to_logical_apicid(int cpu)
106{
107 if (cpu >= nr_cpu_ids)
108 return BAD_APICID;
109 return cpu_physical_id(cpu);
110}
111
112static inline physid_mask_t bigsmp_ioapic_phys_id_map(physid_mask_t phys_map)
113{
114 /* For clustered we don't have a good way to do this yet - hack */
115 return physids_promote(0xFFL);
116}
117
118static inline void bigsmp_setup_portio_remap(void)
119{
120}
121
122static inline int bigsmp_check_phys_apicid_present(int boot_cpu_physical_apicid)
123{
124 return 1;
125}
126
127/* As we are using single CPU as destination, pick only one CPU here */
128static inline unsigned int bigsmp_cpu_mask_to_apicid(const cpumask_t *cpumask)
129{
130 return bigsmp_cpu_to_logical_apicid(first_cpu(*cpumask));
131}
132
133static inline unsigned int
134bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
135 const struct cpumask *andmask)
136{
137 int cpu;
138
139 /*
140 * We're using fixed IRQ delivery, can only return one phys APIC ID.
141 * May as well be the first.
142 */
143 for_each_cpu_and(cpu, cpumask, andmask) {
144 if (cpumask_test_cpu(cpu, cpu_online_mask))
145 break;
146 }
147 if (cpu < nr_cpu_ids)
148 return bigsmp_cpu_to_logical_apicid(cpu);
149
150 return BAD_APICID;
151}
152
153static inline int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb)
154{
155 return cpuid_apic >> index_msb;
156}
157
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158static inline void bigsmp_send_IPI_mask(const struct cpumask *mask, int vector)
159{
43f39890 160 default_send_IPI_mask_sequence_phys(mask, vector);
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IM
161}
162
163static inline void bigsmp_send_IPI_allbutself(int vector)
164{
43f39890 165 default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
9f4187f0
IM
166}
167
168static inline void bigsmp_send_IPI_all(int vector)
169{
170 bigsmp_send_IPI_mask(cpu_online_mask, vector);
171}
1da177e4
LT
172
173static int dmi_bigsmp; /* can be set by dmi scanners */
174
1855256c 175static int hp_ht_bigsmp(const struct dmi_system_id *d)
1da177e4 176{
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LT
177 printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
178 dmi_bigsmp = 1;
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LT
179 return 0;
180}
181
182
1855256c 183static const struct dmi_system_id bigsmp_dmi_table[] = {
637cba02
PC
184 { hp_ht_bigsmp, "HP ProLiant DL760 G2",
185 { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
186 DMI_MATCH(DMI_BIOS_VERSION, "P44-"),}
187 },
188
189 { hp_ht_bigsmp, "HP ProLiant DL740",
190 { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
191 DMI_MATCH(DMI_BIOS_VERSION, "P47-"),}
192 },
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LT
193 { }
194};
195
e2d40b18 196static void bigsmp_vector_allocation_domain(int cpu, cpumask_t *retmask)
497c9a19 197{
e7986739
MT
198 cpus_clear(*retmask);
199 cpu_set(cpu, *retmask);
497c9a19 200}
1da177e4 201
af669c97 202static int probe_bigsmp(void)
637cba02 203{
911a62d4 204 if (def_to_bigsmp)
e0da3364 205 dmi_bigsmp = 1;
911a62d4
VP
206 else
207 dmi_check_system(bigsmp_dmi_table);
637cba02
PC
208 return dmi_bigsmp;
209}
1da177e4 210
d26b6d66
IM
211struct genapic apic_bigsmp = {
212
213 .name = "bigsmp",
214 .probe = probe_bigsmp,
306db03b 215 .acpi_madt_oem_check = NULL,
7ed248da 216 .apic_id_registered = bigsmp_apic_id_registered,
d26b6d66 217
d8a3539e
IM
218 .irq_delivery_mode = dest_Fixed,
219 /* phys delivery to target CPU: */
220 .irq_dest_mode = 0,
d26b6d66 221
0a9cc20b 222 .target_cpus = bigsmp_target_cpus,
08125d3e 223 .disable_esr = 1,
bdb1a9b6 224 .dest_logical = 0,
d1d7cae8
IM
225 .check_apicid_used = bigsmp_check_apicid_used,
226 .check_apicid_present = bigsmp_check_apicid_present,
d26b6d66 227
e2d40b18 228 .vector_allocation_domain = bigsmp_vector_allocation_domain,
a5c43296 229 .init_apic_ldr = bigsmp_init_apic_ldr,
d26b6d66 230
d190cb87 231 .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map,
72ce0165 232 .setup_apic_routing = bigsmp_setup_apic_routing,
33a201fa 233 .multi_timer_check = NULL,
3f57a318 234 .apicid_to_node = bigsmp_apicid_to_node,
5257c511 235 .cpu_to_logical_apicid = bigsmp_cpu_to_logical_apicid,
a21769a4 236 .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid,
8058714a 237 .apicid_to_cpu_present = bigsmp_apicid_to_cpu_present,
d83093b5 238 .setup_portio_remap = NULL,
a27a6210 239 .check_phys_apicid_present = bigsmp_check_phys_apicid_present,
49040333 240 .enable_apic_mode = NULL,
cb8cc442 241 .phys_pkg_id = bigsmp_phys_pkg_id,
9c764247 242 .mps_oem_check = NULL,
d26b6d66 243
ca6c8ed4 244 .get_apic_id = bigsmp_get_apic_id,
d26b6d66 245 .set_apic_id = NULL,
94af1875 246 .apic_id_mask = 0xFF << 24,
d26b6d66 247
debccb3e
IM
248 .cpu_mask_to_apicid = bigsmp_cpu_mask_to_apicid,
249 .cpu_mask_to_apicid_and = bigsmp_cpu_mask_to_apicid_and,
d26b6d66 250
9f4187f0 251 .send_IPI_mask = bigsmp_send_IPI_mask,
d26b6d66 252 .send_IPI_mask_allbutself = NULL,
dac5f412
IM
253 .send_IPI_allbutself = bigsmp_send_IPI_allbutself,
254 .send_IPI_all = bigsmp_send_IPI_all,
6b64ee02 255 .send_IPI_self = default_send_IPI_self,
d26b6d66
IM
256
257 .wakeup_cpu = NULL,
6f177c01
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258 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
259 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
a9659366
IM
260
261 .wait_for_init_deassert = default_wait_for_init_deassert,
262
333344d9 263 .smp_callin_clear_local_apic = NULL,
7bd06ec6 264 .store_NMI_vector = NULL,
25dc0049 265 .inquire_remote_apic = default_inquire_remote_apic,
c1eeb2de
YL
266
267 .read = native_apic_mem_read,
268 .write = native_apic_mem_write,
269 .icr_read = native_apic_icr_read,
270 .icr_write = native_apic_icr_write,
271 .wait_icr_idle = native_apic_wait_icr_idle,
272 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
d26b6d66 273};