Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
e83a5fdc | 36 | #include <asm/hpet.h> |
1da177e4 | 37 | #include <asm/pgalloc.h> |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
6e1cb38a | 43 | #include <asm/i8259.h> |
1da177e4 | 44 | |
5af5573e | 45 | #include <mach_ipi.h> |
dd46e3ca | 46 | #include <mach_apic.h> |
5af5573e | 47 | |
36fef094 | 48 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 49 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 50 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 51 | int disable_apic; |
6e1cb38a | 52 | int disable_x2apic; |
89027d35 | 53 | int x2apic; |
1da177e4 | 54 | |
6e1cb38a SS |
55 | /* x2apic enabled before OS handover */ |
56 | int x2apic_preenabled; | |
57 | ||
e83a5fdc | 58 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
59 | int local_apic_timer_c2_ok; |
60 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
61 | ||
e83a5fdc HS |
62 | /* |
63 | * Debug level, exported for io_apic.c | |
64 | */ | |
baa13188 | 65 | unsigned int apic_verbosity; |
e83a5fdc | 66 | |
bab4b27c AS |
67 | /* Have we found an MP table */ |
68 | int smp_found_config; | |
69 | ||
39928722 AD |
70 | static struct resource lapic_resource = { |
71 | .name = "Local APIC", | |
72 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
73 | }; | |
74 | ||
d03030e9 TG |
75 | static unsigned int calibration_result; |
76 | ||
ba7eda4c TG |
77 | static int lapic_next_event(unsigned long delta, |
78 | struct clock_event_device *evt); | |
79 | static void lapic_timer_setup(enum clock_event_mode mode, | |
80 | struct clock_event_device *evt); | |
ba7eda4c | 81 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 82 | static void apic_pm_activate(void); |
ba7eda4c | 83 | |
274cfe59 CG |
84 | /* |
85 | * The local apic timer can be used for any function which is CPU local. | |
86 | */ | |
ba7eda4c TG |
87 | static struct clock_event_device lapic_clockevent = { |
88 | .name = "lapic", | |
89 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
90 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
91 | .shift = 32, | |
92 | .set_mode = lapic_timer_setup, | |
93 | .set_next_event = lapic_next_event, | |
94 | .broadcast = lapic_timer_broadcast, | |
95 | .rating = 100, | |
96 | .irq = -1, | |
97 | }; | |
98 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
99 | ||
d3432896 | 100 | static unsigned long apic_phys; |
b6c80513 | 101 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
d3432896 | 102 | |
3f530709 AS |
103 | unsigned long mp_lapic_addr; |
104 | ||
0e078e2f TG |
105 | /* |
106 | * Get the LAPIC version | |
107 | */ | |
108 | static inline int lapic_get_version(void) | |
ba7eda4c | 109 | { |
0e078e2f | 110 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
111 | } |
112 | ||
0e078e2f | 113 | /* |
9c803869 | 114 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
115 | */ |
116 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 117 | { |
9c803869 | 118 | #ifdef CONFIG_X86_64 |
0e078e2f | 119 | return 1; |
9c803869 CG |
120 | #else |
121 | return APIC_INTEGRATED(lapic_get_version()); | |
122 | #endif | |
ba7eda4c TG |
123 | } |
124 | ||
125 | /* | |
0e078e2f | 126 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 127 | */ |
0e078e2f | 128 | static int modern_apic(void) |
ba7eda4c | 129 | { |
0e078e2f TG |
130 | /* AMD systems use old APIC versions, so check the CPU */ |
131 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
132 | boot_cpu_data.x86 >= 0xf) | |
133 | return 1; | |
134 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
135 | } |
136 | ||
274cfe59 CG |
137 | /* |
138 | * Paravirt kernels also might be using these below ops. So we still | |
139 | * use generic apic_read()/apic_write(), which might be pointing to different | |
140 | * ops in PARAVIRT case. | |
141 | */ | |
1b374e4d | 142 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
143 | { |
144 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
145 | cpu_relax(); | |
146 | } | |
147 | ||
1b374e4d | 148 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 149 | { |
3c6bb07a | 150 | u32 send_status; |
8339e9fb FLV |
151 | int timeout; |
152 | ||
153 | timeout = 0; | |
154 | do { | |
155 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
156 | if (!send_status) | |
157 | break; | |
158 | udelay(100); | |
159 | } while (timeout++ < 1000); | |
160 | ||
161 | return send_status; | |
162 | } | |
163 | ||
1b374e4d SS |
164 | void xapic_icr_write(u32 low, u32 id) |
165 | { | |
ed4e5ec1 | 166 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
167 | apic_write(APIC_ICR, low); |
168 | } | |
169 | ||
170 | u64 xapic_icr_read(void) | |
171 | { | |
172 | u32 icr1, icr2; | |
173 | ||
174 | icr2 = apic_read(APIC_ICR2); | |
175 | icr1 = apic_read(APIC_ICR); | |
176 | ||
cf9768d7 | 177 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
178 | } |
179 | ||
180 | static struct apic_ops xapic_ops = { | |
181 | .read = native_apic_mem_read, | |
182 | .write = native_apic_mem_write, | |
1b374e4d SS |
183 | .icr_read = xapic_icr_read, |
184 | .icr_write = xapic_icr_write, | |
185 | .wait_icr_idle = xapic_wait_icr_idle, | |
186 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
187 | }; | |
188 | ||
189 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
190 | EXPORT_SYMBOL_GPL(apic_ops); |
191 | ||
13c88fb5 SS |
192 | static void x2apic_wait_icr_idle(void) |
193 | { | |
194 | /* no need to wait for icr idle in x2apic */ | |
195 | return; | |
196 | } | |
197 | ||
198 | static u32 safe_x2apic_wait_icr_idle(void) | |
199 | { | |
200 | /* no need to wait for icr idle in x2apic */ | |
201 | return 0; | |
202 | } | |
203 | ||
204 | void x2apic_icr_write(u32 low, u32 id) | |
205 | { | |
206 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
207 | } | |
208 | ||
209 | u64 x2apic_icr_read(void) | |
210 | { | |
211 | unsigned long val; | |
212 | ||
213 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
214 | return val; | |
215 | } | |
216 | ||
217 | static struct apic_ops x2apic_ops = { | |
218 | .read = native_apic_msr_read, | |
219 | .write = native_apic_msr_write, | |
13c88fb5 SS |
220 | .icr_read = x2apic_icr_read, |
221 | .icr_write = x2apic_icr_write, | |
222 | .wait_icr_idle = x2apic_wait_icr_idle, | |
223 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
224 | }; | |
225 | ||
0e078e2f TG |
226 | /** |
227 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
228 | */ | |
e9427101 | 229 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 230 | { |
11a8e778 | 231 | unsigned int v; |
6935d1f9 TG |
232 | |
233 | /* unmask and set to NMI */ | |
234 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
235 | |
236 | /* Level triggered for 82489DX (32bit mode) */ | |
237 | if (!lapic_is_integrated()) | |
238 | v |= APIC_LVT_LEVEL_TRIGGER; | |
239 | ||
11a8e778 | 240 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
241 | } |
242 | ||
0e078e2f TG |
243 | /** |
244 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
245 | */ | |
37e650c7 | 246 | int lapic_get_maxlvt(void) |
1da177e4 | 247 | { |
36a028de | 248 | unsigned int v; |
1da177e4 LT |
249 | |
250 | v = apic_read(APIC_LVR); | |
36a028de CG |
251 | /* |
252 | * - we always have APIC integrated on 64bit mode | |
253 | * - 82489DXs do not report # of LVT entries | |
254 | */ | |
255 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
256 | } |
257 | ||
274cfe59 CG |
258 | /* |
259 | * Local APIC timer | |
260 | */ | |
261 | ||
f07f4f90 CG |
262 | /* Clock divisor is set to 1 */ |
263 | #define APIC_DIVISOR 1 | |
264 | ||
0e078e2f TG |
265 | /* |
266 | * This function sets up the local APIC timer, with a timeout of | |
267 | * 'clocks' APIC bus clock. During calibration we actually call | |
268 | * this function twice on the boot CPU, once with a bogus timeout | |
269 | * value, second time for real. The other (noncalibrating) CPUs | |
270 | * call this function only once, with the real, calibrated value. | |
271 | * | |
272 | * We do reads before writes even if unnecessary, to get around the | |
273 | * P5 APIC double write bug. | |
274 | */ | |
0e078e2f | 275 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 276 | { |
0e078e2f | 277 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 278 | |
0e078e2f TG |
279 | lvtt_value = LOCAL_TIMER_VECTOR; |
280 | if (!oneshot) | |
281 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
282 | if (!lapic_is_integrated()) |
283 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
284 | ||
0e078e2f TG |
285 | if (!irqen) |
286 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 287 | |
0e078e2f | 288 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
289 | |
290 | /* | |
0e078e2f | 291 | * Divide PICLK by 16 |
1da177e4 | 292 | */ |
0e078e2f TG |
293 | tmp_value = apic_read(APIC_TDCR); |
294 | apic_write(APIC_TDCR, (tmp_value | |
295 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
296 | | APIC_TDR_DIV_16); | |
297 | ||
298 | if (!oneshot) | |
f07f4f90 | 299 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
300 | } |
301 | ||
0e078e2f | 302 | /* |
7b83dae7 RR |
303 | * Setup extended LVT, AMD specific (K8, family 10h) |
304 | * | |
305 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
306 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 307 | */ |
7b83dae7 RR |
308 | |
309 | #define APIC_EILVT_LVTOFF_MCE 0 | |
310 | #define APIC_EILVT_LVTOFF_IBS 1 | |
311 | ||
312 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 313 | { |
7b83dae7 | 314 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 315 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 316 | |
0e078e2f | 317 | apic_write(reg, v); |
1da177e4 LT |
318 | } |
319 | ||
7b83dae7 RR |
320 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
321 | { | |
322 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
323 | return APIC_EILVT_LVTOFF_MCE; | |
324 | } | |
325 | ||
326 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
327 | { | |
328 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
329 | return APIC_EILVT_LVTOFF_IBS; | |
330 | } | |
331 | ||
0e078e2f TG |
332 | /* |
333 | * Program the next event, relative to now | |
334 | */ | |
335 | static int lapic_next_event(unsigned long delta, | |
336 | struct clock_event_device *evt) | |
1da177e4 | 337 | { |
0e078e2f TG |
338 | apic_write(APIC_TMICT, delta); |
339 | return 0; | |
1da177e4 LT |
340 | } |
341 | ||
0e078e2f TG |
342 | /* |
343 | * Setup the lapic timer in periodic or oneshot mode | |
344 | */ | |
345 | static void lapic_timer_setup(enum clock_event_mode mode, | |
346 | struct clock_event_device *evt) | |
9b7711f0 HS |
347 | { |
348 | unsigned long flags; | |
0e078e2f | 349 | unsigned int v; |
9b7711f0 | 350 | |
0e078e2f TG |
351 | /* Lapic used as dummy for broadcast ? */ |
352 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
353 | return; |
354 | ||
355 | local_irq_save(flags); | |
356 | ||
0e078e2f TG |
357 | switch (mode) { |
358 | case CLOCK_EVT_MODE_PERIODIC: | |
359 | case CLOCK_EVT_MODE_ONESHOT: | |
360 | __setup_APIC_LVTT(calibration_result, | |
361 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
362 | break; | |
363 | case CLOCK_EVT_MODE_UNUSED: | |
364 | case CLOCK_EVT_MODE_SHUTDOWN: | |
365 | v = apic_read(APIC_LVTT); | |
366 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
367 | apic_write(APIC_LVTT, v); | |
368 | break; | |
369 | case CLOCK_EVT_MODE_RESUME: | |
370 | /* Nothing to do here */ | |
371 | break; | |
372 | } | |
9b7711f0 HS |
373 | |
374 | local_irq_restore(flags); | |
375 | } | |
376 | ||
1da177e4 | 377 | /* |
0e078e2f | 378 | * Local APIC timer broadcast function |
1da177e4 | 379 | */ |
0e078e2f | 380 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 381 | { |
0e078e2f TG |
382 | #ifdef CONFIG_SMP |
383 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
384 | #endif | |
385 | } | |
1da177e4 | 386 | |
0e078e2f TG |
387 | /* |
388 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
389 | * of the boot CPU and register the clock event in the framework. | |
390 | */ | |
391 | static void setup_APIC_timer(void) | |
392 | { | |
393 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 394 | |
0e078e2f TG |
395 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
396 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 397 | |
0e078e2f TG |
398 | clockevents_register_device(levt); |
399 | } | |
1da177e4 | 400 | |
0e078e2f TG |
401 | /* |
402 | * In this function we calibrate APIC bus clocks to the external | |
403 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
404 | * to calibrate, since some later bootup code depends on getting | |
405 | * the first irq? Ugh. | |
406 | * | |
407 | * We want to do the calibration only once since we | |
408 | * want to have local timer irqs syncron. CPUs connected | |
409 | * by the same APIC bus have the very same bus frequency. | |
410 | * And we want to have irqs off anyways, no accidental | |
411 | * APIC irq that way. | |
412 | */ | |
413 | ||
414 | #define TICK_COUNT 100000000 | |
415 | ||
89b3b1f4 | 416 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
417 | { |
418 | unsigned apic, apic_start; | |
419 | unsigned long tsc, tsc_start; | |
420 | int result; | |
421 | ||
422 | local_irq_disable(); | |
423 | ||
424 | /* | |
425 | * Put whatever arbitrary (but long enough) timeout | |
426 | * value into the APIC clock, we just want to get the | |
427 | * counter running for calibration. | |
428 | * | |
429 | * No interrupt enable ! | |
430 | */ | |
431 | __setup_APIC_LVTT(250000000, 0, 0); | |
432 | ||
433 | apic_start = apic_read(APIC_TMCCT); | |
434 | #ifdef CONFIG_X86_PM_TIMER | |
435 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
436 | pmtimer_wait(5000); /* 5ms wait */ | |
437 | apic = apic_read(APIC_TMCCT); | |
438 | result = (apic_start - apic) * 1000L / 5; | |
439 | } else | |
440 | #endif | |
441 | { | |
442 | rdtscll(tsc_start); | |
443 | ||
444 | do { | |
445 | apic = apic_read(APIC_TMCCT); | |
446 | rdtscll(tsc); | |
447 | } while ((tsc - tsc_start) < TICK_COUNT && | |
448 | (apic_start - apic) < TICK_COUNT); | |
449 | ||
450 | result = (apic_start - apic) * 1000L * tsc_khz / | |
451 | (tsc - tsc_start); | |
452 | } | |
453 | ||
454 | local_irq_enable(); | |
455 | ||
456 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
457 | ||
458 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
459 | result / 1000 / 1000, result / 1000 % 1000); | |
460 | ||
461 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
462 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
463 | lapic_clockevent.shift); | |
0e078e2f TG |
464 | lapic_clockevent.max_delta_ns = |
465 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
466 | lapic_clockevent.min_delta_ns = | |
467 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
468 | ||
f07f4f90 | 469 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
470 | |
471 | /* | |
472 | * Do a sanity check on the APIC calibration result | |
473 | */ | |
474 | if (calibration_result < (1000000 / HZ)) { | |
475 | printk(KERN_WARNING | |
476 | "APIC frequency too slow, disabling apic timer\n"); | |
477 | return -1; | |
478 | } | |
479 | ||
480 | return 0; | |
0e078e2f TG |
481 | } |
482 | ||
e83a5fdc HS |
483 | /* |
484 | * Setup the boot APIC | |
485 | * | |
486 | * Calibrate and verify the result. | |
487 | */ | |
0e078e2f TG |
488 | void __init setup_boot_APIC_clock(void) |
489 | { | |
490 | /* | |
274cfe59 CG |
491 | * The local apic timer can be disabled via the kernel |
492 | * commandline or from the CPU detection code. Register the lapic | |
493 | * timer as a dummy clock event source on SMP systems, so the | |
494 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
495 | */ |
496 | if (disable_apic_timer) { | |
497 | printk(KERN_INFO "Disabling APIC timer\n"); | |
498 | /* No broadcast on UP ! */ | |
9d09951d TG |
499 | if (num_possible_cpus() > 1) { |
500 | lapic_clockevent.mult = 1; | |
0e078e2f | 501 | setup_APIC_timer(); |
9d09951d | 502 | } |
0e078e2f TG |
503 | return; |
504 | } | |
505 | ||
274cfe59 CG |
506 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
507 | "calibrating APIC timer ...\n"); | |
508 | ||
89b3b1f4 | 509 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
510 | /* No broadcast on UP ! */ |
511 | if (num_possible_cpus() > 1) | |
512 | setup_APIC_timer(); | |
513 | return; | |
514 | } | |
515 | ||
0e078e2f TG |
516 | /* |
517 | * If nmi_watchdog is set to IO_APIC, we need the | |
518 | * PIT/HPET going. Otherwise register lapic as a dummy | |
519 | * device. | |
520 | */ | |
521 | if (nmi_watchdog != NMI_IO_APIC) | |
522 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
523 | else | |
524 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 525 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 526 | |
274cfe59 | 527 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
528 | setup_APIC_timer(); |
529 | } | |
530 | ||
0e078e2f TG |
531 | void __cpuinit setup_secondary_APIC_clock(void) |
532 | { | |
0e078e2f TG |
533 | setup_APIC_timer(); |
534 | } | |
535 | ||
536 | /* | |
537 | * The guts of the apic timer interrupt | |
538 | */ | |
539 | static void local_apic_timer_interrupt(void) | |
540 | { | |
541 | int cpu = smp_processor_id(); | |
542 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
543 | ||
544 | /* | |
545 | * Normally we should not be here till LAPIC has been initialized but | |
546 | * in some cases like kdump, its possible that there is a pending LAPIC | |
547 | * timer interrupt from previous kernel's context and is delivered in | |
548 | * new kernel the moment interrupts are enabled. | |
549 | * | |
550 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
551 | * its possible that when we get here evt->event_handler is NULL. | |
552 | * Check for event_handler being NULL and discard the interrupt as | |
553 | * spurious. | |
554 | */ | |
555 | if (!evt->event_handler) { | |
556 | printk(KERN_WARNING | |
557 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
558 | /* Switch it off */ | |
559 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
560 | return; | |
561 | } | |
562 | ||
563 | /* | |
564 | * the NMI deadlock-detector uses this. | |
565 | */ | |
566 | add_pda(apic_timer_irqs, 1); | |
567 | ||
568 | evt->event_handler(evt); | |
569 | } | |
570 | ||
571 | /* | |
572 | * Local APIC timer interrupt. This is the most natural way for doing | |
573 | * local interrupts, but local timer interrupts can be emulated by | |
574 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
575 | * | |
576 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
577 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
578 | */ | |
579 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
580 | { | |
581 | struct pt_regs *old_regs = set_irq_regs(regs); | |
582 | ||
583 | /* | |
584 | * NOTE! We'd better ACK the irq immediately, | |
585 | * because timer handling can be slow. | |
586 | */ | |
587 | ack_APIC_irq(); | |
588 | /* | |
589 | * update_process_times() expects us to have done irq_enter(). | |
590 | * Besides, if we don't timer interrupts ignore the global | |
591 | * interrupt lock, which is the WrongThing (tm) to do. | |
592 | */ | |
593 | exit_idle(); | |
594 | irq_enter(); | |
595 | local_apic_timer_interrupt(); | |
596 | irq_exit(); | |
274cfe59 | 597 | |
0e078e2f TG |
598 | set_irq_regs(old_regs); |
599 | } | |
600 | ||
601 | int setup_profiling_timer(unsigned int multiplier) | |
602 | { | |
603 | return -EINVAL; | |
604 | } | |
605 | ||
606 | ||
607 | /* | |
608 | * Local APIC start and shutdown | |
609 | */ | |
610 | ||
611 | /** | |
612 | * clear_local_APIC - shutdown the local APIC | |
613 | * | |
614 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
615 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
616 | * leftovers during boot. | |
617 | */ | |
618 | void clear_local_APIC(void) | |
619 | { | |
2584a82d | 620 | int maxlvt; |
0e078e2f TG |
621 | u32 v; |
622 | ||
d3432896 AK |
623 | /* APIC hasn't been mapped yet */ |
624 | if (!apic_phys) | |
625 | return; | |
626 | ||
627 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
628 | /* |
629 | * Masking an LVT entry can trigger a local APIC error | |
630 | * if the vector is zero. Mask LVTERR first to prevent this. | |
631 | */ | |
632 | if (maxlvt >= 3) { | |
633 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
634 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
635 | } | |
636 | /* | |
637 | * Careful: we have to set masks only first to deassert | |
638 | * any level-triggered sources. | |
639 | */ | |
640 | v = apic_read(APIC_LVTT); | |
641 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
642 | v = apic_read(APIC_LVT0); | |
643 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
644 | v = apic_read(APIC_LVT1); | |
645 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
646 | if (maxlvt >= 4) { | |
647 | v = apic_read(APIC_LVTPC); | |
648 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
649 | } | |
650 | ||
6764014b CG |
651 | /* lets not touch this if we didn't frob it */ |
652 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
653 | if (maxlvt >= 5) { | |
654 | v = apic_read(APIC_LVTTHMR); | |
655 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
656 | } | |
657 | #endif | |
0e078e2f TG |
658 | /* |
659 | * Clean APIC state for other OSs: | |
660 | */ | |
661 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
662 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
663 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
664 | if (maxlvt >= 3) | |
665 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
666 | if (maxlvt >= 4) | |
667 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
668 | |
669 | /* Integrated APIC (!82489DX) ? */ | |
670 | if (lapic_is_integrated()) { | |
671 | if (maxlvt > 3) | |
672 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
673 | apic_write(APIC_ESR, 0); | |
674 | apic_read(APIC_ESR); | |
675 | } | |
0e078e2f TG |
676 | } |
677 | ||
678 | /** | |
679 | * disable_local_APIC - clear and disable the local APIC | |
680 | */ | |
681 | void disable_local_APIC(void) | |
682 | { | |
683 | unsigned int value; | |
684 | ||
685 | clear_local_APIC(); | |
686 | ||
687 | /* | |
688 | * Disable APIC (implies clearing of registers | |
689 | * for 82489DX!). | |
690 | */ | |
691 | value = apic_read(APIC_SPIV); | |
692 | value &= ~APIC_SPIV_APIC_ENABLED; | |
693 | apic_write(APIC_SPIV, value); | |
990b183e CG |
694 | |
695 | #ifdef CONFIG_X86_32 | |
696 | /* | |
697 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
698 | * restore the disabled state. | |
699 | */ | |
700 | if (enabled_via_apicbase) { | |
701 | unsigned int l, h; | |
702 | ||
703 | rdmsr(MSR_IA32_APICBASE, l, h); | |
704 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
705 | wrmsr(MSR_IA32_APICBASE, l, h); | |
706 | } | |
707 | #endif | |
0e078e2f TG |
708 | } |
709 | ||
fe4024dc CG |
710 | /* |
711 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
712 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
713 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
714 | * for the case where Linux didn't enable the LAPIC. | |
715 | */ | |
0e078e2f TG |
716 | void lapic_shutdown(void) |
717 | { | |
718 | unsigned long flags; | |
719 | ||
720 | if (!cpu_has_apic) | |
721 | return; | |
722 | ||
723 | local_irq_save(flags); | |
724 | ||
fe4024dc CG |
725 | #ifdef CONFIG_X86_32 |
726 | if (!enabled_via_apicbase) | |
727 | clear_local_APIC(); | |
728 | else | |
729 | #endif | |
730 | disable_local_APIC(); | |
731 | ||
0e078e2f TG |
732 | |
733 | local_irq_restore(flags); | |
734 | } | |
735 | ||
736 | /* | |
737 | * This is to verify that we're looking at a real local APIC. | |
738 | * Check these against your board if the CPUs aren't getting | |
739 | * started for no apparent reason. | |
740 | */ | |
741 | int __init verify_local_APIC(void) | |
742 | { | |
743 | unsigned int reg0, reg1; | |
744 | ||
745 | /* | |
746 | * The version register is read-only in a real APIC. | |
747 | */ | |
748 | reg0 = apic_read(APIC_LVR); | |
749 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
750 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
751 | reg1 = apic_read(APIC_LVR); | |
752 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
753 | ||
754 | /* | |
755 | * The two version reads above should print the same | |
756 | * numbers. If the second one is different, then we | |
757 | * poke at a non-APIC. | |
758 | */ | |
759 | if (reg1 != reg0) | |
760 | return 0; | |
761 | ||
762 | /* | |
763 | * Check if the version looks reasonably. | |
764 | */ | |
765 | reg1 = GET_APIC_VERSION(reg0); | |
766 | if (reg1 == 0x00 || reg1 == 0xff) | |
767 | return 0; | |
768 | reg1 = lapic_get_maxlvt(); | |
769 | if (reg1 < 0x02 || reg1 == 0xff) | |
770 | return 0; | |
771 | ||
772 | /* | |
773 | * The ID register is read/write in a real APIC. | |
774 | */ | |
2d7a66d0 | 775 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
776 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
777 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 778 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
779 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
780 | apic_write(APIC_ID, reg0); | |
781 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
782 | return 0; | |
783 | ||
784 | /* | |
1da177e4 LT |
785 | * The next two are just to see if we have sane values. |
786 | * They're only really relevant if we're in Virtual Wire | |
787 | * compatibility mode, but most boxes are anymore. | |
788 | */ | |
789 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 790 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
791 | reg1 = apic_read(APIC_LVT1); |
792 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
793 | ||
794 | return 1; | |
795 | } | |
796 | ||
0e078e2f TG |
797 | /** |
798 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
799 | */ | |
1da177e4 LT |
800 | void __init sync_Arb_IDs(void) |
801 | { | |
296cb951 CG |
802 | /* |
803 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
804 | * needed on AMD. | |
805 | */ | |
806 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
807 | return; |
808 | ||
809 | /* | |
810 | * Wait for idle. | |
811 | */ | |
812 | apic_wait_icr_idle(); | |
813 | ||
814 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
815 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
816 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
817 | } |
818 | ||
1da177e4 LT |
819 | /* |
820 | * An initial setup of the virtual wire mode. | |
821 | */ | |
822 | void __init init_bsp_APIC(void) | |
823 | { | |
11a8e778 | 824 | unsigned int value; |
1da177e4 LT |
825 | |
826 | /* | |
827 | * Don't do the setup now if we have a SMP BIOS as the | |
828 | * through-I/O-APIC virtual wire mode might be active. | |
829 | */ | |
830 | if (smp_found_config || !cpu_has_apic) | |
831 | return; | |
832 | ||
1da177e4 LT |
833 | /* |
834 | * Do not trust the local APIC being empty at bootup. | |
835 | */ | |
836 | clear_local_APIC(); | |
837 | ||
838 | /* | |
839 | * Enable APIC. | |
840 | */ | |
841 | value = apic_read(APIC_SPIV); | |
842 | value &= ~APIC_VECTOR_MASK; | |
843 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
844 | |
845 | #ifdef CONFIG_X86_32 | |
846 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
847 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
848 | (boot_cpu_data.x86 == 15)) | |
849 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
850 | else | |
851 | #endif | |
852 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 853 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 854 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
855 | |
856 | /* | |
857 | * Set up the virtual wire mode. | |
858 | */ | |
11a8e778 | 859 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 860 | value = APIC_DM_NMI; |
638c0411 CG |
861 | if (!lapic_is_integrated()) /* 82489DX */ |
862 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 863 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
864 | } |
865 | ||
0e078e2f TG |
866 | /** |
867 | * setup_local_APIC - setup the local APIC | |
868 | */ | |
869 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 870 | { |
739f33b3 | 871 | unsigned int value; |
da7ed9f9 | 872 | int i, j; |
1da177e4 | 873 | |
ac23d4ee | 874 | preempt_disable(); |
1da177e4 | 875 | value = apic_read(APIC_LVR); |
1da177e4 | 876 | |
fe7414a2 | 877 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
878 | |
879 | /* | |
880 | * Double-check whether this APIC is really registered. | |
881 | * This is meaningless in clustered apic mode, so we skip it. | |
882 | */ | |
883 | if (!apic_id_registered()) | |
884 | BUG(); | |
885 | ||
886 | /* | |
887 | * Intel recommends to set DFR, LDR and TPR before enabling | |
888 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
889 | * document number 292116). So here it goes... | |
890 | */ | |
891 | init_apic_ldr(); | |
892 | ||
893 | /* | |
894 | * Set Task Priority to 'accept all'. We never change this | |
895 | * later on. | |
896 | */ | |
897 | value = apic_read(APIC_TASKPRI); | |
898 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 899 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 900 | |
da7ed9f9 VG |
901 | /* |
902 | * After a crash, we no longer service the interrupts and a pending | |
903 | * interrupt from previous kernel might still have ISR bit set. | |
904 | * | |
905 | * Most probably by now CPU has serviced that pending interrupt and | |
906 | * it might not have done the ack_APIC_irq() because it thought, | |
907 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
908 | * does not clear the ISR bit and cpu thinks it has already serivced | |
909 | * the interrupt. Hence a vector might get locked. It was noticed | |
910 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
911 | */ | |
912 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
913 | value = apic_read(APIC_ISR + i*0x10); | |
914 | for (j = 31; j >= 0; j--) { | |
915 | if (value & (1<<j)) | |
916 | ack_APIC_irq(); | |
917 | } | |
918 | } | |
919 | ||
1da177e4 LT |
920 | /* |
921 | * Now that we are all set up, enable the APIC | |
922 | */ | |
923 | value = apic_read(APIC_SPIV); | |
924 | value &= ~APIC_VECTOR_MASK; | |
925 | /* | |
926 | * Enable APIC | |
927 | */ | |
928 | value |= APIC_SPIV_APIC_ENABLED; | |
929 | ||
3f14c746 AK |
930 | /* We always use processor focus */ |
931 | ||
1da177e4 LT |
932 | /* |
933 | * Set spurious IRQ vector | |
934 | */ | |
935 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 936 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
937 | |
938 | /* | |
939 | * Set up LVT0, LVT1: | |
940 | * | |
941 | * set up through-local-APIC on the BP's LINT0. This is not | |
942 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
943 | * we delegate interrupts to the 8259A. | |
944 | */ | |
945 | /* | |
946 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
947 | */ | |
948 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 949 | if (!smp_processor_id() && !value) { |
1da177e4 | 950 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
951 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
952 | smp_processor_id()); | |
1da177e4 LT |
953 | } else { |
954 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
955 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
956 | smp_processor_id()); | |
1da177e4 | 957 | } |
11a8e778 | 958 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
959 | |
960 | /* | |
961 | * only the BP should see the LINT1 NMI signal, obviously. | |
962 | */ | |
963 | if (!smp_processor_id()) | |
964 | value = APIC_DM_NMI; | |
965 | else | |
966 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 967 | apic_write(APIC_LVT1, value); |
ac23d4ee | 968 | preempt_enable(); |
739f33b3 | 969 | } |
1da177e4 | 970 | |
a4928cff | 971 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
972 | { |
973 | unsigned maxlvt = lapic_get_maxlvt(); | |
974 | ||
975 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 976 | /* |
739f33b3 | 977 | * spec says clear errors after enabling vector. |
1c69524c | 978 | */ |
739f33b3 AK |
979 | if (maxlvt > 3) |
980 | apic_write(APIC_ESR, 0); | |
981 | } | |
1da177e4 | 982 | |
739f33b3 AK |
983 | void __cpuinit end_local_APIC_setup(void) |
984 | { | |
985 | lapic_setup_esr(); | |
f2802e7f | 986 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 987 | apic_pm_activate(); |
1da177e4 | 988 | } |
1da177e4 | 989 | |
6e1cb38a SS |
990 | void check_x2apic(void) |
991 | { | |
992 | int msr, msr2; | |
993 | ||
994 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
995 | ||
996 | if (msr & X2APIC_ENABLE) { | |
997 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
998 | x2apic_preenabled = x2apic = 1; | |
999 | apic_ops = &x2apic_ops; | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | void enable_x2apic(void) | |
1004 | { | |
1005 | int msr, msr2; | |
1006 | ||
1007 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1008 | if (!(msr & X2APIC_ENABLE)) { | |
1009 | printk("Enabling x2apic\n"); | |
1010 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | void enable_IR_x2apic(void) | |
1015 | { | |
1016 | #ifdef CONFIG_INTR_REMAP | |
1017 | int ret; | |
1018 | unsigned long flags; | |
1019 | ||
1020 | if (!cpu_has_x2apic) | |
1021 | return; | |
1022 | ||
1023 | if (!x2apic_preenabled && disable_x2apic) { | |
1024 | printk(KERN_INFO | |
1025 | "Skipped enabling x2apic and Interrupt-remapping " | |
1026 | "because of nox2apic\n"); | |
1027 | return; | |
1028 | } | |
1029 | ||
1030 | if (x2apic_preenabled && disable_x2apic) | |
1031 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1032 | ||
1033 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1034 | printk(KERN_INFO | |
1035 | "Skipped enabling x2apic and Interrupt-remapping " | |
1036 | "because of skipping io-apic setup\n"); | |
1037 | return; | |
1038 | } | |
1039 | ||
1040 | ret = dmar_table_init(); | |
1041 | if (ret) { | |
1042 | printk(KERN_INFO | |
1043 | "dmar_table_init() failed with %d:\n", ret); | |
1044 | ||
1045 | if (x2apic_preenabled) | |
1046 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1047 | else | |
1048 | printk(KERN_INFO | |
1049 | "Not enabling x2apic,Intr-remapping\n"); | |
1050 | return; | |
1051 | } | |
1052 | ||
1053 | local_irq_save(flags); | |
1054 | mask_8259A(); | |
1055 | save_mask_IO_APIC_setup(); | |
1056 | ||
1057 | ret = enable_intr_remapping(1); | |
1058 | ||
1059 | if (ret && x2apic_preenabled) { | |
1060 | local_irq_restore(flags); | |
1061 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1062 | } | |
1063 | ||
1064 | if (ret) | |
1065 | goto end; | |
1066 | ||
1067 | if (!x2apic) { | |
1068 | x2apic = 1; | |
1069 | apic_ops = &x2apic_ops; | |
1070 | enable_x2apic(); | |
1071 | } | |
1072 | end: | |
1073 | if (ret) | |
1074 | /* | |
1075 | * IR enabling failed | |
1076 | */ | |
1077 | restore_IO_APIC_setup(); | |
1078 | else | |
1079 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1080 | ||
1081 | unmask_8259A(); | |
1082 | local_irq_restore(flags); | |
1083 | ||
1084 | if (!ret) { | |
1085 | if (!x2apic_preenabled) | |
1086 | printk(KERN_INFO | |
1087 | "Enabled x2apic and interrupt-remapping\n"); | |
1088 | else | |
1089 | printk(KERN_INFO | |
1090 | "Enabled Interrupt-remapping\n"); | |
1091 | } else | |
1092 | printk(KERN_ERR | |
1093 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1094 | #else | |
1095 | if (!cpu_has_x2apic) | |
1096 | return; | |
1097 | ||
1098 | if (x2apic_preenabled) | |
1099 | panic("x2apic enabled prior OS handover," | |
1100 | " enable CONFIG_INTR_REMAP"); | |
1101 | ||
1102 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1103 | " and x2apic\n"); | |
1104 | #endif | |
1105 | ||
1106 | return; | |
1107 | } | |
1108 | ||
1da177e4 LT |
1109 | /* |
1110 | * Detect and enable local APICs on non-SMP boards. | |
1111 | * Original code written by Keir Fraser. | |
1112 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1113 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1114 | */ |
0e078e2f | 1115 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1116 | { |
1117 | if (!cpu_has_apic) { | |
1118 | printk(KERN_INFO "No local APIC present\n"); | |
1119 | return -1; | |
1120 | } | |
1121 | ||
1122 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1123 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1124 | return 0; |
1125 | } | |
1126 | ||
8643f9d0 YL |
1127 | void __init early_init_lapic_mapping(void) |
1128 | { | |
431ee79d | 1129 | unsigned long phys_addr; |
8643f9d0 YL |
1130 | |
1131 | /* | |
1132 | * If no local APIC can be found then go out | |
1133 | * : it means there is no mpatable and MADT | |
1134 | */ | |
1135 | if (!smp_found_config) | |
1136 | return; | |
1137 | ||
431ee79d | 1138 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1139 | |
431ee79d | 1140 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1141 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1142 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1143 | |
1144 | /* | |
1145 | * Fetch the APIC ID of the BSP in case we have a | |
1146 | * default configuration (or the MP table is broken). | |
1147 | */ | |
4c9961d5 | 1148 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1149 | } |
1150 | ||
0e078e2f TG |
1151 | /** |
1152 | * init_apic_mappings - initialize APIC mappings | |
1153 | */ | |
1da177e4 LT |
1154 | void __init init_apic_mappings(void) |
1155 | { | |
6e1cb38a | 1156 | if (x2apic) { |
4c9961d5 | 1157 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1158 | return; |
1159 | } | |
1160 | ||
1da177e4 LT |
1161 | /* |
1162 | * If no local APIC can be found then set up a fake all | |
1163 | * zeroes page to simulate the local APIC and another | |
1164 | * one for the IO-APIC. | |
1165 | */ | |
1166 | if (!smp_found_config && detect_init_APIC()) { | |
1167 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1168 | apic_phys = __pa(apic_phys); | |
1169 | } else | |
1170 | apic_phys = mp_lapic_addr; | |
1171 | ||
1172 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1173 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1174 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1175 | |
1176 | /* | |
1177 | * Fetch the APIC ID of the BSP in case we have a | |
1178 | * default configuration (or the MP table is broken). | |
1179 | */ | |
4c9961d5 | 1180 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1181 | } |
1182 | ||
1183 | /* | |
0e078e2f TG |
1184 | * This initializes the IO-APIC and APIC hardware if this is |
1185 | * a UP kernel. | |
1da177e4 | 1186 | */ |
0e078e2f | 1187 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1188 | { |
0e078e2f TG |
1189 | if (disable_apic) { |
1190 | printk(KERN_INFO "Apic disabled\n"); | |
1191 | return -1; | |
1192 | } | |
1193 | if (!cpu_has_apic) { | |
1194 | disable_apic = 1; | |
1195 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1196 | return -1; | |
1197 | } | |
1da177e4 | 1198 | |
6e1cb38a SS |
1199 | enable_IR_x2apic(); |
1200 | setup_apic_routing(); | |
1201 | ||
0e078e2f | 1202 | verify_local_APIC(); |
1da177e4 | 1203 | |
b5841765 GC |
1204 | connect_bsp_APIC(); |
1205 | ||
b6df1b8b | 1206 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1207 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1208 | |
0e078e2f | 1209 | setup_local_APIC(); |
1da177e4 | 1210 | |
739f33b3 AK |
1211 | /* |
1212 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1213 | * We need clear_IO_APIC before enabling vector on BP | |
1214 | */ | |
1215 | if (!skip_ioapic_setup && nr_ioapics) | |
1216 | enable_IO_APIC(); | |
1217 | ||
acae7d90 MR |
1218 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1219 | localise_nmi_watchdog(); | |
739f33b3 AK |
1220 | end_local_APIC_setup(); |
1221 | ||
0e078e2f TG |
1222 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1223 | setup_IO_APIC(); | |
1224 | else | |
1225 | nr_ioapics = 0; | |
1226 | setup_boot_APIC_clock(); | |
1227 | check_nmi_watchdog(); | |
1228 | return 0; | |
1da177e4 LT |
1229 | } |
1230 | ||
1231 | /* | |
0e078e2f | 1232 | * Local APIC interrupts |
1da177e4 LT |
1233 | */ |
1234 | ||
0e078e2f TG |
1235 | /* |
1236 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1237 | */ | |
1238 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1239 | { |
0e078e2f TG |
1240 | unsigned int v; |
1241 | exit_idle(); | |
1242 | irq_enter(); | |
1da177e4 | 1243 | /* |
0e078e2f TG |
1244 | * Check if this really is a spurious interrupt and ACK it |
1245 | * if it is a vectored one. Just in case... | |
1246 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1247 | */ |
0e078e2f TG |
1248 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1249 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1250 | ack_APIC_irq(); | |
c4d58cbd | 1251 | |
0e078e2f TG |
1252 | add_pda(irq_spurious_count, 1); |
1253 | irq_exit(); | |
1254 | } | |
1da177e4 | 1255 | |
0e078e2f TG |
1256 | /* |
1257 | * This interrupt should never happen with our APIC/SMP architecture | |
1258 | */ | |
1259 | asmlinkage void smp_error_interrupt(void) | |
1260 | { | |
1261 | unsigned int v, v1; | |
1da177e4 | 1262 | |
0e078e2f TG |
1263 | exit_idle(); |
1264 | irq_enter(); | |
1265 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1266 | v = apic_read(APIC_ESR); | |
1267 | apic_write(APIC_ESR, 0); | |
1268 | v1 = apic_read(APIC_ESR); | |
1269 | ack_APIC_irq(); | |
1270 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1271 | |
0e078e2f TG |
1272 | /* Here is what the APIC error bits mean: |
1273 | 0: Send CS error | |
1274 | 1: Receive CS error | |
1275 | 2: Send accept error | |
1276 | 3: Receive accept error | |
1277 | 4: Reserved | |
1278 | 5: Send illegal vector | |
1279 | 6: Received illegal vector | |
1280 | 7: Illegal register address | |
1281 | */ | |
1282 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1283 | smp_processor_id(), v , v1); | |
1284 | irq_exit(); | |
1da177e4 LT |
1285 | } |
1286 | ||
b5841765 GC |
1287 | /** |
1288 | * * connect_bsp_APIC - attach the APIC to the interrupt system | |
1289 | * */ | |
1290 | void __init connect_bsp_APIC(void) | |
1291 | { | |
1292 | enable_apic_mode(); | |
1293 | } | |
1294 | ||
274cfe59 CG |
1295 | /** |
1296 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1297 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1298 | * | |
1299 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1300 | * APIC is disabled. | |
1301 | */ | |
0e078e2f | 1302 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1303 | { |
0e078e2f TG |
1304 | /* Go back to Virtual Wire compatibility mode */ |
1305 | unsigned long value; | |
1da177e4 | 1306 | |
0e078e2f TG |
1307 | /* For the spurious interrupt use vector F, and enable it */ |
1308 | value = apic_read(APIC_SPIV); | |
1309 | value &= ~APIC_VECTOR_MASK; | |
1310 | value |= APIC_SPIV_APIC_ENABLED; | |
1311 | value |= 0xf; | |
1312 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1313 | |
0e078e2f TG |
1314 | if (!virt_wire_setup) { |
1315 | /* | |
1316 | * For LVT0 make it edge triggered, active high, | |
1317 | * external and enabled | |
1318 | */ | |
1319 | value = apic_read(APIC_LVT0); | |
1320 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1321 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1322 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1323 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1324 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1325 | apic_write(APIC_LVT0, value); | |
1326 | } else { | |
1327 | /* Disable LVT0 */ | |
1328 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1329 | } | |
b8ce3359 | 1330 | |
0e078e2f TG |
1331 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1332 | value = apic_read(APIC_LVT1); | |
1333 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1334 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1335 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1336 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1337 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1338 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1339 | } |
1340 | ||
be8a5685 AS |
1341 | void __cpuinit generic_processor_info(int apicid, int version) |
1342 | { | |
1343 | int cpu; | |
1344 | cpumask_t tmp_map; | |
1345 | ||
1346 | if (num_processors >= NR_CPUS) { | |
1347 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1348 | " Processor ignored.\n", NR_CPUS); | |
1349 | return; | |
1350 | } | |
1351 | ||
1352 | if (num_processors >= maxcpus) { | |
1353 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1354 | " Processor ignored.\n", maxcpus); | |
1355 | return; | |
1356 | } | |
1357 | ||
1358 | num_processors++; | |
1359 | cpus_complement(tmp_map, cpu_present_map); | |
1360 | cpu = first_cpu(tmp_map); | |
1361 | ||
1362 | physid_set(apicid, phys_cpu_present_map); | |
1363 | if (apicid == boot_cpu_physical_apicid) { | |
1364 | /* | |
1365 | * x86_bios_cpu_apicid is required to have processors listed | |
1366 | * in same order as logical cpu numbers. Hence the first | |
1367 | * entry is BSP, and so on. | |
1368 | */ | |
1369 | cpu = 0; | |
1370 | } | |
e0da3364 YL |
1371 | if (apicid > max_physical_apicid) |
1372 | max_physical_apicid = apicid; | |
1373 | ||
be8a5685 | 1374 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1375 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1376 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1377 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1378 | |
1379 | cpu_to_apicid[cpu] = apicid; | |
1380 | bios_cpu_apicid[cpu] = apicid; | |
1381 | } else { | |
1382 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1383 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1384 | } | |
1385 | ||
1386 | cpu_set(cpu, cpu_possible_map); | |
1387 | cpu_set(cpu, cpu_present_map); | |
1388 | } | |
1389 | ||
0c81c746 SS |
1390 | int hard_smp_processor_id(void) |
1391 | { | |
1392 | return read_apic_id(); | |
1393 | } | |
1394 | ||
89039b37 | 1395 | /* |
0e078e2f | 1396 | * Power management |
89039b37 | 1397 | */ |
0e078e2f TG |
1398 | #ifdef CONFIG_PM |
1399 | ||
1400 | static struct { | |
274cfe59 CG |
1401 | /* |
1402 | * 'active' is true if the local APIC was enabled by us and | |
1403 | * not the BIOS; this signifies that we are also responsible | |
1404 | * for disabling it before entering apm/acpi suspend | |
1405 | */ | |
0e078e2f TG |
1406 | int active; |
1407 | /* r/w apic fields */ | |
1408 | unsigned int apic_id; | |
1409 | unsigned int apic_taskpri; | |
1410 | unsigned int apic_ldr; | |
1411 | unsigned int apic_dfr; | |
1412 | unsigned int apic_spiv; | |
1413 | unsigned int apic_lvtt; | |
1414 | unsigned int apic_lvtpc; | |
1415 | unsigned int apic_lvt0; | |
1416 | unsigned int apic_lvt1; | |
1417 | unsigned int apic_lvterr; | |
1418 | unsigned int apic_tmict; | |
1419 | unsigned int apic_tdcr; | |
1420 | unsigned int apic_thmr; | |
1421 | } apic_pm_state; | |
1422 | ||
1423 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1424 | { | |
1425 | unsigned long flags; | |
1426 | int maxlvt; | |
89039b37 | 1427 | |
0e078e2f TG |
1428 | if (!apic_pm_state.active) |
1429 | return 0; | |
89039b37 | 1430 | |
0e078e2f | 1431 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1432 | |
2d7a66d0 | 1433 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1434 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1435 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1436 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1437 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1438 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1439 | if (maxlvt >= 4) | |
1440 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1441 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1442 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1443 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1444 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1445 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1446 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1447 | if (maxlvt >= 5) |
1448 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1449 | #endif | |
24968cfd | 1450 | |
0e078e2f TG |
1451 | local_irq_save(flags); |
1452 | disable_local_APIC(); | |
1453 | local_irq_restore(flags); | |
1454 | return 0; | |
1da177e4 LT |
1455 | } |
1456 | ||
0e078e2f | 1457 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1458 | { |
0e078e2f TG |
1459 | unsigned int l, h; |
1460 | unsigned long flags; | |
1461 | int maxlvt; | |
1da177e4 | 1462 | |
0e078e2f TG |
1463 | if (!apic_pm_state.active) |
1464 | return 0; | |
89b831ef | 1465 | |
0e078e2f | 1466 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1467 | |
0e078e2f | 1468 | local_irq_save(flags); |
92206c90 CG |
1469 | |
1470 | #ifdef CONFIG_X86_64 | |
1471 | if (x2apic) | |
1472 | enable_x2apic(); | |
1473 | else | |
1474 | #endif | |
d5e629a6 | 1475 | { |
92206c90 CG |
1476 | /* |
1477 | * Make sure the APICBASE points to the right address | |
1478 | * | |
1479 | * FIXME! This will be wrong if we ever support suspend on | |
1480 | * SMP! We'll need to do this as part of the CPU restore! | |
1481 | */ | |
6e1cb38a SS |
1482 | rdmsr(MSR_IA32_APICBASE, l, h); |
1483 | l &= ~MSR_IA32_APICBASE_BASE; | |
1484 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1485 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1486 | } |
6e1cb38a | 1487 | |
0e078e2f TG |
1488 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1489 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1490 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1491 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1492 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1493 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1494 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1495 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1496 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1497 | if (maxlvt >= 5) |
1498 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1499 | #endif | |
1500 | if (maxlvt >= 4) | |
1501 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1502 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1503 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1504 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1505 | apic_write(APIC_ESR, 0); | |
1506 | apic_read(APIC_ESR); | |
1507 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1508 | apic_write(APIC_ESR, 0); | |
1509 | apic_read(APIC_ESR); | |
92206c90 | 1510 | |
0e078e2f | 1511 | local_irq_restore(flags); |
92206c90 | 1512 | |
0e078e2f TG |
1513 | return 0; |
1514 | } | |
b8ce3359 | 1515 | |
274cfe59 CG |
1516 | /* |
1517 | * This device has no shutdown method - fully functioning local APICs | |
1518 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1519 | */ | |
1520 | ||
0e078e2f TG |
1521 | static struct sysdev_class lapic_sysclass = { |
1522 | .name = "lapic", | |
1523 | .resume = lapic_resume, | |
1524 | .suspend = lapic_suspend, | |
1525 | }; | |
b8ce3359 | 1526 | |
0e078e2f | 1527 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1528 | .id = 0, |
1529 | .cls = &lapic_sysclass, | |
0e078e2f | 1530 | }; |
b8ce3359 | 1531 | |
0e078e2f TG |
1532 | static void __cpuinit apic_pm_activate(void) |
1533 | { | |
1534 | apic_pm_state.active = 1; | |
1da177e4 LT |
1535 | } |
1536 | ||
0e078e2f | 1537 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1538 | { |
0e078e2f | 1539 | int error; |
e83a5fdc | 1540 | |
0e078e2f TG |
1541 | if (!cpu_has_apic) |
1542 | return 0; | |
1543 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1544 | |
0e078e2f TG |
1545 | error = sysdev_class_register(&lapic_sysclass); |
1546 | if (!error) | |
1547 | error = sysdev_register(&device_lapic); | |
1548 | return error; | |
1da177e4 | 1549 | } |
0e078e2f TG |
1550 | device_initcall(init_lapic_sysfs); |
1551 | ||
1552 | #else /* CONFIG_PM */ | |
1553 | ||
1554 | static void apic_pm_activate(void) { } | |
1555 | ||
1556 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1557 | |
1558 | /* | |
f8bf3c65 | 1559 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1560 | * |
1561 | * Thus far, the major user of this is IBM's Summit2 series: | |
1562 | * | |
637029c6 | 1563 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1564 | * multi-chassis. Use available data to take a good guess. |
1565 | * If in doubt, go HPET. | |
1566 | */ | |
f8bf3c65 | 1567 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1568 | { |
1569 | int i, clusters, zeros; | |
1570 | unsigned id; | |
322850af | 1571 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1572 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1573 | ||
322850af YL |
1574 | /* |
1575 | * there is not this kind of box with AMD CPU yet. | |
1576 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1577 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1578 | * vsmp box still need checking... |
322850af | 1579 | */ |
1cb68487 | 1580 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1581 | return 0; |
1582 | ||
23ca4bba | 1583 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1584 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1585 | |
1586 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1587 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1588 | if (bios_cpu_apicid) { |
1589 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1590 | } |
1591 | else if (i < nr_cpu_ids) { | |
1592 | if (cpu_present(i)) | |
1593 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1594 | else | |
1595 | continue; | |
1596 | } | |
1597 | else | |
1598 | break; | |
1599 | ||
1da177e4 LT |
1600 | if (id != BAD_APICID) |
1601 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1602 | } | |
1603 | ||
1604 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1605 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1606 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1607 | * Since clusters are allocated sequentially, count zeros only if | |
1608 | * they are bounded by ones. | |
1da177e4 LT |
1609 | */ |
1610 | clusters = 0; | |
1611 | zeros = 0; | |
1612 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1613 | if (test_bit(i, clustermap)) { | |
1614 | clusters += 1 + zeros; | |
1615 | zeros = 0; | |
1616 | } else | |
1617 | ++zeros; | |
1618 | } | |
1619 | ||
1cb68487 RT |
1620 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1621 | * not guaranteed to be synced between boards | |
1622 | */ | |
1623 | if (is_vsmp_box() && clusters > 1) | |
1624 | return 1; | |
1625 | ||
1da177e4 | 1626 | /* |
f8bf3c65 | 1627 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1628 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1629 | * out, but AFAIK this will work even for them. | |
1630 | */ | |
1631 | return (clusters > 2); | |
1632 | } | |
1633 | ||
6e1cb38a SS |
1634 | static __init int setup_nox2apic(char *str) |
1635 | { | |
1636 | disable_x2apic = 1; | |
1637 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1638 | return 0; | |
1639 | } | |
1640 | early_param("nox2apic", setup_nox2apic); | |
1641 | ||
1642 | ||
1da177e4 | 1643 | /* |
0e078e2f | 1644 | * APIC command line parameters |
1da177e4 | 1645 | */ |
0e078e2f | 1646 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1647 | { |
0e078e2f TG |
1648 | if (str == NULL) { |
1649 | skip_ioapic_setup = 0; | |
1650 | ioapic_force = 1; | |
1651 | return 0; | |
1da177e4 | 1652 | } |
0e078e2f TG |
1653 | if (strcmp("debug", str) == 0) |
1654 | apic_verbosity = APIC_DEBUG; | |
1655 | else if (strcmp("verbose", str) == 0) | |
1656 | apic_verbosity = APIC_VERBOSE; | |
1657 | else { | |
1658 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1659 | " use apic=verbose or apic=debug\n", str); | |
1660 | return -EINVAL; | |
1da177e4 LT |
1661 | } |
1662 | ||
1da177e4 LT |
1663 | return 0; |
1664 | } | |
0e078e2f | 1665 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1666 | |
6935d1f9 TG |
1667 | static __init int setup_disableapic(char *str) |
1668 | { | |
1da177e4 | 1669 | disable_apic = 1; |
9175fc06 | 1670 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1671 | return 0; |
1672 | } | |
1673 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1674 | |
2c8c0e6b | 1675 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1676 | static __init int setup_nolapic(char *str) |
1677 | { | |
2c8c0e6b | 1678 | return setup_disableapic(str); |
6935d1f9 | 1679 | } |
2c8c0e6b | 1680 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1681 | |
2e7c2838 LT |
1682 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1683 | { | |
1684 | local_apic_timer_c2_ok = 1; | |
1685 | return 0; | |
1686 | } | |
1687 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1688 | ||
36fef094 | 1689 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1690 | { |
1da177e4 | 1691 | disable_apic_timer = 1; |
36fef094 CG |
1692 | return 0; |
1693 | } | |
1694 | early_param("noapictimer", parse_disable_apic_timer); | |
1695 | ||
1696 | static int __init parse_nolapic_timer(char *arg) | |
1697 | { | |
1698 | disable_apic_timer = 1; | |
1699 | return 0; | |
6935d1f9 | 1700 | } |
36fef094 | 1701 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1702 | |
0c3749c4 AK |
1703 | static __init int setup_apicpmtimer(char *s) |
1704 | { | |
1705 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1706 | notsc_setup(NULL); |
b8ce3359 | 1707 | return 0; |
0c3749c4 AK |
1708 | } |
1709 | __setup("apicpmtimer", setup_apicpmtimer); | |
1710 | ||
1e934dda YL |
1711 | static int __init lapic_insert_resource(void) |
1712 | { | |
1713 | if (!apic_phys) | |
1714 | return -1; | |
1715 | ||
1716 | /* Put local APIC into the resource map. */ | |
1717 | lapic_resource.start = apic_phys; | |
1718 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1719 | insert_resource(&iomem_resource, &lapic_resource); | |
1720 | ||
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | /* | |
1725 | * need call insert after e820_reserve_resources() | |
1726 | * that is using request_resource | |
1727 | */ | |
1728 | late_initcall(lapic_insert_resource); |