Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
1da177e4 LT |
33 | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/mtrr.h> | |
37 | #include <asm/mpspec.h> | |
efa2559f | 38 | #include <asm/desc.h> |
773763df | 39 | #include <asm/arch_hooks.h> |
e83a5fdc | 40 | #include <asm/hpet.h> |
1da177e4 | 41 | #include <asm/pgalloc.h> |
773763df | 42 | #include <asm/i8253.h> |
75152114 | 43 | #include <asm/nmi.h> |
95833c83 | 44 | #include <asm/idle.h> |
73dea47f AK |
45 | #include <asm/proto.h> |
46 | #include <asm/timex.h> | |
2c8c0e6b | 47 | #include <asm/apic.h> |
6e1cb38a | 48 | #include <asm/i8259.h> |
1da177e4 | 49 | |
dd46e3ca | 50 | #include <mach_apic.h> |
773763df YL |
51 | #include <mach_apicdef.h> |
52 | #include <mach_ipi.h> | |
5af5573e | 53 | |
80e5609c CG |
54 | /* |
55 | * Sanity check | |
56 | */ | |
57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
58 | # error SPURIOUS_APIC_VECTOR definition error | |
59 | #endif | |
60 | ||
b3c51170 YL |
61 | #ifdef CONFIG_X86_32 |
62 | /* | |
63 | * Knob to control our willingness to enable the local APIC. | |
64 | * | |
65 | * +1=force-enable | |
66 | */ | |
67 | static int force_enable_local_apic; | |
68 | /* | |
69 | * APIC command line parameters | |
70 | */ | |
71 | static int __init parse_lapic(char *arg) | |
72 | { | |
73 | force_enable_local_apic = 1; | |
74 | return 0; | |
75 | } | |
76 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
77 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
78 | static int enabled_via_apicbase; | |
79 | ||
b3c51170 YL |
80 | #endif |
81 | ||
82 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 83 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
84 | static __init int setup_apicpmtimer(char *s) |
85 | { | |
86 | apic_calibrate_pmtmr = 1; | |
87 | notsc_setup(NULL); | |
88 | return 0; | |
89 | } | |
90 | __setup("apicpmtimer", setup_apicpmtimer); | |
91 | #endif | |
92 | ||
49899eac YL |
93 | #ifdef CONFIG_X86_64 |
94 | #define HAVE_X2APIC | |
95 | #endif | |
96 | ||
97 | #ifdef HAVE_X2APIC | |
89027d35 | 98 | int x2apic; |
6e1cb38a SS |
99 | /* x2apic enabled before OS handover */ |
100 | int x2apic_preenabled; | |
49899eac YL |
101 | int disable_x2apic; |
102 | static __init int setup_nox2apic(char *str) | |
103 | { | |
104 | disable_x2apic = 1; | |
105 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
106 | return 0; | |
107 | } | |
108 | early_param("nox2apic", setup_nox2apic); | |
109 | #endif | |
1da177e4 | 110 | |
b3c51170 YL |
111 | unsigned long mp_lapic_addr; |
112 | int disable_apic; | |
113 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
114 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 115 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
116 | int local_apic_timer_c2_ok; |
117 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
118 | ||
efa2559f YL |
119 | int first_system_vector = 0xfe; |
120 | ||
121 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
122 | ||
e83a5fdc HS |
123 | /* |
124 | * Debug level, exported for io_apic.c | |
125 | */ | |
baa13188 | 126 | unsigned int apic_verbosity; |
e83a5fdc | 127 | |
89c38c28 CG |
128 | int pic_mode; |
129 | ||
bab4b27c AS |
130 | /* Have we found an MP table */ |
131 | int smp_found_config; | |
132 | ||
39928722 AD |
133 | static struct resource lapic_resource = { |
134 | .name = "Local APIC", | |
135 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
136 | }; | |
137 | ||
d03030e9 TG |
138 | static unsigned int calibration_result; |
139 | ||
ba7eda4c TG |
140 | static int lapic_next_event(unsigned long delta, |
141 | struct clock_event_device *evt); | |
142 | static void lapic_timer_setup(enum clock_event_mode mode, | |
143 | struct clock_event_device *evt); | |
ba7eda4c | 144 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 145 | static void apic_pm_activate(void); |
ba7eda4c | 146 | |
274cfe59 CG |
147 | /* |
148 | * The local apic timer can be used for any function which is CPU local. | |
149 | */ | |
ba7eda4c TG |
150 | static struct clock_event_device lapic_clockevent = { |
151 | .name = "lapic", | |
152 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
153 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
154 | .shift = 32, | |
155 | .set_mode = lapic_timer_setup, | |
156 | .set_next_event = lapic_next_event, | |
157 | .broadcast = lapic_timer_broadcast, | |
158 | .rating = 100, | |
159 | .irq = -1, | |
160 | }; | |
161 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
162 | ||
d3432896 AK |
163 | static unsigned long apic_phys; |
164 | ||
0e078e2f TG |
165 | /* |
166 | * Get the LAPIC version | |
167 | */ | |
168 | static inline int lapic_get_version(void) | |
ba7eda4c | 169 | { |
0e078e2f | 170 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
171 | } |
172 | ||
0e078e2f | 173 | /* |
9c803869 | 174 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
175 | */ |
176 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 177 | { |
9c803869 | 178 | #ifdef CONFIG_X86_64 |
0e078e2f | 179 | return 1; |
9c803869 CG |
180 | #else |
181 | return APIC_INTEGRATED(lapic_get_version()); | |
182 | #endif | |
ba7eda4c TG |
183 | } |
184 | ||
185 | /* | |
0e078e2f | 186 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 187 | */ |
0e078e2f | 188 | static int modern_apic(void) |
ba7eda4c | 189 | { |
0e078e2f TG |
190 | /* AMD systems use old APIC versions, so check the CPU */ |
191 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
192 | boot_cpu_data.x86 >= 0xf) | |
193 | return 1; | |
194 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
195 | } |
196 | ||
274cfe59 CG |
197 | /* |
198 | * Paravirt kernels also might be using these below ops. So we still | |
199 | * use generic apic_read()/apic_write(), which might be pointing to different | |
200 | * ops in PARAVIRT case. | |
201 | */ | |
1b374e4d | 202 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
203 | { |
204 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
205 | cpu_relax(); | |
206 | } | |
207 | ||
1b374e4d | 208 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 209 | { |
3c6bb07a | 210 | u32 send_status; |
8339e9fb FLV |
211 | int timeout; |
212 | ||
213 | timeout = 0; | |
214 | do { | |
215 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
216 | if (!send_status) | |
217 | break; | |
218 | udelay(100); | |
219 | } while (timeout++ < 1000); | |
220 | ||
221 | return send_status; | |
222 | } | |
223 | ||
1b374e4d SS |
224 | void xapic_icr_write(u32 low, u32 id) |
225 | { | |
ed4e5ec1 | 226 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
227 | apic_write(APIC_ICR, low); |
228 | } | |
229 | ||
230 | u64 xapic_icr_read(void) | |
231 | { | |
232 | u32 icr1, icr2; | |
233 | ||
234 | icr2 = apic_read(APIC_ICR2); | |
235 | icr1 = apic_read(APIC_ICR); | |
236 | ||
cf9768d7 | 237 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
238 | } |
239 | ||
240 | static struct apic_ops xapic_ops = { | |
241 | .read = native_apic_mem_read, | |
242 | .write = native_apic_mem_write, | |
1b374e4d SS |
243 | .icr_read = xapic_icr_read, |
244 | .icr_write = xapic_icr_write, | |
245 | .wait_icr_idle = xapic_wait_icr_idle, | |
246 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
247 | }; | |
248 | ||
249 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
250 | EXPORT_SYMBOL_GPL(apic_ops); |
251 | ||
49899eac | 252 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
253 | static void x2apic_wait_icr_idle(void) |
254 | { | |
255 | /* no need to wait for icr idle in x2apic */ | |
256 | return; | |
257 | } | |
258 | ||
259 | static u32 safe_x2apic_wait_icr_idle(void) | |
260 | { | |
261 | /* no need to wait for icr idle in x2apic */ | |
262 | return 0; | |
263 | } | |
264 | ||
265 | void x2apic_icr_write(u32 low, u32 id) | |
266 | { | |
267 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
268 | } | |
269 | ||
270 | u64 x2apic_icr_read(void) | |
271 | { | |
272 | unsigned long val; | |
273 | ||
274 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
275 | return val; | |
276 | } | |
277 | ||
278 | static struct apic_ops x2apic_ops = { | |
279 | .read = native_apic_msr_read, | |
280 | .write = native_apic_msr_write, | |
13c88fb5 SS |
281 | .icr_read = x2apic_icr_read, |
282 | .icr_write = x2apic_icr_write, | |
283 | .wait_icr_idle = x2apic_wait_icr_idle, | |
284 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
285 | }; | |
49899eac | 286 | #endif |
13c88fb5 | 287 | |
0e078e2f TG |
288 | /** |
289 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
290 | */ | |
e9427101 | 291 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 292 | { |
11a8e778 | 293 | unsigned int v; |
6935d1f9 TG |
294 | |
295 | /* unmask and set to NMI */ | |
296 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
297 | |
298 | /* Level triggered for 82489DX (32bit mode) */ | |
299 | if (!lapic_is_integrated()) | |
300 | v |= APIC_LVT_LEVEL_TRIGGER; | |
301 | ||
11a8e778 | 302 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
303 | } |
304 | ||
7c37e48b CG |
305 | #ifdef CONFIG_X86_32 |
306 | /** | |
307 | * get_physical_broadcast - Get number of physical broadcast IDs | |
308 | */ | |
309 | int get_physical_broadcast(void) | |
310 | { | |
311 | return modern_apic() ? 0xff : 0xf; | |
312 | } | |
313 | #endif | |
314 | ||
0e078e2f TG |
315 | /** |
316 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
317 | */ | |
37e650c7 | 318 | int lapic_get_maxlvt(void) |
1da177e4 | 319 | { |
36a028de | 320 | unsigned int v; |
1da177e4 LT |
321 | |
322 | v = apic_read(APIC_LVR); | |
36a028de CG |
323 | /* |
324 | * - we always have APIC integrated on 64bit mode | |
325 | * - 82489DXs do not report # of LVT entries | |
326 | */ | |
327 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
328 | } |
329 | ||
274cfe59 CG |
330 | /* |
331 | * Local APIC timer | |
332 | */ | |
333 | ||
c40aaec6 CG |
334 | /* Clock divisor */ |
335 | #ifdef CONFG_X86_64 | |
f07f4f90 | 336 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
337 | #else |
338 | #define APIC_DIVISOR 16 | |
339 | #endif | |
f07f4f90 | 340 | |
0e078e2f TG |
341 | /* |
342 | * This function sets up the local APIC timer, with a timeout of | |
343 | * 'clocks' APIC bus clock. During calibration we actually call | |
344 | * this function twice on the boot CPU, once with a bogus timeout | |
345 | * value, second time for real. The other (noncalibrating) CPUs | |
346 | * call this function only once, with the real, calibrated value. | |
347 | * | |
348 | * We do reads before writes even if unnecessary, to get around the | |
349 | * P5 APIC double write bug. | |
350 | */ | |
0e078e2f | 351 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 352 | { |
0e078e2f | 353 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 354 | |
0e078e2f TG |
355 | lvtt_value = LOCAL_TIMER_VECTOR; |
356 | if (!oneshot) | |
357 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
358 | if (!lapic_is_integrated()) |
359 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
360 | ||
0e078e2f TG |
361 | if (!irqen) |
362 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 363 | |
0e078e2f | 364 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
365 | |
366 | /* | |
0e078e2f | 367 | * Divide PICLK by 16 |
1da177e4 | 368 | */ |
0e078e2f | 369 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
370 | apic_write(APIC_TDCR, |
371 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
372 | APIC_TDR_DIV_16); | |
0e078e2f TG |
373 | |
374 | if (!oneshot) | |
f07f4f90 | 375 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
376 | } |
377 | ||
0e078e2f | 378 | /* |
7b83dae7 RR |
379 | * Setup extended LVT, AMD specific (K8, family 10h) |
380 | * | |
381 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
382 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
383 | * |
384 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
385 | * enables the vector. See also the BKDGs. | |
0e078e2f | 386 | */ |
7b83dae7 RR |
387 | |
388 | #define APIC_EILVT_LVTOFF_MCE 0 | |
389 | #define APIC_EILVT_LVTOFF_IBS 1 | |
390 | ||
391 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 392 | { |
7b83dae7 | 393 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 394 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 395 | |
0e078e2f | 396 | apic_write(reg, v); |
1da177e4 LT |
397 | } |
398 | ||
7b83dae7 RR |
399 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
400 | { | |
401 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
402 | return APIC_EILVT_LVTOFF_MCE; | |
403 | } | |
404 | ||
405 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
406 | { | |
407 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
408 | return APIC_EILVT_LVTOFF_IBS; | |
409 | } | |
6aa360e6 | 410 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 411 | |
0e078e2f TG |
412 | /* |
413 | * Program the next event, relative to now | |
414 | */ | |
415 | static int lapic_next_event(unsigned long delta, | |
416 | struct clock_event_device *evt) | |
1da177e4 | 417 | { |
0e078e2f TG |
418 | apic_write(APIC_TMICT, delta); |
419 | return 0; | |
1da177e4 LT |
420 | } |
421 | ||
0e078e2f TG |
422 | /* |
423 | * Setup the lapic timer in periodic or oneshot mode | |
424 | */ | |
425 | static void lapic_timer_setup(enum clock_event_mode mode, | |
426 | struct clock_event_device *evt) | |
9b7711f0 HS |
427 | { |
428 | unsigned long flags; | |
0e078e2f | 429 | unsigned int v; |
9b7711f0 | 430 | |
0e078e2f TG |
431 | /* Lapic used as dummy for broadcast ? */ |
432 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
433 | return; |
434 | ||
435 | local_irq_save(flags); | |
436 | ||
0e078e2f TG |
437 | switch (mode) { |
438 | case CLOCK_EVT_MODE_PERIODIC: | |
439 | case CLOCK_EVT_MODE_ONESHOT: | |
440 | __setup_APIC_LVTT(calibration_result, | |
441 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
442 | break; | |
443 | case CLOCK_EVT_MODE_UNUSED: | |
444 | case CLOCK_EVT_MODE_SHUTDOWN: | |
445 | v = apic_read(APIC_LVTT); | |
446 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
447 | apic_write(APIC_LVTT, v); | |
448 | break; | |
449 | case CLOCK_EVT_MODE_RESUME: | |
450 | /* Nothing to do here */ | |
451 | break; | |
452 | } | |
9b7711f0 HS |
453 | |
454 | local_irq_restore(flags); | |
455 | } | |
456 | ||
1da177e4 | 457 | /* |
0e078e2f | 458 | * Local APIC timer broadcast function |
1da177e4 | 459 | */ |
0e078e2f | 460 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 461 | { |
0e078e2f TG |
462 | #ifdef CONFIG_SMP |
463 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
464 | #endif | |
465 | } | |
1da177e4 | 466 | |
0e078e2f TG |
467 | /* |
468 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
469 | * of the boot CPU and register the clock event in the framework. | |
470 | */ | |
db4b5525 | 471 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
472 | { |
473 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 474 | |
0e078e2f TG |
475 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
476 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 477 | |
0e078e2f TG |
478 | clockevents_register_device(levt); |
479 | } | |
1da177e4 | 480 | |
0e078e2f TG |
481 | /* |
482 | * In this function we calibrate APIC bus clocks to the external | |
483 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
484 | * to calibrate, since some later bootup code depends on getting | |
485 | * the first irq? Ugh. | |
486 | * | |
487 | * We want to do the calibration only once since we | |
488 | * want to have local timer irqs syncron. CPUs connected | |
489 | * by the same APIC bus have the very same bus frequency. | |
490 | * And we want to have irqs off anyways, no accidental | |
491 | * APIC irq that way. | |
492 | */ | |
493 | ||
494 | #define TICK_COUNT 100000000 | |
495 | ||
89b3b1f4 | 496 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
497 | { |
498 | unsigned apic, apic_start; | |
499 | unsigned long tsc, tsc_start; | |
500 | int result; | |
501 | ||
502 | local_irq_disable(); | |
503 | ||
504 | /* | |
505 | * Put whatever arbitrary (but long enough) timeout | |
506 | * value into the APIC clock, we just want to get the | |
507 | * counter running for calibration. | |
508 | * | |
509 | * No interrupt enable ! | |
510 | */ | |
511 | __setup_APIC_LVTT(250000000, 0, 0); | |
512 | ||
513 | apic_start = apic_read(APIC_TMCCT); | |
514 | #ifdef CONFIG_X86_PM_TIMER | |
515 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
516 | pmtimer_wait(5000); /* 5ms wait */ | |
517 | apic = apic_read(APIC_TMCCT); | |
518 | result = (apic_start - apic) * 1000L / 5; | |
519 | } else | |
520 | #endif | |
521 | { | |
522 | rdtscll(tsc_start); | |
523 | ||
524 | do { | |
525 | apic = apic_read(APIC_TMCCT); | |
526 | rdtscll(tsc); | |
527 | } while ((tsc - tsc_start) < TICK_COUNT && | |
528 | (apic_start - apic) < TICK_COUNT); | |
529 | ||
530 | result = (apic_start - apic) * 1000L * tsc_khz / | |
531 | (tsc - tsc_start); | |
532 | } | |
533 | ||
534 | local_irq_enable(); | |
535 | ||
536 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
537 | ||
538 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
539 | result / 1000 / 1000, result / 1000 % 1000); | |
540 | ||
541 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
542 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
543 | lapic_clockevent.shift); | |
0e078e2f TG |
544 | lapic_clockevent.max_delta_ns = |
545 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
546 | lapic_clockevent.min_delta_ns = | |
547 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
548 | ||
f07f4f90 | 549 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
550 | |
551 | /* | |
552 | * Do a sanity check on the APIC calibration result | |
553 | */ | |
554 | if (calibration_result < (1000000 / HZ)) { | |
555 | printk(KERN_WARNING | |
556 | "APIC frequency too slow, disabling apic timer\n"); | |
557 | return -1; | |
558 | } | |
559 | ||
560 | return 0; | |
0e078e2f TG |
561 | } |
562 | ||
e83a5fdc HS |
563 | /* |
564 | * Setup the boot APIC | |
565 | * | |
566 | * Calibrate and verify the result. | |
567 | */ | |
0e078e2f TG |
568 | void __init setup_boot_APIC_clock(void) |
569 | { | |
570 | /* | |
274cfe59 CG |
571 | * The local apic timer can be disabled via the kernel |
572 | * commandline or from the CPU detection code. Register the lapic | |
573 | * timer as a dummy clock event source on SMP systems, so the | |
574 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
575 | */ |
576 | if (disable_apic_timer) { | |
577 | printk(KERN_INFO "Disabling APIC timer\n"); | |
578 | /* No broadcast on UP ! */ | |
9d09951d TG |
579 | if (num_possible_cpus() > 1) { |
580 | lapic_clockevent.mult = 1; | |
0e078e2f | 581 | setup_APIC_timer(); |
9d09951d | 582 | } |
0e078e2f TG |
583 | return; |
584 | } | |
585 | ||
274cfe59 CG |
586 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
587 | "calibrating APIC timer ...\n"); | |
588 | ||
89b3b1f4 | 589 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
590 | /* No broadcast on UP ! */ |
591 | if (num_possible_cpus() > 1) | |
592 | setup_APIC_timer(); | |
593 | return; | |
594 | } | |
595 | ||
0e078e2f TG |
596 | /* |
597 | * If nmi_watchdog is set to IO_APIC, we need the | |
598 | * PIT/HPET going. Otherwise register lapic as a dummy | |
599 | * device. | |
600 | */ | |
601 | if (nmi_watchdog != NMI_IO_APIC) | |
602 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
603 | else | |
604 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 605 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 606 | |
274cfe59 | 607 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
608 | setup_APIC_timer(); |
609 | } | |
610 | ||
0e078e2f TG |
611 | void __cpuinit setup_secondary_APIC_clock(void) |
612 | { | |
0e078e2f TG |
613 | setup_APIC_timer(); |
614 | } | |
615 | ||
616 | /* | |
617 | * The guts of the apic timer interrupt | |
618 | */ | |
619 | static void local_apic_timer_interrupt(void) | |
620 | { | |
621 | int cpu = smp_processor_id(); | |
622 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
623 | ||
624 | /* | |
625 | * Normally we should not be here till LAPIC has been initialized but | |
626 | * in some cases like kdump, its possible that there is a pending LAPIC | |
627 | * timer interrupt from previous kernel's context and is delivered in | |
628 | * new kernel the moment interrupts are enabled. | |
629 | * | |
630 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
631 | * its possible that when we get here evt->event_handler is NULL. | |
632 | * Check for event_handler being NULL and discard the interrupt as | |
633 | * spurious. | |
634 | */ | |
635 | if (!evt->event_handler) { | |
636 | printk(KERN_WARNING | |
637 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
638 | /* Switch it off */ | |
639 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
640 | return; | |
641 | } | |
642 | ||
643 | /* | |
644 | * the NMI deadlock-detector uses this. | |
645 | */ | |
0b23e8cf | 646 | #ifdef CONFIG_X86_64 |
0e078e2f | 647 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
648 | #else |
649 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
650 | #endif | |
0e078e2f TG |
651 | |
652 | evt->event_handler(evt); | |
653 | } | |
654 | ||
655 | /* | |
656 | * Local APIC timer interrupt. This is the most natural way for doing | |
657 | * local interrupts, but local timer interrupts can be emulated by | |
658 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
659 | * | |
660 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
661 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
662 | */ | |
663 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
664 | { | |
665 | struct pt_regs *old_regs = set_irq_regs(regs); | |
666 | ||
667 | /* | |
668 | * NOTE! We'd better ACK the irq immediately, | |
669 | * because timer handling can be slow. | |
670 | */ | |
671 | ack_APIC_irq(); | |
672 | /* | |
673 | * update_process_times() expects us to have done irq_enter(). | |
674 | * Besides, if we don't timer interrupts ignore the global | |
675 | * interrupt lock, which is the WrongThing (tm) to do. | |
676 | */ | |
6460bc73 | 677 | #ifdef CONFIG_X86_64 |
0e078e2f | 678 | exit_idle(); |
6460bc73 | 679 | #endif |
0e078e2f TG |
680 | irq_enter(); |
681 | local_apic_timer_interrupt(); | |
682 | irq_exit(); | |
274cfe59 | 683 | |
0e078e2f TG |
684 | set_irq_regs(old_regs); |
685 | } | |
686 | ||
687 | int setup_profiling_timer(unsigned int multiplier) | |
688 | { | |
689 | return -EINVAL; | |
690 | } | |
691 | ||
0e078e2f TG |
692 | /* |
693 | * Local APIC start and shutdown | |
694 | */ | |
695 | ||
696 | /** | |
697 | * clear_local_APIC - shutdown the local APIC | |
698 | * | |
699 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
700 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
701 | * leftovers during boot. | |
702 | */ | |
703 | void clear_local_APIC(void) | |
704 | { | |
2584a82d | 705 | int maxlvt; |
0e078e2f TG |
706 | u32 v; |
707 | ||
d3432896 AK |
708 | /* APIC hasn't been mapped yet */ |
709 | if (!apic_phys) | |
710 | return; | |
711 | ||
712 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
713 | /* |
714 | * Masking an LVT entry can trigger a local APIC error | |
715 | * if the vector is zero. Mask LVTERR first to prevent this. | |
716 | */ | |
717 | if (maxlvt >= 3) { | |
718 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
719 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
720 | } | |
721 | /* | |
722 | * Careful: we have to set masks only first to deassert | |
723 | * any level-triggered sources. | |
724 | */ | |
725 | v = apic_read(APIC_LVTT); | |
726 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
727 | v = apic_read(APIC_LVT0); | |
728 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
729 | v = apic_read(APIC_LVT1); | |
730 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
731 | if (maxlvt >= 4) { | |
732 | v = apic_read(APIC_LVTPC); | |
733 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
734 | } | |
735 | ||
6764014b CG |
736 | /* lets not touch this if we didn't frob it */ |
737 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
738 | if (maxlvt >= 5) { | |
739 | v = apic_read(APIC_LVTTHMR); | |
740 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
741 | } | |
742 | #endif | |
0e078e2f TG |
743 | /* |
744 | * Clean APIC state for other OSs: | |
745 | */ | |
746 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
747 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
748 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
749 | if (maxlvt >= 3) | |
750 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
751 | if (maxlvt >= 4) | |
752 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
753 | |
754 | /* Integrated APIC (!82489DX) ? */ | |
755 | if (lapic_is_integrated()) { | |
756 | if (maxlvt > 3) | |
757 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
758 | apic_write(APIC_ESR, 0); | |
759 | apic_read(APIC_ESR); | |
760 | } | |
0e078e2f TG |
761 | } |
762 | ||
763 | /** | |
764 | * disable_local_APIC - clear and disable the local APIC | |
765 | */ | |
766 | void disable_local_APIC(void) | |
767 | { | |
768 | unsigned int value; | |
769 | ||
770 | clear_local_APIC(); | |
771 | ||
772 | /* | |
773 | * Disable APIC (implies clearing of registers | |
774 | * for 82489DX!). | |
775 | */ | |
776 | value = apic_read(APIC_SPIV); | |
777 | value &= ~APIC_SPIV_APIC_ENABLED; | |
778 | apic_write(APIC_SPIV, value); | |
990b183e CG |
779 | |
780 | #ifdef CONFIG_X86_32 | |
781 | /* | |
782 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
783 | * restore the disabled state. | |
784 | */ | |
785 | if (enabled_via_apicbase) { | |
786 | unsigned int l, h; | |
787 | ||
788 | rdmsr(MSR_IA32_APICBASE, l, h); | |
789 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
790 | wrmsr(MSR_IA32_APICBASE, l, h); | |
791 | } | |
792 | #endif | |
0e078e2f TG |
793 | } |
794 | ||
fe4024dc CG |
795 | /* |
796 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
797 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
798 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
799 | * for the case where Linux didn't enable the LAPIC. | |
800 | */ | |
0e078e2f TG |
801 | void lapic_shutdown(void) |
802 | { | |
803 | unsigned long flags; | |
804 | ||
805 | if (!cpu_has_apic) | |
806 | return; | |
807 | ||
808 | local_irq_save(flags); | |
809 | ||
fe4024dc CG |
810 | #ifdef CONFIG_X86_32 |
811 | if (!enabled_via_apicbase) | |
812 | clear_local_APIC(); | |
813 | else | |
814 | #endif | |
815 | disable_local_APIC(); | |
816 | ||
0e078e2f TG |
817 | |
818 | local_irq_restore(flags); | |
819 | } | |
820 | ||
821 | /* | |
822 | * This is to verify that we're looking at a real local APIC. | |
823 | * Check these against your board if the CPUs aren't getting | |
824 | * started for no apparent reason. | |
825 | */ | |
826 | int __init verify_local_APIC(void) | |
827 | { | |
828 | unsigned int reg0, reg1; | |
829 | ||
830 | /* | |
831 | * The version register is read-only in a real APIC. | |
832 | */ | |
833 | reg0 = apic_read(APIC_LVR); | |
834 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
835 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
836 | reg1 = apic_read(APIC_LVR); | |
837 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
838 | ||
839 | /* | |
840 | * The two version reads above should print the same | |
841 | * numbers. If the second one is different, then we | |
842 | * poke at a non-APIC. | |
843 | */ | |
844 | if (reg1 != reg0) | |
845 | return 0; | |
846 | ||
847 | /* | |
848 | * Check if the version looks reasonably. | |
849 | */ | |
850 | reg1 = GET_APIC_VERSION(reg0); | |
851 | if (reg1 == 0x00 || reg1 == 0xff) | |
852 | return 0; | |
853 | reg1 = lapic_get_maxlvt(); | |
854 | if (reg1 < 0x02 || reg1 == 0xff) | |
855 | return 0; | |
856 | ||
857 | /* | |
858 | * The ID register is read/write in a real APIC. | |
859 | */ | |
2d7a66d0 | 860 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
861 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
862 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 863 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
864 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
865 | apic_write(APIC_ID, reg0); | |
866 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
867 | return 0; | |
868 | ||
869 | /* | |
1da177e4 LT |
870 | * The next two are just to see if we have sane values. |
871 | * They're only really relevant if we're in Virtual Wire | |
872 | * compatibility mode, but most boxes are anymore. | |
873 | */ | |
874 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 875 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
876 | reg1 = apic_read(APIC_LVT1); |
877 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
878 | ||
879 | return 1; | |
880 | } | |
881 | ||
0e078e2f TG |
882 | /** |
883 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
884 | */ | |
1da177e4 LT |
885 | void __init sync_Arb_IDs(void) |
886 | { | |
296cb951 CG |
887 | /* |
888 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
889 | * needed on AMD. | |
890 | */ | |
891 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
892 | return; |
893 | ||
894 | /* | |
895 | * Wait for idle. | |
896 | */ | |
897 | apic_wait_icr_idle(); | |
898 | ||
899 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
900 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
901 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
902 | } |
903 | ||
1da177e4 LT |
904 | /* |
905 | * An initial setup of the virtual wire mode. | |
906 | */ | |
907 | void __init init_bsp_APIC(void) | |
908 | { | |
11a8e778 | 909 | unsigned int value; |
1da177e4 LT |
910 | |
911 | /* | |
912 | * Don't do the setup now if we have a SMP BIOS as the | |
913 | * through-I/O-APIC virtual wire mode might be active. | |
914 | */ | |
915 | if (smp_found_config || !cpu_has_apic) | |
916 | return; | |
917 | ||
1da177e4 LT |
918 | /* |
919 | * Do not trust the local APIC being empty at bootup. | |
920 | */ | |
921 | clear_local_APIC(); | |
922 | ||
923 | /* | |
924 | * Enable APIC. | |
925 | */ | |
926 | value = apic_read(APIC_SPIV); | |
927 | value &= ~APIC_VECTOR_MASK; | |
928 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
929 | |
930 | #ifdef CONFIG_X86_32 | |
931 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
932 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
933 | (boot_cpu_data.x86 == 15)) | |
934 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
935 | else | |
936 | #endif | |
937 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 938 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 939 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
940 | |
941 | /* | |
942 | * Set up the virtual wire mode. | |
943 | */ | |
11a8e778 | 944 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 945 | value = APIC_DM_NMI; |
638c0411 CG |
946 | if (!lapic_is_integrated()) /* 82489DX */ |
947 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 948 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
949 | } |
950 | ||
c43da2f5 CG |
951 | static void __cpuinit lapic_setup_esr(void) |
952 | { | |
953 | unsigned long oldvalue, value, maxlvt; | |
954 | if (lapic_is_integrated() && !esr_disable) { | |
955 | if (esr_disable) { | |
956 | /* | |
957 | * Something untraceable is creating bad interrupts on | |
958 | * secondary quads ... for the moment, just leave the | |
959 | * ESR disabled - we can't do anything useful with the | |
960 | * errors anyway - mbligh | |
961 | */ | |
962 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
963 | return; | |
964 | } | |
965 | /* !82489DX */ | |
966 | maxlvt = lapic_get_maxlvt(); | |
967 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
968 | apic_write(APIC_ESR, 0); | |
969 | oldvalue = apic_read(APIC_ESR); | |
970 | ||
971 | /* enables sending errors */ | |
972 | value = ERROR_APIC_VECTOR; | |
973 | apic_write(APIC_LVTERR, value); | |
974 | /* | |
975 | * spec says clear errors after enabling vector. | |
976 | */ | |
977 | if (maxlvt > 3) | |
978 | apic_write(APIC_ESR, 0); | |
979 | value = apic_read(APIC_ESR); | |
980 | if (value != oldvalue) | |
981 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
982 | "vector: 0x%08lx after: 0x%08lx\n", | |
983 | oldvalue, value); | |
984 | } else { | |
985 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
986 | } | |
987 | } | |
988 | ||
989 | ||
0e078e2f TG |
990 | /** |
991 | * setup_local_APIC - setup the local APIC | |
992 | */ | |
993 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 994 | { |
739f33b3 | 995 | unsigned int value; |
da7ed9f9 | 996 | int i, j; |
1da177e4 | 997 | |
89c38c28 CG |
998 | #ifdef CONFIG_X86_32 |
999 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
1000 | if (esr_disable) { | |
1001 | apic_write(APIC_ESR, 0); | |
1002 | apic_write(APIC_ESR, 0); | |
1003 | apic_write(APIC_ESR, 0); | |
1004 | apic_write(APIC_ESR, 0); | |
1005 | } | |
1006 | #endif | |
1007 | ||
ac23d4ee | 1008 | preempt_disable(); |
1da177e4 | 1009 | |
1da177e4 LT |
1010 | /* |
1011 | * Double-check whether this APIC is really registered. | |
1012 | * This is meaningless in clustered apic mode, so we skip it. | |
1013 | */ | |
1014 | if (!apic_id_registered()) | |
1015 | BUG(); | |
1016 | ||
1017 | /* | |
1018 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1019 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1020 | * document number 292116). So here it goes... | |
1021 | */ | |
1022 | init_apic_ldr(); | |
1023 | ||
1024 | /* | |
1025 | * Set Task Priority to 'accept all'. We never change this | |
1026 | * later on. | |
1027 | */ | |
1028 | value = apic_read(APIC_TASKPRI); | |
1029 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1030 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1031 | |
da7ed9f9 VG |
1032 | /* |
1033 | * After a crash, we no longer service the interrupts and a pending | |
1034 | * interrupt from previous kernel might still have ISR bit set. | |
1035 | * | |
1036 | * Most probably by now CPU has serviced that pending interrupt and | |
1037 | * it might not have done the ack_APIC_irq() because it thought, | |
1038 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1039 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1040 | * the interrupt. Hence a vector might get locked. It was noticed | |
1041 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1042 | */ | |
1043 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1044 | value = apic_read(APIC_ISR + i*0x10); | |
1045 | for (j = 31; j >= 0; j--) { | |
1046 | if (value & (1<<j)) | |
1047 | ack_APIC_irq(); | |
1048 | } | |
1049 | } | |
1050 | ||
1da177e4 LT |
1051 | /* |
1052 | * Now that we are all set up, enable the APIC | |
1053 | */ | |
1054 | value = apic_read(APIC_SPIV); | |
1055 | value &= ~APIC_VECTOR_MASK; | |
1056 | /* | |
1057 | * Enable APIC | |
1058 | */ | |
1059 | value |= APIC_SPIV_APIC_ENABLED; | |
1060 | ||
89c38c28 CG |
1061 | #ifdef CONFIG_X86_32 |
1062 | /* | |
1063 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1064 | * certain networking cards. If high frequency interrupts are | |
1065 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1066 | * entry is masked/unmasked at a high rate as well then sooner or | |
1067 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1068 | * from the device. If focus CPU is disabled then the hang goes | |
1069 | * away, oh well :-( | |
1070 | * | |
1071 | * [ This bug can be reproduced easily with a level-triggered | |
1072 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1073 | * BX chipset. ] | |
1074 | */ | |
1075 | /* | |
1076 | * Actually disabling the focus CPU check just makes the hang less | |
1077 | * frequent as it makes the interrupt distributon model be more | |
1078 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1079 | * See also the comment in end_level_ioapic_irq(). --macro | |
1080 | */ | |
1081 | ||
1082 | /* | |
1083 | * - enable focus processor (bit==0) | |
1084 | * - 64bit mode always use processor focus | |
1085 | * so no need to set it | |
1086 | */ | |
1087 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1088 | #endif | |
3f14c746 | 1089 | |
1da177e4 LT |
1090 | /* |
1091 | * Set spurious IRQ vector | |
1092 | */ | |
1093 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1094 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1095 | |
1096 | /* | |
1097 | * Set up LVT0, LVT1: | |
1098 | * | |
1099 | * set up through-local-APIC on the BP's LINT0. This is not | |
1100 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1101 | * we delegate interrupts to the 8259A. | |
1102 | */ | |
1103 | /* | |
1104 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1105 | */ | |
1106 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1107 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1108 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1109 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1110 | smp_processor_id()); |
1da177e4 LT |
1111 | } else { |
1112 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1113 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1114 | smp_processor_id()); |
1da177e4 | 1115 | } |
11a8e778 | 1116 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1117 | |
1118 | /* | |
1119 | * only the BP should see the LINT1 NMI signal, obviously. | |
1120 | */ | |
1121 | if (!smp_processor_id()) | |
1122 | value = APIC_DM_NMI; | |
1123 | else | |
1124 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1125 | if (!lapic_is_integrated()) /* 82489DX */ |
1126 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1127 | apic_write(APIC_LVT1, value); |
89c38c28 | 1128 | |
ac23d4ee | 1129 | preempt_enable(); |
739f33b3 | 1130 | } |
1da177e4 | 1131 | |
739f33b3 AK |
1132 | void __cpuinit end_local_APIC_setup(void) |
1133 | { | |
1134 | lapic_setup_esr(); | |
fa6b95fc CG |
1135 | |
1136 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1137 | { |
1138 | unsigned int value; | |
1139 | /* Disable the local apic timer */ | |
1140 | value = apic_read(APIC_LVTT); | |
1141 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1142 | apic_write(APIC_LVTT, value); | |
1143 | } | |
fa6b95fc CG |
1144 | #endif |
1145 | ||
f2802e7f | 1146 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1147 | apic_pm_activate(); |
1da177e4 | 1148 | } |
1da177e4 | 1149 | |
49899eac | 1150 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1151 | void check_x2apic(void) |
1152 | { | |
1153 | int msr, msr2; | |
1154 | ||
1155 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1156 | ||
1157 | if (msr & X2APIC_ENABLE) { | |
1158 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1159 | x2apic_preenabled = x2apic = 1; | |
1160 | apic_ops = &x2apic_ops; | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | void enable_x2apic(void) | |
1165 | { | |
1166 | int msr, msr2; | |
1167 | ||
1168 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1169 | if (!(msr & X2APIC_ENABLE)) { | |
1170 | printk("Enabling x2apic\n"); | |
1171 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | void enable_IR_x2apic(void) | |
1176 | { | |
1177 | #ifdef CONFIG_INTR_REMAP | |
1178 | int ret; | |
1179 | unsigned long flags; | |
1180 | ||
1181 | if (!cpu_has_x2apic) | |
1182 | return; | |
1183 | ||
1184 | if (!x2apic_preenabled && disable_x2apic) { | |
1185 | printk(KERN_INFO | |
1186 | "Skipped enabling x2apic and Interrupt-remapping " | |
1187 | "because of nox2apic\n"); | |
1188 | return; | |
1189 | } | |
1190 | ||
1191 | if (x2apic_preenabled && disable_x2apic) | |
1192 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1193 | ||
1194 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1195 | printk(KERN_INFO | |
1196 | "Skipped enabling x2apic and Interrupt-remapping " | |
1197 | "because of skipping io-apic setup\n"); | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | ret = dmar_table_init(); | |
1202 | if (ret) { | |
1203 | printk(KERN_INFO | |
1204 | "dmar_table_init() failed with %d:\n", ret); | |
1205 | ||
1206 | if (x2apic_preenabled) | |
1207 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1208 | else | |
1209 | printk(KERN_INFO | |
1210 | "Not enabling x2apic,Intr-remapping\n"); | |
1211 | return; | |
1212 | } | |
1213 | ||
1214 | local_irq_save(flags); | |
1215 | mask_8259A(); | |
1216 | save_mask_IO_APIC_setup(); | |
1217 | ||
1218 | ret = enable_intr_remapping(1); | |
1219 | ||
1220 | if (ret && x2apic_preenabled) { | |
1221 | local_irq_restore(flags); | |
1222 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1223 | } | |
1224 | ||
1225 | if (ret) | |
1226 | goto end; | |
1227 | ||
1228 | if (!x2apic) { | |
1229 | x2apic = 1; | |
1230 | apic_ops = &x2apic_ops; | |
1231 | enable_x2apic(); | |
1232 | } | |
1233 | end: | |
1234 | if (ret) | |
1235 | /* | |
1236 | * IR enabling failed | |
1237 | */ | |
1238 | restore_IO_APIC_setup(); | |
1239 | else | |
1240 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1241 | ||
1242 | unmask_8259A(); | |
1243 | local_irq_restore(flags); | |
1244 | ||
1245 | if (!ret) { | |
1246 | if (!x2apic_preenabled) | |
1247 | printk(KERN_INFO | |
1248 | "Enabled x2apic and interrupt-remapping\n"); | |
1249 | else | |
1250 | printk(KERN_INFO | |
1251 | "Enabled Interrupt-remapping\n"); | |
1252 | } else | |
1253 | printk(KERN_ERR | |
1254 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1255 | #else | |
1256 | if (!cpu_has_x2apic) | |
1257 | return; | |
1258 | ||
1259 | if (x2apic_preenabled) | |
1260 | panic("x2apic enabled prior OS handover," | |
1261 | " enable CONFIG_INTR_REMAP"); | |
1262 | ||
1263 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1264 | " and x2apic\n"); | |
1265 | #endif | |
1266 | ||
1267 | return; | |
1268 | } | |
49899eac | 1269 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1270 | |
be7a656f | 1271 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1272 | /* |
1273 | * Detect and enable local APICs on non-SMP boards. | |
1274 | * Original code written by Keir Fraser. | |
1275 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1276 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1277 | */ |
0e078e2f | 1278 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1279 | { |
1280 | if (!cpu_has_apic) { | |
1281 | printk(KERN_INFO "No local APIC present\n"); | |
1282 | return -1; | |
1283 | } | |
1284 | ||
1285 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1286 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1287 | return 0; |
1288 | } | |
be7a656f YL |
1289 | #else |
1290 | /* | |
1291 | * Detect and initialize APIC | |
1292 | */ | |
1293 | static int __init detect_init_APIC(void) | |
1294 | { | |
1295 | u32 h, l, features; | |
1296 | ||
1297 | /* Disabled by kernel option? */ | |
1298 | if (disable_apic) | |
1299 | return -1; | |
1300 | ||
1301 | switch (boot_cpu_data.x86_vendor) { | |
1302 | case X86_VENDOR_AMD: | |
1303 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1304 | (boot_cpu_data.x86 == 15)) | |
1305 | break; | |
1306 | goto no_apic; | |
1307 | case X86_VENDOR_INTEL: | |
1308 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1309 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1310 | break; | |
1311 | goto no_apic; | |
1312 | default: | |
1313 | goto no_apic; | |
1314 | } | |
1315 | ||
1316 | if (!cpu_has_apic) { | |
1317 | /* | |
1318 | * Over-ride BIOS and try to enable the local APIC only if | |
1319 | * "lapic" specified. | |
1320 | */ | |
1321 | if (!force_enable_local_apic) { | |
1322 | printk(KERN_INFO "Local APIC disabled by BIOS -- " | |
1323 | "you can enable it with \"lapic\"\n"); | |
1324 | return -1; | |
1325 | } | |
1326 | /* | |
1327 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1328 | * MSR. This can only be done in software for Intel P6 or later | |
1329 | * and AMD K7 (Model > 1) or later. | |
1330 | */ | |
1331 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1332 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1333 | printk(KERN_INFO | |
1334 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1335 | l &= ~MSR_IA32_APICBASE_BASE; | |
1336 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1337 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1338 | enabled_via_apicbase = 1; | |
1339 | } | |
1340 | } | |
1341 | /* | |
1342 | * The APIC feature bit should now be enabled | |
1343 | * in `cpuid' | |
1344 | */ | |
1345 | features = cpuid_edx(1); | |
1346 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1347 | printk(KERN_WARNING "Could not enable APIC!\n"); | |
1348 | return -1; | |
1349 | } | |
1350 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1351 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1352 | ||
1353 | /* The BIOS may have set up the APIC at some other address */ | |
1354 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1355 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1356 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1357 | ||
1358 | printk(KERN_INFO "Found and enabled local APIC!\n"); | |
1359 | ||
1360 | apic_pm_activate(); | |
1361 | ||
1362 | return 0; | |
1363 | ||
1364 | no_apic: | |
1365 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1366 | return -1; | |
1367 | } | |
1368 | #endif | |
1da177e4 | 1369 | |
f28c0ae2 | 1370 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1371 | void __init early_init_lapic_mapping(void) |
1372 | { | |
431ee79d | 1373 | unsigned long phys_addr; |
8643f9d0 YL |
1374 | |
1375 | /* | |
1376 | * If no local APIC can be found then go out | |
1377 | * : it means there is no mpatable and MADT | |
1378 | */ | |
1379 | if (!smp_found_config) | |
1380 | return; | |
1381 | ||
431ee79d | 1382 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1383 | |
431ee79d | 1384 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1385 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1386 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1387 | |
1388 | /* | |
1389 | * Fetch the APIC ID of the BSP in case we have a | |
1390 | * default configuration (or the MP table is broken). | |
1391 | */ | |
4c9961d5 | 1392 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1393 | } |
f28c0ae2 | 1394 | #endif |
8643f9d0 | 1395 | |
0e078e2f TG |
1396 | /** |
1397 | * init_apic_mappings - initialize APIC mappings | |
1398 | */ | |
1da177e4 LT |
1399 | void __init init_apic_mappings(void) |
1400 | { | |
49899eac | 1401 | #ifdef HAVE_X2APIC |
6e1cb38a | 1402 | if (x2apic) { |
4c9961d5 | 1403 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1404 | return; |
1405 | } | |
49899eac | 1406 | #endif |
6e1cb38a | 1407 | |
1da177e4 LT |
1408 | /* |
1409 | * If no local APIC can be found then set up a fake all | |
1410 | * zeroes page to simulate the local APIC and another | |
1411 | * one for the IO-APIC. | |
1412 | */ | |
1413 | if (!smp_found_config && detect_init_APIC()) { | |
1414 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1415 | apic_phys = __pa(apic_phys); | |
1416 | } else | |
1417 | apic_phys = mp_lapic_addr; | |
1418 | ||
1419 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1420 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1421 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1422 | |
1423 | /* | |
1424 | * Fetch the APIC ID of the BSP in case we have a | |
1425 | * default configuration (or the MP table is broken). | |
1426 | */ | |
f28c0ae2 YL |
1427 | if (boot_cpu_physical_apicid == -1U) |
1428 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1429 | } |
1430 | ||
1431 | /* | |
0e078e2f TG |
1432 | * This initializes the IO-APIC and APIC hardware if this is |
1433 | * a UP kernel. | |
1da177e4 | 1434 | */ |
1b313f4a CG |
1435 | int apic_version[MAX_APICS]; |
1436 | ||
0e078e2f | 1437 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1438 | { |
fa2bd35a | 1439 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1440 | if (disable_apic) { |
1441 | printk(KERN_INFO "Apic disabled\n"); | |
1442 | return -1; | |
1443 | } | |
1444 | if (!cpu_has_apic) { | |
1445 | disable_apic = 1; | |
1446 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1447 | return -1; | |
1448 | } | |
fa2bd35a YL |
1449 | #else |
1450 | if (!smp_found_config && !cpu_has_apic) | |
1451 | return -1; | |
1452 | ||
1453 | /* | |
1454 | * Complain if the BIOS pretends there is one. | |
1455 | */ | |
1456 | if (!cpu_has_apic && | |
1457 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
1458 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1459 | boot_cpu_physical_apicid); | |
1460 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1461 | return -1; | |
1462 | } | |
1463 | #endif | |
1464 | ||
49899eac | 1465 | #ifdef HAVE_X2APIC |
6e1cb38a | 1466 | enable_IR_x2apic(); |
49899eac | 1467 | #endif |
fa2bd35a | 1468 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1469 | setup_apic_routing(); |
fa2bd35a | 1470 | #endif |
6e1cb38a | 1471 | |
0e078e2f | 1472 | verify_local_APIC(); |
b5841765 GC |
1473 | connect_bsp_APIC(); |
1474 | ||
fa2bd35a | 1475 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1476 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1477 | #else |
1478 | /* | |
1479 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1480 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1481 | * might be zero if read from MP tables. Get it from LAPIC. | |
1482 | */ | |
1483 | # ifdef CONFIG_CRASH_DUMP | |
1484 | boot_cpu_physical_apicid = read_apic_id(); | |
1485 | # endif | |
1486 | #endif | |
1487 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1488 | setup_local_APIC(); |
1da177e4 | 1489 | |
fa2bd35a | 1490 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1491 | /* |
1492 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1493 | * We need clear_IO_APIC before enabling vector on BP | |
1494 | */ | |
1495 | if (!skip_ioapic_setup && nr_ioapics) | |
1496 | enable_IO_APIC(); | |
fa2bd35a | 1497 | #endif |
739f33b3 | 1498 | |
fa2bd35a | 1499 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1500 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1501 | #endif |
acae7d90 | 1502 | localise_nmi_watchdog(); |
739f33b3 AK |
1503 | end_local_APIC_setup(); |
1504 | ||
fa2bd35a | 1505 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1506 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1507 | setup_IO_APIC(); | |
fa2bd35a | 1508 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1509 | else |
1510 | nr_ioapics = 0; | |
fa2bd35a YL |
1511 | # endif |
1512 | #endif | |
1513 | ||
1514 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1515 | setup_boot_APIC_clock(); |
1516 | check_nmi_watchdog(); | |
fa2bd35a YL |
1517 | #else |
1518 | setup_boot_clock(); | |
1519 | #endif | |
1520 | ||
0e078e2f | 1521 | return 0; |
1da177e4 LT |
1522 | } |
1523 | ||
1524 | /* | |
0e078e2f | 1525 | * Local APIC interrupts |
1da177e4 LT |
1526 | */ |
1527 | ||
0e078e2f TG |
1528 | /* |
1529 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1530 | */ | |
dc1528dd | 1531 | #ifdef CONFIG_X86_64 |
0e078e2f | 1532 | asmlinkage void smp_spurious_interrupt(void) |
dc1528dd YL |
1533 | #else |
1534 | void smp_spurious_interrupt(struct pt_regs *regs) | |
1535 | #endif | |
1da177e4 | 1536 | { |
dc1528dd YL |
1537 | u32 v; |
1538 | ||
1539 | #ifdef CONFIG_X86_64 | |
0e078e2f | 1540 | exit_idle(); |
dc1528dd | 1541 | #endif |
0e078e2f | 1542 | irq_enter(); |
1da177e4 | 1543 | /* |
0e078e2f TG |
1544 | * Check if this really is a spurious interrupt and ACK it |
1545 | * if it is a vectored one. Just in case... | |
1546 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1547 | */ |
0e078e2f TG |
1548 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1549 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1550 | ack_APIC_irq(); | |
c4d58cbd | 1551 | |
dc1528dd | 1552 | #ifdef CONFIG_X86_64 |
0e078e2f | 1553 | add_pda(irq_spurious_count, 1); |
dc1528dd YL |
1554 | #else |
1555 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1556 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " | |
1557 | "should never happen.\n", smp_processor_id()); | |
1558 | __get_cpu_var(irq_stat).irq_spurious_count++; | |
1559 | #endif | |
0e078e2f TG |
1560 | irq_exit(); |
1561 | } | |
1da177e4 | 1562 | |
0e078e2f TG |
1563 | /* |
1564 | * This interrupt should never happen with our APIC/SMP architecture | |
1565 | */ | |
dc1528dd | 1566 | #ifdef CONFIG_X86_64 |
0e078e2f | 1567 | asmlinkage void smp_error_interrupt(void) |
dc1528dd YL |
1568 | #else |
1569 | void smp_error_interrupt(struct pt_regs *regs) | |
1570 | #endif | |
0e078e2f | 1571 | { |
dc1528dd | 1572 | u32 v, v1; |
1da177e4 | 1573 | |
dc1528dd | 1574 | #ifdef CONFIG_X86_64 |
0e078e2f | 1575 | exit_idle(); |
dc1528dd | 1576 | #endif |
0e078e2f TG |
1577 | irq_enter(); |
1578 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1579 | v = apic_read(APIC_ESR); | |
1580 | apic_write(APIC_ESR, 0); | |
1581 | v1 = apic_read(APIC_ESR); | |
1582 | ack_APIC_irq(); | |
1583 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1584 | |
0e078e2f TG |
1585 | /* Here is what the APIC error bits mean: |
1586 | 0: Send CS error | |
1587 | 1: Receive CS error | |
1588 | 2: Send accept error | |
1589 | 3: Receive accept error | |
1590 | 4: Reserved | |
1591 | 5: Send illegal vector | |
1592 | 6: Received illegal vector | |
1593 | 7: Illegal register address | |
1594 | */ | |
1595 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1596 | smp_processor_id(), v , v1); | |
1597 | irq_exit(); | |
1da177e4 LT |
1598 | } |
1599 | ||
b5841765 | 1600 | /** |
36c9d674 CG |
1601 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1602 | */ | |
b5841765 GC |
1603 | void __init connect_bsp_APIC(void) |
1604 | { | |
36c9d674 CG |
1605 | #ifdef CONFIG_X86_32 |
1606 | if (pic_mode) { | |
1607 | /* | |
1608 | * Do not trust the local APIC being empty at bootup. | |
1609 | */ | |
1610 | clear_local_APIC(); | |
1611 | /* | |
1612 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1613 | * local APIC to INT and NMI lines. | |
1614 | */ | |
1615 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1616 | "enabling APIC mode.\n"); | |
1617 | outb(0x70, 0x22); | |
1618 | outb(0x01, 0x23); | |
1619 | } | |
1620 | #endif | |
b5841765 GC |
1621 | enable_apic_mode(); |
1622 | } | |
1623 | ||
274cfe59 CG |
1624 | /** |
1625 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1626 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1627 | * | |
1628 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1629 | * APIC is disabled. | |
1630 | */ | |
0e078e2f | 1631 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1632 | { |
1b4ee4e4 CG |
1633 | unsigned int value; |
1634 | ||
c177b0bc CG |
1635 | #ifdef CONFIG_X86_32 |
1636 | if (pic_mode) { | |
1637 | /* | |
1638 | * Put the board back into PIC mode (has an effect only on | |
1639 | * certain older boards). Note that APIC interrupts, including | |
1640 | * IPIs, won't work beyond this point! The only exception are | |
1641 | * INIT IPIs. | |
1642 | */ | |
1643 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1644 | "entering PIC mode.\n"); | |
1645 | outb(0x70, 0x22); | |
1646 | outb(0x00, 0x23); | |
1647 | return; | |
1648 | } | |
1649 | #endif | |
1650 | ||
0e078e2f | 1651 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1652 | |
0e078e2f TG |
1653 | /* For the spurious interrupt use vector F, and enable it */ |
1654 | value = apic_read(APIC_SPIV); | |
1655 | value &= ~APIC_VECTOR_MASK; | |
1656 | value |= APIC_SPIV_APIC_ENABLED; | |
1657 | value |= 0xf; | |
1658 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1659 | |
0e078e2f TG |
1660 | if (!virt_wire_setup) { |
1661 | /* | |
1662 | * For LVT0 make it edge triggered, active high, | |
1663 | * external and enabled | |
1664 | */ | |
1665 | value = apic_read(APIC_LVT0); | |
1666 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1667 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1668 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1669 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1670 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1671 | apic_write(APIC_LVT0, value); | |
1672 | } else { | |
1673 | /* Disable LVT0 */ | |
1674 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1675 | } | |
b8ce3359 | 1676 | |
c177b0bc CG |
1677 | /* |
1678 | * For LVT1 make it edge triggered, active high, | |
1679 | * nmi and enabled | |
1680 | */ | |
0e078e2f TG |
1681 | value = apic_read(APIC_LVT1); |
1682 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1683 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1684 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1685 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1686 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1687 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1688 | } |
1689 | ||
be8a5685 AS |
1690 | void __cpuinit generic_processor_info(int apicid, int version) |
1691 | { | |
1692 | int cpu; | |
1693 | cpumask_t tmp_map; | |
1694 | ||
1b313f4a CG |
1695 | /* |
1696 | * Validate version | |
1697 | */ | |
1698 | if (version == 0x0) { | |
1699 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1700 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1701 | version); | |
1702 | version = 0x10; | |
be8a5685 | 1703 | } |
1b313f4a | 1704 | apic_version[apicid] = version; |
be8a5685 | 1705 | |
be8a5685 AS |
1706 | if (num_processors >= NR_CPUS) { |
1707 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1708 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1709 | return; |
1710 | } | |
1711 | ||
1712 | num_processors++; | |
1713 | cpus_complement(tmp_map, cpu_present_map); | |
1714 | cpu = first_cpu(tmp_map); | |
1715 | ||
1716 | physid_set(apicid, phys_cpu_present_map); | |
1717 | if (apicid == boot_cpu_physical_apicid) { | |
1718 | /* | |
1719 | * x86_bios_cpu_apicid is required to have processors listed | |
1720 | * in same order as logical cpu numbers. Hence the first | |
1721 | * entry is BSP, and so on. | |
1722 | */ | |
1723 | cpu = 0; | |
1724 | } | |
e0da3364 YL |
1725 | if (apicid > max_physical_apicid) |
1726 | max_physical_apicid = apicid; | |
1727 | ||
1b313f4a CG |
1728 | #ifdef CONFIG_X86_32 |
1729 | /* | |
1730 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1731 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1732 | * before this can be done without some confusion. | |
1733 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1734 | * - Ashok Raj <ashok.raj@intel.com> | |
1735 | */ | |
1736 | if (max_physical_apicid >= 8) { | |
1737 | switch (boot_cpu_data.x86_vendor) { | |
1738 | case X86_VENDOR_INTEL: | |
1739 | if (!APIC_XAPIC(version)) { | |
1740 | def_to_bigsmp = 0; | |
1741 | break; | |
1742 | } | |
1743 | /* If P4 and above fall through */ | |
1744 | case X86_VENDOR_AMD: | |
1745 | def_to_bigsmp = 1; | |
1746 | } | |
1747 | } | |
1748 | #endif | |
1749 | ||
1750 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1751 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1752 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1753 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1754 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1755 | |
1756 | cpu_to_apicid[cpu] = apicid; | |
1757 | bios_cpu_apicid[cpu] = apicid; | |
1758 | } else { | |
1759 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1760 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1761 | } | |
1b313f4a | 1762 | #endif |
be8a5685 AS |
1763 | |
1764 | cpu_set(cpu, cpu_possible_map); | |
1765 | cpu_set(cpu, cpu_present_map); | |
1766 | } | |
1767 | ||
3491998d | 1768 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1769 | int hard_smp_processor_id(void) |
1770 | { | |
1771 | return read_apic_id(); | |
1772 | } | |
3491998d | 1773 | #endif |
0c81c746 | 1774 | |
89039b37 | 1775 | /* |
0e078e2f | 1776 | * Power management |
89039b37 | 1777 | */ |
0e078e2f TG |
1778 | #ifdef CONFIG_PM |
1779 | ||
1780 | static struct { | |
274cfe59 CG |
1781 | /* |
1782 | * 'active' is true if the local APIC was enabled by us and | |
1783 | * not the BIOS; this signifies that we are also responsible | |
1784 | * for disabling it before entering apm/acpi suspend | |
1785 | */ | |
0e078e2f TG |
1786 | int active; |
1787 | /* r/w apic fields */ | |
1788 | unsigned int apic_id; | |
1789 | unsigned int apic_taskpri; | |
1790 | unsigned int apic_ldr; | |
1791 | unsigned int apic_dfr; | |
1792 | unsigned int apic_spiv; | |
1793 | unsigned int apic_lvtt; | |
1794 | unsigned int apic_lvtpc; | |
1795 | unsigned int apic_lvt0; | |
1796 | unsigned int apic_lvt1; | |
1797 | unsigned int apic_lvterr; | |
1798 | unsigned int apic_tmict; | |
1799 | unsigned int apic_tdcr; | |
1800 | unsigned int apic_thmr; | |
1801 | } apic_pm_state; | |
1802 | ||
1803 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1804 | { | |
1805 | unsigned long flags; | |
1806 | int maxlvt; | |
89039b37 | 1807 | |
0e078e2f TG |
1808 | if (!apic_pm_state.active) |
1809 | return 0; | |
89039b37 | 1810 | |
0e078e2f | 1811 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1812 | |
2d7a66d0 | 1813 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1814 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1815 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1816 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1817 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1818 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1819 | if (maxlvt >= 4) | |
1820 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1821 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1822 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1823 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1824 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1825 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1826 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1827 | if (maxlvt >= 5) |
1828 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1829 | #endif | |
24968cfd | 1830 | |
0e078e2f TG |
1831 | local_irq_save(flags); |
1832 | disable_local_APIC(); | |
1833 | local_irq_restore(flags); | |
1834 | return 0; | |
1da177e4 LT |
1835 | } |
1836 | ||
0e078e2f | 1837 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1838 | { |
0e078e2f TG |
1839 | unsigned int l, h; |
1840 | unsigned long flags; | |
1841 | int maxlvt; | |
1da177e4 | 1842 | |
0e078e2f TG |
1843 | if (!apic_pm_state.active) |
1844 | return 0; | |
89b831ef | 1845 | |
0e078e2f | 1846 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1847 | |
0e078e2f | 1848 | local_irq_save(flags); |
92206c90 | 1849 | |
49899eac | 1850 | #ifdef HAVE_X2APIC |
92206c90 CG |
1851 | if (x2apic) |
1852 | enable_x2apic(); | |
1853 | else | |
1854 | #endif | |
d5e629a6 | 1855 | { |
92206c90 CG |
1856 | /* |
1857 | * Make sure the APICBASE points to the right address | |
1858 | * | |
1859 | * FIXME! This will be wrong if we ever support suspend on | |
1860 | * SMP! We'll need to do this as part of the CPU restore! | |
1861 | */ | |
6e1cb38a SS |
1862 | rdmsr(MSR_IA32_APICBASE, l, h); |
1863 | l &= ~MSR_IA32_APICBASE_BASE; | |
1864 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1865 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1866 | } |
6e1cb38a | 1867 | |
0e078e2f TG |
1868 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1869 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1870 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1871 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1872 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1873 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1874 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1875 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1876 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1877 | if (maxlvt >= 5) |
1878 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1879 | #endif | |
1880 | if (maxlvt >= 4) | |
1881 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1882 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1883 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1884 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1885 | apic_write(APIC_ESR, 0); | |
1886 | apic_read(APIC_ESR); | |
1887 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1888 | apic_write(APIC_ESR, 0); | |
1889 | apic_read(APIC_ESR); | |
92206c90 | 1890 | |
0e078e2f | 1891 | local_irq_restore(flags); |
92206c90 | 1892 | |
0e078e2f TG |
1893 | return 0; |
1894 | } | |
b8ce3359 | 1895 | |
274cfe59 CG |
1896 | /* |
1897 | * This device has no shutdown method - fully functioning local APICs | |
1898 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1899 | */ | |
1900 | ||
0e078e2f TG |
1901 | static struct sysdev_class lapic_sysclass = { |
1902 | .name = "lapic", | |
1903 | .resume = lapic_resume, | |
1904 | .suspend = lapic_suspend, | |
1905 | }; | |
b8ce3359 | 1906 | |
0e078e2f | 1907 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1908 | .id = 0, |
1909 | .cls = &lapic_sysclass, | |
0e078e2f | 1910 | }; |
b8ce3359 | 1911 | |
0e078e2f TG |
1912 | static void __cpuinit apic_pm_activate(void) |
1913 | { | |
1914 | apic_pm_state.active = 1; | |
1da177e4 LT |
1915 | } |
1916 | ||
0e078e2f | 1917 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1918 | { |
0e078e2f | 1919 | int error; |
e83a5fdc | 1920 | |
0e078e2f TG |
1921 | if (!cpu_has_apic) |
1922 | return 0; | |
1923 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1924 | |
0e078e2f TG |
1925 | error = sysdev_class_register(&lapic_sysclass); |
1926 | if (!error) | |
1927 | error = sysdev_register(&device_lapic); | |
1928 | return error; | |
1da177e4 | 1929 | } |
0e078e2f TG |
1930 | device_initcall(init_lapic_sysfs); |
1931 | ||
1932 | #else /* CONFIG_PM */ | |
1933 | ||
1934 | static void apic_pm_activate(void) { } | |
1935 | ||
1936 | #endif /* CONFIG_PM */ | |
1da177e4 | 1937 | |
f28c0ae2 | 1938 | #ifdef CONFIG_X86_64 |
1da177e4 | 1939 | /* |
f8bf3c65 | 1940 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1941 | * |
1942 | * Thus far, the major user of this is IBM's Summit2 series: | |
1943 | * | |
637029c6 | 1944 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1945 | * multi-chassis. Use available data to take a good guess. |
1946 | * If in doubt, go HPET. | |
1947 | */ | |
f8bf3c65 | 1948 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1949 | { |
1950 | int i, clusters, zeros; | |
1951 | unsigned id; | |
322850af | 1952 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1953 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1954 | ||
322850af YL |
1955 | /* |
1956 | * there is not this kind of box with AMD CPU yet. | |
1957 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1958 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1959 | * vsmp box still need checking... |
322850af | 1960 | */ |
1cb68487 | 1961 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1962 | return 0; |
1963 | ||
23ca4bba | 1964 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1965 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1966 | |
1967 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1968 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1969 | if (bios_cpu_apicid) { |
1970 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1971 | } |
1972 | else if (i < nr_cpu_ids) { | |
1973 | if (cpu_present(i)) | |
1974 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1975 | else | |
1976 | continue; | |
1977 | } | |
1978 | else | |
1979 | break; | |
1980 | ||
1da177e4 LT |
1981 | if (id != BAD_APICID) |
1982 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1983 | } | |
1984 | ||
1985 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1986 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1987 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1988 | * Since clusters are allocated sequentially, count zeros only if | |
1989 | * they are bounded by ones. | |
1da177e4 LT |
1990 | */ |
1991 | clusters = 0; | |
1992 | zeros = 0; | |
1993 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1994 | if (test_bit(i, clustermap)) { | |
1995 | clusters += 1 + zeros; | |
1996 | zeros = 0; | |
1997 | } else | |
1998 | ++zeros; | |
1999 | } | |
2000 | ||
1cb68487 RT |
2001 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2002 | * not guaranteed to be synced between boards | |
2003 | */ | |
2004 | if (is_vsmp_box() && clusters > 1) | |
2005 | return 1; | |
2006 | ||
1da177e4 | 2007 | /* |
f8bf3c65 | 2008 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2009 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2010 | * out, but AFAIK this will work even for them. | |
2011 | */ | |
2012 | return (clusters > 2); | |
2013 | } | |
f28c0ae2 | 2014 | #endif |
1da177e4 LT |
2015 | |
2016 | /* | |
0e078e2f | 2017 | * APIC command line parameters |
1da177e4 | 2018 | */ |
789fa735 | 2019 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2020 | { |
1da177e4 | 2021 | disable_apic = 1; |
9175fc06 | 2022 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2023 | return 0; |
2024 | } | |
2025 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2026 | |
2c8c0e6b | 2027 | /* same as disableapic, for compatibility */ |
789fa735 | 2028 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2029 | { |
789fa735 | 2030 | return setup_disableapic(arg); |
6935d1f9 | 2031 | } |
2c8c0e6b | 2032 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2033 | |
2e7c2838 LT |
2034 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2035 | { | |
2036 | local_apic_timer_c2_ok = 1; | |
2037 | return 0; | |
2038 | } | |
2039 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2040 | ||
36fef094 | 2041 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2042 | { |
1da177e4 | 2043 | disable_apic_timer = 1; |
36fef094 | 2044 | return 0; |
6935d1f9 | 2045 | } |
36fef094 CG |
2046 | early_param("noapictimer", parse_disable_apic_timer); |
2047 | ||
2048 | static int __init parse_nolapic_timer(char *arg) | |
2049 | { | |
2050 | disable_apic_timer = 1; | |
2051 | return 0; | |
6935d1f9 | 2052 | } |
36fef094 | 2053 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2054 | |
79af9bec CG |
2055 | static int __init apic_set_verbosity(char *arg) |
2056 | { | |
2057 | if (!arg) { | |
2058 | #ifdef CONFIG_X86_64 | |
2059 | skip_ioapic_setup = 0; | |
79af9bec CG |
2060 | return 0; |
2061 | #endif | |
2062 | return -EINVAL; | |
2063 | } | |
2064 | ||
2065 | if (strcmp("debug", arg) == 0) | |
2066 | apic_verbosity = APIC_DEBUG; | |
2067 | else if (strcmp("verbose", arg) == 0) | |
2068 | apic_verbosity = APIC_VERBOSE; | |
2069 | else { | |
2070 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
2071 | " use apic=verbose or apic=debug\n", arg); | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | return 0; | |
2076 | } | |
2077 | early_param("apic", apic_set_verbosity); | |
2078 | ||
1e934dda YL |
2079 | static int __init lapic_insert_resource(void) |
2080 | { | |
2081 | if (!apic_phys) | |
2082 | return -1; | |
2083 | ||
2084 | /* Put local APIC into the resource map. */ | |
2085 | lapic_resource.start = apic_phys; | |
2086 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2087 | insert_resource(&iomem_resource, &lapic_resource); | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
2092 | /* | |
2093 | * need call insert after e820_reserve_resources() | |
2094 | * that is using request_resource | |
2095 | */ | |
2096 | late_initcall(lapic_insert_resource); |