Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
d25bf7e5 | 26 | #include <linux/module.h> |
39928722 | 27 | #include <linux/ioport.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
35 | #include <asm/pgalloc.h> | |
36 | #include <asm/mach_apic.h> | |
75152114 | 37 | #include <asm/nmi.h> |
95833c83 | 38 | #include <asm/idle.h> |
73dea47f AK |
39 | #include <asm/proto.h> |
40 | #include <asm/timex.h> | |
2d0c87c3 | 41 | #include <asm/hpet.h> |
2c8c0e6b | 42 | #include <asm/apic.h> |
1da177e4 LT |
43 | |
44 | int apic_verbosity; | |
fb79d22e | 45 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 46 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 47 | int disable_apic; |
1da177e4 | 48 | |
2e7c2838 LT |
49 | /* Local APIC timer works in C2? */ |
50 | int local_apic_timer_c2_ok; | |
51 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
52 | ||
39928722 AD |
53 | static struct resource lapic_resource = { |
54 | .name = "Local APIC", | |
55 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
56 | }; | |
57 | ||
d03030e9 TG |
58 | static unsigned int calibration_result; |
59 | ||
ba7eda4c TG |
60 | static int lapic_next_event(unsigned long delta, |
61 | struct clock_event_device *evt); | |
62 | static void lapic_timer_setup(enum clock_event_mode mode, | |
63 | struct clock_event_device *evt); | |
ba7eda4c | 64 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 65 | static void apic_pm_activate(void); |
ba7eda4c TG |
66 | |
67 | static struct clock_event_device lapic_clockevent = { | |
68 | .name = "lapic", | |
69 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
70 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
71 | .shift = 32, | |
72 | .set_mode = lapic_timer_setup, | |
73 | .set_next_event = lapic_next_event, | |
74 | .broadcast = lapic_timer_broadcast, | |
75 | .rating = 100, | |
76 | .irq = -1, | |
77 | }; | |
78 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
79 | ||
0e078e2f TG |
80 | /* |
81 | * Get the LAPIC version | |
82 | */ | |
83 | static inline int lapic_get_version(void) | |
ba7eda4c | 84 | { |
0e078e2f | 85 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
86 | } |
87 | ||
0e078e2f TG |
88 | /* |
89 | * Check, if the APIC is integrated or a seperate chip | |
90 | */ | |
91 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 92 | { |
0e078e2f | 93 | return 1; |
ba7eda4c TG |
94 | } |
95 | ||
96 | /* | |
0e078e2f | 97 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 98 | */ |
0e078e2f | 99 | static int modern_apic(void) |
ba7eda4c | 100 | { |
0e078e2f TG |
101 | /* AMD systems use old APIC versions, so check the CPU */ |
102 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
103 | boot_cpu_data.x86 >= 0xf) | |
104 | return 1; | |
105 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
106 | } |
107 | ||
8339e9fb FLV |
108 | void apic_wait_icr_idle(void) |
109 | { | |
110 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
111 | cpu_relax(); | |
112 | } | |
113 | ||
3c6bb07a | 114 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 115 | { |
3c6bb07a | 116 | u32 send_status; |
8339e9fb FLV |
117 | int timeout; |
118 | ||
119 | timeout = 0; | |
120 | do { | |
121 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
122 | if (!send_status) | |
123 | break; | |
124 | udelay(100); | |
125 | } while (timeout++ < 1000); | |
126 | ||
127 | return send_status; | |
128 | } | |
129 | ||
0e078e2f TG |
130 | /** |
131 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
132 | */ | |
e9427101 | 133 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 134 | { |
11a8e778 | 135 | unsigned int v; |
6935d1f9 TG |
136 | |
137 | /* unmask and set to NMI */ | |
138 | v = APIC_DM_NMI; | |
11a8e778 | 139 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
140 | } |
141 | ||
0e078e2f TG |
142 | /** |
143 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
144 | */ | |
37e650c7 | 145 | int lapic_get_maxlvt(void) |
1da177e4 | 146 | { |
11a8e778 | 147 | unsigned int v, maxlvt; |
1da177e4 LT |
148 | |
149 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
150 | maxlvt = GET_APIC_MAXLVT(v); |
151 | return maxlvt; | |
152 | } | |
153 | ||
0e078e2f TG |
154 | /* |
155 | * This function sets up the local APIC timer, with a timeout of | |
156 | * 'clocks' APIC bus clock. During calibration we actually call | |
157 | * this function twice on the boot CPU, once with a bogus timeout | |
158 | * value, second time for real. The other (noncalibrating) CPUs | |
159 | * call this function only once, with the real, calibrated value. | |
160 | * | |
161 | * We do reads before writes even if unnecessary, to get around the | |
162 | * P5 APIC double write bug. | |
163 | */ | |
164 | ||
165 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 166 | { |
0e078e2f | 167 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 168 | |
0e078e2f TG |
169 | lvtt_value = LOCAL_TIMER_VECTOR; |
170 | if (!oneshot) | |
171 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
172 | if (!irqen) | |
173 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 174 | |
0e078e2f | 175 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
176 | |
177 | /* | |
0e078e2f | 178 | * Divide PICLK by 16 |
1da177e4 | 179 | */ |
0e078e2f TG |
180 | tmp_value = apic_read(APIC_TDCR); |
181 | apic_write(APIC_TDCR, (tmp_value | |
182 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
183 | | APIC_TDR_DIV_16); | |
184 | ||
185 | if (!oneshot) | |
186 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
187 | } |
188 | ||
0e078e2f | 189 | /* |
7b83dae7 RR |
190 | * Setup extended LVT, AMD specific (K8, family 10h) |
191 | * | |
192 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
193 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 194 | */ |
7b83dae7 RR |
195 | |
196 | #define APIC_EILVT_LVTOFF_MCE 0 | |
197 | #define APIC_EILVT_LVTOFF_IBS 1 | |
198 | ||
199 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 200 | { |
7b83dae7 | 201 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 202 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 203 | |
0e078e2f | 204 | apic_write(reg, v); |
1da177e4 LT |
205 | } |
206 | ||
7b83dae7 RR |
207 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
208 | { | |
209 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
210 | return APIC_EILVT_LVTOFF_MCE; | |
211 | } | |
212 | ||
213 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
214 | { | |
215 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
216 | return APIC_EILVT_LVTOFF_IBS; | |
217 | } | |
218 | ||
0e078e2f TG |
219 | /* |
220 | * Program the next event, relative to now | |
221 | */ | |
222 | static int lapic_next_event(unsigned long delta, | |
223 | struct clock_event_device *evt) | |
1da177e4 | 224 | { |
0e078e2f TG |
225 | apic_write(APIC_TMICT, delta); |
226 | return 0; | |
1da177e4 LT |
227 | } |
228 | ||
0e078e2f TG |
229 | /* |
230 | * Setup the lapic timer in periodic or oneshot mode | |
231 | */ | |
232 | static void lapic_timer_setup(enum clock_event_mode mode, | |
233 | struct clock_event_device *evt) | |
9b7711f0 HS |
234 | { |
235 | unsigned long flags; | |
0e078e2f | 236 | unsigned int v; |
9b7711f0 | 237 | |
0e078e2f TG |
238 | /* Lapic used as dummy for broadcast ? */ |
239 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
240 | return; |
241 | ||
242 | local_irq_save(flags); | |
243 | ||
0e078e2f TG |
244 | switch (mode) { |
245 | case CLOCK_EVT_MODE_PERIODIC: | |
246 | case CLOCK_EVT_MODE_ONESHOT: | |
247 | __setup_APIC_LVTT(calibration_result, | |
248 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
249 | break; | |
250 | case CLOCK_EVT_MODE_UNUSED: | |
251 | case CLOCK_EVT_MODE_SHUTDOWN: | |
252 | v = apic_read(APIC_LVTT); | |
253 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
254 | apic_write(APIC_LVTT, v); | |
255 | break; | |
256 | case CLOCK_EVT_MODE_RESUME: | |
257 | /* Nothing to do here */ | |
258 | break; | |
259 | } | |
9b7711f0 HS |
260 | |
261 | local_irq_restore(flags); | |
262 | } | |
263 | ||
1da177e4 | 264 | /* |
0e078e2f | 265 | * Local APIC timer broadcast function |
1da177e4 | 266 | */ |
0e078e2f | 267 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 268 | { |
0e078e2f TG |
269 | #ifdef CONFIG_SMP |
270 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
271 | #endif | |
272 | } | |
1da177e4 | 273 | |
0e078e2f TG |
274 | /* |
275 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
276 | * of the boot CPU and register the clock event in the framework. | |
277 | */ | |
278 | static void setup_APIC_timer(void) | |
279 | { | |
280 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 281 | |
0e078e2f TG |
282 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
283 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 284 | |
0e078e2f TG |
285 | clockevents_register_device(levt); |
286 | } | |
1da177e4 | 287 | |
0e078e2f TG |
288 | /* |
289 | * In this function we calibrate APIC bus clocks to the external | |
290 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
291 | * to calibrate, since some later bootup code depends on getting | |
292 | * the first irq? Ugh. | |
293 | * | |
294 | * We want to do the calibration only once since we | |
295 | * want to have local timer irqs syncron. CPUs connected | |
296 | * by the same APIC bus have the very same bus frequency. | |
297 | * And we want to have irqs off anyways, no accidental | |
298 | * APIC irq that way. | |
299 | */ | |
300 | ||
301 | #define TICK_COUNT 100000000 | |
302 | ||
303 | static void __init calibrate_APIC_clock(void) | |
304 | { | |
305 | unsigned apic, apic_start; | |
306 | unsigned long tsc, tsc_start; | |
307 | int result; | |
308 | ||
309 | local_irq_disable(); | |
310 | ||
311 | /* | |
312 | * Put whatever arbitrary (but long enough) timeout | |
313 | * value into the APIC clock, we just want to get the | |
314 | * counter running for calibration. | |
315 | * | |
316 | * No interrupt enable ! | |
317 | */ | |
318 | __setup_APIC_LVTT(250000000, 0, 0); | |
319 | ||
320 | apic_start = apic_read(APIC_TMCCT); | |
321 | #ifdef CONFIG_X86_PM_TIMER | |
322 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
323 | pmtimer_wait(5000); /* 5ms wait */ | |
324 | apic = apic_read(APIC_TMCCT); | |
325 | result = (apic_start - apic) * 1000L / 5; | |
326 | } else | |
327 | #endif | |
328 | { | |
329 | rdtscll(tsc_start); | |
330 | ||
331 | do { | |
332 | apic = apic_read(APIC_TMCCT); | |
333 | rdtscll(tsc); | |
334 | } while ((tsc - tsc_start) < TICK_COUNT && | |
335 | (apic_start - apic) < TICK_COUNT); | |
336 | ||
337 | result = (apic_start - apic) * 1000L * tsc_khz / | |
338 | (tsc - tsc_start); | |
339 | } | |
340 | ||
341 | local_irq_enable(); | |
342 | ||
343 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
344 | ||
345 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
346 | result / 1000 / 1000, result / 1000 % 1000); | |
347 | ||
348 | /* Calculate the scaled math multiplication factor */ | |
349 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32); | |
350 | lapic_clockevent.max_delta_ns = | |
351 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
352 | lapic_clockevent.min_delta_ns = | |
353 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
354 | ||
355 | calibration_result = result / HZ; | |
356 | } | |
357 | ||
358 | void __init setup_boot_APIC_clock(void) | |
359 | { | |
360 | /* | |
361 | * The local apic timer can be disabled via the kernel commandline. | |
362 | * Register the lapic timer as a dummy clock event source on SMP | |
363 | * systems, so the broadcast mechanism is used. On UP systems simply | |
364 | * ignore it. | |
365 | */ | |
366 | if (disable_apic_timer) { | |
367 | printk(KERN_INFO "Disabling APIC timer\n"); | |
368 | /* No broadcast on UP ! */ | |
369 | if (num_possible_cpus() > 1) | |
370 | setup_APIC_timer(); | |
371 | return; | |
372 | } | |
373 | ||
374 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
375 | calibrate_APIC_clock(); | |
376 | ||
377 | /* | |
378 | * If nmi_watchdog is set to IO_APIC, we need the | |
379 | * PIT/HPET going. Otherwise register lapic as a dummy | |
380 | * device. | |
381 | */ | |
382 | if (nmi_watchdog != NMI_IO_APIC) | |
383 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
384 | else | |
385 | printk(KERN_WARNING "APIC timer registered as dummy," | |
386 | " due to nmi_watchdog=1!\n"); | |
387 | ||
388 | setup_APIC_timer(); | |
389 | } | |
390 | ||
391 | /* | |
392 | * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the | |
393 | * C1E flag only in the secondary CPU, so when we detect the wreckage | |
394 | * we already have enabled the boot CPU local apic timer. Check, if | |
395 | * disable_apic_timer is set and the DUMMY flag is cleared. If yes, | |
396 | * set the DUMMY flag again and force the broadcast mode in the | |
397 | * clockevents layer. | |
398 | */ | |
399 | void __cpuinit check_boot_apic_timer_broadcast(void) | |
400 | { | |
401 | if (!disable_apic_timer || | |
402 | (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY)) | |
403 | return; | |
404 | ||
405 | printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n"); | |
406 | lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY; | |
407 | ||
408 | local_irq_enable(); | |
409 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id); | |
410 | local_irq_disable(); | |
411 | } | |
412 | ||
413 | void __cpuinit setup_secondary_APIC_clock(void) | |
414 | { | |
415 | check_boot_apic_timer_broadcast(); | |
416 | setup_APIC_timer(); | |
417 | } | |
418 | ||
419 | /* | |
420 | * The guts of the apic timer interrupt | |
421 | */ | |
422 | static void local_apic_timer_interrupt(void) | |
423 | { | |
424 | int cpu = smp_processor_id(); | |
425 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
426 | ||
427 | /* | |
428 | * Normally we should not be here till LAPIC has been initialized but | |
429 | * in some cases like kdump, its possible that there is a pending LAPIC | |
430 | * timer interrupt from previous kernel's context and is delivered in | |
431 | * new kernel the moment interrupts are enabled. | |
432 | * | |
433 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
434 | * its possible that when we get here evt->event_handler is NULL. | |
435 | * Check for event_handler being NULL and discard the interrupt as | |
436 | * spurious. | |
437 | */ | |
438 | if (!evt->event_handler) { | |
439 | printk(KERN_WARNING | |
440 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
441 | /* Switch it off */ | |
442 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
443 | return; | |
444 | } | |
445 | ||
446 | /* | |
447 | * the NMI deadlock-detector uses this. | |
448 | */ | |
449 | add_pda(apic_timer_irqs, 1); | |
450 | ||
451 | evt->event_handler(evt); | |
452 | } | |
453 | ||
454 | /* | |
455 | * Local APIC timer interrupt. This is the most natural way for doing | |
456 | * local interrupts, but local timer interrupts can be emulated by | |
457 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
458 | * | |
459 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
460 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
461 | */ | |
462 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
463 | { | |
464 | struct pt_regs *old_regs = set_irq_regs(regs); | |
465 | ||
466 | /* | |
467 | * NOTE! We'd better ACK the irq immediately, | |
468 | * because timer handling can be slow. | |
469 | */ | |
470 | ack_APIC_irq(); | |
471 | /* | |
472 | * update_process_times() expects us to have done irq_enter(). | |
473 | * Besides, if we don't timer interrupts ignore the global | |
474 | * interrupt lock, which is the WrongThing (tm) to do. | |
475 | */ | |
476 | exit_idle(); | |
477 | irq_enter(); | |
478 | local_apic_timer_interrupt(); | |
479 | irq_exit(); | |
480 | set_irq_regs(old_regs); | |
481 | } | |
482 | ||
483 | int setup_profiling_timer(unsigned int multiplier) | |
484 | { | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | ||
489 | /* | |
490 | * Local APIC start and shutdown | |
491 | */ | |
492 | ||
493 | /** | |
494 | * clear_local_APIC - shutdown the local APIC | |
495 | * | |
496 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
497 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
498 | * leftovers during boot. | |
499 | */ | |
500 | void clear_local_APIC(void) | |
501 | { | |
502 | int maxlvt = lapic_get_maxlvt(); | |
503 | u32 v; | |
504 | ||
505 | /* | |
506 | * Masking an LVT entry can trigger a local APIC error | |
507 | * if the vector is zero. Mask LVTERR first to prevent this. | |
508 | */ | |
509 | if (maxlvt >= 3) { | |
510 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
511 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
512 | } | |
513 | /* | |
514 | * Careful: we have to set masks only first to deassert | |
515 | * any level-triggered sources. | |
516 | */ | |
517 | v = apic_read(APIC_LVTT); | |
518 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
519 | v = apic_read(APIC_LVT0); | |
520 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
521 | v = apic_read(APIC_LVT1); | |
522 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
523 | if (maxlvt >= 4) { | |
524 | v = apic_read(APIC_LVTPC); | |
525 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
526 | } | |
527 | ||
528 | /* | |
529 | * Clean APIC state for other OSs: | |
530 | */ | |
531 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
532 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
533 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
534 | if (maxlvt >= 3) | |
535 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
536 | if (maxlvt >= 4) | |
537 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
538 | apic_write(APIC_ESR, 0); | |
539 | apic_read(APIC_ESR); | |
540 | } | |
541 | ||
542 | /** | |
543 | * disable_local_APIC - clear and disable the local APIC | |
544 | */ | |
545 | void disable_local_APIC(void) | |
546 | { | |
547 | unsigned int value; | |
548 | ||
549 | clear_local_APIC(); | |
550 | ||
551 | /* | |
552 | * Disable APIC (implies clearing of registers | |
553 | * for 82489DX!). | |
554 | */ | |
555 | value = apic_read(APIC_SPIV); | |
556 | value &= ~APIC_SPIV_APIC_ENABLED; | |
557 | apic_write(APIC_SPIV, value); | |
558 | } | |
559 | ||
560 | void lapic_shutdown(void) | |
561 | { | |
562 | unsigned long flags; | |
563 | ||
564 | if (!cpu_has_apic) | |
565 | return; | |
566 | ||
567 | local_irq_save(flags); | |
568 | ||
569 | disable_local_APIC(); | |
570 | ||
571 | local_irq_restore(flags); | |
572 | } | |
573 | ||
574 | /* | |
575 | * This is to verify that we're looking at a real local APIC. | |
576 | * Check these against your board if the CPUs aren't getting | |
577 | * started for no apparent reason. | |
578 | */ | |
579 | int __init verify_local_APIC(void) | |
580 | { | |
581 | unsigned int reg0, reg1; | |
582 | ||
583 | /* | |
584 | * The version register is read-only in a real APIC. | |
585 | */ | |
586 | reg0 = apic_read(APIC_LVR); | |
587 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
588 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
589 | reg1 = apic_read(APIC_LVR); | |
590 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
591 | ||
592 | /* | |
593 | * The two version reads above should print the same | |
594 | * numbers. If the second one is different, then we | |
595 | * poke at a non-APIC. | |
596 | */ | |
597 | if (reg1 != reg0) | |
598 | return 0; | |
599 | ||
600 | /* | |
601 | * Check if the version looks reasonably. | |
602 | */ | |
603 | reg1 = GET_APIC_VERSION(reg0); | |
604 | if (reg1 == 0x00 || reg1 == 0xff) | |
605 | return 0; | |
606 | reg1 = lapic_get_maxlvt(); | |
607 | if (reg1 < 0x02 || reg1 == 0xff) | |
608 | return 0; | |
609 | ||
610 | /* | |
611 | * The ID register is read/write in a real APIC. | |
612 | */ | |
613 | reg0 = apic_read(APIC_ID); | |
614 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
615 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
616 | reg1 = apic_read(APIC_ID); | |
617 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
618 | apic_write(APIC_ID, reg0); | |
619 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
620 | return 0; | |
621 | ||
622 | /* | |
1da177e4 LT |
623 | * The next two are just to see if we have sane values. |
624 | * They're only really relevant if we're in Virtual Wire | |
625 | * compatibility mode, but most boxes are anymore. | |
626 | */ | |
627 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 628 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
629 | reg1 = apic_read(APIC_LVT1); |
630 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
631 | ||
632 | return 1; | |
633 | } | |
634 | ||
0e078e2f TG |
635 | /** |
636 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
637 | */ | |
1da177e4 LT |
638 | void __init sync_Arb_IDs(void) |
639 | { | |
640 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 641 | if (modern_apic()) |
1da177e4 LT |
642 | return; |
643 | ||
644 | /* | |
645 | * Wait for idle. | |
646 | */ | |
647 | apic_wait_icr_idle(); | |
648 | ||
649 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 650 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
651 | | APIC_DM_INIT); |
652 | } | |
653 | ||
1da177e4 LT |
654 | /* |
655 | * An initial setup of the virtual wire mode. | |
656 | */ | |
657 | void __init init_bsp_APIC(void) | |
658 | { | |
11a8e778 | 659 | unsigned int value; |
1da177e4 LT |
660 | |
661 | /* | |
662 | * Don't do the setup now if we have a SMP BIOS as the | |
663 | * through-I/O-APIC virtual wire mode might be active. | |
664 | */ | |
665 | if (smp_found_config || !cpu_has_apic) | |
666 | return; | |
667 | ||
668 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
669 | |
670 | /* | |
671 | * Do not trust the local APIC being empty at bootup. | |
672 | */ | |
673 | clear_local_APIC(); | |
674 | ||
675 | /* | |
676 | * Enable APIC. | |
677 | */ | |
678 | value = apic_read(APIC_SPIV); | |
679 | value &= ~APIC_VECTOR_MASK; | |
680 | value |= APIC_SPIV_APIC_ENABLED; | |
681 | value |= APIC_SPIV_FOCUS_DISABLED; | |
682 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 683 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
684 | |
685 | /* | |
686 | * Set up the virtual wire mode. | |
687 | */ | |
11a8e778 | 688 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 689 | value = APIC_DM_NMI; |
11a8e778 | 690 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
691 | } |
692 | ||
0e078e2f TG |
693 | /** |
694 | * setup_local_APIC - setup the local APIC | |
695 | */ | |
696 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 697 | { |
739f33b3 | 698 | unsigned int value; |
da7ed9f9 | 699 | int i, j; |
1da177e4 | 700 | |
1da177e4 | 701 | value = apic_read(APIC_LVR); |
1da177e4 | 702 | |
fe7414a2 | 703 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
704 | |
705 | /* | |
706 | * Double-check whether this APIC is really registered. | |
707 | * This is meaningless in clustered apic mode, so we skip it. | |
708 | */ | |
709 | if (!apic_id_registered()) | |
710 | BUG(); | |
711 | ||
712 | /* | |
713 | * Intel recommends to set DFR, LDR and TPR before enabling | |
714 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
715 | * document number 292116). So here it goes... | |
716 | */ | |
717 | init_apic_ldr(); | |
718 | ||
719 | /* | |
720 | * Set Task Priority to 'accept all'. We never change this | |
721 | * later on. | |
722 | */ | |
723 | value = apic_read(APIC_TASKPRI); | |
724 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 725 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 726 | |
da7ed9f9 VG |
727 | /* |
728 | * After a crash, we no longer service the interrupts and a pending | |
729 | * interrupt from previous kernel might still have ISR bit set. | |
730 | * | |
731 | * Most probably by now CPU has serviced that pending interrupt and | |
732 | * it might not have done the ack_APIC_irq() because it thought, | |
733 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
734 | * does not clear the ISR bit and cpu thinks it has already serivced | |
735 | * the interrupt. Hence a vector might get locked. It was noticed | |
736 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
737 | */ | |
738 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
739 | value = apic_read(APIC_ISR + i*0x10); | |
740 | for (j = 31; j >= 0; j--) { | |
741 | if (value & (1<<j)) | |
742 | ack_APIC_irq(); | |
743 | } | |
744 | } | |
745 | ||
1da177e4 LT |
746 | /* |
747 | * Now that we are all set up, enable the APIC | |
748 | */ | |
749 | value = apic_read(APIC_SPIV); | |
750 | value &= ~APIC_VECTOR_MASK; | |
751 | /* | |
752 | * Enable APIC | |
753 | */ | |
754 | value |= APIC_SPIV_APIC_ENABLED; | |
755 | ||
3f14c746 AK |
756 | /* We always use processor focus */ |
757 | ||
1da177e4 LT |
758 | /* |
759 | * Set spurious IRQ vector | |
760 | */ | |
761 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 762 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
763 | |
764 | /* | |
765 | * Set up LVT0, LVT1: | |
766 | * | |
767 | * set up through-local-APIC on the BP's LINT0. This is not | |
768 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
769 | * we delegate interrupts to the 8259A. | |
770 | */ | |
771 | /* | |
772 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
773 | */ | |
774 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 775 | if (!smp_processor_id() && !value) { |
1da177e4 | 776 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
777 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
778 | smp_processor_id()); | |
1da177e4 LT |
779 | } else { |
780 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
781 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
782 | smp_processor_id()); | |
1da177e4 | 783 | } |
11a8e778 | 784 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
785 | |
786 | /* | |
787 | * only the BP should see the LINT1 NMI signal, obviously. | |
788 | */ | |
789 | if (!smp_processor_id()) | |
790 | value = APIC_DM_NMI; | |
791 | else | |
792 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 793 | apic_write(APIC_LVT1, value); |
739f33b3 | 794 | } |
1da177e4 | 795 | |
739f33b3 AK |
796 | void __cpuinit lapic_setup_esr(void) |
797 | { | |
798 | unsigned maxlvt = lapic_get_maxlvt(); | |
799 | ||
800 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 801 | /* |
739f33b3 | 802 | * spec says clear errors after enabling vector. |
1c69524c | 803 | */ |
739f33b3 AK |
804 | if (maxlvt > 3) |
805 | apic_write(APIC_ESR, 0); | |
806 | } | |
1da177e4 | 807 | |
739f33b3 AK |
808 | void __cpuinit end_local_APIC_setup(void) |
809 | { | |
810 | lapic_setup_esr(); | |
1da177e4 | 811 | nmi_watchdog_default(); |
f2802e7f | 812 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 813 | apic_pm_activate(); |
1da177e4 | 814 | } |
1da177e4 LT |
815 | |
816 | /* | |
817 | * Detect and enable local APICs on non-SMP boards. | |
818 | * Original code written by Keir Fraser. | |
819 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 820 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 821 | */ |
0e078e2f | 822 | static int __init detect_init_APIC(void) |
1da177e4 LT |
823 | { |
824 | if (!cpu_has_apic) { | |
825 | printk(KERN_INFO "No local APIC present\n"); | |
826 | return -1; | |
827 | } | |
828 | ||
829 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
830 | boot_cpu_id = 0; | |
831 | return 0; | |
832 | } | |
833 | ||
0e078e2f TG |
834 | /** |
835 | * init_apic_mappings - initialize APIC mappings | |
836 | */ | |
1da177e4 LT |
837 | void __init init_apic_mappings(void) |
838 | { | |
839 | unsigned long apic_phys; | |
840 | ||
841 | /* | |
842 | * If no local APIC can be found then set up a fake all | |
843 | * zeroes page to simulate the local APIC and another | |
844 | * one for the IO-APIC. | |
845 | */ | |
846 | if (!smp_found_config && detect_init_APIC()) { | |
847 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
848 | apic_phys = __pa(apic_phys); | |
849 | } else | |
850 | apic_phys = mp_lapic_addr; | |
851 | ||
852 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
853 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
854 | APIC_BASE, apic_phys); | |
1da177e4 | 855 | |
39928722 AD |
856 | /* Put local APIC into the resource map. */ |
857 | lapic_resource.start = apic_phys; | |
858 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
859 | insert_resource(&iomem_resource, &lapic_resource); | |
860 | ||
1da177e4 LT |
861 | /* |
862 | * Fetch the APIC ID of the BSP in case we have a | |
863 | * default configuration (or the MP table is broken). | |
864 | */ | |
1d3fbbf9 | 865 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
866 | } |
867 | ||
868 | /* | |
0e078e2f TG |
869 | * This initializes the IO-APIC and APIC hardware if this is |
870 | * a UP kernel. | |
1da177e4 | 871 | */ |
0e078e2f | 872 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 873 | { |
0e078e2f TG |
874 | if (disable_apic) { |
875 | printk(KERN_INFO "Apic disabled\n"); | |
876 | return -1; | |
877 | } | |
878 | if (!cpu_has_apic) { | |
879 | disable_apic = 1; | |
880 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
881 | return -1; | |
882 | } | |
1da177e4 | 883 | |
0e078e2f | 884 | verify_local_APIC(); |
1da177e4 | 885 | |
0e078e2f TG |
886 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id); |
887 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id)); | |
1da177e4 | 888 | |
0e078e2f | 889 | setup_local_APIC(); |
1da177e4 | 890 | |
739f33b3 AK |
891 | /* |
892 | * Now enable IO-APICs, actually call clear_IO_APIC | |
893 | * We need clear_IO_APIC before enabling vector on BP | |
894 | */ | |
895 | if (!skip_ioapic_setup && nr_ioapics) | |
896 | enable_IO_APIC(); | |
897 | ||
898 | end_local_APIC_setup(); | |
899 | ||
0e078e2f TG |
900 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
901 | setup_IO_APIC(); | |
902 | else | |
903 | nr_ioapics = 0; | |
904 | setup_boot_APIC_clock(); | |
905 | check_nmi_watchdog(); | |
906 | return 0; | |
1da177e4 LT |
907 | } |
908 | ||
909 | /* | |
0e078e2f | 910 | * Local APIC interrupts |
1da177e4 LT |
911 | */ |
912 | ||
0e078e2f TG |
913 | /* |
914 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
915 | */ | |
916 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 917 | { |
0e078e2f TG |
918 | unsigned int v; |
919 | exit_idle(); | |
920 | irq_enter(); | |
1da177e4 | 921 | /* |
0e078e2f TG |
922 | * Check if this really is a spurious interrupt and ACK it |
923 | * if it is a vectored one. Just in case... | |
924 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 925 | */ |
0e078e2f TG |
926 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
927 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
928 | ack_APIC_irq(); | |
c4d58cbd | 929 | |
0e078e2f TG |
930 | add_pda(irq_spurious_count, 1); |
931 | irq_exit(); | |
932 | } | |
1da177e4 | 933 | |
0e078e2f TG |
934 | /* |
935 | * This interrupt should never happen with our APIC/SMP architecture | |
936 | */ | |
937 | asmlinkage void smp_error_interrupt(void) | |
938 | { | |
939 | unsigned int v, v1; | |
1da177e4 | 940 | |
0e078e2f TG |
941 | exit_idle(); |
942 | irq_enter(); | |
943 | /* First tickle the hardware, only then report what went on. -- REW */ | |
944 | v = apic_read(APIC_ESR); | |
945 | apic_write(APIC_ESR, 0); | |
946 | v1 = apic_read(APIC_ESR); | |
947 | ack_APIC_irq(); | |
948 | atomic_inc(&irq_err_count); | |
ba7eda4c | 949 | |
0e078e2f TG |
950 | /* Here is what the APIC error bits mean: |
951 | 0: Send CS error | |
952 | 1: Receive CS error | |
953 | 2: Send accept error | |
954 | 3: Receive accept error | |
955 | 4: Reserved | |
956 | 5: Send illegal vector | |
957 | 6: Received illegal vector | |
958 | 7: Illegal register address | |
959 | */ | |
960 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
961 | smp_processor_id(), v , v1); | |
962 | irq_exit(); | |
1da177e4 LT |
963 | } |
964 | ||
0e078e2f | 965 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 966 | { |
0e078e2f TG |
967 | /* Go back to Virtual Wire compatibility mode */ |
968 | unsigned long value; | |
1da177e4 | 969 | |
0e078e2f TG |
970 | /* For the spurious interrupt use vector F, and enable it */ |
971 | value = apic_read(APIC_SPIV); | |
972 | value &= ~APIC_VECTOR_MASK; | |
973 | value |= APIC_SPIV_APIC_ENABLED; | |
974 | value |= 0xf; | |
975 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 976 | |
0e078e2f TG |
977 | if (!virt_wire_setup) { |
978 | /* | |
979 | * For LVT0 make it edge triggered, active high, | |
980 | * external and enabled | |
981 | */ | |
982 | value = apic_read(APIC_LVT0); | |
983 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
984 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
985 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
986 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
987 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
988 | apic_write(APIC_LVT0, value); | |
989 | } else { | |
990 | /* Disable LVT0 */ | |
991 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
992 | } | |
b8ce3359 | 993 | |
0e078e2f TG |
994 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
995 | value = apic_read(APIC_LVT1); | |
996 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
997 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
998 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
999 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1000 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1001 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1002 | } |
1003 | ||
89039b37 | 1004 | /* |
0e078e2f | 1005 | * Power management |
89039b37 | 1006 | */ |
0e078e2f TG |
1007 | #ifdef CONFIG_PM |
1008 | ||
1009 | static struct { | |
1010 | /* 'active' is true if the local APIC was enabled by us and | |
1011 | not the BIOS; this signifies that we are also responsible | |
1012 | for disabling it before entering apm/acpi suspend */ | |
1013 | int active; | |
1014 | /* r/w apic fields */ | |
1015 | unsigned int apic_id; | |
1016 | unsigned int apic_taskpri; | |
1017 | unsigned int apic_ldr; | |
1018 | unsigned int apic_dfr; | |
1019 | unsigned int apic_spiv; | |
1020 | unsigned int apic_lvtt; | |
1021 | unsigned int apic_lvtpc; | |
1022 | unsigned int apic_lvt0; | |
1023 | unsigned int apic_lvt1; | |
1024 | unsigned int apic_lvterr; | |
1025 | unsigned int apic_tmict; | |
1026 | unsigned int apic_tdcr; | |
1027 | unsigned int apic_thmr; | |
1028 | } apic_pm_state; | |
1029 | ||
1030 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1031 | { | |
1032 | unsigned long flags; | |
1033 | int maxlvt; | |
89039b37 | 1034 | |
0e078e2f TG |
1035 | if (!apic_pm_state.active) |
1036 | return 0; | |
89039b37 | 1037 | |
0e078e2f | 1038 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1039 | |
0e078e2f TG |
1040 | apic_pm_state.apic_id = apic_read(APIC_ID); |
1041 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1042 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1043 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1044 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1045 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1046 | if (maxlvt >= 4) | |
1047 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1048 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1049 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1050 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1051 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1052 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1053 | #ifdef CONFIG_X86_MCE_INTEL | |
1054 | if (maxlvt >= 5) | |
1055 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1056 | #endif | |
1057 | local_irq_save(flags); | |
1058 | disable_local_APIC(); | |
1059 | local_irq_restore(flags); | |
1060 | return 0; | |
1da177e4 LT |
1061 | } |
1062 | ||
0e078e2f | 1063 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1064 | { |
0e078e2f TG |
1065 | unsigned int l, h; |
1066 | unsigned long flags; | |
1067 | int maxlvt; | |
1da177e4 | 1068 | |
0e078e2f TG |
1069 | if (!apic_pm_state.active) |
1070 | return 0; | |
89b831ef | 1071 | |
0e078e2f | 1072 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1073 | |
0e078e2f TG |
1074 | local_irq_save(flags); |
1075 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1076 | l &= ~MSR_IA32_APICBASE_BASE; | |
1077 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1078 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1079 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1080 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1081 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1082 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1083 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1084 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1085 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1086 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1087 | #ifdef CONFIG_X86_MCE_INTEL | |
1088 | if (maxlvt >= 5) | |
1089 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1090 | #endif | |
1091 | if (maxlvt >= 4) | |
1092 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1093 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1094 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1095 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1096 | apic_write(APIC_ESR, 0); | |
1097 | apic_read(APIC_ESR); | |
1098 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1099 | apic_write(APIC_ESR, 0); | |
1100 | apic_read(APIC_ESR); | |
1101 | local_irq_restore(flags); | |
1102 | return 0; | |
1103 | } | |
b8ce3359 | 1104 | |
0e078e2f TG |
1105 | static struct sysdev_class lapic_sysclass = { |
1106 | .name = "lapic", | |
1107 | .resume = lapic_resume, | |
1108 | .suspend = lapic_suspend, | |
1109 | }; | |
b8ce3359 | 1110 | |
0e078e2f TG |
1111 | static struct sys_device device_lapic = { |
1112 | .id = 0, | |
1113 | .cls = &lapic_sysclass, | |
1114 | }; | |
b8ce3359 | 1115 | |
0e078e2f TG |
1116 | static void __cpuinit apic_pm_activate(void) |
1117 | { | |
1118 | apic_pm_state.active = 1; | |
1da177e4 LT |
1119 | } |
1120 | ||
0e078e2f | 1121 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1122 | { |
0e078e2f TG |
1123 | int error; |
1124 | if (!cpu_has_apic) | |
1125 | return 0; | |
1126 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
1127 | error = sysdev_class_register(&lapic_sysclass); | |
1128 | if (!error) | |
1129 | error = sysdev_register(&device_lapic); | |
1130 | return error; | |
1da177e4 | 1131 | } |
0e078e2f TG |
1132 | device_initcall(init_lapic_sysfs); |
1133 | ||
1134 | #else /* CONFIG_PM */ | |
1135 | ||
1136 | static void apic_pm_activate(void) { } | |
1137 | ||
1138 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1139 | |
1140 | /* | |
f8bf3c65 | 1141 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1142 | * |
1143 | * Thus far, the major user of this is IBM's Summit2 series: | |
1144 | * | |
637029c6 | 1145 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1146 | * multi-chassis. Use available data to take a good guess. |
1147 | * If in doubt, go HPET. | |
1148 | */ | |
f8bf3c65 | 1149 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1150 | { |
1151 | int i, clusters, zeros; | |
1152 | unsigned id; | |
1153 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); | |
1154 | ||
376ec33f | 1155 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1156 | |
1157 | for (i = 0; i < NR_CPUS; i++) { | |
1158 | id = bios_cpu_apicid[i]; | |
1159 | if (id != BAD_APICID) | |
1160 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1161 | } | |
1162 | ||
1163 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1164 | * the APIC clusters they have been allocated. Only present CPUs have | |
1165 | * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since | |
1166 | * clusters are allocated sequentially, count zeros only if they are | |
1167 | * bounded by ones. | |
1168 | */ | |
1169 | clusters = 0; | |
1170 | zeros = 0; | |
1171 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1172 | if (test_bit(i, clustermap)) { | |
1173 | clusters += 1 + zeros; | |
1174 | zeros = 0; | |
1175 | } else | |
1176 | ++zeros; | |
1177 | } | |
1178 | ||
1179 | /* | |
f8bf3c65 | 1180 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1181 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1182 | * out, but AFAIK this will work even for them. | |
1183 | */ | |
1184 | return (clusters > 2); | |
1185 | } | |
1186 | ||
1187 | /* | |
0e078e2f | 1188 | * APIC command line parameters |
1da177e4 | 1189 | */ |
0e078e2f | 1190 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1191 | { |
0e078e2f TG |
1192 | if (str == NULL) { |
1193 | skip_ioapic_setup = 0; | |
1194 | ioapic_force = 1; | |
1195 | return 0; | |
1da177e4 | 1196 | } |
0e078e2f TG |
1197 | if (strcmp("debug", str) == 0) |
1198 | apic_verbosity = APIC_DEBUG; | |
1199 | else if (strcmp("verbose", str) == 0) | |
1200 | apic_verbosity = APIC_VERBOSE; | |
1201 | else { | |
1202 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1203 | " use apic=verbose or apic=debug\n", str); | |
1204 | return -EINVAL; | |
1da177e4 LT |
1205 | } |
1206 | ||
1da177e4 LT |
1207 | return 0; |
1208 | } | |
0e078e2f | 1209 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1210 | |
6935d1f9 TG |
1211 | static __init int setup_disableapic(char *str) |
1212 | { | |
1da177e4 | 1213 | disable_apic = 1; |
53756d37 | 1214 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1215 | return 0; |
1216 | } | |
1217 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1218 | |
2c8c0e6b | 1219 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1220 | static __init int setup_nolapic(char *str) |
1221 | { | |
2c8c0e6b | 1222 | return setup_disableapic(str); |
6935d1f9 | 1223 | } |
2c8c0e6b | 1224 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1225 | |
2e7c2838 LT |
1226 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1227 | { | |
1228 | local_apic_timer_c2_ok = 1; | |
1229 | return 0; | |
1230 | } | |
1231 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1232 | ||
6935d1f9 TG |
1233 | static __init int setup_noapictimer(char *str) |
1234 | { | |
73dea47f | 1235 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1236 | return 0; |
1da177e4 | 1237 | disable_apic_timer = 1; |
9b41046c | 1238 | return 1; |
6935d1f9 | 1239 | } |
9f75e9b7 | 1240 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1241 | |
0c3749c4 AK |
1242 | static __init int setup_apicpmtimer(char *s) |
1243 | { | |
1244 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1245 | notsc_setup(NULL); |
b8ce3359 | 1246 | return 0; |
0c3749c4 AK |
1247 | } |
1248 | __setup("apicpmtimer", setup_apicpmtimer); | |
1249 |