Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
efa2559f | 36 | #include <asm/desc.h> |
e83a5fdc | 37 | #include <asm/hpet.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
75152114 | 39 | #include <asm/nmi.h> |
95833c83 | 40 | #include <asm/idle.h> |
73dea47f AK |
41 | #include <asm/proto.h> |
42 | #include <asm/timex.h> | |
2c8c0e6b | 43 | #include <asm/apic.h> |
6e1cb38a | 44 | #include <asm/i8259.h> |
1da177e4 | 45 | |
5af5573e | 46 | #include <mach_ipi.h> |
dd46e3ca | 47 | #include <mach_apic.h> |
5af5573e | 48 | |
36fef094 | 49 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 50 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 51 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 52 | int disable_apic; |
6e1cb38a | 53 | int disable_x2apic; |
89027d35 | 54 | int x2apic; |
1da177e4 | 55 | |
6e1cb38a SS |
56 | /* x2apic enabled before OS handover */ |
57 | int x2apic_preenabled; | |
1da177e4 | 58 | |
e83a5fdc | 59 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
60 | int local_apic_timer_c2_ok; |
61 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
62 | ||
efa2559f YL |
63 | int first_system_vector = 0xfe; |
64 | ||
65 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
66 | ||
e83a5fdc HS |
67 | /* |
68 | * Debug level, exported for io_apic.c | |
69 | */ | |
baa13188 | 70 | unsigned int apic_verbosity; |
e83a5fdc | 71 | |
bab4b27c AS |
72 | /* Have we found an MP table */ |
73 | int smp_found_config; | |
74 | ||
39928722 AD |
75 | static struct resource lapic_resource = { |
76 | .name = "Local APIC", | |
77 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
78 | }; | |
79 | ||
d03030e9 TG |
80 | static unsigned int calibration_result; |
81 | ||
ba7eda4c TG |
82 | static int lapic_next_event(unsigned long delta, |
83 | struct clock_event_device *evt); | |
84 | static void lapic_timer_setup(enum clock_event_mode mode, | |
85 | struct clock_event_device *evt); | |
ba7eda4c | 86 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 87 | static void apic_pm_activate(void); |
ba7eda4c | 88 | |
274cfe59 CG |
89 | /* |
90 | * The local apic timer can be used for any function which is CPU local. | |
91 | */ | |
ba7eda4c TG |
92 | static struct clock_event_device lapic_clockevent = { |
93 | .name = "lapic", | |
94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
95 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
96 | .shift = 32, | |
97 | .set_mode = lapic_timer_setup, | |
98 | .set_next_event = lapic_next_event, | |
99 | .broadcast = lapic_timer_broadcast, | |
100 | .rating = 100, | |
101 | .irq = -1, | |
102 | }; | |
103 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
104 | ||
d3432896 AK |
105 | static unsigned long apic_phys; |
106 | ||
3f530709 AS |
107 | unsigned long mp_lapic_addr; |
108 | ||
0e078e2f TG |
109 | /* |
110 | * Get the LAPIC version | |
111 | */ | |
112 | static inline int lapic_get_version(void) | |
ba7eda4c | 113 | { |
0e078e2f | 114 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
115 | } |
116 | ||
0e078e2f | 117 | /* |
9c803869 | 118 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
119 | */ |
120 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 121 | { |
9c803869 | 122 | #ifdef CONFIG_X86_64 |
0e078e2f | 123 | return 1; |
9c803869 CG |
124 | #else |
125 | return APIC_INTEGRATED(lapic_get_version()); | |
126 | #endif | |
ba7eda4c TG |
127 | } |
128 | ||
129 | /* | |
0e078e2f | 130 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 131 | */ |
0e078e2f | 132 | static int modern_apic(void) |
ba7eda4c | 133 | { |
0e078e2f TG |
134 | /* AMD systems use old APIC versions, so check the CPU */ |
135 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
136 | boot_cpu_data.x86 >= 0xf) | |
137 | return 1; | |
138 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
139 | } |
140 | ||
274cfe59 CG |
141 | /* |
142 | * Paravirt kernels also might be using these below ops. So we still | |
143 | * use generic apic_read()/apic_write(), which might be pointing to different | |
144 | * ops in PARAVIRT case. | |
145 | */ | |
1b374e4d | 146 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
147 | { |
148 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
149 | cpu_relax(); | |
150 | } | |
151 | ||
1b374e4d | 152 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 153 | { |
3c6bb07a | 154 | u32 send_status; |
8339e9fb FLV |
155 | int timeout; |
156 | ||
157 | timeout = 0; | |
158 | do { | |
159 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
160 | if (!send_status) | |
161 | break; | |
162 | udelay(100); | |
163 | } while (timeout++ < 1000); | |
164 | ||
165 | return send_status; | |
166 | } | |
167 | ||
1b374e4d SS |
168 | void xapic_icr_write(u32 low, u32 id) |
169 | { | |
ed4e5ec1 | 170 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
171 | apic_write(APIC_ICR, low); |
172 | } | |
173 | ||
174 | u64 xapic_icr_read(void) | |
175 | { | |
176 | u32 icr1, icr2; | |
177 | ||
178 | icr2 = apic_read(APIC_ICR2); | |
179 | icr1 = apic_read(APIC_ICR); | |
180 | ||
cf9768d7 | 181 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
182 | } |
183 | ||
184 | static struct apic_ops xapic_ops = { | |
185 | .read = native_apic_mem_read, | |
186 | .write = native_apic_mem_write, | |
1b374e4d SS |
187 | .icr_read = xapic_icr_read, |
188 | .icr_write = xapic_icr_write, | |
189 | .wait_icr_idle = xapic_wait_icr_idle, | |
190 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
191 | }; | |
192 | ||
193 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
194 | EXPORT_SYMBOL_GPL(apic_ops); |
195 | ||
13c88fb5 SS |
196 | static void x2apic_wait_icr_idle(void) |
197 | { | |
198 | /* no need to wait for icr idle in x2apic */ | |
199 | return; | |
200 | } | |
201 | ||
202 | static u32 safe_x2apic_wait_icr_idle(void) | |
203 | { | |
204 | /* no need to wait for icr idle in x2apic */ | |
205 | return 0; | |
206 | } | |
207 | ||
208 | void x2apic_icr_write(u32 low, u32 id) | |
209 | { | |
210 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
211 | } | |
212 | ||
213 | u64 x2apic_icr_read(void) | |
214 | { | |
215 | unsigned long val; | |
216 | ||
217 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
218 | return val; | |
219 | } | |
220 | ||
221 | static struct apic_ops x2apic_ops = { | |
222 | .read = native_apic_msr_read, | |
223 | .write = native_apic_msr_write, | |
13c88fb5 SS |
224 | .icr_read = x2apic_icr_read, |
225 | .icr_write = x2apic_icr_write, | |
226 | .wait_icr_idle = x2apic_wait_icr_idle, | |
227 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
228 | }; | |
229 | ||
0e078e2f TG |
230 | /** |
231 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
232 | */ | |
e9427101 | 233 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 234 | { |
11a8e778 | 235 | unsigned int v; |
6935d1f9 TG |
236 | |
237 | /* unmask and set to NMI */ | |
238 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
239 | |
240 | /* Level triggered for 82489DX (32bit mode) */ | |
241 | if (!lapic_is_integrated()) | |
242 | v |= APIC_LVT_LEVEL_TRIGGER; | |
243 | ||
11a8e778 | 244 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
245 | } |
246 | ||
7c37e48b CG |
247 | #ifdef CONFIG_X86_32 |
248 | /** | |
249 | * get_physical_broadcast - Get number of physical broadcast IDs | |
250 | */ | |
251 | int get_physical_broadcast(void) | |
252 | { | |
253 | return modern_apic() ? 0xff : 0xf; | |
254 | } | |
255 | #endif | |
256 | ||
0e078e2f TG |
257 | /** |
258 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
259 | */ | |
37e650c7 | 260 | int lapic_get_maxlvt(void) |
1da177e4 | 261 | { |
36a028de | 262 | unsigned int v; |
1da177e4 LT |
263 | |
264 | v = apic_read(APIC_LVR); | |
36a028de CG |
265 | /* |
266 | * - we always have APIC integrated on 64bit mode | |
267 | * - 82489DXs do not report # of LVT entries | |
268 | */ | |
269 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
270 | } |
271 | ||
274cfe59 CG |
272 | /* |
273 | * Local APIC timer | |
274 | */ | |
275 | ||
c40aaec6 CG |
276 | /* Clock divisor */ |
277 | #ifdef CONFG_X86_64 | |
f07f4f90 | 278 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
279 | #else |
280 | #define APIC_DIVISOR 16 | |
281 | #endif | |
f07f4f90 | 282 | |
0e078e2f TG |
283 | /* |
284 | * This function sets up the local APIC timer, with a timeout of | |
285 | * 'clocks' APIC bus clock. During calibration we actually call | |
286 | * this function twice on the boot CPU, once with a bogus timeout | |
287 | * value, second time for real. The other (noncalibrating) CPUs | |
288 | * call this function only once, with the real, calibrated value. | |
289 | * | |
290 | * We do reads before writes even if unnecessary, to get around the | |
291 | * P5 APIC double write bug. | |
292 | */ | |
0e078e2f | 293 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 294 | { |
0e078e2f | 295 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 296 | |
0e078e2f TG |
297 | lvtt_value = LOCAL_TIMER_VECTOR; |
298 | if (!oneshot) | |
299 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
300 | if (!lapic_is_integrated()) |
301 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
302 | ||
0e078e2f TG |
303 | if (!irqen) |
304 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 305 | |
0e078e2f | 306 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
307 | |
308 | /* | |
0e078e2f | 309 | * Divide PICLK by 16 |
1da177e4 | 310 | */ |
0e078e2f | 311 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
312 | apic_write(APIC_TDCR, |
313 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
314 | APIC_TDR_DIV_16); | |
0e078e2f TG |
315 | |
316 | if (!oneshot) | |
f07f4f90 | 317 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
318 | } |
319 | ||
0e078e2f | 320 | /* |
7b83dae7 RR |
321 | * Setup extended LVT, AMD specific (K8, family 10h) |
322 | * | |
323 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
324 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
325 | * |
326 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
327 | * enables the vector. See also the BKDGs. | |
0e078e2f | 328 | */ |
7b83dae7 RR |
329 | |
330 | #define APIC_EILVT_LVTOFF_MCE 0 | |
331 | #define APIC_EILVT_LVTOFF_IBS 1 | |
332 | ||
333 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 334 | { |
7b83dae7 | 335 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 336 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 337 | |
0e078e2f | 338 | apic_write(reg, v); |
1da177e4 LT |
339 | } |
340 | ||
7b83dae7 RR |
341 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
342 | { | |
343 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
344 | return APIC_EILVT_LVTOFF_MCE; | |
345 | } | |
346 | ||
347 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
348 | { | |
349 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
350 | return APIC_EILVT_LVTOFF_IBS; | |
351 | } | |
6aa360e6 | 352 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 353 | |
0e078e2f TG |
354 | /* |
355 | * Program the next event, relative to now | |
356 | */ | |
357 | static int lapic_next_event(unsigned long delta, | |
358 | struct clock_event_device *evt) | |
1da177e4 | 359 | { |
0e078e2f TG |
360 | apic_write(APIC_TMICT, delta); |
361 | return 0; | |
1da177e4 LT |
362 | } |
363 | ||
0e078e2f TG |
364 | /* |
365 | * Setup the lapic timer in periodic or oneshot mode | |
366 | */ | |
367 | static void lapic_timer_setup(enum clock_event_mode mode, | |
368 | struct clock_event_device *evt) | |
9b7711f0 HS |
369 | { |
370 | unsigned long flags; | |
0e078e2f | 371 | unsigned int v; |
9b7711f0 | 372 | |
0e078e2f TG |
373 | /* Lapic used as dummy for broadcast ? */ |
374 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
375 | return; |
376 | ||
377 | local_irq_save(flags); | |
378 | ||
0e078e2f TG |
379 | switch (mode) { |
380 | case CLOCK_EVT_MODE_PERIODIC: | |
381 | case CLOCK_EVT_MODE_ONESHOT: | |
382 | __setup_APIC_LVTT(calibration_result, | |
383 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
384 | break; | |
385 | case CLOCK_EVT_MODE_UNUSED: | |
386 | case CLOCK_EVT_MODE_SHUTDOWN: | |
387 | v = apic_read(APIC_LVTT); | |
388 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
389 | apic_write(APIC_LVTT, v); | |
390 | break; | |
391 | case CLOCK_EVT_MODE_RESUME: | |
392 | /* Nothing to do here */ | |
393 | break; | |
394 | } | |
9b7711f0 HS |
395 | |
396 | local_irq_restore(flags); | |
397 | } | |
398 | ||
1da177e4 | 399 | /* |
0e078e2f | 400 | * Local APIC timer broadcast function |
1da177e4 | 401 | */ |
0e078e2f | 402 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 403 | { |
0e078e2f TG |
404 | #ifdef CONFIG_SMP |
405 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
406 | #endif | |
407 | } | |
1da177e4 | 408 | |
0e078e2f TG |
409 | /* |
410 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
411 | * of the boot CPU and register the clock event in the framework. | |
412 | */ | |
db4b5525 | 413 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
414 | { |
415 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 416 | |
0e078e2f TG |
417 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
418 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 419 | |
0e078e2f TG |
420 | clockevents_register_device(levt); |
421 | } | |
1da177e4 | 422 | |
0e078e2f TG |
423 | /* |
424 | * In this function we calibrate APIC bus clocks to the external | |
425 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
426 | * to calibrate, since some later bootup code depends on getting | |
427 | * the first irq? Ugh. | |
428 | * | |
429 | * We want to do the calibration only once since we | |
430 | * want to have local timer irqs syncron. CPUs connected | |
431 | * by the same APIC bus have the very same bus frequency. | |
432 | * And we want to have irqs off anyways, no accidental | |
433 | * APIC irq that way. | |
434 | */ | |
435 | ||
436 | #define TICK_COUNT 100000000 | |
437 | ||
89b3b1f4 | 438 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
439 | { |
440 | unsigned apic, apic_start; | |
441 | unsigned long tsc, tsc_start; | |
442 | int result; | |
443 | ||
444 | local_irq_disable(); | |
445 | ||
446 | /* | |
447 | * Put whatever arbitrary (but long enough) timeout | |
448 | * value into the APIC clock, we just want to get the | |
449 | * counter running for calibration. | |
450 | * | |
451 | * No interrupt enable ! | |
452 | */ | |
453 | __setup_APIC_LVTT(250000000, 0, 0); | |
454 | ||
455 | apic_start = apic_read(APIC_TMCCT); | |
456 | #ifdef CONFIG_X86_PM_TIMER | |
457 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
458 | pmtimer_wait(5000); /* 5ms wait */ | |
459 | apic = apic_read(APIC_TMCCT); | |
460 | result = (apic_start - apic) * 1000L / 5; | |
461 | } else | |
462 | #endif | |
463 | { | |
464 | rdtscll(tsc_start); | |
465 | ||
466 | do { | |
467 | apic = apic_read(APIC_TMCCT); | |
468 | rdtscll(tsc); | |
469 | } while ((tsc - tsc_start) < TICK_COUNT && | |
470 | (apic_start - apic) < TICK_COUNT); | |
471 | ||
472 | result = (apic_start - apic) * 1000L * tsc_khz / | |
473 | (tsc - tsc_start); | |
474 | } | |
475 | ||
476 | local_irq_enable(); | |
477 | ||
478 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
479 | ||
480 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
481 | result / 1000 / 1000, result / 1000 % 1000); | |
482 | ||
483 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
484 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
485 | lapic_clockevent.shift); | |
0e078e2f TG |
486 | lapic_clockevent.max_delta_ns = |
487 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
488 | lapic_clockevent.min_delta_ns = | |
489 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
490 | ||
f07f4f90 | 491 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
492 | |
493 | /* | |
494 | * Do a sanity check on the APIC calibration result | |
495 | */ | |
496 | if (calibration_result < (1000000 / HZ)) { | |
497 | printk(KERN_WARNING | |
498 | "APIC frequency too slow, disabling apic timer\n"); | |
499 | return -1; | |
500 | } | |
501 | ||
502 | return 0; | |
0e078e2f TG |
503 | } |
504 | ||
e83a5fdc HS |
505 | /* |
506 | * Setup the boot APIC | |
507 | * | |
508 | * Calibrate and verify the result. | |
509 | */ | |
0e078e2f TG |
510 | void __init setup_boot_APIC_clock(void) |
511 | { | |
512 | /* | |
274cfe59 CG |
513 | * The local apic timer can be disabled via the kernel |
514 | * commandline or from the CPU detection code. Register the lapic | |
515 | * timer as a dummy clock event source on SMP systems, so the | |
516 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
517 | */ |
518 | if (disable_apic_timer) { | |
519 | printk(KERN_INFO "Disabling APIC timer\n"); | |
520 | /* No broadcast on UP ! */ | |
9d09951d TG |
521 | if (num_possible_cpus() > 1) { |
522 | lapic_clockevent.mult = 1; | |
0e078e2f | 523 | setup_APIC_timer(); |
9d09951d | 524 | } |
0e078e2f TG |
525 | return; |
526 | } | |
527 | ||
274cfe59 CG |
528 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
529 | "calibrating APIC timer ...\n"); | |
530 | ||
89b3b1f4 | 531 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
532 | /* No broadcast on UP ! */ |
533 | if (num_possible_cpus() > 1) | |
534 | setup_APIC_timer(); | |
535 | return; | |
536 | } | |
537 | ||
0e078e2f TG |
538 | /* |
539 | * If nmi_watchdog is set to IO_APIC, we need the | |
540 | * PIT/HPET going. Otherwise register lapic as a dummy | |
541 | * device. | |
542 | */ | |
543 | if (nmi_watchdog != NMI_IO_APIC) | |
544 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
545 | else | |
546 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 547 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 548 | |
274cfe59 | 549 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
550 | setup_APIC_timer(); |
551 | } | |
552 | ||
0e078e2f TG |
553 | void __cpuinit setup_secondary_APIC_clock(void) |
554 | { | |
0e078e2f TG |
555 | setup_APIC_timer(); |
556 | } | |
557 | ||
558 | /* | |
559 | * The guts of the apic timer interrupt | |
560 | */ | |
561 | static void local_apic_timer_interrupt(void) | |
562 | { | |
563 | int cpu = smp_processor_id(); | |
564 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
565 | ||
566 | /* | |
567 | * Normally we should not be here till LAPIC has been initialized but | |
568 | * in some cases like kdump, its possible that there is a pending LAPIC | |
569 | * timer interrupt from previous kernel's context and is delivered in | |
570 | * new kernel the moment interrupts are enabled. | |
571 | * | |
572 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
573 | * its possible that when we get here evt->event_handler is NULL. | |
574 | * Check for event_handler being NULL and discard the interrupt as | |
575 | * spurious. | |
576 | */ | |
577 | if (!evt->event_handler) { | |
578 | printk(KERN_WARNING | |
579 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
580 | /* Switch it off */ | |
581 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
582 | return; | |
583 | } | |
584 | ||
585 | /* | |
586 | * the NMI deadlock-detector uses this. | |
587 | */ | |
0b23e8cf | 588 | #ifdef CONFIG_X86_64 |
0e078e2f | 589 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
590 | #else |
591 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
592 | #endif | |
0e078e2f TG |
593 | |
594 | evt->event_handler(evt); | |
595 | } | |
596 | ||
597 | /* | |
598 | * Local APIC timer interrupt. This is the most natural way for doing | |
599 | * local interrupts, but local timer interrupts can be emulated by | |
600 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
601 | * | |
602 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
603 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
604 | */ | |
605 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
606 | { | |
607 | struct pt_regs *old_regs = set_irq_regs(regs); | |
608 | ||
609 | /* | |
610 | * NOTE! We'd better ACK the irq immediately, | |
611 | * because timer handling can be slow. | |
612 | */ | |
613 | ack_APIC_irq(); | |
614 | /* | |
615 | * update_process_times() expects us to have done irq_enter(). | |
616 | * Besides, if we don't timer interrupts ignore the global | |
617 | * interrupt lock, which is the WrongThing (tm) to do. | |
618 | */ | |
619 | exit_idle(); | |
620 | irq_enter(); | |
621 | local_apic_timer_interrupt(); | |
622 | irq_exit(); | |
274cfe59 | 623 | |
0e078e2f TG |
624 | set_irq_regs(old_regs); |
625 | } | |
626 | ||
627 | int setup_profiling_timer(unsigned int multiplier) | |
628 | { | |
629 | return -EINVAL; | |
630 | } | |
631 | ||
632 | ||
633 | /* | |
634 | * Local APIC start and shutdown | |
635 | */ | |
636 | ||
637 | /** | |
638 | * clear_local_APIC - shutdown the local APIC | |
639 | * | |
640 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
641 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
642 | * leftovers during boot. | |
643 | */ | |
644 | void clear_local_APIC(void) | |
645 | { | |
2584a82d | 646 | int maxlvt; |
0e078e2f TG |
647 | u32 v; |
648 | ||
d3432896 AK |
649 | /* APIC hasn't been mapped yet */ |
650 | if (!apic_phys) | |
651 | return; | |
652 | ||
653 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
654 | /* |
655 | * Masking an LVT entry can trigger a local APIC error | |
656 | * if the vector is zero. Mask LVTERR first to prevent this. | |
657 | */ | |
658 | if (maxlvt >= 3) { | |
659 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
660 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
661 | } | |
662 | /* | |
663 | * Careful: we have to set masks only first to deassert | |
664 | * any level-triggered sources. | |
665 | */ | |
666 | v = apic_read(APIC_LVTT); | |
667 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
668 | v = apic_read(APIC_LVT0); | |
669 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
670 | v = apic_read(APIC_LVT1); | |
671 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
672 | if (maxlvt >= 4) { | |
673 | v = apic_read(APIC_LVTPC); | |
674 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
675 | } | |
676 | ||
6764014b CG |
677 | /* lets not touch this if we didn't frob it */ |
678 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
679 | if (maxlvt >= 5) { | |
680 | v = apic_read(APIC_LVTTHMR); | |
681 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
682 | } | |
683 | #endif | |
0e078e2f TG |
684 | /* |
685 | * Clean APIC state for other OSs: | |
686 | */ | |
687 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
688 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
689 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
690 | if (maxlvt >= 3) | |
691 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
692 | if (maxlvt >= 4) | |
693 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
694 | |
695 | /* Integrated APIC (!82489DX) ? */ | |
696 | if (lapic_is_integrated()) { | |
697 | if (maxlvt > 3) | |
698 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
699 | apic_write(APIC_ESR, 0); | |
700 | apic_read(APIC_ESR); | |
701 | } | |
0e078e2f TG |
702 | } |
703 | ||
704 | /** | |
705 | * disable_local_APIC - clear and disable the local APIC | |
706 | */ | |
707 | void disable_local_APIC(void) | |
708 | { | |
709 | unsigned int value; | |
710 | ||
711 | clear_local_APIC(); | |
712 | ||
713 | /* | |
714 | * Disable APIC (implies clearing of registers | |
715 | * for 82489DX!). | |
716 | */ | |
717 | value = apic_read(APIC_SPIV); | |
718 | value &= ~APIC_SPIV_APIC_ENABLED; | |
719 | apic_write(APIC_SPIV, value); | |
990b183e CG |
720 | |
721 | #ifdef CONFIG_X86_32 | |
722 | /* | |
723 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
724 | * restore the disabled state. | |
725 | */ | |
726 | if (enabled_via_apicbase) { | |
727 | unsigned int l, h; | |
728 | ||
729 | rdmsr(MSR_IA32_APICBASE, l, h); | |
730 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
731 | wrmsr(MSR_IA32_APICBASE, l, h); | |
732 | } | |
733 | #endif | |
0e078e2f TG |
734 | } |
735 | ||
fe4024dc CG |
736 | /* |
737 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
738 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
739 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
740 | * for the case where Linux didn't enable the LAPIC. | |
741 | */ | |
0e078e2f TG |
742 | void lapic_shutdown(void) |
743 | { | |
744 | unsigned long flags; | |
745 | ||
746 | if (!cpu_has_apic) | |
747 | return; | |
748 | ||
749 | local_irq_save(flags); | |
750 | ||
fe4024dc CG |
751 | #ifdef CONFIG_X86_32 |
752 | if (!enabled_via_apicbase) | |
753 | clear_local_APIC(); | |
754 | else | |
755 | #endif | |
756 | disable_local_APIC(); | |
757 | ||
0e078e2f TG |
758 | |
759 | local_irq_restore(flags); | |
760 | } | |
761 | ||
762 | /* | |
763 | * This is to verify that we're looking at a real local APIC. | |
764 | * Check these against your board if the CPUs aren't getting | |
765 | * started for no apparent reason. | |
766 | */ | |
767 | int __init verify_local_APIC(void) | |
768 | { | |
769 | unsigned int reg0, reg1; | |
770 | ||
771 | /* | |
772 | * The version register is read-only in a real APIC. | |
773 | */ | |
774 | reg0 = apic_read(APIC_LVR); | |
775 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
776 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
777 | reg1 = apic_read(APIC_LVR); | |
778 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
779 | ||
780 | /* | |
781 | * The two version reads above should print the same | |
782 | * numbers. If the second one is different, then we | |
783 | * poke at a non-APIC. | |
784 | */ | |
785 | if (reg1 != reg0) | |
786 | return 0; | |
787 | ||
788 | /* | |
789 | * Check if the version looks reasonably. | |
790 | */ | |
791 | reg1 = GET_APIC_VERSION(reg0); | |
792 | if (reg1 == 0x00 || reg1 == 0xff) | |
793 | return 0; | |
794 | reg1 = lapic_get_maxlvt(); | |
795 | if (reg1 < 0x02 || reg1 == 0xff) | |
796 | return 0; | |
797 | ||
798 | /* | |
799 | * The ID register is read/write in a real APIC. | |
800 | */ | |
2d7a66d0 | 801 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
802 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
803 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 804 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
805 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
806 | apic_write(APIC_ID, reg0); | |
807 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
808 | return 0; | |
809 | ||
810 | /* | |
1da177e4 LT |
811 | * The next two are just to see if we have sane values. |
812 | * They're only really relevant if we're in Virtual Wire | |
813 | * compatibility mode, but most boxes are anymore. | |
814 | */ | |
815 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 816 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
817 | reg1 = apic_read(APIC_LVT1); |
818 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
819 | ||
820 | return 1; | |
821 | } | |
822 | ||
0e078e2f TG |
823 | /** |
824 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
825 | */ | |
1da177e4 LT |
826 | void __init sync_Arb_IDs(void) |
827 | { | |
296cb951 CG |
828 | /* |
829 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
830 | * needed on AMD. | |
831 | */ | |
832 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
833 | return; |
834 | ||
835 | /* | |
836 | * Wait for idle. | |
837 | */ | |
838 | apic_wait_icr_idle(); | |
839 | ||
840 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
841 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
842 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
843 | } |
844 | ||
1da177e4 LT |
845 | /* |
846 | * An initial setup of the virtual wire mode. | |
847 | */ | |
848 | void __init init_bsp_APIC(void) | |
849 | { | |
11a8e778 | 850 | unsigned int value; |
1da177e4 LT |
851 | |
852 | /* | |
853 | * Don't do the setup now if we have a SMP BIOS as the | |
854 | * through-I/O-APIC virtual wire mode might be active. | |
855 | */ | |
856 | if (smp_found_config || !cpu_has_apic) | |
857 | return; | |
858 | ||
1da177e4 LT |
859 | /* |
860 | * Do not trust the local APIC being empty at bootup. | |
861 | */ | |
862 | clear_local_APIC(); | |
863 | ||
864 | /* | |
865 | * Enable APIC. | |
866 | */ | |
867 | value = apic_read(APIC_SPIV); | |
868 | value &= ~APIC_VECTOR_MASK; | |
869 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
870 | |
871 | #ifdef CONFIG_X86_32 | |
872 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
873 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
874 | (boot_cpu_data.x86 == 15)) | |
875 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
876 | else | |
877 | #endif | |
878 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 879 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 880 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
881 | |
882 | /* | |
883 | * Set up the virtual wire mode. | |
884 | */ | |
11a8e778 | 885 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 886 | value = APIC_DM_NMI; |
638c0411 CG |
887 | if (!lapic_is_integrated()) /* 82489DX */ |
888 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 889 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
890 | } |
891 | ||
c43da2f5 CG |
892 | static void __cpuinit lapic_setup_esr(void) |
893 | { | |
894 | unsigned long oldvalue, value, maxlvt; | |
895 | if (lapic_is_integrated() && !esr_disable) { | |
896 | if (esr_disable) { | |
897 | /* | |
898 | * Something untraceable is creating bad interrupts on | |
899 | * secondary quads ... for the moment, just leave the | |
900 | * ESR disabled - we can't do anything useful with the | |
901 | * errors anyway - mbligh | |
902 | */ | |
903 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
904 | return; | |
905 | } | |
906 | /* !82489DX */ | |
907 | maxlvt = lapic_get_maxlvt(); | |
908 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
909 | apic_write(APIC_ESR, 0); | |
910 | oldvalue = apic_read(APIC_ESR); | |
911 | ||
912 | /* enables sending errors */ | |
913 | value = ERROR_APIC_VECTOR; | |
914 | apic_write(APIC_LVTERR, value); | |
915 | /* | |
916 | * spec says clear errors after enabling vector. | |
917 | */ | |
918 | if (maxlvt > 3) | |
919 | apic_write(APIC_ESR, 0); | |
920 | value = apic_read(APIC_ESR); | |
921 | if (value != oldvalue) | |
922 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
923 | "vector: 0x%08lx after: 0x%08lx\n", | |
924 | oldvalue, value); | |
925 | } else { | |
926 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
927 | } | |
928 | } | |
929 | ||
930 | ||
0e078e2f TG |
931 | /** |
932 | * setup_local_APIC - setup the local APIC | |
933 | */ | |
934 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 935 | { |
739f33b3 | 936 | unsigned int value; |
da7ed9f9 | 937 | int i, j; |
1da177e4 | 938 | |
ac23d4ee | 939 | preempt_disable(); |
1da177e4 | 940 | value = apic_read(APIC_LVR); |
1da177e4 | 941 | |
fe7414a2 | 942 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
943 | |
944 | /* | |
945 | * Double-check whether this APIC is really registered. | |
946 | * This is meaningless in clustered apic mode, so we skip it. | |
947 | */ | |
948 | if (!apic_id_registered()) | |
949 | BUG(); | |
950 | ||
951 | /* | |
952 | * Intel recommends to set DFR, LDR and TPR before enabling | |
953 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
954 | * document number 292116). So here it goes... | |
955 | */ | |
956 | init_apic_ldr(); | |
957 | ||
958 | /* | |
959 | * Set Task Priority to 'accept all'. We never change this | |
960 | * later on. | |
961 | */ | |
962 | value = apic_read(APIC_TASKPRI); | |
963 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 964 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 965 | |
da7ed9f9 VG |
966 | /* |
967 | * After a crash, we no longer service the interrupts and a pending | |
968 | * interrupt from previous kernel might still have ISR bit set. | |
969 | * | |
970 | * Most probably by now CPU has serviced that pending interrupt and | |
971 | * it might not have done the ack_APIC_irq() because it thought, | |
972 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
973 | * does not clear the ISR bit and cpu thinks it has already serivced | |
974 | * the interrupt. Hence a vector might get locked. It was noticed | |
975 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
976 | */ | |
977 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
978 | value = apic_read(APIC_ISR + i*0x10); | |
979 | for (j = 31; j >= 0; j--) { | |
980 | if (value & (1<<j)) | |
981 | ack_APIC_irq(); | |
982 | } | |
983 | } | |
984 | ||
1da177e4 LT |
985 | /* |
986 | * Now that we are all set up, enable the APIC | |
987 | */ | |
988 | value = apic_read(APIC_SPIV); | |
989 | value &= ~APIC_VECTOR_MASK; | |
990 | /* | |
991 | * Enable APIC | |
992 | */ | |
993 | value |= APIC_SPIV_APIC_ENABLED; | |
994 | ||
3f14c746 AK |
995 | /* We always use processor focus */ |
996 | ||
1da177e4 LT |
997 | /* |
998 | * Set spurious IRQ vector | |
999 | */ | |
1000 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1001 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1002 | |
1003 | /* | |
1004 | * Set up LVT0, LVT1: | |
1005 | * | |
1006 | * set up through-local-APIC on the BP's LINT0. This is not | |
1007 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1008 | * we delegate interrupts to the 8259A. | |
1009 | */ | |
1010 | /* | |
1011 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1012 | */ | |
1013 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 1014 | if (!smp_processor_id() && !value) { |
1da177e4 | 1015 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
1016 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
1017 | smp_processor_id()); | |
1da177e4 LT |
1018 | } else { |
1019 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
1020 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
1021 | smp_processor_id()); | |
1da177e4 | 1022 | } |
11a8e778 | 1023 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1024 | |
1025 | /* | |
1026 | * only the BP should see the LINT1 NMI signal, obviously. | |
1027 | */ | |
1028 | if (!smp_processor_id()) | |
1029 | value = APIC_DM_NMI; | |
1030 | else | |
1031 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 1032 | apic_write(APIC_LVT1, value); |
ac23d4ee | 1033 | preempt_enable(); |
739f33b3 | 1034 | } |
1da177e4 | 1035 | |
739f33b3 AK |
1036 | void __cpuinit end_local_APIC_setup(void) |
1037 | { | |
1038 | lapic_setup_esr(); | |
fa6b95fc CG |
1039 | |
1040 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1041 | { |
1042 | unsigned int value; | |
1043 | /* Disable the local apic timer */ | |
1044 | value = apic_read(APIC_LVTT); | |
1045 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1046 | apic_write(APIC_LVTT, value); | |
1047 | } | |
fa6b95fc CG |
1048 | #endif |
1049 | ||
f2802e7f | 1050 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1051 | apic_pm_activate(); |
1da177e4 | 1052 | } |
1da177e4 | 1053 | |
6e1cb38a SS |
1054 | void check_x2apic(void) |
1055 | { | |
1056 | int msr, msr2; | |
1057 | ||
1058 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1059 | ||
1060 | if (msr & X2APIC_ENABLE) { | |
1061 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1062 | x2apic_preenabled = x2apic = 1; | |
1063 | apic_ops = &x2apic_ops; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | void enable_x2apic(void) | |
1068 | { | |
1069 | int msr, msr2; | |
1070 | ||
1071 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1072 | if (!(msr & X2APIC_ENABLE)) { | |
1073 | printk("Enabling x2apic\n"); | |
1074 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | void enable_IR_x2apic(void) | |
1079 | { | |
1080 | #ifdef CONFIG_INTR_REMAP | |
1081 | int ret; | |
1082 | unsigned long flags; | |
1083 | ||
1084 | if (!cpu_has_x2apic) | |
1085 | return; | |
1086 | ||
1087 | if (!x2apic_preenabled && disable_x2apic) { | |
1088 | printk(KERN_INFO | |
1089 | "Skipped enabling x2apic and Interrupt-remapping " | |
1090 | "because of nox2apic\n"); | |
1091 | return; | |
1092 | } | |
1093 | ||
1094 | if (x2apic_preenabled && disable_x2apic) | |
1095 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1096 | ||
1097 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1098 | printk(KERN_INFO | |
1099 | "Skipped enabling x2apic and Interrupt-remapping " | |
1100 | "because of skipping io-apic setup\n"); | |
1101 | return; | |
1102 | } | |
1103 | ||
1104 | ret = dmar_table_init(); | |
1105 | if (ret) { | |
1106 | printk(KERN_INFO | |
1107 | "dmar_table_init() failed with %d:\n", ret); | |
1108 | ||
1109 | if (x2apic_preenabled) | |
1110 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1111 | else | |
1112 | printk(KERN_INFO | |
1113 | "Not enabling x2apic,Intr-remapping\n"); | |
1114 | return; | |
1115 | } | |
1116 | ||
1117 | local_irq_save(flags); | |
1118 | mask_8259A(); | |
1119 | save_mask_IO_APIC_setup(); | |
1120 | ||
1121 | ret = enable_intr_remapping(1); | |
1122 | ||
1123 | if (ret && x2apic_preenabled) { | |
1124 | local_irq_restore(flags); | |
1125 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1126 | } | |
1127 | ||
1128 | if (ret) | |
1129 | goto end; | |
1130 | ||
1131 | if (!x2apic) { | |
1132 | x2apic = 1; | |
1133 | apic_ops = &x2apic_ops; | |
1134 | enable_x2apic(); | |
1135 | } | |
1136 | end: | |
1137 | if (ret) | |
1138 | /* | |
1139 | * IR enabling failed | |
1140 | */ | |
1141 | restore_IO_APIC_setup(); | |
1142 | else | |
1143 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1144 | ||
1145 | unmask_8259A(); | |
1146 | local_irq_restore(flags); | |
1147 | ||
1148 | if (!ret) { | |
1149 | if (!x2apic_preenabled) | |
1150 | printk(KERN_INFO | |
1151 | "Enabled x2apic and interrupt-remapping\n"); | |
1152 | else | |
1153 | printk(KERN_INFO | |
1154 | "Enabled Interrupt-remapping\n"); | |
1155 | } else | |
1156 | printk(KERN_ERR | |
1157 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1158 | #else | |
1159 | if (!cpu_has_x2apic) | |
1160 | return; | |
1161 | ||
1162 | if (x2apic_preenabled) | |
1163 | panic("x2apic enabled prior OS handover," | |
1164 | " enable CONFIG_INTR_REMAP"); | |
1165 | ||
1166 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1167 | " and x2apic\n"); | |
1168 | #endif | |
1169 | ||
1170 | return; | |
1171 | } | |
1172 | ||
1da177e4 LT |
1173 | /* |
1174 | * Detect and enable local APICs on non-SMP boards. | |
1175 | * Original code written by Keir Fraser. | |
1176 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1177 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1178 | */ |
0e078e2f | 1179 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1180 | { |
1181 | if (!cpu_has_apic) { | |
1182 | printk(KERN_INFO "No local APIC present\n"); | |
1183 | return -1; | |
1184 | } | |
1185 | ||
1186 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1187 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1188 | return 0; |
1189 | } | |
1190 | ||
8643f9d0 YL |
1191 | void __init early_init_lapic_mapping(void) |
1192 | { | |
431ee79d | 1193 | unsigned long phys_addr; |
8643f9d0 YL |
1194 | |
1195 | /* | |
1196 | * If no local APIC can be found then go out | |
1197 | * : it means there is no mpatable and MADT | |
1198 | */ | |
1199 | if (!smp_found_config) | |
1200 | return; | |
1201 | ||
431ee79d | 1202 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1203 | |
431ee79d | 1204 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1205 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1206 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1207 | |
1208 | /* | |
1209 | * Fetch the APIC ID of the BSP in case we have a | |
1210 | * default configuration (or the MP table is broken). | |
1211 | */ | |
4c9961d5 | 1212 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1213 | } |
1214 | ||
0e078e2f TG |
1215 | /** |
1216 | * init_apic_mappings - initialize APIC mappings | |
1217 | */ | |
1da177e4 LT |
1218 | void __init init_apic_mappings(void) |
1219 | { | |
6e1cb38a | 1220 | if (x2apic) { |
4c9961d5 | 1221 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1222 | return; |
1223 | } | |
1224 | ||
1da177e4 LT |
1225 | /* |
1226 | * If no local APIC can be found then set up a fake all | |
1227 | * zeroes page to simulate the local APIC and another | |
1228 | * one for the IO-APIC. | |
1229 | */ | |
1230 | if (!smp_found_config && detect_init_APIC()) { | |
1231 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1232 | apic_phys = __pa(apic_phys); | |
1233 | } else | |
1234 | apic_phys = mp_lapic_addr; | |
1235 | ||
1236 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1237 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1238 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1239 | |
1240 | /* | |
1241 | * Fetch the APIC ID of the BSP in case we have a | |
1242 | * default configuration (or the MP table is broken). | |
1243 | */ | |
4c9961d5 | 1244 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1245 | } |
1246 | ||
1247 | /* | |
0e078e2f TG |
1248 | * This initializes the IO-APIC and APIC hardware if this is |
1249 | * a UP kernel. | |
1da177e4 | 1250 | */ |
1b313f4a CG |
1251 | int apic_version[MAX_APICS]; |
1252 | ||
0e078e2f | 1253 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1254 | { |
0e078e2f TG |
1255 | if (disable_apic) { |
1256 | printk(KERN_INFO "Apic disabled\n"); | |
1257 | return -1; | |
1258 | } | |
1259 | if (!cpu_has_apic) { | |
1260 | disable_apic = 1; | |
1261 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1262 | return -1; | |
1263 | } | |
1da177e4 | 1264 | |
6e1cb38a SS |
1265 | enable_IR_x2apic(); |
1266 | setup_apic_routing(); | |
1267 | ||
0e078e2f | 1268 | verify_local_APIC(); |
1da177e4 | 1269 | |
b5841765 GC |
1270 | connect_bsp_APIC(); |
1271 | ||
b6df1b8b | 1272 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1273 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1274 | |
0e078e2f | 1275 | setup_local_APIC(); |
1da177e4 | 1276 | |
739f33b3 AK |
1277 | /* |
1278 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1279 | * We need clear_IO_APIC before enabling vector on BP | |
1280 | */ | |
1281 | if (!skip_ioapic_setup && nr_ioapics) | |
1282 | enable_IO_APIC(); | |
1283 | ||
acae7d90 MR |
1284 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1285 | localise_nmi_watchdog(); | |
739f33b3 AK |
1286 | end_local_APIC_setup(); |
1287 | ||
0e078e2f TG |
1288 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1289 | setup_IO_APIC(); | |
1290 | else | |
1291 | nr_ioapics = 0; | |
1292 | setup_boot_APIC_clock(); | |
1293 | check_nmi_watchdog(); | |
1294 | return 0; | |
1da177e4 LT |
1295 | } |
1296 | ||
1297 | /* | |
0e078e2f | 1298 | * Local APIC interrupts |
1da177e4 LT |
1299 | */ |
1300 | ||
0e078e2f TG |
1301 | /* |
1302 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1303 | */ | |
1304 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1305 | { |
0e078e2f TG |
1306 | unsigned int v; |
1307 | exit_idle(); | |
1308 | irq_enter(); | |
1da177e4 | 1309 | /* |
0e078e2f TG |
1310 | * Check if this really is a spurious interrupt and ACK it |
1311 | * if it is a vectored one. Just in case... | |
1312 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1313 | */ |
0e078e2f TG |
1314 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1315 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1316 | ack_APIC_irq(); | |
c4d58cbd | 1317 | |
0e078e2f TG |
1318 | add_pda(irq_spurious_count, 1); |
1319 | irq_exit(); | |
1320 | } | |
1da177e4 | 1321 | |
0e078e2f TG |
1322 | /* |
1323 | * This interrupt should never happen with our APIC/SMP architecture | |
1324 | */ | |
1325 | asmlinkage void smp_error_interrupt(void) | |
1326 | { | |
1327 | unsigned int v, v1; | |
1da177e4 | 1328 | |
0e078e2f TG |
1329 | exit_idle(); |
1330 | irq_enter(); | |
1331 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1332 | v = apic_read(APIC_ESR); | |
1333 | apic_write(APIC_ESR, 0); | |
1334 | v1 = apic_read(APIC_ESR); | |
1335 | ack_APIC_irq(); | |
1336 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1337 | |
0e078e2f TG |
1338 | /* Here is what the APIC error bits mean: |
1339 | 0: Send CS error | |
1340 | 1: Receive CS error | |
1341 | 2: Send accept error | |
1342 | 3: Receive accept error | |
1343 | 4: Reserved | |
1344 | 5: Send illegal vector | |
1345 | 6: Received illegal vector | |
1346 | 7: Illegal register address | |
1347 | */ | |
1348 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1349 | smp_processor_id(), v , v1); | |
1350 | irq_exit(); | |
1da177e4 LT |
1351 | } |
1352 | ||
b5841765 | 1353 | /** |
36c9d674 CG |
1354 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1355 | */ | |
b5841765 GC |
1356 | void __init connect_bsp_APIC(void) |
1357 | { | |
36c9d674 CG |
1358 | #ifdef CONFIG_X86_32 |
1359 | if (pic_mode) { | |
1360 | /* | |
1361 | * Do not trust the local APIC being empty at bootup. | |
1362 | */ | |
1363 | clear_local_APIC(); | |
1364 | /* | |
1365 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1366 | * local APIC to INT and NMI lines. | |
1367 | */ | |
1368 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1369 | "enabling APIC mode.\n"); | |
1370 | outb(0x70, 0x22); | |
1371 | outb(0x01, 0x23); | |
1372 | } | |
1373 | #endif | |
b5841765 GC |
1374 | enable_apic_mode(); |
1375 | } | |
1376 | ||
274cfe59 CG |
1377 | /** |
1378 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1379 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1380 | * | |
1381 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1382 | * APIC is disabled. | |
1383 | */ | |
0e078e2f | 1384 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1385 | { |
1b4ee4e4 CG |
1386 | unsigned int value; |
1387 | ||
c177b0bc CG |
1388 | #ifdef CONFIG_X86_32 |
1389 | if (pic_mode) { | |
1390 | /* | |
1391 | * Put the board back into PIC mode (has an effect only on | |
1392 | * certain older boards). Note that APIC interrupts, including | |
1393 | * IPIs, won't work beyond this point! The only exception are | |
1394 | * INIT IPIs. | |
1395 | */ | |
1396 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1397 | "entering PIC mode.\n"); | |
1398 | outb(0x70, 0x22); | |
1399 | outb(0x00, 0x23); | |
1400 | return; | |
1401 | } | |
1402 | #endif | |
1403 | ||
0e078e2f | 1404 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1405 | |
0e078e2f TG |
1406 | /* For the spurious interrupt use vector F, and enable it */ |
1407 | value = apic_read(APIC_SPIV); | |
1408 | value &= ~APIC_VECTOR_MASK; | |
1409 | value |= APIC_SPIV_APIC_ENABLED; | |
1410 | value |= 0xf; | |
1411 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1412 | |
0e078e2f TG |
1413 | if (!virt_wire_setup) { |
1414 | /* | |
1415 | * For LVT0 make it edge triggered, active high, | |
1416 | * external and enabled | |
1417 | */ | |
1418 | value = apic_read(APIC_LVT0); | |
1419 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1420 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1421 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1422 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1423 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1424 | apic_write(APIC_LVT0, value); | |
1425 | } else { | |
1426 | /* Disable LVT0 */ | |
1427 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1428 | } | |
b8ce3359 | 1429 | |
c177b0bc CG |
1430 | /* |
1431 | * For LVT1 make it edge triggered, active high, | |
1432 | * nmi and enabled | |
1433 | */ | |
0e078e2f TG |
1434 | value = apic_read(APIC_LVT1); |
1435 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1436 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1437 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1438 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1439 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1440 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1441 | } |
1442 | ||
be8a5685 AS |
1443 | void __cpuinit generic_processor_info(int apicid, int version) |
1444 | { | |
1445 | int cpu; | |
1446 | cpumask_t tmp_map; | |
1447 | ||
1b313f4a CG |
1448 | /* |
1449 | * Validate version | |
1450 | */ | |
1451 | if (version == 0x0) { | |
1452 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1453 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1454 | version); | |
1455 | version = 0x10; | |
be8a5685 | 1456 | } |
1b313f4a | 1457 | apic_version[apicid] = version; |
be8a5685 | 1458 | |
be8a5685 AS |
1459 | if (num_processors >= NR_CPUS) { |
1460 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1461 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1462 | return; |
1463 | } | |
1464 | ||
1465 | num_processors++; | |
1466 | cpus_complement(tmp_map, cpu_present_map); | |
1467 | cpu = first_cpu(tmp_map); | |
1468 | ||
1469 | physid_set(apicid, phys_cpu_present_map); | |
1470 | if (apicid == boot_cpu_physical_apicid) { | |
1471 | /* | |
1472 | * x86_bios_cpu_apicid is required to have processors listed | |
1473 | * in same order as logical cpu numbers. Hence the first | |
1474 | * entry is BSP, and so on. | |
1475 | */ | |
1476 | cpu = 0; | |
1477 | } | |
e0da3364 YL |
1478 | if (apicid > max_physical_apicid) |
1479 | max_physical_apicid = apicid; | |
1480 | ||
1b313f4a CG |
1481 | #ifdef CONFIG_X86_32 |
1482 | /* | |
1483 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1484 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1485 | * before this can be done without some confusion. | |
1486 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1487 | * - Ashok Raj <ashok.raj@intel.com> | |
1488 | */ | |
1489 | if (max_physical_apicid >= 8) { | |
1490 | switch (boot_cpu_data.x86_vendor) { | |
1491 | case X86_VENDOR_INTEL: | |
1492 | if (!APIC_XAPIC(version)) { | |
1493 | def_to_bigsmp = 0; | |
1494 | break; | |
1495 | } | |
1496 | /* If P4 and above fall through */ | |
1497 | case X86_VENDOR_AMD: | |
1498 | def_to_bigsmp = 1; | |
1499 | } | |
1500 | } | |
1501 | #endif | |
1502 | ||
1503 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1504 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1505 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1506 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1507 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1508 | |
1509 | cpu_to_apicid[cpu] = apicid; | |
1510 | bios_cpu_apicid[cpu] = apicid; | |
1511 | } else { | |
1512 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1513 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1514 | } | |
1b313f4a | 1515 | #endif |
be8a5685 AS |
1516 | |
1517 | cpu_set(cpu, cpu_possible_map); | |
1518 | cpu_set(cpu, cpu_present_map); | |
1519 | } | |
1520 | ||
0c81c746 SS |
1521 | int hard_smp_processor_id(void) |
1522 | { | |
1523 | return read_apic_id(); | |
1524 | } | |
1525 | ||
89039b37 | 1526 | /* |
0e078e2f | 1527 | * Power management |
89039b37 | 1528 | */ |
0e078e2f TG |
1529 | #ifdef CONFIG_PM |
1530 | ||
1531 | static struct { | |
274cfe59 CG |
1532 | /* |
1533 | * 'active' is true if the local APIC was enabled by us and | |
1534 | * not the BIOS; this signifies that we are also responsible | |
1535 | * for disabling it before entering apm/acpi suspend | |
1536 | */ | |
0e078e2f TG |
1537 | int active; |
1538 | /* r/w apic fields */ | |
1539 | unsigned int apic_id; | |
1540 | unsigned int apic_taskpri; | |
1541 | unsigned int apic_ldr; | |
1542 | unsigned int apic_dfr; | |
1543 | unsigned int apic_spiv; | |
1544 | unsigned int apic_lvtt; | |
1545 | unsigned int apic_lvtpc; | |
1546 | unsigned int apic_lvt0; | |
1547 | unsigned int apic_lvt1; | |
1548 | unsigned int apic_lvterr; | |
1549 | unsigned int apic_tmict; | |
1550 | unsigned int apic_tdcr; | |
1551 | unsigned int apic_thmr; | |
1552 | } apic_pm_state; | |
1553 | ||
1554 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1555 | { | |
1556 | unsigned long flags; | |
1557 | int maxlvt; | |
89039b37 | 1558 | |
0e078e2f TG |
1559 | if (!apic_pm_state.active) |
1560 | return 0; | |
89039b37 | 1561 | |
0e078e2f | 1562 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1563 | |
2d7a66d0 | 1564 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1565 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1566 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1567 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1568 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1569 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1570 | if (maxlvt >= 4) | |
1571 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1572 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1573 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1574 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1575 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1576 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1577 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1578 | if (maxlvt >= 5) |
1579 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1580 | #endif | |
24968cfd | 1581 | |
0e078e2f TG |
1582 | local_irq_save(flags); |
1583 | disable_local_APIC(); | |
1584 | local_irq_restore(flags); | |
1585 | return 0; | |
1da177e4 LT |
1586 | } |
1587 | ||
0e078e2f | 1588 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1589 | { |
0e078e2f TG |
1590 | unsigned int l, h; |
1591 | unsigned long flags; | |
1592 | int maxlvt; | |
1da177e4 | 1593 | |
0e078e2f TG |
1594 | if (!apic_pm_state.active) |
1595 | return 0; | |
89b831ef | 1596 | |
0e078e2f | 1597 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1598 | |
0e078e2f | 1599 | local_irq_save(flags); |
92206c90 CG |
1600 | |
1601 | #ifdef CONFIG_X86_64 | |
1602 | if (x2apic) | |
1603 | enable_x2apic(); | |
1604 | else | |
1605 | #endif | |
d5e629a6 | 1606 | { |
92206c90 CG |
1607 | /* |
1608 | * Make sure the APICBASE points to the right address | |
1609 | * | |
1610 | * FIXME! This will be wrong if we ever support suspend on | |
1611 | * SMP! We'll need to do this as part of the CPU restore! | |
1612 | */ | |
6e1cb38a SS |
1613 | rdmsr(MSR_IA32_APICBASE, l, h); |
1614 | l &= ~MSR_IA32_APICBASE_BASE; | |
1615 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1616 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1617 | } |
6e1cb38a | 1618 | |
0e078e2f TG |
1619 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1620 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1621 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1622 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1623 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1624 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1625 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1626 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1627 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1628 | if (maxlvt >= 5) |
1629 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1630 | #endif | |
1631 | if (maxlvt >= 4) | |
1632 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1633 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1634 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1635 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1636 | apic_write(APIC_ESR, 0); | |
1637 | apic_read(APIC_ESR); | |
1638 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1639 | apic_write(APIC_ESR, 0); | |
1640 | apic_read(APIC_ESR); | |
92206c90 | 1641 | |
0e078e2f | 1642 | local_irq_restore(flags); |
92206c90 | 1643 | |
0e078e2f TG |
1644 | return 0; |
1645 | } | |
b8ce3359 | 1646 | |
274cfe59 CG |
1647 | /* |
1648 | * This device has no shutdown method - fully functioning local APICs | |
1649 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1650 | */ | |
1651 | ||
0e078e2f TG |
1652 | static struct sysdev_class lapic_sysclass = { |
1653 | .name = "lapic", | |
1654 | .resume = lapic_resume, | |
1655 | .suspend = lapic_suspend, | |
1656 | }; | |
b8ce3359 | 1657 | |
0e078e2f | 1658 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1659 | .id = 0, |
1660 | .cls = &lapic_sysclass, | |
0e078e2f | 1661 | }; |
b8ce3359 | 1662 | |
0e078e2f TG |
1663 | static void __cpuinit apic_pm_activate(void) |
1664 | { | |
1665 | apic_pm_state.active = 1; | |
1da177e4 LT |
1666 | } |
1667 | ||
0e078e2f | 1668 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1669 | { |
0e078e2f | 1670 | int error; |
e83a5fdc | 1671 | |
0e078e2f TG |
1672 | if (!cpu_has_apic) |
1673 | return 0; | |
1674 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1675 | |
0e078e2f TG |
1676 | error = sysdev_class_register(&lapic_sysclass); |
1677 | if (!error) | |
1678 | error = sysdev_register(&device_lapic); | |
1679 | return error; | |
1da177e4 | 1680 | } |
0e078e2f TG |
1681 | device_initcall(init_lapic_sysfs); |
1682 | ||
1683 | #else /* CONFIG_PM */ | |
1684 | ||
1685 | static void apic_pm_activate(void) { } | |
1686 | ||
1687 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1688 | |
1689 | /* | |
f8bf3c65 | 1690 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1691 | * |
1692 | * Thus far, the major user of this is IBM's Summit2 series: | |
1693 | * | |
637029c6 | 1694 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1695 | * multi-chassis. Use available data to take a good guess. |
1696 | * If in doubt, go HPET. | |
1697 | */ | |
f8bf3c65 | 1698 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1699 | { |
1700 | int i, clusters, zeros; | |
1701 | unsigned id; | |
322850af | 1702 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1703 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1704 | ||
322850af YL |
1705 | /* |
1706 | * there is not this kind of box with AMD CPU yet. | |
1707 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1708 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1709 | * vsmp box still need checking... |
322850af | 1710 | */ |
1cb68487 | 1711 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1712 | return 0; |
1713 | ||
23ca4bba | 1714 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1715 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1716 | |
1717 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1718 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1719 | if (bios_cpu_apicid) { |
1720 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1721 | } |
1722 | else if (i < nr_cpu_ids) { | |
1723 | if (cpu_present(i)) | |
1724 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1725 | else | |
1726 | continue; | |
1727 | } | |
1728 | else | |
1729 | break; | |
1730 | ||
1da177e4 LT |
1731 | if (id != BAD_APICID) |
1732 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1733 | } | |
1734 | ||
1735 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1736 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1737 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1738 | * Since clusters are allocated sequentially, count zeros only if | |
1739 | * they are bounded by ones. | |
1da177e4 LT |
1740 | */ |
1741 | clusters = 0; | |
1742 | zeros = 0; | |
1743 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1744 | if (test_bit(i, clustermap)) { | |
1745 | clusters += 1 + zeros; | |
1746 | zeros = 0; | |
1747 | } else | |
1748 | ++zeros; | |
1749 | } | |
1750 | ||
1cb68487 RT |
1751 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1752 | * not guaranteed to be synced between boards | |
1753 | */ | |
1754 | if (is_vsmp_box() && clusters > 1) | |
1755 | return 1; | |
1756 | ||
1da177e4 | 1757 | /* |
f8bf3c65 | 1758 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1759 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1760 | * out, but AFAIK this will work even for them. | |
1761 | */ | |
1762 | return (clusters > 2); | |
1763 | } | |
1764 | ||
6e1cb38a | 1765 | static __init int setup_nox2apic(char *str) |
1da177e4 | 1766 | { |
6e1cb38a SS |
1767 | disable_x2apic = 1; |
1768 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1da177e4 LT |
1769 | return 0; |
1770 | } | |
6e1cb38a | 1771 | early_param("nox2apic", setup_nox2apic); |
1da177e4 | 1772 | |
1da177e4 | 1773 | |
1da177e4 | 1774 | /* |
0e078e2f | 1775 | * APIC command line parameters |
1da177e4 | 1776 | */ |
789fa735 | 1777 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1778 | { |
1da177e4 | 1779 | disable_apic = 1; |
9175fc06 | 1780 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1781 | return 0; |
1782 | } | |
1783 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1784 | |
2c8c0e6b | 1785 | /* same as disableapic, for compatibility */ |
789fa735 | 1786 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1787 | { |
789fa735 | 1788 | return setup_disableapic(arg); |
6935d1f9 | 1789 | } |
2c8c0e6b | 1790 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1791 | |
2e7c2838 LT |
1792 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1793 | { | |
1794 | local_apic_timer_c2_ok = 1; | |
1795 | return 0; | |
1796 | } | |
1797 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1798 | ||
36fef094 | 1799 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1800 | { |
1da177e4 | 1801 | disable_apic_timer = 1; |
36fef094 | 1802 | return 0; |
6935d1f9 | 1803 | } |
36fef094 CG |
1804 | early_param("noapictimer", parse_disable_apic_timer); |
1805 | ||
1806 | static int __init parse_nolapic_timer(char *arg) | |
1807 | { | |
1808 | disable_apic_timer = 1; | |
1809 | return 0; | |
6935d1f9 | 1810 | } |
36fef094 | 1811 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1812 | |
920fa7a5 | 1813 | #ifdef CONFIG_X86_64 |
0c3749c4 AK |
1814 | static __init int setup_apicpmtimer(char *s) |
1815 | { | |
1816 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1817 | notsc_setup(NULL); |
b8ce3359 | 1818 | return 0; |
0c3749c4 AK |
1819 | } |
1820 | __setup("apicpmtimer", setup_apicpmtimer); | |
920fa7a5 | 1821 | #endif |
0c3749c4 | 1822 | |
79af9bec CG |
1823 | static int __init apic_set_verbosity(char *arg) |
1824 | { | |
1825 | if (!arg) { | |
1826 | #ifdef CONFIG_X86_64 | |
1827 | skip_ioapic_setup = 0; | |
79af9bec CG |
1828 | return 0; |
1829 | #endif | |
1830 | return -EINVAL; | |
1831 | } | |
1832 | ||
1833 | if (strcmp("debug", arg) == 0) | |
1834 | apic_verbosity = APIC_DEBUG; | |
1835 | else if (strcmp("verbose", arg) == 0) | |
1836 | apic_verbosity = APIC_VERBOSE; | |
1837 | else { | |
1838 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1839 | " use apic=verbose or apic=debug\n", arg); | |
1840 | return -EINVAL; | |
1841 | } | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | early_param("apic", apic_set_verbosity); | |
1846 | ||
1e934dda YL |
1847 | static int __init lapic_insert_resource(void) |
1848 | { | |
1849 | if (!apic_phys) | |
1850 | return -1; | |
1851 | ||
1852 | /* Put local APIC into the resource map. */ | |
1853 | lapic_resource.start = apic_phys; | |
1854 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1855 | insert_resource(&iomem_resource, &lapic_resource); | |
1856 | ||
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | /* | |
1861 | * need call insert after e820_reserve_resources() | |
1862 | * that is using request_resource | |
1863 | */ | |
1864 | late_initcall(lapic_insert_resource); |