Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
e83a5fdc | 36 | #include <asm/hpet.h> |
1da177e4 | 37 | #include <asm/pgalloc.h> |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
6e1cb38a | 43 | #include <asm/i8259.h> |
1da177e4 | 44 | |
5af5573e | 45 | #include <mach_ipi.h> |
dd46e3ca | 46 | #include <mach_apic.h> |
5af5573e | 47 | |
36fef094 | 48 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 49 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 50 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 51 | int disable_apic; |
6e1cb38a | 52 | int disable_x2apic; |
89027d35 | 53 | int x2apic; |
1da177e4 | 54 | |
6e1cb38a SS |
55 | /* x2apic enabled before OS handover */ |
56 | int x2apic_preenabled; | |
1da177e4 | 57 | |
e83a5fdc | 58 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
59 | int local_apic_timer_c2_ok; |
60 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
61 | ||
e83a5fdc HS |
62 | /* |
63 | * Debug level, exported for io_apic.c | |
64 | */ | |
baa13188 | 65 | unsigned int apic_verbosity; |
e83a5fdc | 66 | |
bab4b27c AS |
67 | /* Have we found an MP table */ |
68 | int smp_found_config; | |
69 | ||
39928722 AD |
70 | static struct resource lapic_resource = { |
71 | .name = "Local APIC", | |
72 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
73 | }; | |
74 | ||
d03030e9 TG |
75 | static unsigned int calibration_result; |
76 | ||
ba7eda4c TG |
77 | static int lapic_next_event(unsigned long delta, |
78 | struct clock_event_device *evt); | |
79 | static void lapic_timer_setup(enum clock_event_mode mode, | |
80 | struct clock_event_device *evt); | |
ba7eda4c | 81 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 82 | static void apic_pm_activate(void); |
ba7eda4c | 83 | |
274cfe59 CG |
84 | /* |
85 | * The local apic timer can be used for any function which is CPU local. | |
86 | */ | |
ba7eda4c TG |
87 | static struct clock_event_device lapic_clockevent = { |
88 | .name = "lapic", | |
89 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
90 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
91 | .shift = 32, | |
92 | .set_mode = lapic_timer_setup, | |
93 | .set_next_event = lapic_next_event, | |
94 | .broadcast = lapic_timer_broadcast, | |
95 | .rating = 100, | |
96 | .irq = -1, | |
97 | }; | |
98 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
99 | ||
d3432896 AK |
100 | static unsigned long apic_phys; |
101 | ||
3f530709 AS |
102 | unsigned long mp_lapic_addr; |
103 | ||
0e078e2f TG |
104 | /* |
105 | * Get the LAPIC version | |
106 | */ | |
107 | static inline int lapic_get_version(void) | |
ba7eda4c | 108 | { |
0e078e2f | 109 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
110 | } |
111 | ||
0e078e2f | 112 | /* |
9c803869 | 113 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
114 | */ |
115 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 116 | { |
9c803869 | 117 | #ifdef CONFIG_X86_64 |
0e078e2f | 118 | return 1; |
9c803869 CG |
119 | #else |
120 | return APIC_INTEGRATED(lapic_get_version()); | |
121 | #endif | |
ba7eda4c TG |
122 | } |
123 | ||
124 | /* | |
0e078e2f | 125 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 126 | */ |
0e078e2f | 127 | static int modern_apic(void) |
ba7eda4c | 128 | { |
0e078e2f TG |
129 | /* AMD systems use old APIC versions, so check the CPU */ |
130 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
131 | boot_cpu_data.x86 >= 0xf) | |
132 | return 1; | |
133 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
134 | } |
135 | ||
274cfe59 CG |
136 | /* |
137 | * Paravirt kernels also might be using these below ops. So we still | |
138 | * use generic apic_read()/apic_write(), which might be pointing to different | |
139 | * ops in PARAVIRT case. | |
140 | */ | |
1b374e4d | 141 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
142 | { |
143 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
144 | cpu_relax(); | |
145 | } | |
146 | ||
1b374e4d | 147 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 148 | { |
3c6bb07a | 149 | u32 send_status; |
8339e9fb FLV |
150 | int timeout; |
151 | ||
152 | timeout = 0; | |
153 | do { | |
154 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
155 | if (!send_status) | |
156 | break; | |
157 | udelay(100); | |
158 | } while (timeout++ < 1000); | |
159 | ||
160 | return send_status; | |
161 | } | |
162 | ||
1b374e4d SS |
163 | void xapic_icr_write(u32 low, u32 id) |
164 | { | |
ed4e5ec1 | 165 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
166 | apic_write(APIC_ICR, low); |
167 | } | |
168 | ||
169 | u64 xapic_icr_read(void) | |
170 | { | |
171 | u32 icr1, icr2; | |
172 | ||
173 | icr2 = apic_read(APIC_ICR2); | |
174 | icr1 = apic_read(APIC_ICR); | |
175 | ||
cf9768d7 | 176 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
177 | } |
178 | ||
179 | static struct apic_ops xapic_ops = { | |
180 | .read = native_apic_mem_read, | |
181 | .write = native_apic_mem_write, | |
1b374e4d SS |
182 | .icr_read = xapic_icr_read, |
183 | .icr_write = xapic_icr_write, | |
184 | .wait_icr_idle = xapic_wait_icr_idle, | |
185 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
186 | }; | |
187 | ||
188 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
189 | EXPORT_SYMBOL_GPL(apic_ops); |
190 | ||
13c88fb5 SS |
191 | static void x2apic_wait_icr_idle(void) |
192 | { | |
193 | /* no need to wait for icr idle in x2apic */ | |
194 | return; | |
195 | } | |
196 | ||
197 | static u32 safe_x2apic_wait_icr_idle(void) | |
198 | { | |
199 | /* no need to wait for icr idle in x2apic */ | |
200 | return 0; | |
201 | } | |
202 | ||
203 | void x2apic_icr_write(u32 low, u32 id) | |
204 | { | |
205 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
206 | } | |
207 | ||
208 | u64 x2apic_icr_read(void) | |
209 | { | |
210 | unsigned long val; | |
211 | ||
212 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
213 | return val; | |
214 | } | |
215 | ||
216 | static struct apic_ops x2apic_ops = { | |
217 | .read = native_apic_msr_read, | |
218 | .write = native_apic_msr_write, | |
13c88fb5 SS |
219 | .icr_read = x2apic_icr_read, |
220 | .icr_write = x2apic_icr_write, | |
221 | .wait_icr_idle = x2apic_wait_icr_idle, | |
222 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
223 | }; | |
224 | ||
0e078e2f TG |
225 | /** |
226 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
227 | */ | |
e9427101 | 228 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 229 | { |
11a8e778 | 230 | unsigned int v; |
6935d1f9 TG |
231 | |
232 | /* unmask and set to NMI */ | |
233 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
234 | |
235 | /* Level triggered for 82489DX (32bit mode) */ | |
236 | if (!lapic_is_integrated()) | |
237 | v |= APIC_LVT_LEVEL_TRIGGER; | |
238 | ||
11a8e778 | 239 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
240 | } |
241 | ||
0e078e2f TG |
242 | /** |
243 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
244 | */ | |
37e650c7 | 245 | int lapic_get_maxlvt(void) |
1da177e4 | 246 | { |
36a028de | 247 | unsigned int v; |
1da177e4 LT |
248 | |
249 | v = apic_read(APIC_LVR); | |
36a028de CG |
250 | /* |
251 | * - we always have APIC integrated on 64bit mode | |
252 | * - 82489DXs do not report # of LVT entries | |
253 | */ | |
254 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
255 | } |
256 | ||
274cfe59 CG |
257 | /* |
258 | * Local APIC timer | |
259 | */ | |
260 | ||
c40aaec6 CG |
261 | /* Clock divisor */ |
262 | #ifdef CONFG_X86_64 | |
f07f4f90 | 263 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
264 | #else |
265 | #define APIC_DIVISOR 16 | |
266 | #endif | |
f07f4f90 | 267 | |
0e078e2f TG |
268 | /* |
269 | * This function sets up the local APIC timer, with a timeout of | |
270 | * 'clocks' APIC bus clock. During calibration we actually call | |
271 | * this function twice on the boot CPU, once with a bogus timeout | |
272 | * value, second time for real. The other (noncalibrating) CPUs | |
273 | * call this function only once, with the real, calibrated value. | |
274 | * | |
275 | * We do reads before writes even if unnecessary, to get around the | |
276 | * P5 APIC double write bug. | |
277 | */ | |
0e078e2f | 278 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 279 | { |
0e078e2f | 280 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 281 | |
0e078e2f TG |
282 | lvtt_value = LOCAL_TIMER_VECTOR; |
283 | if (!oneshot) | |
284 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
285 | if (!lapic_is_integrated()) |
286 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
287 | ||
0e078e2f TG |
288 | if (!irqen) |
289 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 290 | |
0e078e2f | 291 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
292 | |
293 | /* | |
0e078e2f | 294 | * Divide PICLK by 16 |
1da177e4 | 295 | */ |
0e078e2f | 296 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
297 | apic_write(APIC_TDCR, |
298 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
299 | APIC_TDR_DIV_16); | |
0e078e2f TG |
300 | |
301 | if (!oneshot) | |
f07f4f90 | 302 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
303 | } |
304 | ||
0e078e2f | 305 | /* |
7b83dae7 RR |
306 | * Setup extended LVT, AMD specific (K8, family 10h) |
307 | * | |
308 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
309 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
310 | * |
311 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
312 | * enables the vector. See also the BKDGs. | |
0e078e2f | 313 | */ |
7b83dae7 RR |
314 | |
315 | #define APIC_EILVT_LVTOFF_MCE 0 | |
316 | #define APIC_EILVT_LVTOFF_IBS 1 | |
317 | ||
318 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 319 | { |
7b83dae7 | 320 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 321 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 322 | |
0e078e2f | 323 | apic_write(reg, v); |
1da177e4 LT |
324 | } |
325 | ||
7b83dae7 RR |
326 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
327 | { | |
328 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
329 | return APIC_EILVT_LVTOFF_MCE; | |
330 | } | |
331 | ||
332 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
333 | { | |
334 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
335 | return APIC_EILVT_LVTOFF_IBS; | |
336 | } | |
6aa360e6 | 337 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 338 | |
0e078e2f TG |
339 | /* |
340 | * Program the next event, relative to now | |
341 | */ | |
342 | static int lapic_next_event(unsigned long delta, | |
343 | struct clock_event_device *evt) | |
1da177e4 | 344 | { |
0e078e2f TG |
345 | apic_write(APIC_TMICT, delta); |
346 | return 0; | |
1da177e4 LT |
347 | } |
348 | ||
0e078e2f TG |
349 | /* |
350 | * Setup the lapic timer in periodic or oneshot mode | |
351 | */ | |
352 | static void lapic_timer_setup(enum clock_event_mode mode, | |
353 | struct clock_event_device *evt) | |
9b7711f0 HS |
354 | { |
355 | unsigned long flags; | |
0e078e2f | 356 | unsigned int v; |
9b7711f0 | 357 | |
0e078e2f TG |
358 | /* Lapic used as dummy for broadcast ? */ |
359 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
360 | return; |
361 | ||
362 | local_irq_save(flags); | |
363 | ||
0e078e2f TG |
364 | switch (mode) { |
365 | case CLOCK_EVT_MODE_PERIODIC: | |
366 | case CLOCK_EVT_MODE_ONESHOT: | |
367 | __setup_APIC_LVTT(calibration_result, | |
368 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
369 | break; | |
370 | case CLOCK_EVT_MODE_UNUSED: | |
371 | case CLOCK_EVT_MODE_SHUTDOWN: | |
372 | v = apic_read(APIC_LVTT); | |
373 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
374 | apic_write(APIC_LVTT, v); | |
375 | break; | |
376 | case CLOCK_EVT_MODE_RESUME: | |
377 | /* Nothing to do here */ | |
378 | break; | |
379 | } | |
9b7711f0 HS |
380 | |
381 | local_irq_restore(flags); | |
382 | } | |
383 | ||
1da177e4 | 384 | /* |
0e078e2f | 385 | * Local APIC timer broadcast function |
1da177e4 | 386 | */ |
0e078e2f | 387 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 388 | { |
0e078e2f TG |
389 | #ifdef CONFIG_SMP |
390 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
391 | #endif | |
392 | } | |
1da177e4 | 393 | |
0e078e2f TG |
394 | /* |
395 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
396 | * of the boot CPU and register the clock event in the framework. | |
397 | */ | |
398 | static void setup_APIC_timer(void) | |
399 | { | |
400 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 401 | |
0e078e2f TG |
402 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
403 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 404 | |
0e078e2f TG |
405 | clockevents_register_device(levt); |
406 | } | |
1da177e4 | 407 | |
0e078e2f TG |
408 | /* |
409 | * In this function we calibrate APIC bus clocks to the external | |
410 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
411 | * to calibrate, since some later bootup code depends on getting | |
412 | * the first irq? Ugh. | |
413 | * | |
414 | * We want to do the calibration only once since we | |
415 | * want to have local timer irqs syncron. CPUs connected | |
416 | * by the same APIC bus have the very same bus frequency. | |
417 | * And we want to have irqs off anyways, no accidental | |
418 | * APIC irq that way. | |
419 | */ | |
420 | ||
421 | #define TICK_COUNT 100000000 | |
422 | ||
89b3b1f4 | 423 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
424 | { |
425 | unsigned apic, apic_start; | |
426 | unsigned long tsc, tsc_start; | |
427 | int result; | |
428 | ||
429 | local_irq_disable(); | |
430 | ||
431 | /* | |
432 | * Put whatever arbitrary (but long enough) timeout | |
433 | * value into the APIC clock, we just want to get the | |
434 | * counter running for calibration. | |
435 | * | |
436 | * No interrupt enable ! | |
437 | */ | |
438 | __setup_APIC_LVTT(250000000, 0, 0); | |
439 | ||
440 | apic_start = apic_read(APIC_TMCCT); | |
441 | #ifdef CONFIG_X86_PM_TIMER | |
442 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
443 | pmtimer_wait(5000); /* 5ms wait */ | |
444 | apic = apic_read(APIC_TMCCT); | |
445 | result = (apic_start - apic) * 1000L / 5; | |
446 | } else | |
447 | #endif | |
448 | { | |
449 | rdtscll(tsc_start); | |
450 | ||
451 | do { | |
452 | apic = apic_read(APIC_TMCCT); | |
453 | rdtscll(tsc); | |
454 | } while ((tsc - tsc_start) < TICK_COUNT && | |
455 | (apic_start - apic) < TICK_COUNT); | |
456 | ||
457 | result = (apic_start - apic) * 1000L * tsc_khz / | |
458 | (tsc - tsc_start); | |
459 | } | |
460 | ||
461 | local_irq_enable(); | |
462 | ||
463 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
464 | ||
465 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
466 | result / 1000 / 1000, result / 1000 % 1000); | |
467 | ||
468 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
469 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
470 | lapic_clockevent.shift); | |
0e078e2f TG |
471 | lapic_clockevent.max_delta_ns = |
472 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
473 | lapic_clockevent.min_delta_ns = | |
474 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
475 | ||
f07f4f90 | 476 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
477 | |
478 | /* | |
479 | * Do a sanity check on the APIC calibration result | |
480 | */ | |
481 | if (calibration_result < (1000000 / HZ)) { | |
482 | printk(KERN_WARNING | |
483 | "APIC frequency too slow, disabling apic timer\n"); | |
484 | return -1; | |
485 | } | |
486 | ||
487 | return 0; | |
0e078e2f TG |
488 | } |
489 | ||
e83a5fdc HS |
490 | /* |
491 | * Setup the boot APIC | |
492 | * | |
493 | * Calibrate and verify the result. | |
494 | */ | |
0e078e2f TG |
495 | void __init setup_boot_APIC_clock(void) |
496 | { | |
497 | /* | |
274cfe59 CG |
498 | * The local apic timer can be disabled via the kernel |
499 | * commandline or from the CPU detection code. Register the lapic | |
500 | * timer as a dummy clock event source on SMP systems, so the | |
501 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
502 | */ |
503 | if (disable_apic_timer) { | |
504 | printk(KERN_INFO "Disabling APIC timer\n"); | |
505 | /* No broadcast on UP ! */ | |
9d09951d TG |
506 | if (num_possible_cpus() > 1) { |
507 | lapic_clockevent.mult = 1; | |
0e078e2f | 508 | setup_APIC_timer(); |
9d09951d | 509 | } |
0e078e2f TG |
510 | return; |
511 | } | |
512 | ||
274cfe59 CG |
513 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
514 | "calibrating APIC timer ...\n"); | |
515 | ||
89b3b1f4 | 516 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
517 | /* No broadcast on UP ! */ |
518 | if (num_possible_cpus() > 1) | |
519 | setup_APIC_timer(); | |
520 | return; | |
521 | } | |
522 | ||
0e078e2f TG |
523 | /* |
524 | * If nmi_watchdog is set to IO_APIC, we need the | |
525 | * PIT/HPET going. Otherwise register lapic as a dummy | |
526 | * device. | |
527 | */ | |
528 | if (nmi_watchdog != NMI_IO_APIC) | |
529 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
530 | else | |
531 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 532 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 533 | |
274cfe59 | 534 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
535 | setup_APIC_timer(); |
536 | } | |
537 | ||
0e078e2f TG |
538 | void __cpuinit setup_secondary_APIC_clock(void) |
539 | { | |
0e078e2f TG |
540 | setup_APIC_timer(); |
541 | } | |
542 | ||
543 | /* | |
544 | * The guts of the apic timer interrupt | |
545 | */ | |
546 | static void local_apic_timer_interrupt(void) | |
547 | { | |
548 | int cpu = smp_processor_id(); | |
549 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
550 | ||
551 | /* | |
552 | * Normally we should not be here till LAPIC has been initialized but | |
553 | * in some cases like kdump, its possible that there is a pending LAPIC | |
554 | * timer interrupt from previous kernel's context and is delivered in | |
555 | * new kernel the moment interrupts are enabled. | |
556 | * | |
557 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
558 | * its possible that when we get here evt->event_handler is NULL. | |
559 | * Check for event_handler being NULL and discard the interrupt as | |
560 | * spurious. | |
561 | */ | |
562 | if (!evt->event_handler) { | |
563 | printk(KERN_WARNING | |
564 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
565 | /* Switch it off */ | |
566 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
567 | return; | |
568 | } | |
569 | ||
570 | /* | |
571 | * the NMI deadlock-detector uses this. | |
572 | */ | |
0b23e8cf | 573 | #ifdef CONFIG_X86_64 |
0e078e2f | 574 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
575 | #else |
576 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
577 | #endif | |
0e078e2f TG |
578 | |
579 | evt->event_handler(evt); | |
580 | } | |
581 | ||
582 | /* | |
583 | * Local APIC timer interrupt. This is the most natural way for doing | |
584 | * local interrupts, but local timer interrupts can be emulated by | |
585 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
586 | * | |
587 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
588 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
589 | */ | |
590 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
591 | { | |
592 | struct pt_regs *old_regs = set_irq_regs(regs); | |
593 | ||
594 | /* | |
595 | * NOTE! We'd better ACK the irq immediately, | |
596 | * because timer handling can be slow. | |
597 | */ | |
598 | ack_APIC_irq(); | |
599 | /* | |
600 | * update_process_times() expects us to have done irq_enter(). | |
601 | * Besides, if we don't timer interrupts ignore the global | |
602 | * interrupt lock, which is the WrongThing (tm) to do. | |
603 | */ | |
604 | exit_idle(); | |
605 | irq_enter(); | |
606 | local_apic_timer_interrupt(); | |
607 | irq_exit(); | |
274cfe59 | 608 | |
0e078e2f TG |
609 | set_irq_regs(old_regs); |
610 | } | |
611 | ||
612 | int setup_profiling_timer(unsigned int multiplier) | |
613 | { | |
614 | return -EINVAL; | |
615 | } | |
616 | ||
617 | ||
618 | /* | |
619 | * Local APIC start and shutdown | |
620 | */ | |
621 | ||
622 | /** | |
623 | * clear_local_APIC - shutdown the local APIC | |
624 | * | |
625 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
626 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
627 | * leftovers during boot. | |
628 | */ | |
629 | void clear_local_APIC(void) | |
630 | { | |
2584a82d | 631 | int maxlvt; |
0e078e2f TG |
632 | u32 v; |
633 | ||
d3432896 AK |
634 | /* APIC hasn't been mapped yet */ |
635 | if (!apic_phys) | |
636 | return; | |
637 | ||
638 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
639 | /* |
640 | * Masking an LVT entry can trigger a local APIC error | |
641 | * if the vector is zero. Mask LVTERR first to prevent this. | |
642 | */ | |
643 | if (maxlvt >= 3) { | |
644 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
645 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
646 | } | |
647 | /* | |
648 | * Careful: we have to set masks only first to deassert | |
649 | * any level-triggered sources. | |
650 | */ | |
651 | v = apic_read(APIC_LVTT); | |
652 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
653 | v = apic_read(APIC_LVT0); | |
654 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
655 | v = apic_read(APIC_LVT1); | |
656 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
657 | if (maxlvt >= 4) { | |
658 | v = apic_read(APIC_LVTPC); | |
659 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
660 | } | |
661 | ||
6764014b CG |
662 | /* lets not touch this if we didn't frob it */ |
663 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
664 | if (maxlvt >= 5) { | |
665 | v = apic_read(APIC_LVTTHMR); | |
666 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
667 | } | |
668 | #endif | |
0e078e2f TG |
669 | /* |
670 | * Clean APIC state for other OSs: | |
671 | */ | |
672 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
673 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
674 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
675 | if (maxlvt >= 3) | |
676 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
677 | if (maxlvt >= 4) | |
678 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
679 | |
680 | /* Integrated APIC (!82489DX) ? */ | |
681 | if (lapic_is_integrated()) { | |
682 | if (maxlvt > 3) | |
683 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
684 | apic_write(APIC_ESR, 0); | |
685 | apic_read(APIC_ESR); | |
686 | } | |
0e078e2f TG |
687 | } |
688 | ||
689 | /** | |
690 | * disable_local_APIC - clear and disable the local APIC | |
691 | */ | |
692 | void disable_local_APIC(void) | |
693 | { | |
694 | unsigned int value; | |
695 | ||
696 | clear_local_APIC(); | |
697 | ||
698 | /* | |
699 | * Disable APIC (implies clearing of registers | |
700 | * for 82489DX!). | |
701 | */ | |
702 | value = apic_read(APIC_SPIV); | |
703 | value &= ~APIC_SPIV_APIC_ENABLED; | |
704 | apic_write(APIC_SPIV, value); | |
990b183e CG |
705 | |
706 | #ifdef CONFIG_X86_32 | |
707 | /* | |
708 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
709 | * restore the disabled state. | |
710 | */ | |
711 | if (enabled_via_apicbase) { | |
712 | unsigned int l, h; | |
713 | ||
714 | rdmsr(MSR_IA32_APICBASE, l, h); | |
715 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
716 | wrmsr(MSR_IA32_APICBASE, l, h); | |
717 | } | |
718 | #endif | |
0e078e2f TG |
719 | } |
720 | ||
fe4024dc CG |
721 | /* |
722 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
723 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
724 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
725 | * for the case where Linux didn't enable the LAPIC. | |
726 | */ | |
0e078e2f TG |
727 | void lapic_shutdown(void) |
728 | { | |
729 | unsigned long flags; | |
730 | ||
731 | if (!cpu_has_apic) | |
732 | return; | |
733 | ||
734 | local_irq_save(flags); | |
735 | ||
fe4024dc CG |
736 | #ifdef CONFIG_X86_32 |
737 | if (!enabled_via_apicbase) | |
738 | clear_local_APIC(); | |
739 | else | |
740 | #endif | |
741 | disable_local_APIC(); | |
742 | ||
0e078e2f TG |
743 | |
744 | local_irq_restore(flags); | |
745 | } | |
746 | ||
747 | /* | |
748 | * This is to verify that we're looking at a real local APIC. | |
749 | * Check these against your board if the CPUs aren't getting | |
750 | * started for no apparent reason. | |
751 | */ | |
752 | int __init verify_local_APIC(void) | |
753 | { | |
754 | unsigned int reg0, reg1; | |
755 | ||
756 | /* | |
757 | * The version register is read-only in a real APIC. | |
758 | */ | |
759 | reg0 = apic_read(APIC_LVR); | |
760 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
761 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
762 | reg1 = apic_read(APIC_LVR); | |
763 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
764 | ||
765 | /* | |
766 | * The two version reads above should print the same | |
767 | * numbers. If the second one is different, then we | |
768 | * poke at a non-APIC. | |
769 | */ | |
770 | if (reg1 != reg0) | |
771 | return 0; | |
772 | ||
773 | /* | |
774 | * Check if the version looks reasonably. | |
775 | */ | |
776 | reg1 = GET_APIC_VERSION(reg0); | |
777 | if (reg1 == 0x00 || reg1 == 0xff) | |
778 | return 0; | |
779 | reg1 = lapic_get_maxlvt(); | |
780 | if (reg1 < 0x02 || reg1 == 0xff) | |
781 | return 0; | |
782 | ||
783 | /* | |
784 | * The ID register is read/write in a real APIC. | |
785 | */ | |
2d7a66d0 | 786 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
787 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
788 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 789 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
790 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
791 | apic_write(APIC_ID, reg0); | |
792 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
793 | return 0; | |
794 | ||
795 | /* | |
1da177e4 LT |
796 | * The next two are just to see if we have sane values. |
797 | * They're only really relevant if we're in Virtual Wire | |
798 | * compatibility mode, but most boxes are anymore. | |
799 | */ | |
800 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 801 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
802 | reg1 = apic_read(APIC_LVT1); |
803 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
804 | ||
805 | return 1; | |
806 | } | |
807 | ||
0e078e2f TG |
808 | /** |
809 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
810 | */ | |
1da177e4 LT |
811 | void __init sync_Arb_IDs(void) |
812 | { | |
296cb951 CG |
813 | /* |
814 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
815 | * needed on AMD. | |
816 | */ | |
817 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
818 | return; |
819 | ||
820 | /* | |
821 | * Wait for idle. | |
822 | */ | |
823 | apic_wait_icr_idle(); | |
824 | ||
825 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
826 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
827 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
828 | } |
829 | ||
1da177e4 LT |
830 | /* |
831 | * An initial setup of the virtual wire mode. | |
832 | */ | |
833 | void __init init_bsp_APIC(void) | |
834 | { | |
11a8e778 | 835 | unsigned int value; |
1da177e4 LT |
836 | |
837 | /* | |
838 | * Don't do the setup now if we have a SMP BIOS as the | |
839 | * through-I/O-APIC virtual wire mode might be active. | |
840 | */ | |
841 | if (smp_found_config || !cpu_has_apic) | |
842 | return; | |
843 | ||
1da177e4 LT |
844 | /* |
845 | * Do not trust the local APIC being empty at bootup. | |
846 | */ | |
847 | clear_local_APIC(); | |
848 | ||
849 | /* | |
850 | * Enable APIC. | |
851 | */ | |
852 | value = apic_read(APIC_SPIV); | |
853 | value &= ~APIC_VECTOR_MASK; | |
854 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
855 | |
856 | #ifdef CONFIG_X86_32 | |
857 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
858 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
859 | (boot_cpu_data.x86 == 15)) | |
860 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
861 | else | |
862 | #endif | |
863 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 864 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 865 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
866 | |
867 | /* | |
868 | * Set up the virtual wire mode. | |
869 | */ | |
11a8e778 | 870 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 871 | value = APIC_DM_NMI; |
638c0411 CG |
872 | if (!lapic_is_integrated()) /* 82489DX */ |
873 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 874 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
875 | } |
876 | ||
c43da2f5 CG |
877 | static void __cpuinit lapic_setup_esr(void) |
878 | { | |
879 | unsigned long oldvalue, value, maxlvt; | |
880 | if (lapic_is_integrated() && !esr_disable) { | |
881 | if (esr_disable) { | |
882 | /* | |
883 | * Something untraceable is creating bad interrupts on | |
884 | * secondary quads ... for the moment, just leave the | |
885 | * ESR disabled - we can't do anything useful with the | |
886 | * errors anyway - mbligh | |
887 | */ | |
888 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
889 | return; | |
890 | } | |
891 | /* !82489DX */ | |
892 | maxlvt = lapic_get_maxlvt(); | |
893 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
894 | apic_write(APIC_ESR, 0); | |
895 | oldvalue = apic_read(APIC_ESR); | |
896 | ||
897 | /* enables sending errors */ | |
898 | value = ERROR_APIC_VECTOR; | |
899 | apic_write(APIC_LVTERR, value); | |
900 | /* | |
901 | * spec says clear errors after enabling vector. | |
902 | */ | |
903 | if (maxlvt > 3) | |
904 | apic_write(APIC_ESR, 0); | |
905 | value = apic_read(APIC_ESR); | |
906 | if (value != oldvalue) | |
907 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
908 | "vector: 0x%08lx after: 0x%08lx\n", | |
909 | oldvalue, value); | |
910 | } else { | |
911 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
912 | } | |
913 | } | |
914 | ||
915 | ||
0e078e2f TG |
916 | /** |
917 | * setup_local_APIC - setup the local APIC | |
918 | */ | |
919 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 920 | { |
739f33b3 | 921 | unsigned int value; |
da7ed9f9 | 922 | int i, j; |
1da177e4 | 923 | |
ac23d4ee | 924 | preempt_disable(); |
1da177e4 | 925 | value = apic_read(APIC_LVR); |
1da177e4 | 926 | |
fe7414a2 | 927 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
928 | |
929 | /* | |
930 | * Double-check whether this APIC is really registered. | |
931 | * This is meaningless in clustered apic mode, so we skip it. | |
932 | */ | |
933 | if (!apic_id_registered()) | |
934 | BUG(); | |
935 | ||
936 | /* | |
937 | * Intel recommends to set DFR, LDR and TPR before enabling | |
938 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
939 | * document number 292116). So here it goes... | |
940 | */ | |
941 | init_apic_ldr(); | |
942 | ||
943 | /* | |
944 | * Set Task Priority to 'accept all'. We never change this | |
945 | * later on. | |
946 | */ | |
947 | value = apic_read(APIC_TASKPRI); | |
948 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 949 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 950 | |
da7ed9f9 VG |
951 | /* |
952 | * After a crash, we no longer service the interrupts and a pending | |
953 | * interrupt from previous kernel might still have ISR bit set. | |
954 | * | |
955 | * Most probably by now CPU has serviced that pending interrupt and | |
956 | * it might not have done the ack_APIC_irq() because it thought, | |
957 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
958 | * does not clear the ISR bit and cpu thinks it has already serivced | |
959 | * the interrupt. Hence a vector might get locked. It was noticed | |
960 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
961 | */ | |
962 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
963 | value = apic_read(APIC_ISR + i*0x10); | |
964 | for (j = 31; j >= 0; j--) { | |
965 | if (value & (1<<j)) | |
966 | ack_APIC_irq(); | |
967 | } | |
968 | } | |
969 | ||
1da177e4 LT |
970 | /* |
971 | * Now that we are all set up, enable the APIC | |
972 | */ | |
973 | value = apic_read(APIC_SPIV); | |
974 | value &= ~APIC_VECTOR_MASK; | |
975 | /* | |
976 | * Enable APIC | |
977 | */ | |
978 | value |= APIC_SPIV_APIC_ENABLED; | |
979 | ||
3f14c746 AK |
980 | /* We always use processor focus */ |
981 | ||
1da177e4 LT |
982 | /* |
983 | * Set spurious IRQ vector | |
984 | */ | |
985 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 986 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
987 | |
988 | /* | |
989 | * Set up LVT0, LVT1: | |
990 | * | |
991 | * set up through-local-APIC on the BP's LINT0. This is not | |
992 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
993 | * we delegate interrupts to the 8259A. | |
994 | */ | |
995 | /* | |
996 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
997 | */ | |
998 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 999 | if (!smp_processor_id() && !value) { |
1da177e4 | 1000 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
1001 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
1002 | smp_processor_id()); | |
1da177e4 LT |
1003 | } else { |
1004 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
1005 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
1006 | smp_processor_id()); | |
1da177e4 | 1007 | } |
11a8e778 | 1008 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1009 | |
1010 | /* | |
1011 | * only the BP should see the LINT1 NMI signal, obviously. | |
1012 | */ | |
1013 | if (!smp_processor_id()) | |
1014 | value = APIC_DM_NMI; | |
1015 | else | |
1016 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 1017 | apic_write(APIC_LVT1, value); |
ac23d4ee | 1018 | preempt_enable(); |
739f33b3 | 1019 | } |
1da177e4 | 1020 | |
739f33b3 AK |
1021 | void __cpuinit end_local_APIC_setup(void) |
1022 | { | |
1023 | lapic_setup_esr(); | |
fa6b95fc CG |
1024 | |
1025 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1026 | { |
1027 | unsigned int value; | |
1028 | /* Disable the local apic timer */ | |
1029 | value = apic_read(APIC_LVTT); | |
1030 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1031 | apic_write(APIC_LVTT, value); | |
1032 | } | |
fa6b95fc CG |
1033 | #endif |
1034 | ||
f2802e7f | 1035 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1036 | apic_pm_activate(); |
1da177e4 | 1037 | } |
1da177e4 | 1038 | |
6e1cb38a SS |
1039 | void check_x2apic(void) |
1040 | { | |
1041 | int msr, msr2; | |
1042 | ||
1043 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1044 | ||
1045 | if (msr & X2APIC_ENABLE) { | |
1046 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1047 | x2apic_preenabled = x2apic = 1; | |
1048 | apic_ops = &x2apic_ops; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | void enable_x2apic(void) | |
1053 | { | |
1054 | int msr, msr2; | |
1055 | ||
1056 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1057 | if (!(msr & X2APIC_ENABLE)) { | |
1058 | printk("Enabling x2apic\n"); | |
1059 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | void enable_IR_x2apic(void) | |
1064 | { | |
1065 | #ifdef CONFIG_INTR_REMAP | |
1066 | int ret; | |
1067 | unsigned long flags; | |
1068 | ||
1069 | if (!cpu_has_x2apic) | |
1070 | return; | |
1071 | ||
1072 | if (!x2apic_preenabled && disable_x2apic) { | |
1073 | printk(KERN_INFO | |
1074 | "Skipped enabling x2apic and Interrupt-remapping " | |
1075 | "because of nox2apic\n"); | |
1076 | return; | |
1077 | } | |
1078 | ||
1079 | if (x2apic_preenabled && disable_x2apic) | |
1080 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1081 | ||
1082 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1083 | printk(KERN_INFO | |
1084 | "Skipped enabling x2apic and Interrupt-remapping " | |
1085 | "because of skipping io-apic setup\n"); | |
1086 | return; | |
1087 | } | |
1088 | ||
1089 | ret = dmar_table_init(); | |
1090 | if (ret) { | |
1091 | printk(KERN_INFO | |
1092 | "dmar_table_init() failed with %d:\n", ret); | |
1093 | ||
1094 | if (x2apic_preenabled) | |
1095 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1096 | else | |
1097 | printk(KERN_INFO | |
1098 | "Not enabling x2apic,Intr-remapping\n"); | |
1099 | return; | |
1100 | } | |
1101 | ||
1102 | local_irq_save(flags); | |
1103 | mask_8259A(); | |
1104 | save_mask_IO_APIC_setup(); | |
1105 | ||
1106 | ret = enable_intr_remapping(1); | |
1107 | ||
1108 | if (ret && x2apic_preenabled) { | |
1109 | local_irq_restore(flags); | |
1110 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1111 | } | |
1112 | ||
1113 | if (ret) | |
1114 | goto end; | |
1115 | ||
1116 | if (!x2apic) { | |
1117 | x2apic = 1; | |
1118 | apic_ops = &x2apic_ops; | |
1119 | enable_x2apic(); | |
1120 | } | |
1121 | end: | |
1122 | if (ret) | |
1123 | /* | |
1124 | * IR enabling failed | |
1125 | */ | |
1126 | restore_IO_APIC_setup(); | |
1127 | else | |
1128 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1129 | ||
1130 | unmask_8259A(); | |
1131 | local_irq_restore(flags); | |
1132 | ||
1133 | if (!ret) { | |
1134 | if (!x2apic_preenabled) | |
1135 | printk(KERN_INFO | |
1136 | "Enabled x2apic and interrupt-remapping\n"); | |
1137 | else | |
1138 | printk(KERN_INFO | |
1139 | "Enabled Interrupt-remapping\n"); | |
1140 | } else | |
1141 | printk(KERN_ERR | |
1142 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1143 | #else | |
1144 | if (!cpu_has_x2apic) | |
1145 | return; | |
1146 | ||
1147 | if (x2apic_preenabled) | |
1148 | panic("x2apic enabled prior OS handover," | |
1149 | " enable CONFIG_INTR_REMAP"); | |
1150 | ||
1151 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1152 | " and x2apic\n"); | |
1153 | #endif | |
1154 | ||
1155 | return; | |
1156 | } | |
1157 | ||
1da177e4 LT |
1158 | /* |
1159 | * Detect and enable local APICs on non-SMP boards. | |
1160 | * Original code written by Keir Fraser. | |
1161 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1162 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1163 | */ |
0e078e2f | 1164 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1165 | { |
1166 | if (!cpu_has_apic) { | |
1167 | printk(KERN_INFO "No local APIC present\n"); | |
1168 | return -1; | |
1169 | } | |
1170 | ||
1171 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1172 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1173 | return 0; |
1174 | } | |
1175 | ||
8643f9d0 YL |
1176 | void __init early_init_lapic_mapping(void) |
1177 | { | |
431ee79d | 1178 | unsigned long phys_addr; |
8643f9d0 YL |
1179 | |
1180 | /* | |
1181 | * If no local APIC can be found then go out | |
1182 | * : it means there is no mpatable and MADT | |
1183 | */ | |
1184 | if (!smp_found_config) | |
1185 | return; | |
1186 | ||
431ee79d | 1187 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1188 | |
431ee79d | 1189 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1190 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1191 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1192 | |
1193 | /* | |
1194 | * Fetch the APIC ID of the BSP in case we have a | |
1195 | * default configuration (or the MP table is broken). | |
1196 | */ | |
4c9961d5 | 1197 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1198 | } |
1199 | ||
0e078e2f TG |
1200 | /** |
1201 | * init_apic_mappings - initialize APIC mappings | |
1202 | */ | |
1da177e4 LT |
1203 | void __init init_apic_mappings(void) |
1204 | { | |
6e1cb38a | 1205 | if (x2apic) { |
4c9961d5 | 1206 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1207 | return; |
1208 | } | |
1209 | ||
1da177e4 LT |
1210 | /* |
1211 | * If no local APIC can be found then set up a fake all | |
1212 | * zeroes page to simulate the local APIC and another | |
1213 | * one for the IO-APIC. | |
1214 | */ | |
1215 | if (!smp_found_config && detect_init_APIC()) { | |
1216 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1217 | apic_phys = __pa(apic_phys); | |
1218 | } else | |
1219 | apic_phys = mp_lapic_addr; | |
1220 | ||
1221 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1222 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1223 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1224 | |
1225 | /* | |
1226 | * Fetch the APIC ID of the BSP in case we have a | |
1227 | * default configuration (or the MP table is broken). | |
1228 | */ | |
4c9961d5 | 1229 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1230 | } |
1231 | ||
1232 | /* | |
0e078e2f TG |
1233 | * This initializes the IO-APIC and APIC hardware if this is |
1234 | * a UP kernel. | |
1da177e4 | 1235 | */ |
1b313f4a CG |
1236 | int apic_version[MAX_APICS]; |
1237 | ||
0e078e2f | 1238 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1239 | { |
0e078e2f TG |
1240 | if (disable_apic) { |
1241 | printk(KERN_INFO "Apic disabled\n"); | |
1242 | return -1; | |
1243 | } | |
1244 | if (!cpu_has_apic) { | |
1245 | disable_apic = 1; | |
1246 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1247 | return -1; | |
1248 | } | |
1da177e4 | 1249 | |
6e1cb38a SS |
1250 | enable_IR_x2apic(); |
1251 | setup_apic_routing(); | |
1252 | ||
0e078e2f | 1253 | verify_local_APIC(); |
1da177e4 | 1254 | |
b5841765 GC |
1255 | connect_bsp_APIC(); |
1256 | ||
b6df1b8b | 1257 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1258 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1259 | |
0e078e2f | 1260 | setup_local_APIC(); |
1da177e4 | 1261 | |
739f33b3 AK |
1262 | /* |
1263 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1264 | * We need clear_IO_APIC before enabling vector on BP | |
1265 | */ | |
1266 | if (!skip_ioapic_setup && nr_ioapics) | |
1267 | enable_IO_APIC(); | |
1268 | ||
acae7d90 MR |
1269 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1270 | localise_nmi_watchdog(); | |
739f33b3 AK |
1271 | end_local_APIC_setup(); |
1272 | ||
0e078e2f TG |
1273 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1274 | setup_IO_APIC(); | |
1275 | else | |
1276 | nr_ioapics = 0; | |
1277 | setup_boot_APIC_clock(); | |
1278 | check_nmi_watchdog(); | |
1279 | return 0; | |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | /* | |
0e078e2f | 1283 | * Local APIC interrupts |
1da177e4 LT |
1284 | */ |
1285 | ||
0e078e2f TG |
1286 | /* |
1287 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1288 | */ | |
1289 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1290 | { |
0e078e2f TG |
1291 | unsigned int v; |
1292 | exit_idle(); | |
1293 | irq_enter(); | |
1da177e4 | 1294 | /* |
0e078e2f TG |
1295 | * Check if this really is a spurious interrupt and ACK it |
1296 | * if it is a vectored one. Just in case... | |
1297 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1298 | */ |
0e078e2f TG |
1299 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1300 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1301 | ack_APIC_irq(); | |
c4d58cbd | 1302 | |
0e078e2f TG |
1303 | add_pda(irq_spurious_count, 1); |
1304 | irq_exit(); | |
1305 | } | |
1da177e4 | 1306 | |
0e078e2f TG |
1307 | /* |
1308 | * This interrupt should never happen with our APIC/SMP architecture | |
1309 | */ | |
1310 | asmlinkage void smp_error_interrupt(void) | |
1311 | { | |
1312 | unsigned int v, v1; | |
1da177e4 | 1313 | |
0e078e2f TG |
1314 | exit_idle(); |
1315 | irq_enter(); | |
1316 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1317 | v = apic_read(APIC_ESR); | |
1318 | apic_write(APIC_ESR, 0); | |
1319 | v1 = apic_read(APIC_ESR); | |
1320 | ack_APIC_irq(); | |
1321 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1322 | |
0e078e2f TG |
1323 | /* Here is what the APIC error bits mean: |
1324 | 0: Send CS error | |
1325 | 1: Receive CS error | |
1326 | 2: Send accept error | |
1327 | 3: Receive accept error | |
1328 | 4: Reserved | |
1329 | 5: Send illegal vector | |
1330 | 6: Received illegal vector | |
1331 | 7: Illegal register address | |
1332 | */ | |
1333 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1334 | smp_processor_id(), v , v1); | |
1335 | irq_exit(); | |
1da177e4 LT |
1336 | } |
1337 | ||
b5841765 | 1338 | /** |
36c9d674 CG |
1339 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1340 | */ | |
b5841765 GC |
1341 | void __init connect_bsp_APIC(void) |
1342 | { | |
36c9d674 CG |
1343 | #ifdef CONFIG_X86_32 |
1344 | if (pic_mode) { | |
1345 | /* | |
1346 | * Do not trust the local APIC being empty at bootup. | |
1347 | */ | |
1348 | clear_local_APIC(); | |
1349 | /* | |
1350 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1351 | * local APIC to INT and NMI lines. | |
1352 | */ | |
1353 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1354 | "enabling APIC mode.\n"); | |
1355 | outb(0x70, 0x22); | |
1356 | outb(0x01, 0x23); | |
1357 | } | |
1358 | #endif | |
b5841765 GC |
1359 | enable_apic_mode(); |
1360 | } | |
1361 | ||
274cfe59 CG |
1362 | /** |
1363 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1364 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1365 | * | |
1366 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1367 | * APIC is disabled. | |
1368 | */ | |
0e078e2f | 1369 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1370 | { |
1b4ee4e4 CG |
1371 | unsigned int value; |
1372 | ||
c177b0bc CG |
1373 | #ifdef CONFIG_X86_32 |
1374 | if (pic_mode) { | |
1375 | /* | |
1376 | * Put the board back into PIC mode (has an effect only on | |
1377 | * certain older boards). Note that APIC interrupts, including | |
1378 | * IPIs, won't work beyond this point! The only exception are | |
1379 | * INIT IPIs. | |
1380 | */ | |
1381 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1382 | "entering PIC mode.\n"); | |
1383 | outb(0x70, 0x22); | |
1384 | outb(0x00, 0x23); | |
1385 | return; | |
1386 | } | |
1387 | #endif | |
1388 | ||
0e078e2f | 1389 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1390 | |
0e078e2f TG |
1391 | /* For the spurious interrupt use vector F, and enable it */ |
1392 | value = apic_read(APIC_SPIV); | |
1393 | value &= ~APIC_VECTOR_MASK; | |
1394 | value |= APIC_SPIV_APIC_ENABLED; | |
1395 | value |= 0xf; | |
1396 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1397 | |
0e078e2f TG |
1398 | if (!virt_wire_setup) { |
1399 | /* | |
1400 | * For LVT0 make it edge triggered, active high, | |
1401 | * external and enabled | |
1402 | */ | |
1403 | value = apic_read(APIC_LVT0); | |
1404 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1405 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1406 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1407 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1408 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1409 | apic_write(APIC_LVT0, value); | |
1410 | } else { | |
1411 | /* Disable LVT0 */ | |
1412 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1413 | } | |
b8ce3359 | 1414 | |
c177b0bc CG |
1415 | /* |
1416 | * For LVT1 make it edge triggered, active high, | |
1417 | * nmi and enabled | |
1418 | */ | |
0e078e2f TG |
1419 | value = apic_read(APIC_LVT1); |
1420 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1421 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1422 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1423 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1424 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1425 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1426 | } |
1427 | ||
be8a5685 AS |
1428 | void __cpuinit generic_processor_info(int apicid, int version) |
1429 | { | |
1430 | int cpu; | |
1431 | cpumask_t tmp_map; | |
1432 | ||
1b313f4a CG |
1433 | /* |
1434 | * Validate version | |
1435 | */ | |
1436 | if (version == 0x0) { | |
1437 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1438 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1439 | version); | |
1440 | version = 0x10; | |
be8a5685 | 1441 | } |
1b313f4a | 1442 | apic_version[apicid] = version; |
be8a5685 | 1443 | |
be8a5685 AS |
1444 | if (num_processors >= NR_CPUS) { |
1445 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1446 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1447 | return; |
1448 | } | |
1449 | ||
1450 | num_processors++; | |
1451 | cpus_complement(tmp_map, cpu_present_map); | |
1452 | cpu = first_cpu(tmp_map); | |
1453 | ||
1454 | physid_set(apicid, phys_cpu_present_map); | |
1455 | if (apicid == boot_cpu_physical_apicid) { | |
1456 | /* | |
1457 | * x86_bios_cpu_apicid is required to have processors listed | |
1458 | * in same order as logical cpu numbers. Hence the first | |
1459 | * entry is BSP, and so on. | |
1460 | */ | |
1461 | cpu = 0; | |
1462 | } | |
e0da3364 YL |
1463 | if (apicid > max_physical_apicid) |
1464 | max_physical_apicid = apicid; | |
1465 | ||
1b313f4a CG |
1466 | #ifdef CONFIG_X86_32 |
1467 | /* | |
1468 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1469 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1470 | * before this can be done without some confusion. | |
1471 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1472 | * - Ashok Raj <ashok.raj@intel.com> | |
1473 | */ | |
1474 | if (max_physical_apicid >= 8) { | |
1475 | switch (boot_cpu_data.x86_vendor) { | |
1476 | case X86_VENDOR_INTEL: | |
1477 | if (!APIC_XAPIC(version)) { | |
1478 | def_to_bigsmp = 0; | |
1479 | break; | |
1480 | } | |
1481 | /* If P4 and above fall through */ | |
1482 | case X86_VENDOR_AMD: | |
1483 | def_to_bigsmp = 1; | |
1484 | } | |
1485 | } | |
1486 | #endif | |
1487 | ||
1488 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1489 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1490 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1491 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1492 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1493 | |
1494 | cpu_to_apicid[cpu] = apicid; | |
1495 | bios_cpu_apicid[cpu] = apicid; | |
1496 | } else { | |
1497 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1498 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1499 | } | |
1b313f4a | 1500 | #endif |
be8a5685 AS |
1501 | |
1502 | cpu_set(cpu, cpu_possible_map); | |
1503 | cpu_set(cpu, cpu_present_map); | |
1504 | } | |
1505 | ||
0c81c746 SS |
1506 | int hard_smp_processor_id(void) |
1507 | { | |
1508 | return read_apic_id(); | |
1509 | } | |
1510 | ||
89039b37 | 1511 | /* |
0e078e2f | 1512 | * Power management |
89039b37 | 1513 | */ |
0e078e2f TG |
1514 | #ifdef CONFIG_PM |
1515 | ||
1516 | static struct { | |
274cfe59 CG |
1517 | /* |
1518 | * 'active' is true if the local APIC was enabled by us and | |
1519 | * not the BIOS; this signifies that we are also responsible | |
1520 | * for disabling it before entering apm/acpi suspend | |
1521 | */ | |
0e078e2f TG |
1522 | int active; |
1523 | /* r/w apic fields */ | |
1524 | unsigned int apic_id; | |
1525 | unsigned int apic_taskpri; | |
1526 | unsigned int apic_ldr; | |
1527 | unsigned int apic_dfr; | |
1528 | unsigned int apic_spiv; | |
1529 | unsigned int apic_lvtt; | |
1530 | unsigned int apic_lvtpc; | |
1531 | unsigned int apic_lvt0; | |
1532 | unsigned int apic_lvt1; | |
1533 | unsigned int apic_lvterr; | |
1534 | unsigned int apic_tmict; | |
1535 | unsigned int apic_tdcr; | |
1536 | unsigned int apic_thmr; | |
1537 | } apic_pm_state; | |
1538 | ||
1539 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1540 | { | |
1541 | unsigned long flags; | |
1542 | int maxlvt; | |
89039b37 | 1543 | |
0e078e2f TG |
1544 | if (!apic_pm_state.active) |
1545 | return 0; | |
89039b37 | 1546 | |
0e078e2f | 1547 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1548 | |
2d7a66d0 | 1549 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1550 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1551 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1552 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1553 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1554 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1555 | if (maxlvt >= 4) | |
1556 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1557 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1558 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1559 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1560 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1561 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1562 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1563 | if (maxlvt >= 5) |
1564 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1565 | #endif | |
24968cfd | 1566 | |
0e078e2f TG |
1567 | local_irq_save(flags); |
1568 | disable_local_APIC(); | |
1569 | local_irq_restore(flags); | |
1570 | return 0; | |
1da177e4 LT |
1571 | } |
1572 | ||
0e078e2f | 1573 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1574 | { |
0e078e2f TG |
1575 | unsigned int l, h; |
1576 | unsigned long flags; | |
1577 | int maxlvt; | |
1da177e4 | 1578 | |
0e078e2f TG |
1579 | if (!apic_pm_state.active) |
1580 | return 0; | |
89b831ef | 1581 | |
0e078e2f | 1582 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1583 | |
0e078e2f | 1584 | local_irq_save(flags); |
92206c90 CG |
1585 | |
1586 | #ifdef CONFIG_X86_64 | |
1587 | if (x2apic) | |
1588 | enable_x2apic(); | |
1589 | else | |
1590 | #endif | |
d5e629a6 | 1591 | { |
92206c90 CG |
1592 | /* |
1593 | * Make sure the APICBASE points to the right address | |
1594 | * | |
1595 | * FIXME! This will be wrong if we ever support suspend on | |
1596 | * SMP! We'll need to do this as part of the CPU restore! | |
1597 | */ | |
6e1cb38a SS |
1598 | rdmsr(MSR_IA32_APICBASE, l, h); |
1599 | l &= ~MSR_IA32_APICBASE_BASE; | |
1600 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1601 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1602 | } |
6e1cb38a | 1603 | |
0e078e2f TG |
1604 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1605 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1606 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1607 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1608 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1609 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1610 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1611 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1612 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1613 | if (maxlvt >= 5) |
1614 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1615 | #endif | |
1616 | if (maxlvt >= 4) | |
1617 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1618 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1619 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1620 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1621 | apic_write(APIC_ESR, 0); | |
1622 | apic_read(APIC_ESR); | |
1623 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1624 | apic_write(APIC_ESR, 0); | |
1625 | apic_read(APIC_ESR); | |
92206c90 | 1626 | |
0e078e2f | 1627 | local_irq_restore(flags); |
92206c90 | 1628 | |
0e078e2f TG |
1629 | return 0; |
1630 | } | |
b8ce3359 | 1631 | |
274cfe59 CG |
1632 | /* |
1633 | * This device has no shutdown method - fully functioning local APICs | |
1634 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1635 | */ | |
1636 | ||
0e078e2f TG |
1637 | static struct sysdev_class lapic_sysclass = { |
1638 | .name = "lapic", | |
1639 | .resume = lapic_resume, | |
1640 | .suspend = lapic_suspend, | |
1641 | }; | |
b8ce3359 | 1642 | |
0e078e2f | 1643 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1644 | .id = 0, |
1645 | .cls = &lapic_sysclass, | |
0e078e2f | 1646 | }; |
b8ce3359 | 1647 | |
0e078e2f TG |
1648 | static void __cpuinit apic_pm_activate(void) |
1649 | { | |
1650 | apic_pm_state.active = 1; | |
1da177e4 LT |
1651 | } |
1652 | ||
0e078e2f | 1653 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1654 | { |
0e078e2f | 1655 | int error; |
e83a5fdc | 1656 | |
0e078e2f TG |
1657 | if (!cpu_has_apic) |
1658 | return 0; | |
1659 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1660 | |
0e078e2f TG |
1661 | error = sysdev_class_register(&lapic_sysclass); |
1662 | if (!error) | |
1663 | error = sysdev_register(&device_lapic); | |
1664 | return error; | |
1da177e4 | 1665 | } |
0e078e2f TG |
1666 | device_initcall(init_lapic_sysfs); |
1667 | ||
1668 | #else /* CONFIG_PM */ | |
1669 | ||
1670 | static void apic_pm_activate(void) { } | |
1671 | ||
1672 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1673 | |
1674 | /* | |
f8bf3c65 | 1675 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1676 | * |
1677 | * Thus far, the major user of this is IBM's Summit2 series: | |
1678 | * | |
637029c6 | 1679 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1680 | * multi-chassis. Use available data to take a good guess. |
1681 | * If in doubt, go HPET. | |
1682 | */ | |
f8bf3c65 | 1683 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1684 | { |
1685 | int i, clusters, zeros; | |
1686 | unsigned id; | |
322850af | 1687 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1688 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1689 | ||
322850af YL |
1690 | /* |
1691 | * there is not this kind of box with AMD CPU yet. | |
1692 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1693 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1694 | * vsmp box still need checking... |
322850af | 1695 | */ |
1cb68487 | 1696 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1697 | return 0; |
1698 | ||
23ca4bba | 1699 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1700 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1701 | |
1702 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1703 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1704 | if (bios_cpu_apicid) { |
1705 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1706 | } |
1707 | else if (i < nr_cpu_ids) { | |
1708 | if (cpu_present(i)) | |
1709 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1710 | else | |
1711 | continue; | |
1712 | } | |
1713 | else | |
1714 | break; | |
1715 | ||
1da177e4 LT |
1716 | if (id != BAD_APICID) |
1717 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1718 | } | |
1719 | ||
1720 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1721 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1722 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1723 | * Since clusters are allocated sequentially, count zeros only if | |
1724 | * they are bounded by ones. | |
1da177e4 LT |
1725 | */ |
1726 | clusters = 0; | |
1727 | zeros = 0; | |
1728 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1729 | if (test_bit(i, clustermap)) { | |
1730 | clusters += 1 + zeros; | |
1731 | zeros = 0; | |
1732 | } else | |
1733 | ++zeros; | |
1734 | } | |
1735 | ||
1cb68487 RT |
1736 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1737 | * not guaranteed to be synced between boards | |
1738 | */ | |
1739 | if (is_vsmp_box() && clusters > 1) | |
1740 | return 1; | |
1741 | ||
1da177e4 | 1742 | /* |
f8bf3c65 | 1743 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1744 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1745 | * out, but AFAIK this will work even for them. | |
1746 | */ | |
1747 | return (clusters > 2); | |
1748 | } | |
1749 | ||
6e1cb38a | 1750 | static __init int setup_nox2apic(char *str) |
1da177e4 | 1751 | { |
6e1cb38a SS |
1752 | disable_x2apic = 1; |
1753 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1da177e4 LT |
1754 | return 0; |
1755 | } | |
6e1cb38a | 1756 | early_param("nox2apic", setup_nox2apic); |
1da177e4 | 1757 | |
1da177e4 | 1758 | |
1da177e4 | 1759 | /* |
0e078e2f | 1760 | * APIC command line parameters |
1da177e4 | 1761 | */ |
789fa735 | 1762 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 1763 | { |
1da177e4 | 1764 | disable_apic = 1; |
9175fc06 | 1765 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1766 | return 0; |
1767 | } | |
1768 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1769 | |
2c8c0e6b | 1770 | /* same as disableapic, for compatibility */ |
789fa735 | 1771 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 1772 | { |
789fa735 | 1773 | return setup_disableapic(arg); |
6935d1f9 | 1774 | } |
2c8c0e6b | 1775 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1776 | |
2e7c2838 LT |
1777 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1778 | { | |
1779 | local_apic_timer_c2_ok = 1; | |
1780 | return 0; | |
1781 | } | |
1782 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1783 | ||
36fef094 | 1784 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1785 | { |
1da177e4 | 1786 | disable_apic_timer = 1; |
36fef094 | 1787 | return 0; |
6935d1f9 | 1788 | } |
36fef094 CG |
1789 | early_param("noapictimer", parse_disable_apic_timer); |
1790 | ||
1791 | static int __init parse_nolapic_timer(char *arg) | |
1792 | { | |
1793 | disable_apic_timer = 1; | |
1794 | return 0; | |
6935d1f9 | 1795 | } |
36fef094 | 1796 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1797 | |
0c3749c4 AK |
1798 | static __init int setup_apicpmtimer(char *s) |
1799 | { | |
1800 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1801 | notsc_setup(NULL); |
b8ce3359 | 1802 | return 0; |
0c3749c4 AK |
1803 | } |
1804 | __setup("apicpmtimer", setup_apicpmtimer); | |
1805 | ||
79af9bec CG |
1806 | static int __init apic_set_verbosity(char *arg) |
1807 | { | |
1808 | if (!arg) { | |
1809 | #ifdef CONFIG_X86_64 | |
1810 | skip_ioapic_setup = 0; | |
1811 | ioapic_force = 1; | |
1812 | return 0; | |
1813 | #endif | |
1814 | return -EINVAL; | |
1815 | } | |
1816 | ||
1817 | if (strcmp("debug", arg) == 0) | |
1818 | apic_verbosity = APIC_DEBUG; | |
1819 | else if (strcmp("verbose", arg) == 0) | |
1820 | apic_verbosity = APIC_VERBOSE; | |
1821 | else { | |
1822 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1823 | " use apic=verbose or apic=debug\n", arg); | |
1824 | return -EINVAL; | |
1825 | } | |
1826 | ||
1827 | return 0; | |
1828 | } | |
1829 | early_param("apic", apic_set_verbosity); | |
1830 | ||
1e934dda YL |
1831 | static int __init lapic_insert_resource(void) |
1832 | { | |
1833 | if (!apic_phys) | |
1834 | return -1; | |
1835 | ||
1836 | /* Put local APIC into the resource map. */ | |
1837 | lapic_resource.start = apic_phys; | |
1838 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1839 | insert_resource(&iomem_resource, &lapic_resource); | |
1840 | ||
1841 | return 0; | |
1842 | } | |
1843 | ||
1844 | /* | |
1845 | * need call insert after e820_reserve_resources() | |
1846 | * that is using request_resource | |
1847 | */ | |
1848 | late_initcall(lapic_insert_resource); |