Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
e83a5fdc | 35 | #include <asm/hpet.h> |
1da177e4 LT |
36 | #include <asm/pgalloc.h> |
37 | #include <asm/mach_apic.h> | |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
1da177e4 | 43 | |
fb79d22e | 44 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 45 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 46 | int disable_apic; |
1da177e4 | 47 | |
e83a5fdc | 48 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
49 | int local_apic_timer_c2_ok; |
50 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
51 | ||
e83a5fdc HS |
52 | /* |
53 | * Debug level, exported for io_apic.c | |
54 | */ | |
55 | int apic_verbosity; | |
56 | ||
39928722 AD |
57 | static struct resource lapic_resource = { |
58 | .name = "Local APIC", | |
59 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
60 | }; | |
61 | ||
d03030e9 TG |
62 | static unsigned int calibration_result; |
63 | ||
ba7eda4c TG |
64 | static int lapic_next_event(unsigned long delta, |
65 | struct clock_event_device *evt); | |
66 | static void lapic_timer_setup(enum clock_event_mode mode, | |
67 | struct clock_event_device *evt); | |
ba7eda4c | 68 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 69 | static void apic_pm_activate(void); |
ba7eda4c TG |
70 | |
71 | static struct clock_event_device lapic_clockevent = { | |
72 | .name = "lapic", | |
73 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
74 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
75 | .shift = 32, | |
76 | .set_mode = lapic_timer_setup, | |
77 | .set_next_event = lapic_next_event, | |
78 | .broadcast = lapic_timer_broadcast, | |
79 | .rating = 100, | |
80 | .irq = -1, | |
81 | }; | |
82 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
83 | ||
d3432896 AK |
84 | static unsigned long apic_phys; |
85 | ||
0e078e2f TG |
86 | /* |
87 | * Get the LAPIC version | |
88 | */ | |
89 | static inline int lapic_get_version(void) | |
ba7eda4c | 90 | { |
0e078e2f | 91 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
92 | } |
93 | ||
0e078e2f TG |
94 | /* |
95 | * Check, if the APIC is integrated or a seperate chip | |
96 | */ | |
97 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 98 | { |
0e078e2f | 99 | return 1; |
ba7eda4c TG |
100 | } |
101 | ||
102 | /* | |
0e078e2f | 103 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 104 | */ |
0e078e2f | 105 | static int modern_apic(void) |
ba7eda4c | 106 | { |
0e078e2f TG |
107 | /* AMD systems use old APIC versions, so check the CPU */ |
108 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
109 | boot_cpu_data.x86 >= 0xf) | |
110 | return 1; | |
111 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
112 | } |
113 | ||
8339e9fb FLV |
114 | void apic_wait_icr_idle(void) |
115 | { | |
116 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
117 | cpu_relax(); | |
118 | } | |
119 | ||
3c6bb07a | 120 | u32 safe_apic_wait_icr_idle(void) |
8339e9fb | 121 | { |
3c6bb07a | 122 | u32 send_status; |
8339e9fb FLV |
123 | int timeout; |
124 | ||
125 | timeout = 0; | |
126 | do { | |
127 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
128 | if (!send_status) | |
129 | break; | |
130 | udelay(100); | |
131 | } while (timeout++ < 1000); | |
132 | ||
133 | return send_status; | |
134 | } | |
135 | ||
0e078e2f TG |
136 | /** |
137 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
138 | */ | |
e9427101 | 139 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 140 | { |
11a8e778 | 141 | unsigned int v; |
6935d1f9 TG |
142 | |
143 | /* unmask and set to NMI */ | |
144 | v = APIC_DM_NMI; | |
11a8e778 | 145 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
146 | } |
147 | ||
0e078e2f TG |
148 | /** |
149 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
150 | */ | |
37e650c7 | 151 | int lapic_get_maxlvt(void) |
1da177e4 | 152 | { |
11a8e778 | 153 | unsigned int v, maxlvt; |
1da177e4 LT |
154 | |
155 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
156 | maxlvt = GET_APIC_MAXLVT(v); |
157 | return maxlvt; | |
158 | } | |
159 | ||
0e078e2f TG |
160 | /* |
161 | * This function sets up the local APIC timer, with a timeout of | |
162 | * 'clocks' APIC bus clock. During calibration we actually call | |
163 | * this function twice on the boot CPU, once with a bogus timeout | |
164 | * value, second time for real. The other (noncalibrating) CPUs | |
165 | * call this function only once, with the real, calibrated value. | |
166 | * | |
167 | * We do reads before writes even if unnecessary, to get around the | |
168 | * P5 APIC double write bug. | |
169 | */ | |
170 | ||
171 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 172 | { |
0e078e2f | 173 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 174 | |
0e078e2f TG |
175 | lvtt_value = LOCAL_TIMER_VECTOR; |
176 | if (!oneshot) | |
177 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
178 | if (!irqen) | |
179 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 180 | |
0e078e2f | 181 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
182 | |
183 | /* | |
0e078e2f | 184 | * Divide PICLK by 16 |
1da177e4 | 185 | */ |
0e078e2f TG |
186 | tmp_value = apic_read(APIC_TDCR); |
187 | apic_write(APIC_TDCR, (tmp_value | |
188 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
189 | | APIC_TDR_DIV_16); | |
190 | ||
191 | if (!oneshot) | |
192 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
193 | } |
194 | ||
0e078e2f | 195 | /* |
7b83dae7 RR |
196 | * Setup extended LVT, AMD specific (K8, family 10h) |
197 | * | |
198 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
199 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 200 | */ |
7b83dae7 RR |
201 | |
202 | #define APIC_EILVT_LVTOFF_MCE 0 | |
203 | #define APIC_EILVT_LVTOFF_IBS 1 | |
204 | ||
205 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 206 | { |
7b83dae7 | 207 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 208 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 209 | |
0e078e2f | 210 | apic_write(reg, v); |
1da177e4 LT |
211 | } |
212 | ||
7b83dae7 RR |
213 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
214 | { | |
215 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
216 | return APIC_EILVT_LVTOFF_MCE; | |
217 | } | |
218 | ||
219 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
220 | { | |
221 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
222 | return APIC_EILVT_LVTOFF_IBS; | |
223 | } | |
224 | ||
0e078e2f TG |
225 | /* |
226 | * Program the next event, relative to now | |
227 | */ | |
228 | static int lapic_next_event(unsigned long delta, | |
229 | struct clock_event_device *evt) | |
1da177e4 | 230 | { |
0e078e2f TG |
231 | apic_write(APIC_TMICT, delta); |
232 | return 0; | |
1da177e4 LT |
233 | } |
234 | ||
0e078e2f TG |
235 | /* |
236 | * Setup the lapic timer in periodic or oneshot mode | |
237 | */ | |
238 | static void lapic_timer_setup(enum clock_event_mode mode, | |
239 | struct clock_event_device *evt) | |
9b7711f0 HS |
240 | { |
241 | unsigned long flags; | |
0e078e2f | 242 | unsigned int v; |
9b7711f0 | 243 | |
0e078e2f TG |
244 | /* Lapic used as dummy for broadcast ? */ |
245 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
246 | return; |
247 | ||
248 | local_irq_save(flags); | |
249 | ||
0e078e2f TG |
250 | switch (mode) { |
251 | case CLOCK_EVT_MODE_PERIODIC: | |
252 | case CLOCK_EVT_MODE_ONESHOT: | |
253 | __setup_APIC_LVTT(calibration_result, | |
254 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
255 | break; | |
256 | case CLOCK_EVT_MODE_UNUSED: | |
257 | case CLOCK_EVT_MODE_SHUTDOWN: | |
258 | v = apic_read(APIC_LVTT); | |
259 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
260 | apic_write(APIC_LVTT, v); | |
261 | break; | |
262 | case CLOCK_EVT_MODE_RESUME: | |
263 | /* Nothing to do here */ | |
264 | break; | |
265 | } | |
9b7711f0 HS |
266 | |
267 | local_irq_restore(flags); | |
268 | } | |
269 | ||
1da177e4 | 270 | /* |
0e078e2f | 271 | * Local APIC timer broadcast function |
1da177e4 | 272 | */ |
0e078e2f | 273 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 274 | { |
0e078e2f TG |
275 | #ifdef CONFIG_SMP |
276 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
277 | #endif | |
278 | } | |
1da177e4 | 279 | |
0e078e2f TG |
280 | /* |
281 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
282 | * of the boot CPU and register the clock event in the framework. | |
283 | */ | |
284 | static void setup_APIC_timer(void) | |
285 | { | |
286 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 287 | |
0e078e2f TG |
288 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
289 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 290 | |
0e078e2f TG |
291 | clockevents_register_device(levt); |
292 | } | |
1da177e4 | 293 | |
0e078e2f TG |
294 | /* |
295 | * In this function we calibrate APIC bus clocks to the external | |
296 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
297 | * to calibrate, since some later bootup code depends on getting | |
298 | * the first irq? Ugh. | |
299 | * | |
300 | * We want to do the calibration only once since we | |
301 | * want to have local timer irqs syncron. CPUs connected | |
302 | * by the same APIC bus have the very same bus frequency. | |
303 | * And we want to have irqs off anyways, no accidental | |
304 | * APIC irq that way. | |
305 | */ | |
306 | ||
307 | #define TICK_COUNT 100000000 | |
308 | ||
309 | static void __init calibrate_APIC_clock(void) | |
310 | { | |
311 | unsigned apic, apic_start; | |
312 | unsigned long tsc, tsc_start; | |
313 | int result; | |
314 | ||
315 | local_irq_disable(); | |
316 | ||
317 | /* | |
318 | * Put whatever arbitrary (but long enough) timeout | |
319 | * value into the APIC clock, we just want to get the | |
320 | * counter running for calibration. | |
321 | * | |
322 | * No interrupt enable ! | |
323 | */ | |
324 | __setup_APIC_LVTT(250000000, 0, 0); | |
325 | ||
326 | apic_start = apic_read(APIC_TMCCT); | |
327 | #ifdef CONFIG_X86_PM_TIMER | |
328 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
329 | pmtimer_wait(5000); /* 5ms wait */ | |
330 | apic = apic_read(APIC_TMCCT); | |
331 | result = (apic_start - apic) * 1000L / 5; | |
332 | } else | |
333 | #endif | |
334 | { | |
335 | rdtscll(tsc_start); | |
336 | ||
337 | do { | |
338 | apic = apic_read(APIC_TMCCT); | |
339 | rdtscll(tsc); | |
340 | } while ((tsc - tsc_start) < TICK_COUNT && | |
341 | (apic_start - apic) < TICK_COUNT); | |
342 | ||
343 | result = (apic_start - apic) * 1000L * tsc_khz / | |
344 | (tsc - tsc_start); | |
345 | } | |
346 | ||
347 | local_irq_enable(); | |
348 | ||
349 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
350 | ||
351 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
352 | result / 1000 / 1000, result / 1000 % 1000); | |
353 | ||
354 | /* Calculate the scaled math multiplication factor */ | |
355 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32); | |
356 | lapic_clockevent.max_delta_ns = | |
357 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
358 | lapic_clockevent.min_delta_ns = | |
359 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
360 | ||
361 | calibration_result = result / HZ; | |
362 | } | |
363 | ||
e83a5fdc HS |
364 | /* |
365 | * Setup the boot APIC | |
366 | * | |
367 | * Calibrate and verify the result. | |
368 | */ | |
0e078e2f TG |
369 | void __init setup_boot_APIC_clock(void) |
370 | { | |
371 | /* | |
372 | * The local apic timer can be disabled via the kernel commandline. | |
373 | * Register the lapic timer as a dummy clock event source on SMP | |
374 | * systems, so the broadcast mechanism is used. On UP systems simply | |
375 | * ignore it. | |
376 | */ | |
377 | if (disable_apic_timer) { | |
378 | printk(KERN_INFO "Disabling APIC timer\n"); | |
379 | /* No broadcast on UP ! */ | |
9d09951d TG |
380 | if (num_possible_cpus() > 1) { |
381 | lapic_clockevent.mult = 1; | |
0e078e2f | 382 | setup_APIC_timer(); |
9d09951d | 383 | } |
0e078e2f TG |
384 | return; |
385 | } | |
386 | ||
387 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
388 | calibrate_APIC_clock(); | |
389 | ||
c2b84b30 TG |
390 | /* |
391 | * Do a sanity check on the APIC calibration result | |
392 | */ | |
393 | if (calibration_result < (1000000 / HZ)) { | |
394 | printk(KERN_WARNING | |
395 | "APIC frequency too slow, disabling apic timer\n"); | |
396 | /* No broadcast on UP ! */ | |
397 | if (num_possible_cpus() > 1) | |
398 | setup_APIC_timer(); | |
399 | return; | |
400 | } | |
401 | ||
0e078e2f TG |
402 | /* |
403 | * If nmi_watchdog is set to IO_APIC, we need the | |
404 | * PIT/HPET going. Otherwise register lapic as a dummy | |
405 | * device. | |
406 | */ | |
407 | if (nmi_watchdog != NMI_IO_APIC) | |
408 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
409 | else | |
410 | printk(KERN_WARNING "APIC timer registered as dummy," | |
411 | " due to nmi_watchdog=1!\n"); | |
412 | ||
413 | setup_APIC_timer(); | |
414 | } | |
415 | ||
416 | /* | |
417 | * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the | |
418 | * C1E flag only in the secondary CPU, so when we detect the wreckage | |
419 | * we already have enabled the boot CPU local apic timer. Check, if | |
420 | * disable_apic_timer is set and the DUMMY flag is cleared. If yes, | |
421 | * set the DUMMY flag again and force the broadcast mode in the | |
422 | * clockevents layer. | |
423 | */ | |
424 | void __cpuinit check_boot_apic_timer_broadcast(void) | |
425 | { | |
426 | if (!disable_apic_timer || | |
427 | (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY)) | |
428 | return; | |
429 | ||
430 | printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n"); | |
431 | lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY; | |
432 | ||
433 | local_irq_enable(); | |
c70dcb74 GOC |
434 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
435 | &boot_cpu_physical_apicid); | |
0e078e2f TG |
436 | local_irq_disable(); |
437 | } | |
438 | ||
439 | void __cpuinit setup_secondary_APIC_clock(void) | |
440 | { | |
441 | check_boot_apic_timer_broadcast(); | |
442 | setup_APIC_timer(); | |
443 | } | |
444 | ||
445 | /* | |
446 | * The guts of the apic timer interrupt | |
447 | */ | |
448 | static void local_apic_timer_interrupt(void) | |
449 | { | |
450 | int cpu = smp_processor_id(); | |
451 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
452 | ||
453 | /* | |
454 | * Normally we should not be here till LAPIC has been initialized but | |
455 | * in some cases like kdump, its possible that there is a pending LAPIC | |
456 | * timer interrupt from previous kernel's context and is delivered in | |
457 | * new kernel the moment interrupts are enabled. | |
458 | * | |
459 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
460 | * its possible that when we get here evt->event_handler is NULL. | |
461 | * Check for event_handler being NULL and discard the interrupt as | |
462 | * spurious. | |
463 | */ | |
464 | if (!evt->event_handler) { | |
465 | printk(KERN_WARNING | |
466 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
467 | /* Switch it off */ | |
468 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
469 | return; | |
470 | } | |
471 | ||
472 | /* | |
473 | * the NMI deadlock-detector uses this. | |
474 | */ | |
475 | add_pda(apic_timer_irqs, 1); | |
476 | ||
477 | evt->event_handler(evt); | |
478 | } | |
479 | ||
480 | /* | |
481 | * Local APIC timer interrupt. This is the most natural way for doing | |
482 | * local interrupts, but local timer interrupts can be emulated by | |
483 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
484 | * | |
485 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
486 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
487 | */ | |
488 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
489 | { | |
490 | struct pt_regs *old_regs = set_irq_regs(regs); | |
491 | ||
492 | /* | |
493 | * NOTE! We'd better ACK the irq immediately, | |
494 | * because timer handling can be slow. | |
495 | */ | |
496 | ack_APIC_irq(); | |
497 | /* | |
498 | * update_process_times() expects us to have done irq_enter(). | |
499 | * Besides, if we don't timer interrupts ignore the global | |
500 | * interrupt lock, which is the WrongThing (tm) to do. | |
501 | */ | |
502 | exit_idle(); | |
503 | irq_enter(); | |
504 | local_apic_timer_interrupt(); | |
505 | irq_exit(); | |
506 | set_irq_regs(old_regs); | |
507 | } | |
508 | ||
509 | int setup_profiling_timer(unsigned int multiplier) | |
510 | { | |
511 | return -EINVAL; | |
512 | } | |
513 | ||
514 | ||
515 | /* | |
516 | * Local APIC start and shutdown | |
517 | */ | |
518 | ||
519 | /** | |
520 | * clear_local_APIC - shutdown the local APIC | |
521 | * | |
522 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
523 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
524 | * leftovers during boot. | |
525 | */ | |
526 | void clear_local_APIC(void) | |
527 | { | |
528 | int maxlvt = lapic_get_maxlvt(); | |
529 | u32 v; | |
530 | ||
d3432896 AK |
531 | /* APIC hasn't been mapped yet */ |
532 | if (!apic_phys) | |
533 | return; | |
534 | ||
535 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
536 | /* |
537 | * Masking an LVT entry can trigger a local APIC error | |
538 | * if the vector is zero. Mask LVTERR first to prevent this. | |
539 | */ | |
540 | if (maxlvt >= 3) { | |
541 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
542 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
543 | } | |
544 | /* | |
545 | * Careful: we have to set masks only first to deassert | |
546 | * any level-triggered sources. | |
547 | */ | |
548 | v = apic_read(APIC_LVTT); | |
549 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
550 | v = apic_read(APIC_LVT0); | |
551 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
552 | v = apic_read(APIC_LVT1); | |
553 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
554 | if (maxlvt >= 4) { | |
555 | v = apic_read(APIC_LVTPC); | |
556 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
557 | } | |
558 | ||
559 | /* | |
560 | * Clean APIC state for other OSs: | |
561 | */ | |
562 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
563 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
564 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
565 | if (maxlvt >= 3) | |
566 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
567 | if (maxlvt >= 4) | |
568 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
569 | apic_write(APIC_ESR, 0); | |
570 | apic_read(APIC_ESR); | |
571 | } | |
572 | ||
573 | /** | |
574 | * disable_local_APIC - clear and disable the local APIC | |
575 | */ | |
576 | void disable_local_APIC(void) | |
577 | { | |
578 | unsigned int value; | |
579 | ||
580 | clear_local_APIC(); | |
581 | ||
582 | /* | |
583 | * Disable APIC (implies clearing of registers | |
584 | * for 82489DX!). | |
585 | */ | |
586 | value = apic_read(APIC_SPIV); | |
587 | value &= ~APIC_SPIV_APIC_ENABLED; | |
588 | apic_write(APIC_SPIV, value); | |
589 | } | |
590 | ||
591 | void lapic_shutdown(void) | |
592 | { | |
593 | unsigned long flags; | |
594 | ||
595 | if (!cpu_has_apic) | |
596 | return; | |
597 | ||
598 | local_irq_save(flags); | |
599 | ||
600 | disable_local_APIC(); | |
601 | ||
602 | local_irq_restore(flags); | |
603 | } | |
604 | ||
605 | /* | |
606 | * This is to verify that we're looking at a real local APIC. | |
607 | * Check these against your board if the CPUs aren't getting | |
608 | * started for no apparent reason. | |
609 | */ | |
610 | int __init verify_local_APIC(void) | |
611 | { | |
612 | unsigned int reg0, reg1; | |
613 | ||
614 | /* | |
615 | * The version register is read-only in a real APIC. | |
616 | */ | |
617 | reg0 = apic_read(APIC_LVR); | |
618 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
619 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
620 | reg1 = apic_read(APIC_LVR); | |
621 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
622 | ||
623 | /* | |
624 | * The two version reads above should print the same | |
625 | * numbers. If the second one is different, then we | |
626 | * poke at a non-APIC. | |
627 | */ | |
628 | if (reg1 != reg0) | |
629 | return 0; | |
630 | ||
631 | /* | |
632 | * Check if the version looks reasonably. | |
633 | */ | |
634 | reg1 = GET_APIC_VERSION(reg0); | |
635 | if (reg1 == 0x00 || reg1 == 0xff) | |
636 | return 0; | |
637 | reg1 = lapic_get_maxlvt(); | |
638 | if (reg1 < 0x02 || reg1 == 0xff) | |
639 | return 0; | |
640 | ||
641 | /* | |
642 | * The ID register is read/write in a real APIC. | |
643 | */ | |
644 | reg0 = apic_read(APIC_ID); | |
645 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
646 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
647 | reg1 = apic_read(APIC_ID); | |
648 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
649 | apic_write(APIC_ID, reg0); | |
650 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
651 | return 0; | |
652 | ||
653 | /* | |
1da177e4 LT |
654 | * The next two are just to see if we have sane values. |
655 | * They're only really relevant if we're in Virtual Wire | |
656 | * compatibility mode, but most boxes are anymore. | |
657 | */ | |
658 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 659 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
660 | reg1 = apic_read(APIC_LVT1); |
661 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
662 | ||
663 | return 1; | |
664 | } | |
665 | ||
0e078e2f TG |
666 | /** |
667 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
668 | */ | |
1da177e4 LT |
669 | void __init sync_Arb_IDs(void) |
670 | { | |
671 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 672 | if (modern_apic()) |
1da177e4 LT |
673 | return; |
674 | ||
675 | /* | |
676 | * Wait for idle. | |
677 | */ | |
678 | apic_wait_icr_idle(); | |
679 | ||
680 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 681 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
682 | | APIC_DM_INIT); |
683 | } | |
684 | ||
1da177e4 LT |
685 | /* |
686 | * An initial setup of the virtual wire mode. | |
687 | */ | |
688 | void __init init_bsp_APIC(void) | |
689 | { | |
11a8e778 | 690 | unsigned int value; |
1da177e4 LT |
691 | |
692 | /* | |
693 | * Don't do the setup now if we have a SMP BIOS as the | |
694 | * through-I/O-APIC virtual wire mode might be active. | |
695 | */ | |
696 | if (smp_found_config || !cpu_has_apic) | |
697 | return; | |
698 | ||
699 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
700 | |
701 | /* | |
702 | * Do not trust the local APIC being empty at bootup. | |
703 | */ | |
704 | clear_local_APIC(); | |
705 | ||
706 | /* | |
707 | * Enable APIC. | |
708 | */ | |
709 | value = apic_read(APIC_SPIV); | |
710 | value &= ~APIC_VECTOR_MASK; | |
711 | value |= APIC_SPIV_APIC_ENABLED; | |
712 | value |= APIC_SPIV_FOCUS_DISABLED; | |
713 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 714 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
715 | |
716 | /* | |
717 | * Set up the virtual wire mode. | |
718 | */ | |
11a8e778 | 719 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 720 | value = APIC_DM_NMI; |
11a8e778 | 721 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
722 | } |
723 | ||
0e078e2f TG |
724 | /** |
725 | * setup_local_APIC - setup the local APIC | |
726 | */ | |
727 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 728 | { |
739f33b3 | 729 | unsigned int value; |
da7ed9f9 | 730 | int i, j; |
1da177e4 | 731 | |
1da177e4 | 732 | value = apic_read(APIC_LVR); |
1da177e4 | 733 | |
fe7414a2 | 734 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
735 | |
736 | /* | |
737 | * Double-check whether this APIC is really registered. | |
738 | * This is meaningless in clustered apic mode, so we skip it. | |
739 | */ | |
740 | if (!apic_id_registered()) | |
741 | BUG(); | |
742 | ||
743 | /* | |
744 | * Intel recommends to set DFR, LDR and TPR before enabling | |
745 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
746 | * document number 292116). So here it goes... | |
747 | */ | |
748 | init_apic_ldr(); | |
749 | ||
750 | /* | |
751 | * Set Task Priority to 'accept all'. We never change this | |
752 | * later on. | |
753 | */ | |
754 | value = apic_read(APIC_TASKPRI); | |
755 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 756 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 757 | |
da7ed9f9 VG |
758 | /* |
759 | * After a crash, we no longer service the interrupts and a pending | |
760 | * interrupt from previous kernel might still have ISR bit set. | |
761 | * | |
762 | * Most probably by now CPU has serviced that pending interrupt and | |
763 | * it might not have done the ack_APIC_irq() because it thought, | |
764 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
765 | * does not clear the ISR bit and cpu thinks it has already serivced | |
766 | * the interrupt. Hence a vector might get locked. It was noticed | |
767 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
768 | */ | |
769 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
770 | value = apic_read(APIC_ISR + i*0x10); | |
771 | for (j = 31; j >= 0; j--) { | |
772 | if (value & (1<<j)) | |
773 | ack_APIC_irq(); | |
774 | } | |
775 | } | |
776 | ||
1da177e4 LT |
777 | /* |
778 | * Now that we are all set up, enable the APIC | |
779 | */ | |
780 | value = apic_read(APIC_SPIV); | |
781 | value &= ~APIC_VECTOR_MASK; | |
782 | /* | |
783 | * Enable APIC | |
784 | */ | |
785 | value |= APIC_SPIV_APIC_ENABLED; | |
786 | ||
3f14c746 AK |
787 | /* We always use processor focus */ |
788 | ||
1da177e4 LT |
789 | /* |
790 | * Set spurious IRQ vector | |
791 | */ | |
792 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 793 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
794 | |
795 | /* | |
796 | * Set up LVT0, LVT1: | |
797 | * | |
798 | * set up through-local-APIC on the BP's LINT0. This is not | |
799 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
800 | * we delegate interrupts to the 8259A. | |
801 | */ | |
802 | /* | |
803 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
804 | */ | |
805 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 806 | if (!smp_processor_id() && !value) { |
1da177e4 | 807 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
808 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
809 | smp_processor_id()); | |
1da177e4 LT |
810 | } else { |
811 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
812 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
813 | smp_processor_id()); | |
1da177e4 | 814 | } |
11a8e778 | 815 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
816 | |
817 | /* | |
818 | * only the BP should see the LINT1 NMI signal, obviously. | |
819 | */ | |
820 | if (!smp_processor_id()) | |
821 | value = APIC_DM_NMI; | |
822 | else | |
823 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 824 | apic_write(APIC_LVT1, value); |
739f33b3 | 825 | } |
1da177e4 | 826 | |
739f33b3 AK |
827 | void __cpuinit lapic_setup_esr(void) |
828 | { | |
829 | unsigned maxlvt = lapic_get_maxlvt(); | |
830 | ||
831 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 832 | /* |
739f33b3 | 833 | * spec says clear errors after enabling vector. |
1c69524c | 834 | */ |
739f33b3 AK |
835 | if (maxlvt > 3) |
836 | apic_write(APIC_ESR, 0); | |
837 | } | |
1da177e4 | 838 | |
739f33b3 AK |
839 | void __cpuinit end_local_APIC_setup(void) |
840 | { | |
841 | lapic_setup_esr(); | |
1da177e4 | 842 | nmi_watchdog_default(); |
f2802e7f | 843 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 844 | apic_pm_activate(); |
1da177e4 | 845 | } |
1da177e4 LT |
846 | |
847 | /* | |
848 | * Detect and enable local APICs on non-SMP boards. | |
849 | * Original code written by Keir Fraser. | |
850 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 851 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 852 | */ |
0e078e2f | 853 | static int __init detect_init_APIC(void) |
1da177e4 LT |
854 | { |
855 | if (!cpu_has_apic) { | |
856 | printk(KERN_INFO "No local APIC present\n"); | |
857 | return -1; | |
858 | } | |
859 | ||
860 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 861 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
862 | return 0; |
863 | } | |
864 | ||
8643f9d0 YL |
865 | void __init early_init_lapic_mapping(void) |
866 | { | |
867 | unsigned long apic_phys; | |
868 | ||
869 | /* | |
870 | * If no local APIC can be found then go out | |
871 | * : it means there is no mpatable and MADT | |
872 | */ | |
873 | if (!smp_found_config) | |
874 | return; | |
875 | ||
876 | apic_phys = mp_lapic_addr; | |
877 | ||
878 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
879 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", | |
880 | APIC_BASE, apic_phys); | |
881 | ||
882 | /* | |
883 | * Fetch the APIC ID of the BSP in case we have a | |
884 | * default configuration (or the MP table is broken). | |
885 | */ | |
c70dcb74 | 886 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
8643f9d0 YL |
887 | } |
888 | ||
0e078e2f TG |
889 | /** |
890 | * init_apic_mappings - initialize APIC mappings | |
891 | */ | |
1da177e4 LT |
892 | void __init init_apic_mappings(void) |
893 | { | |
1da177e4 LT |
894 | /* |
895 | * If no local APIC can be found then set up a fake all | |
896 | * zeroes page to simulate the local APIC and another | |
897 | * one for the IO-APIC. | |
898 | */ | |
899 | if (!smp_found_config && detect_init_APIC()) { | |
900 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
901 | apic_phys = __pa(apic_phys); | |
902 | } else | |
903 | apic_phys = mp_lapic_addr; | |
904 | ||
905 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
906 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
907 | APIC_BASE, apic_phys); | |
1da177e4 LT |
908 | |
909 | /* | |
910 | * Fetch the APIC ID of the BSP in case we have a | |
911 | * default configuration (or the MP table is broken). | |
912 | */ | |
c70dcb74 | 913 | boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); |
1da177e4 LT |
914 | } |
915 | ||
916 | /* | |
0e078e2f TG |
917 | * This initializes the IO-APIC and APIC hardware if this is |
918 | * a UP kernel. | |
1da177e4 | 919 | */ |
0e078e2f | 920 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 921 | { |
0e078e2f TG |
922 | if (disable_apic) { |
923 | printk(KERN_INFO "Apic disabled\n"); | |
924 | return -1; | |
925 | } | |
926 | if (!cpu_has_apic) { | |
927 | disable_apic = 1; | |
928 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
929 | return -1; | |
930 | } | |
1da177e4 | 931 | |
0e078e2f | 932 | verify_local_APIC(); |
1da177e4 | 933 | |
c70dcb74 GOC |
934 | phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid); |
935 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); | |
1da177e4 | 936 | |
0e078e2f | 937 | setup_local_APIC(); |
1da177e4 | 938 | |
739f33b3 AK |
939 | /* |
940 | * Now enable IO-APICs, actually call clear_IO_APIC | |
941 | * We need clear_IO_APIC before enabling vector on BP | |
942 | */ | |
943 | if (!skip_ioapic_setup && nr_ioapics) | |
944 | enable_IO_APIC(); | |
945 | ||
946 | end_local_APIC_setup(); | |
947 | ||
0e078e2f TG |
948 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
949 | setup_IO_APIC(); | |
950 | else | |
951 | nr_ioapics = 0; | |
952 | setup_boot_APIC_clock(); | |
953 | check_nmi_watchdog(); | |
954 | return 0; | |
1da177e4 LT |
955 | } |
956 | ||
957 | /* | |
0e078e2f | 958 | * Local APIC interrupts |
1da177e4 LT |
959 | */ |
960 | ||
0e078e2f TG |
961 | /* |
962 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
963 | */ | |
964 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 965 | { |
0e078e2f TG |
966 | unsigned int v; |
967 | exit_idle(); | |
968 | irq_enter(); | |
1da177e4 | 969 | /* |
0e078e2f TG |
970 | * Check if this really is a spurious interrupt and ACK it |
971 | * if it is a vectored one. Just in case... | |
972 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 973 | */ |
0e078e2f TG |
974 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
975 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
976 | ack_APIC_irq(); | |
c4d58cbd | 977 | |
0e078e2f TG |
978 | add_pda(irq_spurious_count, 1); |
979 | irq_exit(); | |
980 | } | |
1da177e4 | 981 | |
0e078e2f TG |
982 | /* |
983 | * This interrupt should never happen with our APIC/SMP architecture | |
984 | */ | |
985 | asmlinkage void smp_error_interrupt(void) | |
986 | { | |
987 | unsigned int v, v1; | |
1da177e4 | 988 | |
0e078e2f TG |
989 | exit_idle(); |
990 | irq_enter(); | |
991 | /* First tickle the hardware, only then report what went on. -- REW */ | |
992 | v = apic_read(APIC_ESR); | |
993 | apic_write(APIC_ESR, 0); | |
994 | v1 = apic_read(APIC_ESR); | |
995 | ack_APIC_irq(); | |
996 | atomic_inc(&irq_err_count); | |
ba7eda4c | 997 | |
0e078e2f TG |
998 | /* Here is what the APIC error bits mean: |
999 | 0: Send CS error | |
1000 | 1: Receive CS error | |
1001 | 2: Send accept error | |
1002 | 3: Receive accept error | |
1003 | 4: Reserved | |
1004 | 5: Send illegal vector | |
1005 | 6: Received illegal vector | |
1006 | 7: Illegal register address | |
1007 | */ | |
1008 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1009 | smp_processor_id(), v , v1); | |
1010 | irq_exit(); | |
1da177e4 LT |
1011 | } |
1012 | ||
0e078e2f | 1013 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1014 | { |
0e078e2f TG |
1015 | /* Go back to Virtual Wire compatibility mode */ |
1016 | unsigned long value; | |
1da177e4 | 1017 | |
0e078e2f TG |
1018 | /* For the spurious interrupt use vector F, and enable it */ |
1019 | value = apic_read(APIC_SPIV); | |
1020 | value &= ~APIC_VECTOR_MASK; | |
1021 | value |= APIC_SPIV_APIC_ENABLED; | |
1022 | value |= 0xf; | |
1023 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1024 | |
0e078e2f TG |
1025 | if (!virt_wire_setup) { |
1026 | /* | |
1027 | * For LVT0 make it edge triggered, active high, | |
1028 | * external and enabled | |
1029 | */ | |
1030 | value = apic_read(APIC_LVT0); | |
1031 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1032 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1033 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1034 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1035 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1036 | apic_write(APIC_LVT0, value); | |
1037 | } else { | |
1038 | /* Disable LVT0 */ | |
1039 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1040 | } | |
b8ce3359 | 1041 | |
0e078e2f TG |
1042 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1043 | value = apic_read(APIC_LVT1); | |
1044 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1045 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1046 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1047 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1048 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1049 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1050 | } |
1051 | ||
89039b37 | 1052 | /* |
0e078e2f | 1053 | * Power management |
89039b37 | 1054 | */ |
0e078e2f TG |
1055 | #ifdef CONFIG_PM |
1056 | ||
1057 | static struct { | |
1058 | /* 'active' is true if the local APIC was enabled by us and | |
1059 | not the BIOS; this signifies that we are also responsible | |
1060 | for disabling it before entering apm/acpi suspend */ | |
1061 | int active; | |
1062 | /* r/w apic fields */ | |
1063 | unsigned int apic_id; | |
1064 | unsigned int apic_taskpri; | |
1065 | unsigned int apic_ldr; | |
1066 | unsigned int apic_dfr; | |
1067 | unsigned int apic_spiv; | |
1068 | unsigned int apic_lvtt; | |
1069 | unsigned int apic_lvtpc; | |
1070 | unsigned int apic_lvt0; | |
1071 | unsigned int apic_lvt1; | |
1072 | unsigned int apic_lvterr; | |
1073 | unsigned int apic_tmict; | |
1074 | unsigned int apic_tdcr; | |
1075 | unsigned int apic_thmr; | |
1076 | } apic_pm_state; | |
1077 | ||
1078 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1079 | { | |
1080 | unsigned long flags; | |
1081 | int maxlvt; | |
89039b37 | 1082 | |
0e078e2f TG |
1083 | if (!apic_pm_state.active) |
1084 | return 0; | |
89039b37 | 1085 | |
0e078e2f | 1086 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1087 | |
0e078e2f TG |
1088 | apic_pm_state.apic_id = apic_read(APIC_ID); |
1089 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
1090 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1091 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1092 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1093 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1094 | if (maxlvt >= 4) | |
1095 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1096 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1097 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1098 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1099 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1100 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1101 | #ifdef CONFIG_X86_MCE_INTEL | |
1102 | if (maxlvt >= 5) | |
1103 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1104 | #endif | |
1105 | local_irq_save(flags); | |
1106 | disable_local_APIC(); | |
1107 | local_irq_restore(flags); | |
1108 | return 0; | |
1da177e4 LT |
1109 | } |
1110 | ||
0e078e2f | 1111 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1112 | { |
0e078e2f TG |
1113 | unsigned int l, h; |
1114 | unsigned long flags; | |
1115 | int maxlvt; | |
1da177e4 | 1116 | |
0e078e2f TG |
1117 | if (!apic_pm_state.active) |
1118 | return 0; | |
89b831ef | 1119 | |
0e078e2f | 1120 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1121 | |
0e078e2f TG |
1122 | local_irq_save(flags); |
1123 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1124 | l &= ~MSR_IA32_APICBASE_BASE; | |
1125 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1126 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1127 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1128 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1129 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1130 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1131 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1132 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1133 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1134 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1135 | #ifdef CONFIG_X86_MCE_INTEL | |
1136 | if (maxlvt >= 5) | |
1137 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1138 | #endif | |
1139 | if (maxlvt >= 4) | |
1140 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1141 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1142 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1143 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1144 | apic_write(APIC_ESR, 0); | |
1145 | apic_read(APIC_ESR); | |
1146 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1147 | apic_write(APIC_ESR, 0); | |
1148 | apic_read(APIC_ESR); | |
1149 | local_irq_restore(flags); | |
1150 | return 0; | |
1151 | } | |
b8ce3359 | 1152 | |
0e078e2f TG |
1153 | static struct sysdev_class lapic_sysclass = { |
1154 | .name = "lapic", | |
1155 | .resume = lapic_resume, | |
1156 | .suspend = lapic_suspend, | |
1157 | }; | |
b8ce3359 | 1158 | |
0e078e2f | 1159 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1160 | .id = 0, |
1161 | .cls = &lapic_sysclass, | |
0e078e2f | 1162 | }; |
b8ce3359 | 1163 | |
0e078e2f TG |
1164 | static void __cpuinit apic_pm_activate(void) |
1165 | { | |
1166 | apic_pm_state.active = 1; | |
1da177e4 LT |
1167 | } |
1168 | ||
0e078e2f | 1169 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1170 | { |
0e078e2f | 1171 | int error; |
e83a5fdc | 1172 | |
0e078e2f TG |
1173 | if (!cpu_has_apic) |
1174 | return 0; | |
1175 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1176 | |
0e078e2f TG |
1177 | error = sysdev_class_register(&lapic_sysclass); |
1178 | if (!error) | |
1179 | error = sysdev_register(&device_lapic); | |
1180 | return error; | |
1da177e4 | 1181 | } |
0e078e2f TG |
1182 | device_initcall(init_lapic_sysfs); |
1183 | ||
1184 | #else /* CONFIG_PM */ | |
1185 | ||
1186 | static void apic_pm_activate(void) { } | |
1187 | ||
1188 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1189 | |
1190 | /* | |
f8bf3c65 | 1191 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1192 | * |
1193 | * Thus far, the major user of this is IBM's Summit2 series: | |
1194 | * | |
637029c6 | 1195 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1196 | * multi-chassis. Use available data to take a good guess. |
1197 | * If in doubt, go HPET. | |
1198 | */ | |
f8bf3c65 | 1199 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1200 | { |
1201 | int i, clusters, zeros; | |
1202 | unsigned id; | |
322850af | 1203 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1204 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1205 | ||
322850af YL |
1206 | /* |
1207 | * there is not this kind of box with AMD CPU yet. | |
1208 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1209 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1210 | * vsmp box still need checking... |
322850af | 1211 | */ |
1cb68487 | 1212 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1213 | return 0; |
1214 | ||
1215 | bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr; | |
376ec33f | 1216 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1217 | |
1218 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1219 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1220 | if (bios_cpu_apicid) { |
1221 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1222 | } |
1223 | else if (i < nr_cpu_ids) { | |
1224 | if (cpu_present(i)) | |
1225 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1226 | else | |
1227 | continue; | |
1228 | } | |
1229 | else | |
1230 | break; | |
1231 | ||
1da177e4 LT |
1232 | if (id != BAD_APICID) |
1233 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1234 | } | |
1235 | ||
1236 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1237 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1238 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1239 | * Since clusters are allocated sequentially, count zeros only if | |
1240 | * they are bounded by ones. | |
1da177e4 LT |
1241 | */ |
1242 | clusters = 0; | |
1243 | zeros = 0; | |
1244 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1245 | if (test_bit(i, clustermap)) { | |
1246 | clusters += 1 + zeros; | |
1247 | zeros = 0; | |
1248 | } else | |
1249 | ++zeros; | |
1250 | } | |
1251 | ||
1cb68487 RT |
1252 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1253 | * not guaranteed to be synced between boards | |
1254 | */ | |
1255 | if (is_vsmp_box() && clusters > 1) | |
1256 | return 1; | |
1257 | ||
1da177e4 | 1258 | /* |
f8bf3c65 | 1259 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1260 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1261 | * out, but AFAIK this will work even for them. | |
1262 | */ | |
1263 | return (clusters > 2); | |
1264 | } | |
1265 | ||
1266 | /* | |
0e078e2f | 1267 | * APIC command line parameters |
1da177e4 | 1268 | */ |
0e078e2f | 1269 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1270 | { |
0e078e2f TG |
1271 | if (str == NULL) { |
1272 | skip_ioapic_setup = 0; | |
1273 | ioapic_force = 1; | |
1274 | return 0; | |
1da177e4 | 1275 | } |
0e078e2f TG |
1276 | if (strcmp("debug", str) == 0) |
1277 | apic_verbosity = APIC_DEBUG; | |
1278 | else if (strcmp("verbose", str) == 0) | |
1279 | apic_verbosity = APIC_VERBOSE; | |
1280 | else { | |
1281 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1282 | " use apic=verbose or apic=debug\n", str); | |
1283 | return -EINVAL; | |
1da177e4 LT |
1284 | } |
1285 | ||
1da177e4 LT |
1286 | return 0; |
1287 | } | |
0e078e2f | 1288 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1289 | |
6935d1f9 TG |
1290 | static __init int setup_disableapic(char *str) |
1291 | { | |
1da177e4 | 1292 | disable_apic = 1; |
53756d37 | 1293 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1294 | return 0; |
1295 | } | |
1296 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1297 | |
2c8c0e6b | 1298 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1299 | static __init int setup_nolapic(char *str) |
1300 | { | |
2c8c0e6b | 1301 | return setup_disableapic(str); |
6935d1f9 | 1302 | } |
2c8c0e6b | 1303 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1304 | |
2e7c2838 LT |
1305 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1306 | { | |
1307 | local_apic_timer_c2_ok = 1; | |
1308 | return 0; | |
1309 | } | |
1310 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1311 | ||
6935d1f9 TG |
1312 | static __init int setup_noapictimer(char *str) |
1313 | { | |
73dea47f | 1314 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1315 | return 0; |
1da177e4 | 1316 | disable_apic_timer = 1; |
9b41046c | 1317 | return 1; |
6935d1f9 | 1318 | } |
9f75e9b7 | 1319 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1320 | |
0c3749c4 AK |
1321 | static __init int setup_apicpmtimer(char *s) |
1322 | { | |
1323 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1324 | notsc_setup(NULL); |
b8ce3359 | 1325 | return 0; |
0c3749c4 AK |
1326 | } |
1327 | __setup("apicpmtimer", setup_apicpmtimer); | |
1328 | ||
1e934dda YL |
1329 | static int __init lapic_insert_resource(void) |
1330 | { | |
1331 | if (!apic_phys) | |
1332 | return -1; | |
1333 | ||
1334 | /* Put local APIC into the resource map. */ | |
1335 | lapic_resource.start = apic_phys; | |
1336 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1337 | insert_resource(&iomem_resource, &lapic_resource); | |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * need call insert after e820_reserve_resources() | |
1344 | * that is using request_resource | |
1345 | */ | |
1346 | late_initcall(lapic_insert_resource); |