Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
1da177e4 LT |
30 | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/smp.h> | |
33 | #include <asm/mtrr.h> | |
34 | #include <asm/mpspec.h> | |
e83a5fdc | 35 | #include <asm/hpet.h> |
1da177e4 | 36 | #include <asm/pgalloc.h> |
75152114 | 37 | #include <asm/nmi.h> |
95833c83 | 38 | #include <asm/idle.h> |
73dea47f AK |
39 | #include <asm/proto.h> |
40 | #include <asm/timex.h> | |
2c8c0e6b | 41 | #include <asm/apic.h> |
1da177e4 | 42 | |
5af5573e | 43 | #include <mach_ipi.h> |
dd46e3ca | 44 | #include <mach_apic.h> |
5af5573e | 45 | |
aa276e1c | 46 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 47 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 48 | int disable_apic; |
89027d35 | 49 | int x2apic; |
1da177e4 | 50 | |
e83a5fdc | 51 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
52 | int local_apic_timer_c2_ok; |
53 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
54 | ||
e83a5fdc HS |
55 | /* |
56 | * Debug level, exported for io_apic.c | |
57 | */ | |
58 | int apic_verbosity; | |
59 | ||
bab4b27c AS |
60 | /* Have we found an MP table */ |
61 | int smp_found_config; | |
62 | ||
39928722 AD |
63 | static struct resource lapic_resource = { |
64 | .name = "Local APIC", | |
65 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
66 | }; | |
67 | ||
d03030e9 TG |
68 | static unsigned int calibration_result; |
69 | ||
ba7eda4c TG |
70 | static int lapic_next_event(unsigned long delta, |
71 | struct clock_event_device *evt); | |
72 | static void lapic_timer_setup(enum clock_event_mode mode, | |
73 | struct clock_event_device *evt); | |
ba7eda4c | 74 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 75 | static void apic_pm_activate(void); |
ba7eda4c TG |
76 | |
77 | static struct clock_event_device lapic_clockevent = { | |
78 | .name = "lapic", | |
79 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
80 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
81 | .shift = 32, | |
82 | .set_mode = lapic_timer_setup, | |
83 | .set_next_event = lapic_next_event, | |
84 | .broadcast = lapic_timer_broadcast, | |
85 | .rating = 100, | |
86 | .irq = -1, | |
87 | }; | |
88 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
89 | ||
d3432896 AK |
90 | static unsigned long apic_phys; |
91 | ||
3f530709 AS |
92 | unsigned long mp_lapic_addr; |
93 | ||
be8a5685 | 94 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
0e078e2f TG |
95 | /* |
96 | * Get the LAPIC version | |
97 | */ | |
98 | static inline int lapic_get_version(void) | |
ba7eda4c | 99 | { |
0e078e2f | 100 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
101 | } |
102 | ||
0e078e2f TG |
103 | /* |
104 | * Check, if the APIC is integrated or a seperate chip | |
105 | */ | |
106 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 107 | { |
0e078e2f | 108 | return 1; |
ba7eda4c TG |
109 | } |
110 | ||
111 | /* | |
0e078e2f | 112 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 113 | */ |
0e078e2f | 114 | static int modern_apic(void) |
ba7eda4c | 115 | { |
0e078e2f TG |
116 | /* AMD systems use old APIC versions, so check the CPU */ |
117 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
118 | boot_cpu_data.x86 >= 0xf) | |
119 | return 1; | |
120 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
121 | } |
122 | ||
1b374e4d | 123 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
124 | { |
125 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
126 | cpu_relax(); | |
127 | } | |
128 | ||
1b374e4d | 129 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 130 | { |
3c6bb07a | 131 | u32 send_status; |
8339e9fb FLV |
132 | int timeout; |
133 | ||
134 | timeout = 0; | |
135 | do { | |
136 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
137 | if (!send_status) | |
138 | break; | |
139 | udelay(100); | |
140 | } while (timeout++ < 1000); | |
141 | ||
142 | return send_status; | |
143 | } | |
144 | ||
1b374e4d SS |
145 | void xapic_icr_write(u32 low, u32 id) |
146 | { | |
147 | apic_write(APIC_ICR2, id << 24); | |
148 | apic_write(APIC_ICR, low); | |
149 | } | |
150 | ||
151 | u64 xapic_icr_read(void) | |
152 | { | |
153 | u32 icr1, icr2; | |
154 | ||
155 | icr2 = apic_read(APIC_ICR2); | |
156 | icr1 = apic_read(APIC_ICR); | |
157 | ||
158 | return (icr1 | ((u64)icr2 << 32)); | |
159 | } | |
160 | ||
161 | static struct apic_ops xapic_ops = { | |
162 | .read = native_apic_mem_read, | |
163 | .write = native_apic_mem_write, | |
164 | .write_atomic = native_apic_mem_write_atomic, | |
165 | .icr_read = xapic_icr_read, | |
166 | .icr_write = xapic_icr_write, | |
167 | .wait_icr_idle = xapic_wait_icr_idle, | |
168 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
169 | }; | |
170 | ||
171 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
172 | ||
173 | EXPORT_SYMBOL_GPL(apic_ops); | |
174 | ||
13c88fb5 SS |
175 | static void x2apic_wait_icr_idle(void) |
176 | { | |
177 | /* no need to wait for icr idle in x2apic */ | |
178 | return; | |
179 | } | |
180 | ||
181 | static u32 safe_x2apic_wait_icr_idle(void) | |
182 | { | |
183 | /* no need to wait for icr idle in x2apic */ | |
184 | return 0; | |
185 | } | |
186 | ||
187 | void x2apic_icr_write(u32 low, u32 id) | |
188 | { | |
189 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
190 | } | |
191 | ||
192 | u64 x2apic_icr_read(void) | |
193 | { | |
194 | unsigned long val; | |
195 | ||
196 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
197 | return val; | |
198 | } | |
199 | ||
200 | static struct apic_ops x2apic_ops = { | |
201 | .read = native_apic_msr_read, | |
202 | .write = native_apic_msr_write, | |
203 | .write_atomic = native_apic_msr_write, | |
204 | .icr_read = x2apic_icr_read, | |
205 | .icr_write = x2apic_icr_write, | |
206 | .wait_icr_idle = x2apic_wait_icr_idle, | |
207 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
208 | }; | |
209 | ||
0e078e2f TG |
210 | /** |
211 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
212 | */ | |
e9427101 | 213 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 214 | { |
11a8e778 | 215 | unsigned int v; |
6935d1f9 TG |
216 | |
217 | /* unmask and set to NMI */ | |
218 | v = APIC_DM_NMI; | |
11a8e778 | 219 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
220 | } |
221 | ||
0e078e2f TG |
222 | /** |
223 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
224 | */ | |
37e650c7 | 225 | int lapic_get_maxlvt(void) |
1da177e4 | 226 | { |
11a8e778 | 227 | unsigned int v, maxlvt; |
1da177e4 LT |
228 | |
229 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
230 | maxlvt = GET_APIC_MAXLVT(v); |
231 | return maxlvt; | |
232 | } | |
233 | ||
0e078e2f TG |
234 | /* |
235 | * This function sets up the local APIC timer, with a timeout of | |
236 | * 'clocks' APIC bus clock. During calibration we actually call | |
237 | * this function twice on the boot CPU, once with a bogus timeout | |
238 | * value, second time for real. The other (noncalibrating) CPUs | |
239 | * call this function only once, with the real, calibrated value. | |
240 | * | |
241 | * We do reads before writes even if unnecessary, to get around the | |
242 | * P5 APIC double write bug. | |
243 | */ | |
244 | ||
245 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) | |
1da177e4 | 246 | { |
0e078e2f | 247 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 248 | |
0e078e2f TG |
249 | lvtt_value = LOCAL_TIMER_VECTOR; |
250 | if (!oneshot) | |
251 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
252 | if (!irqen) | |
253 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 254 | |
0e078e2f | 255 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
256 | |
257 | /* | |
0e078e2f | 258 | * Divide PICLK by 16 |
1da177e4 | 259 | */ |
0e078e2f TG |
260 | tmp_value = apic_read(APIC_TDCR); |
261 | apic_write(APIC_TDCR, (tmp_value | |
262 | & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | |
263 | | APIC_TDR_DIV_16); | |
264 | ||
265 | if (!oneshot) | |
266 | apic_write(APIC_TMICT, clocks); | |
1da177e4 LT |
267 | } |
268 | ||
0e078e2f | 269 | /* |
7b83dae7 RR |
270 | * Setup extended LVT, AMD specific (K8, family 10h) |
271 | * | |
272 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
273 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 274 | */ |
7b83dae7 RR |
275 | |
276 | #define APIC_EILVT_LVTOFF_MCE 0 | |
277 | #define APIC_EILVT_LVTOFF_IBS 1 | |
278 | ||
279 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 280 | { |
7b83dae7 | 281 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 282 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 283 | |
0e078e2f | 284 | apic_write(reg, v); |
1da177e4 LT |
285 | } |
286 | ||
7b83dae7 RR |
287 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
288 | { | |
289 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
290 | return APIC_EILVT_LVTOFF_MCE; | |
291 | } | |
292 | ||
293 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
294 | { | |
295 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
296 | return APIC_EILVT_LVTOFF_IBS; | |
297 | } | |
298 | ||
0e078e2f TG |
299 | /* |
300 | * Program the next event, relative to now | |
301 | */ | |
302 | static int lapic_next_event(unsigned long delta, | |
303 | struct clock_event_device *evt) | |
1da177e4 | 304 | { |
0e078e2f TG |
305 | apic_write(APIC_TMICT, delta); |
306 | return 0; | |
1da177e4 LT |
307 | } |
308 | ||
0e078e2f TG |
309 | /* |
310 | * Setup the lapic timer in periodic or oneshot mode | |
311 | */ | |
312 | static void lapic_timer_setup(enum clock_event_mode mode, | |
313 | struct clock_event_device *evt) | |
9b7711f0 HS |
314 | { |
315 | unsigned long flags; | |
0e078e2f | 316 | unsigned int v; |
9b7711f0 | 317 | |
0e078e2f TG |
318 | /* Lapic used as dummy for broadcast ? */ |
319 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
320 | return; |
321 | ||
322 | local_irq_save(flags); | |
323 | ||
0e078e2f TG |
324 | switch (mode) { |
325 | case CLOCK_EVT_MODE_PERIODIC: | |
326 | case CLOCK_EVT_MODE_ONESHOT: | |
327 | __setup_APIC_LVTT(calibration_result, | |
328 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
329 | break; | |
330 | case CLOCK_EVT_MODE_UNUSED: | |
331 | case CLOCK_EVT_MODE_SHUTDOWN: | |
332 | v = apic_read(APIC_LVTT); | |
333 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
334 | apic_write(APIC_LVTT, v); | |
335 | break; | |
336 | case CLOCK_EVT_MODE_RESUME: | |
337 | /* Nothing to do here */ | |
338 | break; | |
339 | } | |
9b7711f0 HS |
340 | |
341 | local_irq_restore(flags); | |
342 | } | |
343 | ||
1da177e4 | 344 | /* |
0e078e2f | 345 | * Local APIC timer broadcast function |
1da177e4 | 346 | */ |
0e078e2f | 347 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 348 | { |
0e078e2f TG |
349 | #ifdef CONFIG_SMP |
350 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
351 | #endif | |
352 | } | |
1da177e4 | 353 | |
0e078e2f TG |
354 | /* |
355 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
356 | * of the boot CPU and register the clock event in the framework. | |
357 | */ | |
358 | static void setup_APIC_timer(void) | |
359 | { | |
360 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 361 | |
0e078e2f TG |
362 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
363 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 364 | |
0e078e2f TG |
365 | clockevents_register_device(levt); |
366 | } | |
1da177e4 | 367 | |
0e078e2f TG |
368 | /* |
369 | * In this function we calibrate APIC bus clocks to the external | |
370 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
371 | * to calibrate, since some later bootup code depends on getting | |
372 | * the first irq? Ugh. | |
373 | * | |
374 | * We want to do the calibration only once since we | |
375 | * want to have local timer irqs syncron. CPUs connected | |
376 | * by the same APIC bus have the very same bus frequency. | |
377 | * And we want to have irqs off anyways, no accidental | |
378 | * APIC irq that way. | |
379 | */ | |
380 | ||
381 | #define TICK_COUNT 100000000 | |
382 | ||
383 | static void __init calibrate_APIC_clock(void) | |
384 | { | |
385 | unsigned apic, apic_start; | |
386 | unsigned long tsc, tsc_start; | |
387 | int result; | |
388 | ||
389 | local_irq_disable(); | |
390 | ||
391 | /* | |
392 | * Put whatever arbitrary (but long enough) timeout | |
393 | * value into the APIC clock, we just want to get the | |
394 | * counter running for calibration. | |
395 | * | |
396 | * No interrupt enable ! | |
397 | */ | |
398 | __setup_APIC_LVTT(250000000, 0, 0); | |
399 | ||
400 | apic_start = apic_read(APIC_TMCCT); | |
401 | #ifdef CONFIG_X86_PM_TIMER | |
402 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
403 | pmtimer_wait(5000); /* 5ms wait */ | |
404 | apic = apic_read(APIC_TMCCT); | |
405 | result = (apic_start - apic) * 1000L / 5; | |
406 | } else | |
407 | #endif | |
408 | { | |
409 | rdtscll(tsc_start); | |
410 | ||
411 | do { | |
412 | apic = apic_read(APIC_TMCCT); | |
413 | rdtscll(tsc); | |
414 | } while ((tsc - tsc_start) < TICK_COUNT && | |
415 | (apic_start - apic) < TICK_COUNT); | |
416 | ||
417 | result = (apic_start - apic) * 1000L * tsc_khz / | |
418 | (tsc - tsc_start); | |
419 | } | |
420 | ||
421 | local_irq_enable(); | |
422 | ||
423 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
424 | ||
425 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
426 | result / 1000 / 1000, result / 1000 % 1000); | |
427 | ||
428 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
429 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
430 | lapic_clockevent.shift); | |
0e078e2f TG |
431 | lapic_clockevent.max_delta_ns = |
432 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
433 | lapic_clockevent.min_delta_ns = | |
434 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
435 | ||
436 | calibration_result = result / HZ; | |
437 | } | |
438 | ||
e83a5fdc HS |
439 | /* |
440 | * Setup the boot APIC | |
441 | * | |
442 | * Calibrate and verify the result. | |
443 | */ | |
0e078e2f TG |
444 | void __init setup_boot_APIC_clock(void) |
445 | { | |
446 | /* | |
447 | * The local apic timer can be disabled via the kernel commandline. | |
448 | * Register the lapic timer as a dummy clock event source on SMP | |
449 | * systems, so the broadcast mechanism is used. On UP systems simply | |
450 | * ignore it. | |
451 | */ | |
452 | if (disable_apic_timer) { | |
453 | printk(KERN_INFO "Disabling APIC timer\n"); | |
454 | /* No broadcast on UP ! */ | |
9d09951d TG |
455 | if (num_possible_cpus() > 1) { |
456 | lapic_clockevent.mult = 1; | |
0e078e2f | 457 | setup_APIC_timer(); |
9d09951d | 458 | } |
0e078e2f TG |
459 | return; |
460 | } | |
461 | ||
462 | printk(KERN_INFO "Using local APIC timer interrupts.\n"); | |
463 | calibrate_APIC_clock(); | |
464 | ||
c2b84b30 TG |
465 | /* |
466 | * Do a sanity check on the APIC calibration result | |
467 | */ | |
468 | if (calibration_result < (1000000 / HZ)) { | |
469 | printk(KERN_WARNING | |
470 | "APIC frequency too slow, disabling apic timer\n"); | |
471 | /* No broadcast on UP ! */ | |
472 | if (num_possible_cpus() > 1) | |
473 | setup_APIC_timer(); | |
474 | return; | |
475 | } | |
476 | ||
0e078e2f TG |
477 | /* |
478 | * If nmi_watchdog is set to IO_APIC, we need the | |
479 | * PIT/HPET going. Otherwise register lapic as a dummy | |
480 | * device. | |
481 | */ | |
482 | if (nmi_watchdog != NMI_IO_APIC) | |
483 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
484 | else | |
485 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 486 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f TG |
487 | |
488 | setup_APIC_timer(); | |
489 | } | |
490 | ||
0e078e2f TG |
491 | void __cpuinit setup_secondary_APIC_clock(void) |
492 | { | |
0e078e2f TG |
493 | setup_APIC_timer(); |
494 | } | |
495 | ||
496 | /* | |
497 | * The guts of the apic timer interrupt | |
498 | */ | |
499 | static void local_apic_timer_interrupt(void) | |
500 | { | |
501 | int cpu = smp_processor_id(); | |
502 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
503 | ||
504 | /* | |
505 | * Normally we should not be here till LAPIC has been initialized but | |
506 | * in some cases like kdump, its possible that there is a pending LAPIC | |
507 | * timer interrupt from previous kernel's context and is delivered in | |
508 | * new kernel the moment interrupts are enabled. | |
509 | * | |
510 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
511 | * its possible that when we get here evt->event_handler is NULL. | |
512 | * Check for event_handler being NULL and discard the interrupt as | |
513 | * spurious. | |
514 | */ | |
515 | if (!evt->event_handler) { | |
516 | printk(KERN_WARNING | |
517 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
518 | /* Switch it off */ | |
519 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
520 | return; | |
521 | } | |
522 | ||
523 | /* | |
524 | * the NMI deadlock-detector uses this. | |
525 | */ | |
526 | add_pda(apic_timer_irqs, 1); | |
527 | ||
528 | evt->event_handler(evt); | |
529 | } | |
530 | ||
531 | /* | |
532 | * Local APIC timer interrupt. This is the most natural way for doing | |
533 | * local interrupts, but local timer interrupts can be emulated by | |
534 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
535 | * | |
536 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
537 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
538 | */ | |
539 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
540 | { | |
541 | struct pt_regs *old_regs = set_irq_regs(regs); | |
542 | ||
543 | /* | |
544 | * NOTE! We'd better ACK the irq immediately, | |
545 | * because timer handling can be slow. | |
546 | */ | |
547 | ack_APIC_irq(); | |
548 | /* | |
549 | * update_process_times() expects us to have done irq_enter(). | |
550 | * Besides, if we don't timer interrupts ignore the global | |
551 | * interrupt lock, which is the WrongThing (tm) to do. | |
552 | */ | |
553 | exit_idle(); | |
554 | irq_enter(); | |
555 | local_apic_timer_interrupt(); | |
556 | irq_exit(); | |
557 | set_irq_regs(old_regs); | |
558 | } | |
559 | ||
560 | int setup_profiling_timer(unsigned int multiplier) | |
561 | { | |
562 | return -EINVAL; | |
563 | } | |
564 | ||
565 | ||
566 | /* | |
567 | * Local APIC start and shutdown | |
568 | */ | |
569 | ||
570 | /** | |
571 | * clear_local_APIC - shutdown the local APIC | |
572 | * | |
573 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
574 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
575 | * leftovers during boot. | |
576 | */ | |
577 | void clear_local_APIC(void) | |
578 | { | |
2584a82d | 579 | int maxlvt; |
0e078e2f TG |
580 | u32 v; |
581 | ||
d3432896 AK |
582 | /* APIC hasn't been mapped yet */ |
583 | if (!apic_phys) | |
584 | return; | |
585 | ||
586 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
587 | /* |
588 | * Masking an LVT entry can trigger a local APIC error | |
589 | * if the vector is zero. Mask LVTERR first to prevent this. | |
590 | */ | |
591 | if (maxlvt >= 3) { | |
592 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
593 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
594 | } | |
595 | /* | |
596 | * Careful: we have to set masks only first to deassert | |
597 | * any level-triggered sources. | |
598 | */ | |
599 | v = apic_read(APIC_LVTT); | |
600 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
601 | v = apic_read(APIC_LVT0); | |
602 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
603 | v = apic_read(APIC_LVT1); | |
604 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
605 | if (maxlvt >= 4) { | |
606 | v = apic_read(APIC_LVTPC); | |
607 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
608 | } | |
609 | ||
610 | /* | |
611 | * Clean APIC state for other OSs: | |
612 | */ | |
613 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
614 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
615 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
616 | if (maxlvt >= 3) | |
617 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
618 | if (maxlvt >= 4) | |
619 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
620 | apic_write(APIC_ESR, 0); | |
621 | apic_read(APIC_ESR); | |
622 | } | |
623 | ||
624 | /** | |
625 | * disable_local_APIC - clear and disable the local APIC | |
626 | */ | |
627 | void disable_local_APIC(void) | |
628 | { | |
629 | unsigned int value; | |
630 | ||
631 | clear_local_APIC(); | |
632 | ||
633 | /* | |
634 | * Disable APIC (implies clearing of registers | |
635 | * for 82489DX!). | |
636 | */ | |
637 | value = apic_read(APIC_SPIV); | |
638 | value &= ~APIC_SPIV_APIC_ENABLED; | |
639 | apic_write(APIC_SPIV, value); | |
640 | } | |
641 | ||
642 | void lapic_shutdown(void) | |
643 | { | |
644 | unsigned long flags; | |
645 | ||
646 | if (!cpu_has_apic) | |
647 | return; | |
648 | ||
649 | local_irq_save(flags); | |
650 | ||
651 | disable_local_APIC(); | |
652 | ||
653 | local_irq_restore(flags); | |
654 | } | |
655 | ||
656 | /* | |
657 | * This is to verify that we're looking at a real local APIC. | |
658 | * Check these against your board if the CPUs aren't getting | |
659 | * started for no apparent reason. | |
660 | */ | |
661 | int __init verify_local_APIC(void) | |
662 | { | |
663 | unsigned int reg0, reg1; | |
664 | ||
665 | /* | |
666 | * The version register is read-only in a real APIC. | |
667 | */ | |
668 | reg0 = apic_read(APIC_LVR); | |
669 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
670 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
671 | reg1 = apic_read(APIC_LVR); | |
672 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
673 | ||
674 | /* | |
675 | * The two version reads above should print the same | |
676 | * numbers. If the second one is different, then we | |
677 | * poke at a non-APIC. | |
678 | */ | |
679 | if (reg1 != reg0) | |
680 | return 0; | |
681 | ||
682 | /* | |
683 | * Check if the version looks reasonably. | |
684 | */ | |
685 | reg1 = GET_APIC_VERSION(reg0); | |
686 | if (reg1 == 0x00 || reg1 == 0xff) | |
687 | return 0; | |
688 | reg1 = lapic_get_maxlvt(); | |
689 | if (reg1 < 0x02 || reg1 == 0xff) | |
690 | return 0; | |
691 | ||
692 | /* | |
693 | * The ID register is read/write in a real APIC. | |
694 | */ | |
2d7a66d0 | 695 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
696 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
697 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 698 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
699 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
700 | apic_write(APIC_ID, reg0); | |
701 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
702 | return 0; | |
703 | ||
704 | /* | |
1da177e4 LT |
705 | * The next two are just to see if we have sane values. |
706 | * They're only really relevant if we're in Virtual Wire | |
707 | * compatibility mode, but most boxes are anymore. | |
708 | */ | |
709 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 710 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
711 | reg1 = apic_read(APIC_LVT1); |
712 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
713 | ||
714 | return 1; | |
715 | } | |
716 | ||
0e078e2f TG |
717 | /** |
718 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
719 | */ | |
1da177e4 LT |
720 | void __init sync_Arb_IDs(void) |
721 | { | |
722 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
0e078e2f | 723 | if (modern_apic()) |
1da177e4 LT |
724 | return; |
725 | ||
726 | /* | |
727 | * Wait for idle. | |
728 | */ | |
729 | apic_wait_icr_idle(); | |
730 | ||
731 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 732 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
733 | | APIC_DM_INIT); |
734 | } | |
735 | ||
1da177e4 LT |
736 | /* |
737 | * An initial setup of the virtual wire mode. | |
738 | */ | |
739 | void __init init_bsp_APIC(void) | |
740 | { | |
11a8e778 | 741 | unsigned int value; |
1da177e4 LT |
742 | |
743 | /* | |
744 | * Don't do the setup now if we have a SMP BIOS as the | |
745 | * through-I/O-APIC virtual wire mode might be active. | |
746 | */ | |
747 | if (smp_found_config || !cpu_has_apic) | |
748 | return; | |
749 | ||
750 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
751 | |
752 | /* | |
753 | * Do not trust the local APIC being empty at bootup. | |
754 | */ | |
755 | clear_local_APIC(); | |
756 | ||
757 | /* | |
758 | * Enable APIC. | |
759 | */ | |
760 | value = apic_read(APIC_SPIV); | |
761 | value &= ~APIC_VECTOR_MASK; | |
762 | value |= APIC_SPIV_APIC_ENABLED; | |
763 | value |= APIC_SPIV_FOCUS_DISABLED; | |
764 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 765 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
766 | |
767 | /* | |
768 | * Set up the virtual wire mode. | |
769 | */ | |
11a8e778 | 770 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 771 | value = APIC_DM_NMI; |
11a8e778 | 772 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
773 | } |
774 | ||
0e078e2f TG |
775 | /** |
776 | * setup_local_APIC - setup the local APIC | |
777 | */ | |
778 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 779 | { |
739f33b3 | 780 | unsigned int value; |
da7ed9f9 | 781 | int i, j; |
1da177e4 | 782 | |
ac23d4ee | 783 | preempt_disable(); |
1da177e4 | 784 | value = apic_read(APIC_LVR); |
1da177e4 | 785 | |
fe7414a2 | 786 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
787 | |
788 | /* | |
789 | * Double-check whether this APIC is really registered. | |
790 | * This is meaningless in clustered apic mode, so we skip it. | |
791 | */ | |
792 | if (!apic_id_registered()) | |
793 | BUG(); | |
794 | ||
795 | /* | |
796 | * Intel recommends to set DFR, LDR and TPR before enabling | |
797 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
798 | * document number 292116). So here it goes... | |
799 | */ | |
800 | init_apic_ldr(); | |
801 | ||
802 | /* | |
803 | * Set Task Priority to 'accept all'. We never change this | |
804 | * later on. | |
805 | */ | |
806 | value = apic_read(APIC_TASKPRI); | |
807 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 808 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 809 | |
da7ed9f9 VG |
810 | /* |
811 | * After a crash, we no longer service the interrupts and a pending | |
812 | * interrupt from previous kernel might still have ISR bit set. | |
813 | * | |
814 | * Most probably by now CPU has serviced that pending interrupt and | |
815 | * it might not have done the ack_APIC_irq() because it thought, | |
816 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
817 | * does not clear the ISR bit and cpu thinks it has already serivced | |
818 | * the interrupt. Hence a vector might get locked. It was noticed | |
819 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
820 | */ | |
821 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
822 | value = apic_read(APIC_ISR + i*0x10); | |
823 | for (j = 31; j >= 0; j--) { | |
824 | if (value & (1<<j)) | |
825 | ack_APIC_irq(); | |
826 | } | |
827 | } | |
828 | ||
1da177e4 LT |
829 | /* |
830 | * Now that we are all set up, enable the APIC | |
831 | */ | |
832 | value = apic_read(APIC_SPIV); | |
833 | value &= ~APIC_VECTOR_MASK; | |
834 | /* | |
835 | * Enable APIC | |
836 | */ | |
837 | value |= APIC_SPIV_APIC_ENABLED; | |
838 | ||
3f14c746 AK |
839 | /* We always use processor focus */ |
840 | ||
1da177e4 LT |
841 | /* |
842 | * Set spurious IRQ vector | |
843 | */ | |
844 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 845 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
846 | |
847 | /* | |
848 | * Set up LVT0, LVT1: | |
849 | * | |
850 | * set up through-local-APIC on the BP's LINT0. This is not | |
851 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
852 | * we delegate interrupts to the 8259A. | |
853 | */ | |
854 | /* | |
855 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
856 | */ | |
857 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 858 | if (!smp_processor_id() && !value) { |
1da177e4 | 859 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
860 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
861 | smp_processor_id()); | |
1da177e4 LT |
862 | } else { |
863 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
864 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
865 | smp_processor_id()); | |
1da177e4 | 866 | } |
11a8e778 | 867 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
868 | |
869 | /* | |
870 | * only the BP should see the LINT1 NMI signal, obviously. | |
871 | */ | |
872 | if (!smp_processor_id()) | |
873 | value = APIC_DM_NMI; | |
874 | else | |
875 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 876 | apic_write(APIC_LVT1, value); |
ac23d4ee | 877 | preempt_enable(); |
739f33b3 | 878 | } |
1da177e4 | 879 | |
a4928cff | 880 | static void __cpuinit lapic_setup_esr(void) |
739f33b3 AK |
881 | { |
882 | unsigned maxlvt = lapic_get_maxlvt(); | |
883 | ||
884 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR); | |
1c69524c | 885 | /* |
739f33b3 | 886 | * spec says clear errors after enabling vector. |
1c69524c | 887 | */ |
739f33b3 AK |
888 | if (maxlvt > 3) |
889 | apic_write(APIC_ESR, 0); | |
890 | } | |
1da177e4 | 891 | |
739f33b3 AK |
892 | void __cpuinit end_local_APIC_setup(void) |
893 | { | |
894 | lapic_setup_esr(); | |
f2802e7f | 895 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 896 | apic_pm_activate(); |
1da177e4 | 897 | } |
1da177e4 LT |
898 | |
899 | /* | |
900 | * Detect and enable local APICs on non-SMP boards. | |
901 | * Original code written by Keir Fraser. | |
902 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 903 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 904 | */ |
0e078e2f | 905 | static int __init detect_init_APIC(void) |
1da177e4 LT |
906 | { |
907 | if (!cpu_has_apic) { | |
908 | printk(KERN_INFO "No local APIC present\n"); | |
909 | return -1; | |
910 | } | |
911 | ||
912 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 913 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
914 | return 0; |
915 | } | |
916 | ||
8643f9d0 YL |
917 | void __init early_init_lapic_mapping(void) |
918 | { | |
431ee79d | 919 | unsigned long phys_addr; |
8643f9d0 YL |
920 | |
921 | /* | |
922 | * If no local APIC can be found then go out | |
923 | * : it means there is no mpatable and MADT | |
924 | */ | |
925 | if (!smp_found_config) | |
926 | return; | |
927 | ||
431ee79d | 928 | phys_addr = mp_lapic_addr; |
8643f9d0 | 929 | |
431ee79d | 930 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 931 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 932 | APIC_BASE, phys_addr); |
8643f9d0 YL |
933 | |
934 | /* | |
935 | * Fetch the APIC ID of the BSP in case we have a | |
936 | * default configuration (or the MP table is broken). | |
937 | */ | |
05f2d12c | 938 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
8643f9d0 YL |
939 | } |
940 | ||
0e078e2f TG |
941 | /** |
942 | * init_apic_mappings - initialize APIC mappings | |
943 | */ | |
1da177e4 LT |
944 | void __init init_apic_mappings(void) |
945 | { | |
1da177e4 LT |
946 | /* |
947 | * If no local APIC can be found then set up a fake all | |
948 | * zeroes page to simulate the local APIC and another | |
949 | * one for the IO-APIC. | |
950 | */ | |
951 | if (!smp_found_config && detect_init_APIC()) { | |
952 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
953 | apic_phys = __pa(apic_phys); | |
954 | } else | |
955 | apic_phys = mp_lapic_addr; | |
956 | ||
957 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
958 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
959 | APIC_BASE, apic_phys); | |
1da177e4 LT |
960 | |
961 | /* | |
962 | * Fetch the APIC ID of the BSP in case we have a | |
963 | * default configuration (or the MP table is broken). | |
964 | */ | |
05f2d12c | 965 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 LT |
966 | } |
967 | ||
968 | /* | |
0e078e2f TG |
969 | * This initializes the IO-APIC and APIC hardware if this is |
970 | * a UP kernel. | |
1da177e4 | 971 | */ |
0e078e2f | 972 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 973 | { |
0e078e2f TG |
974 | if (disable_apic) { |
975 | printk(KERN_INFO "Apic disabled\n"); | |
976 | return -1; | |
977 | } | |
978 | if (!cpu_has_apic) { | |
979 | disable_apic = 1; | |
980 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
981 | return -1; | |
982 | } | |
1da177e4 | 983 | |
0e078e2f | 984 | verify_local_APIC(); |
1da177e4 | 985 | |
b5841765 GC |
986 | connect_bsp_APIC(); |
987 | ||
b6df1b8b | 988 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 989 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 990 | |
0e078e2f | 991 | setup_local_APIC(); |
1da177e4 | 992 | |
739f33b3 AK |
993 | /* |
994 | * Now enable IO-APICs, actually call clear_IO_APIC | |
995 | * We need clear_IO_APIC before enabling vector on BP | |
996 | */ | |
997 | if (!skip_ioapic_setup && nr_ioapics) | |
998 | enable_IO_APIC(); | |
999 | ||
acae7d90 MR |
1000 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1001 | localise_nmi_watchdog(); | |
739f33b3 AK |
1002 | end_local_APIC_setup(); |
1003 | ||
0e078e2f TG |
1004 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1005 | setup_IO_APIC(); | |
1006 | else | |
1007 | nr_ioapics = 0; | |
1008 | setup_boot_APIC_clock(); | |
1009 | check_nmi_watchdog(); | |
1010 | return 0; | |
1da177e4 LT |
1011 | } |
1012 | ||
1013 | /* | |
0e078e2f | 1014 | * Local APIC interrupts |
1da177e4 LT |
1015 | */ |
1016 | ||
0e078e2f TG |
1017 | /* |
1018 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1019 | */ | |
1020 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1021 | { |
0e078e2f TG |
1022 | unsigned int v; |
1023 | exit_idle(); | |
1024 | irq_enter(); | |
1da177e4 | 1025 | /* |
0e078e2f TG |
1026 | * Check if this really is a spurious interrupt and ACK it |
1027 | * if it is a vectored one. Just in case... | |
1028 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1029 | */ |
0e078e2f TG |
1030 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1031 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1032 | ack_APIC_irq(); | |
c4d58cbd | 1033 | |
0e078e2f TG |
1034 | add_pda(irq_spurious_count, 1); |
1035 | irq_exit(); | |
1036 | } | |
1da177e4 | 1037 | |
0e078e2f TG |
1038 | /* |
1039 | * This interrupt should never happen with our APIC/SMP architecture | |
1040 | */ | |
1041 | asmlinkage void smp_error_interrupt(void) | |
1042 | { | |
1043 | unsigned int v, v1; | |
1da177e4 | 1044 | |
0e078e2f TG |
1045 | exit_idle(); |
1046 | irq_enter(); | |
1047 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1048 | v = apic_read(APIC_ESR); | |
1049 | apic_write(APIC_ESR, 0); | |
1050 | v1 = apic_read(APIC_ESR); | |
1051 | ack_APIC_irq(); | |
1052 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1053 | |
0e078e2f TG |
1054 | /* Here is what the APIC error bits mean: |
1055 | 0: Send CS error | |
1056 | 1: Receive CS error | |
1057 | 2: Send accept error | |
1058 | 3: Receive accept error | |
1059 | 4: Reserved | |
1060 | 5: Send illegal vector | |
1061 | 6: Received illegal vector | |
1062 | 7: Illegal register address | |
1063 | */ | |
1064 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1065 | smp_processor_id(), v , v1); | |
1066 | irq_exit(); | |
1da177e4 LT |
1067 | } |
1068 | ||
b5841765 GC |
1069 | /** |
1070 | * * connect_bsp_APIC - attach the APIC to the interrupt system | |
1071 | * */ | |
1072 | void __init connect_bsp_APIC(void) | |
1073 | { | |
1074 | enable_apic_mode(); | |
1075 | } | |
1076 | ||
0e078e2f | 1077 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1078 | { |
0e078e2f TG |
1079 | /* Go back to Virtual Wire compatibility mode */ |
1080 | unsigned long value; | |
1da177e4 | 1081 | |
0e078e2f TG |
1082 | /* For the spurious interrupt use vector F, and enable it */ |
1083 | value = apic_read(APIC_SPIV); | |
1084 | value &= ~APIC_VECTOR_MASK; | |
1085 | value |= APIC_SPIV_APIC_ENABLED; | |
1086 | value |= 0xf; | |
1087 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1088 | |
0e078e2f TG |
1089 | if (!virt_wire_setup) { |
1090 | /* | |
1091 | * For LVT0 make it edge triggered, active high, | |
1092 | * external and enabled | |
1093 | */ | |
1094 | value = apic_read(APIC_LVT0); | |
1095 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1096 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1097 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1098 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1099 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1100 | apic_write(APIC_LVT0, value); | |
1101 | } else { | |
1102 | /* Disable LVT0 */ | |
1103 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1104 | } | |
b8ce3359 | 1105 | |
0e078e2f TG |
1106 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ |
1107 | value = apic_read(APIC_LVT1); | |
1108 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1109 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1110 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1111 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1112 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1113 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1114 | } |
1115 | ||
be8a5685 AS |
1116 | void __cpuinit generic_processor_info(int apicid, int version) |
1117 | { | |
1118 | int cpu; | |
1119 | cpumask_t tmp_map; | |
1120 | ||
1121 | if (num_processors >= NR_CPUS) { | |
1122 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1123 | " Processor ignored.\n", NR_CPUS); | |
1124 | return; | |
1125 | } | |
1126 | ||
1127 | if (num_processors >= maxcpus) { | |
1128 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1129 | " Processor ignored.\n", maxcpus); | |
1130 | return; | |
1131 | } | |
1132 | ||
1133 | num_processors++; | |
1134 | cpus_complement(tmp_map, cpu_present_map); | |
1135 | cpu = first_cpu(tmp_map); | |
1136 | ||
1137 | physid_set(apicid, phys_cpu_present_map); | |
1138 | if (apicid == boot_cpu_physical_apicid) { | |
1139 | /* | |
1140 | * x86_bios_cpu_apicid is required to have processors listed | |
1141 | * in same order as logical cpu numbers. Hence the first | |
1142 | * entry is BSP, and so on. | |
1143 | */ | |
1144 | cpu = 0; | |
1145 | } | |
e0da3364 YL |
1146 | if (apicid > max_physical_apicid) |
1147 | max_physical_apicid = apicid; | |
1148 | ||
be8a5685 | 1149 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1150 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1151 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1152 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1153 | |
1154 | cpu_to_apicid[cpu] = apicid; | |
1155 | bios_cpu_apicid[cpu] = apicid; | |
1156 | } else { | |
1157 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1158 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1159 | } | |
1160 | ||
1161 | cpu_set(cpu, cpu_possible_map); | |
1162 | cpu_set(cpu, cpu_present_map); | |
1163 | } | |
1164 | ||
0c81c746 SS |
1165 | int hard_smp_processor_id(void) |
1166 | { | |
1167 | return read_apic_id(); | |
1168 | } | |
1169 | ||
89039b37 | 1170 | /* |
0e078e2f | 1171 | * Power management |
89039b37 | 1172 | */ |
0e078e2f TG |
1173 | #ifdef CONFIG_PM |
1174 | ||
1175 | static struct { | |
1176 | /* 'active' is true if the local APIC was enabled by us and | |
1177 | not the BIOS; this signifies that we are also responsible | |
1178 | for disabling it before entering apm/acpi suspend */ | |
1179 | int active; | |
1180 | /* r/w apic fields */ | |
1181 | unsigned int apic_id; | |
1182 | unsigned int apic_taskpri; | |
1183 | unsigned int apic_ldr; | |
1184 | unsigned int apic_dfr; | |
1185 | unsigned int apic_spiv; | |
1186 | unsigned int apic_lvtt; | |
1187 | unsigned int apic_lvtpc; | |
1188 | unsigned int apic_lvt0; | |
1189 | unsigned int apic_lvt1; | |
1190 | unsigned int apic_lvterr; | |
1191 | unsigned int apic_tmict; | |
1192 | unsigned int apic_tdcr; | |
1193 | unsigned int apic_thmr; | |
1194 | } apic_pm_state; | |
1195 | ||
1196 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1197 | { | |
1198 | unsigned long flags; | |
1199 | int maxlvt; | |
89039b37 | 1200 | |
0e078e2f TG |
1201 | if (!apic_pm_state.active) |
1202 | return 0; | |
89039b37 | 1203 | |
0e078e2f | 1204 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1205 | |
2d7a66d0 | 1206 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1207 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1208 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1209 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1210 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1211 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1212 | if (maxlvt >= 4) | |
1213 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1214 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1215 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1216 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1217 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1218 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
1219 | #ifdef CONFIG_X86_MCE_INTEL | |
1220 | if (maxlvt >= 5) | |
1221 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1222 | #endif | |
1223 | local_irq_save(flags); | |
1224 | disable_local_APIC(); | |
1225 | local_irq_restore(flags); | |
1226 | return 0; | |
1da177e4 LT |
1227 | } |
1228 | ||
0e078e2f | 1229 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1230 | { |
0e078e2f TG |
1231 | unsigned int l, h; |
1232 | unsigned long flags; | |
1233 | int maxlvt; | |
1da177e4 | 1234 | |
0e078e2f TG |
1235 | if (!apic_pm_state.active) |
1236 | return 0; | |
89b831ef | 1237 | |
0e078e2f | 1238 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1239 | |
0e078e2f TG |
1240 | local_irq_save(flags); |
1241 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1242 | l &= ~MSR_IA32_APICBASE_BASE; | |
1243 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1244 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1245 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); | |
1246 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1247 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1248 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1249 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1250 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1251 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1252 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
1253 | #ifdef CONFIG_X86_MCE_INTEL | |
1254 | if (maxlvt >= 5) | |
1255 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1256 | #endif | |
1257 | if (maxlvt >= 4) | |
1258 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1259 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1260 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1261 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1262 | apic_write(APIC_ESR, 0); | |
1263 | apic_read(APIC_ESR); | |
1264 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1265 | apic_write(APIC_ESR, 0); | |
1266 | apic_read(APIC_ESR); | |
1267 | local_irq_restore(flags); | |
1268 | return 0; | |
1269 | } | |
b8ce3359 | 1270 | |
0e078e2f TG |
1271 | static struct sysdev_class lapic_sysclass = { |
1272 | .name = "lapic", | |
1273 | .resume = lapic_resume, | |
1274 | .suspend = lapic_suspend, | |
1275 | }; | |
b8ce3359 | 1276 | |
0e078e2f | 1277 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1278 | .id = 0, |
1279 | .cls = &lapic_sysclass, | |
0e078e2f | 1280 | }; |
b8ce3359 | 1281 | |
0e078e2f TG |
1282 | static void __cpuinit apic_pm_activate(void) |
1283 | { | |
1284 | apic_pm_state.active = 1; | |
1da177e4 LT |
1285 | } |
1286 | ||
0e078e2f | 1287 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1288 | { |
0e078e2f | 1289 | int error; |
e83a5fdc | 1290 | |
0e078e2f TG |
1291 | if (!cpu_has_apic) |
1292 | return 0; | |
1293 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1294 | |
0e078e2f TG |
1295 | error = sysdev_class_register(&lapic_sysclass); |
1296 | if (!error) | |
1297 | error = sysdev_register(&device_lapic); | |
1298 | return error; | |
1da177e4 | 1299 | } |
0e078e2f TG |
1300 | device_initcall(init_lapic_sysfs); |
1301 | ||
1302 | #else /* CONFIG_PM */ | |
1303 | ||
1304 | static void apic_pm_activate(void) { } | |
1305 | ||
1306 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1307 | |
1308 | /* | |
f8bf3c65 | 1309 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1310 | * |
1311 | * Thus far, the major user of this is IBM's Summit2 series: | |
1312 | * | |
637029c6 | 1313 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1314 | * multi-chassis. Use available data to take a good guess. |
1315 | * If in doubt, go HPET. | |
1316 | */ | |
f8bf3c65 | 1317 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1318 | { |
1319 | int i, clusters, zeros; | |
1320 | unsigned id; | |
322850af | 1321 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1322 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1323 | ||
322850af YL |
1324 | /* |
1325 | * there is not this kind of box with AMD CPU yet. | |
1326 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1327 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1328 | * vsmp box still need checking... |
322850af | 1329 | */ |
1cb68487 | 1330 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1331 | return 0; |
1332 | ||
23ca4bba | 1333 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1334 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1335 | |
1336 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1337 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1338 | if (bios_cpu_apicid) { |
1339 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1340 | } |
1341 | else if (i < nr_cpu_ids) { | |
1342 | if (cpu_present(i)) | |
1343 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1344 | else | |
1345 | continue; | |
1346 | } | |
1347 | else | |
1348 | break; | |
1349 | ||
1da177e4 LT |
1350 | if (id != BAD_APICID) |
1351 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1352 | } | |
1353 | ||
1354 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1355 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1356 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1357 | * Since clusters are allocated sequentially, count zeros only if | |
1358 | * they are bounded by ones. | |
1da177e4 LT |
1359 | */ |
1360 | clusters = 0; | |
1361 | zeros = 0; | |
1362 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1363 | if (test_bit(i, clustermap)) { | |
1364 | clusters += 1 + zeros; | |
1365 | zeros = 0; | |
1366 | } else | |
1367 | ++zeros; | |
1368 | } | |
1369 | ||
1cb68487 RT |
1370 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1371 | * not guaranteed to be synced between boards | |
1372 | */ | |
1373 | if (is_vsmp_box() && clusters > 1) | |
1374 | return 1; | |
1375 | ||
1da177e4 | 1376 | /* |
f8bf3c65 | 1377 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1378 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1379 | * out, but AFAIK this will work even for them. | |
1380 | */ | |
1381 | return (clusters > 2); | |
1382 | } | |
1383 | ||
1384 | /* | |
0e078e2f | 1385 | * APIC command line parameters |
1da177e4 | 1386 | */ |
0e078e2f | 1387 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1388 | { |
0e078e2f TG |
1389 | if (str == NULL) { |
1390 | skip_ioapic_setup = 0; | |
1391 | ioapic_force = 1; | |
1392 | return 0; | |
1da177e4 | 1393 | } |
0e078e2f TG |
1394 | if (strcmp("debug", str) == 0) |
1395 | apic_verbosity = APIC_DEBUG; | |
1396 | else if (strcmp("verbose", str) == 0) | |
1397 | apic_verbosity = APIC_VERBOSE; | |
1398 | else { | |
1399 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1400 | " use apic=verbose or apic=debug\n", str); | |
1401 | return -EINVAL; | |
1da177e4 LT |
1402 | } |
1403 | ||
1da177e4 LT |
1404 | return 0; |
1405 | } | |
0e078e2f | 1406 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1407 | |
6935d1f9 TG |
1408 | static __init int setup_disableapic(char *str) |
1409 | { | |
1da177e4 | 1410 | disable_apic = 1; |
53756d37 | 1411 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
2c8c0e6b AK |
1412 | return 0; |
1413 | } | |
1414 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1415 | |
2c8c0e6b | 1416 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1417 | static __init int setup_nolapic(char *str) |
1418 | { | |
2c8c0e6b | 1419 | return setup_disableapic(str); |
6935d1f9 | 1420 | } |
2c8c0e6b | 1421 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1422 | |
2e7c2838 LT |
1423 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1424 | { | |
1425 | local_apic_timer_c2_ok = 1; | |
1426 | return 0; | |
1427 | } | |
1428 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1429 | ||
6935d1f9 TG |
1430 | static __init int setup_noapictimer(char *str) |
1431 | { | |
73dea47f | 1432 | if (str[0] != ' ' && str[0] != 0) |
9b41046c | 1433 | return 0; |
1da177e4 | 1434 | disable_apic_timer = 1; |
9b41046c | 1435 | return 1; |
6935d1f9 | 1436 | } |
9f75e9b7 | 1437 | __setup("noapictimer", setup_noapictimer); |
73dea47f | 1438 | |
0c3749c4 AK |
1439 | static __init int setup_apicpmtimer(char *s) |
1440 | { | |
1441 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1442 | notsc_setup(NULL); |
b8ce3359 | 1443 | return 0; |
0c3749c4 AK |
1444 | } |
1445 | __setup("apicpmtimer", setup_apicpmtimer); | |
1446 | ||
1e934dda YL |
1447 | static int __init lapic_insert_resource(void) |
1448 | { | |
1449 | if (!apic_phys) | |
1450 | return -1; | |
1451 | ||
1452 | /* Put local APIC into the resource map. */ | |
1453 | lapic_resource.start = apic_phys; | |
1454 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1455 | insert_resource(&iomem_resource, &lapic_resource); | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | /* | |
1461 | * need call insert after e820_reserve_resources() | |
1462 | * that is using request_resource | |
1463 | */ | |
1464 | late_initcall(lapic_insert_resource); |