Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
d25bf7e5 | 26 | #include <linux/module.h> |
39928722 | 27 | #include <linux/ioport.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
1da177e4 LT |
29 | |
30 | #include <asm/atomic.h> | |
31 | #include <asm/smp.h> | |
32 | #include <asm/mtrr.h> | |
33 | #include <asm/mpspec.h> | |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/mach_apic.h> | |
75152114 | 36 | #include <asm/nmi.h> |
95833c83 | 37 | #include <asm/idle.h> |
73dea47f AK |
38 | #include <asm/proto.h> |
39 | #include <asm/timex.h> | |
2d0c87c3 | 40 | #include <asm/hpet.h> |
2c8c0e6b | 41 | #include <asm/apic.h> |
1da177e4 LT |
42 | |
43 | int apic_verbosity; | |
fb79d22e | 44 | int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 45 | static int apic_calibrate_pmtmr __initdata; |
1da177e4 | 46 | |
2e7c2838 LT |
47 | /* Local APIC timer works in C2? */ |
48 | int local_apic_timer_c2_ok; | |
49 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
50 | ||
39928722 AD |
51 | static struct resource *ioapic_resources; |
52 | static struct resource lapic_resource = { | |
53 | .name = "Local APIC", | |
54 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
55 | }; | |
56 | ||
d03030e9 TG |
57 | static unsigned int calibration_result; |
58 | ||
ba7eda4c TG |
59 | static int lapic_next_event(unsigned long delta, |
60 | struct clock_event_device *evt); | |
61 | static void lapic_timer_setup(enum clock_event_mode mode, | |
62 | struct clock_event_device *evt); | |
63 | ||
64 | static void lapic_timer_broadcast(cpumask_t mask); | |
65 | ||
66 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen); | |
67 | ||
68 | static struct clock_event_device lapic_clockevent = { | |
69 | .name = "lapic", | |
70 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
71 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
72 | .shift = 32, | |
73 | .set_mode = lapic_timer_setup, | |
74 | .set_next_event = lapic_next_event, | |
75 | .broadcast = lapic_timer_broadcast, | |
76 | .rating = 100, | |
77 | .irq = -1, | |
78 | }; | |
79 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
80 | ||
81 | static int lapic_next_event(unsigned long delta, | |
82 | struct clock_event_device *evt) | |
83 | { | |
84 | apic_write(APIC_TMICT, delta); | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static void lapic_timer_setup(enum clock_event_mode mode, | |
89 | struct clock_event_device *evt) | |
90 | { | |
91 | unsigned long flags; | |
92 | unsigned int v; | |
93 | ||
94 | /* Lapic used as dummy for broadcast ? */ | |
95 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
96 | return; | |
97 | ||
98 | local_irq_save(flags); | |
99 | ||
100 | switch (mode) { | |
101 | case CLOCK_EVT_MODE_PERIODIC: | |
102 | case CLOCK_EVT_MODE_ONESHOT: | |
103 | __setup_APIC_LVTT(calibration_result, | |
104 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
105 | break; | |
106 | case CLOCK_EVT_MODE_UNUSED: | |
107 | case CLOCK_EVT_MODE_SHUTDOWN: | |
108 | v = apic_read(APIC_LVTT); | |
109 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
110 | apic_write(APIC_LVTT, v); | |
111 | break; | |
112 | case CLOCK_EVT_MODE_RESUME: | |
113 | /* Nothing to do here */ | |
114 | break; | |
115 | } | |
116 | ||
117 | local_irq_restore(flags); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Local APIC timer broadcast function | |
122 | */ | |
123 | static void lapic_timer_broadcast(cpumask_t mask) | |
124 | { | |
125 | #ifdef CONFIG_SMP | |
126 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
127 | #endif | |
128 | } | |
129 | ||
1da177e4 LT |
130 | static void apic_pm_activate(void); |
131 | ||
8339e9fb FLV |
132 | void apic_wait_icr_idle(void) |
133 | { | |
134 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
135 | cpu_relax(); | |
136 | } | |
137 | ||
138 | unsigned int safe_apic_wait_icr_idle(void) | |
139 | { | |
140 | unsigned int send_status; | |
141 | int timeout; | |
142 | ||
143 | timeout = 0; | |
144 | do { | |
145 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
146 | if (!send_status) | |
147 | break; | |
148 | udelay(100); | |
149 | } while (timeout++ < 1000); | |
150 | ||
151 | return send_status; | |
152 | } | |
153 | ||
1da177e4 LT |
154 | void enable_NMI_through_LVT0 (void * dummy) |
155 | { | |
11a8e778 | 156 | unsigned int v; |
6935d1f9 TG |
157 | |
158 | /* unmask and set to NMI */ | |
159 | v = APIC_DM_NMI; | |
11a8e778 | 160 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
161 | } |
162 | ||
37e650c7 | 163 | int lapic_get_maxlvt(void) |
1da177e4 | 164 | { |
11a8e778 | 165 | unsigned int v, maxlvt; |
1da177e4 LT |
166 | |
167 | v = apic_read(APIC_LVR); | |
1da177e4 LT |
168 | maxlvt = GET_APIC_MAXLVT(v); |
169 | return maxlvt; | |
170 | } | |
171 | ||
3777a959 AK |
172 | /* |
173 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
174 | * each architecture has to answer this themselves. | |
175 | */ | |
176 | void ack_bad_irq(unsigned int irq) | |
177 | { | |
178 | printk("unexpected IRQ trap at vector %02x\n", irq); | |
179 | /* | |
180 | * Currently unexpected vectors happen only on SMP and APIC. | |
181 | * We _must_ ack these because every local APIC has only N | |
182 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
183 | * holds up an irq slot - in excessive cases (when multiple | |
184 | * unexpected vectors occur) that might lock up the APIC | |
185 | * completely. | |
6935d1f9 | 186 | * But don't ack when the APIC is disabled. -AK |
3777a959 AK |
187 | */ |
188 | if (!disable_apic) | |
189 | ack_APIC_irq(); | |
190 | } | |
191 | ||
1da177e4 LT |
192 | void clear_local_APIC(void) |
193 | { | |
194 | int maxlvt; | |
195 | unsigned int v; | |
196 | ||
37e650c7 | 197 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
198 | |
199 | /* | |
704fc59e | 200 | * Masking an LVT entry can trigger a local APIC error |
1da177e4 LT |
201 | * if the vector is zero. Mask LVTERR first to prevent this. |
202 | */ | |
203 | if (maxlvt >= 3) { | |
204 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
11a8e778 | 205 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
1da177e4 LT |
206 | } |
207 | /* | |
208 | * Careful: we have to set masks only first to deassert | |
209 | * any level-triggered sources. | |
210 | */ | |
211 | v = apic_read(APIC_LVTT); | |
11a8e778 | 212 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); |
1da177e4 | 213 | v = apic_read(APIC_LVT0); |
11a8e778 | 214 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 | 215 | v = apic_read(APIC_LVT1); |
11a8e778 | 216 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); |
1da177e4 LT |
217 | if (maxlvt >= 4) { |
218 | v = apic_read(APIC_LVTPC); | |
11a8e778 | 219 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); |
1da177e4 LT |
220 | } |
221 | ||
222 | /* | |
223 | * Clean APIC state for other OSs: | |
224 | */ | |
11a8e778 AK |
225 | apic_write(APIC_LVTT, APIC_LVT_MASKED); |
226 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
227 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
1da177e4 | 228 | if (maxlvt >= 3) |
11a8e778 | 229 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); |
1da177e4 | 230 | if (maxlvt >= 4) |
11a8e778 | 231 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); |
5a40b7c2 AK |
232 | apic_write(APIC_ESR, 0); |
233 | apic_read(APIC_ESR); | |
1da177e4 LT |
234 | } |
235 | ||
208fb931 | 236 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 237 | { |
a8fcf1a2 AK |
238 | /* Go back to Virtual Wire compatibility mode */ |
239 | unsigned long value; | |
208fb931 | 240 | |
a8fcf1a2 AK |
241 | /* For the spurious interrupt use vector F, and enable it */ |
242 | value = apic_read(APIC_SPIV); | |
243 | value &= ~APIC_VECTOR_MASK; | |
244 | value |= APIC_SPIV_APIC_ENABLED; | |
245 | value |= 0xf; | |
246 | apic_write(APIC_SPIV, value); | |
247 | ||
248 | if (!virt_wire_setup) { | |
bc1d99c1 CW |
249 | /* |
250 | * For LVT0 make it edge triggered, active high, | |
251 | * external and enabled | |
252 | */ | |
a8fcf1a2 AK |
253 | value = apic_read(APIC_LVT0); |
254 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
208fb931 | 255 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | |
a8fcf1a2 | 256 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED ); |
208fb931 | 257 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; |
a8fcf1a2 AK |
258 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); |
259 | apic_write(APIC_LVT0, value); | |
260 | } else { | |
261 | /* Disable LVT0 */ | |
262 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
208fb931 | 263 | } |
a8fcf1a2 AK |
264 | |
265 | /* For LVT1 make it edge triggered, active high, nmi and enabled */ | |
266 | value = apic_read(APIC_LVT1); | |
267 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
268 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
269 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
270 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
271 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
272 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
273 | } |
274 | ||
275 | void disable_local_APIC(void) | |
276 | { | |
277 | unsigned int value; | |
278 | ||
279 | clear_local_APIC(); | |
280 | ||
281 | /* | |
282 | * Disable APIC (implies clearing of registers | |
283 | * for 82489DX!). | |
284 | */ | |
285 | value = apic_read(APIC_SPIV); | |
286 | value &= ~APIC_SPIV_APIC_ENABLED; | |
11a8e778 | 287 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
288 | } |
289 | ||
9b7711f0 HS |
290 | void lapic_shutdown(void) |
291 | { | |
292 | unsigned long flags; | |
293 | ||
294 | if (!cpu_has_apic) | |
295 | return; | |
296 | ||
297 | local_irq_save(flags); | |
298 | ||
299 | disable_local_APIC(); | |
300 | ||
301 | local_irq_restore(flags); | |
302 | } | |
303 | ||
1da177e4 LT |
304 | /* |
305 | * This is to verify that we're looking at a real local APIC. | |
306 | * Check these against your board if the CPUs aren't getting | |
307 | * started for no apparent reason. | |
308 | */ | |
309 | int __init verify_local_APIC(void) | |
310 | { | |
311 | unsigned int reg0, reg1; | |
312 | ||
313 | /* | |
314 | * The version register is read-only in a real APIC. | |
315 | */ | |
316 | reg0 = apic_read(APIC_LVR); | |
317 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
318 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
319 | reg1 = apic_read(APIC_LVR); | |
320 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
321 | ||
322 | /* | |
323 | * The two version reads above should print the same | |
324 | * numbers. If the second one is different, then we | |
325 | * poke at a non-APIC. | |
326 | */ | |
327 | if (reg1 != reg0) | |
328 | return 0; | |
329 | ||
330 | /* | |
331 | * Check if the version looks reasonably. | |
332 | */ | |
333 | reg1 = GET_APIC_VERSION(reg0); | |
334 | if (reg1 == 0x00 || reg1 == 0xff) | |
335 | return 0; | |
37e650c7 | 336 | reg1 = lapic_get_maxlvt(); |
1da177e4 LT |
337 | if (reg1 < 0x02 || reg1 == 0xff) |
338 | return 0; | |
339 | ||
340 | /* | |
341 | * The ID register is read/write in a real APIC. | |
342 | */ | |
343 | reg0 = apic_read(APIC_ID); | |
344 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); | |
345 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
346 | reg1 = apic_read(APIC_ID); | |
347 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); | |
348 | apic_write(APIC_ID, reg0); | |
349 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
350 | return 0; | |
351 | ||
352 | /* | |
353 | * The next two are just to see if we have sane values. | |
354 | * They're only really relevant if we're in Virtual Wire | |
355 | * compatibility mode, but most boxes are anymore. | |
356 | */ | |
357 | reg0 = apic_read(APIC_LVT0); | |
358 | apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0); | |
359 | reg1 = apic_read(APIC_LVT1); | |
360 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
361 | ||
362 | return 1; | |
363 | } | |
364 | ||
365 | void __init sync_Arb_IDs(void) | |
366 | { | |
367 | /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */ | |
368 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
369 | if (ver >= 0x14) /* P4 or higher */ | |
370 | return; | |
371 | ||
372 | /* | |
373 | * Wait for idle. | |
374 | */ | |
375 | apic_wait_icr_idle(); | |
376 | ||
377 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
11a8e778 | 378 | apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG |
1da177e4 LT |
379 | | APIC_DM_INIT); |
380 | } | |
381 | ||
1da177e4 LT |
382 | /* |
383 | * An initial setup of the virtual wire mode. | |
384 | */ | |
385 | void __init init_bsp_APIC(void) | |
386 | { | |
11a8e778 | 387 | unsigned int value; |
1da177e4 LT |
388 | |
389 | /* | |
390 | * Don't do the setup now if we have a SMP BIOS as the | |
391 | * through-I/O-APIC virtual wire mode might be active. | |
392 | */ | |
393 | if (smp_found_config || !cpu_has_apic) | |
394 | return; | |
395 | ||
396 | value = apic_read(APIC_LVR); | |
1da177e4 LT |
397 | |
398 | /* | |
399 | * Do not trust the local APIC being empty at bootup. | |
400 | */ | |
401 | clear_local_APIC(); | |
402 | ||
403 | /* | |
404 | * Enable APIC. | |
405 | */ | |
406 | value = apic_read(APIC_SPIV); | |
407 | value &= ~APIC_VECTOR_MASK; | |
408 | value |= APIC_SPIV_APIC_ENABLED; | |
409 | value |= APIC_SPIV_FOCUS_DISABLED; | |
410 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 411 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
412 | |
413 | /* | |
414 | * Set up the virtual wire mode. | |
415 | */ | |
11a8e778 | 416 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 417 | value = APIC_DM_NMI; |
11a8e778 | 418 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
419 | } |
420 | ||
e6982c67 | 421 | void __cpuinit setup_local_APIC (void) |
1da177e4 | 422 | { |
11a8e778 | 423 | unsigned int value, maxlvt; |
da7ed9f9 | 424 | int i, j; |
1da177e4 | 425 | |
1da177e4 | 426 | value = apic_read(APIC_LVR); |
1da177e4 | 427 | |
fe7414a2 | 428 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
429 | |
430 | /* | |
431 | * Double-check whether this APIC is really registered. | |
432 | * This is meaningless in clustered apic mode, so we skip it. | |
433 | */ | |
434 | if (!apic_id_registered()) | |
435 | BUG(); | |
436 | ||
437 | /* | |
438 | * Intel recommends to set DFR, LDR and TPR before enabling | |
439 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
440 | * document number 292116). So here it goes... | |
441 | */ | |
442 | init_apic_ldr(); | |
443 | ||
444 | /* | |
445 | * Set Task Priority to 'accept all'. We never change this | |
446 | * later on. | |
447 | */ | |
448 | value = apic_read(APIC_TASKPRI); | |
449 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 450 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 451 | |
da7ed9f9 VG |
452 | /* |
453 | * After a crash, we no longer service the interrupts and a pending | |
454 | * interrupt from previous kernel might still have ISR bit set. | |
455 | * | |
456 | * Most probably by now CPU has serviced that pending interrupt and | |
457 | * it might not have done the ack_APIC_irq() because it thought, | |
458 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
459 | * does not clear the ISR bit and cpu thinks it has already serivced | |
460 | * the interrupt. Hence a vector might get locked. It was noticed | |
461 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
462 | */ | |
463 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
464 | value = apic_read(APIC_ISR + i*0x10); | |
465 | for (j = 31; j >= 0; j--) { | |
466 | if (value & (1<<j)) | |
467 | ack_APIC_irq(); | |
468 | } | |
469 | } | |
470 | ||
1da177e4 LT |
471 | /* |
472 | * Now that we are all set up, enable the APIC | |
473 | */ | |
474 | value = apic_read(APIC_SPIV); | |
475 | value &= ~APIC_VECTOR_MASK; | |
476 | /* | |
477 | * Enable APIC | |
478 | */ | |
479 | value |= APIC_SPIV_APIC_ENABLED; | |
480 | ||
3f14c746 AK |
481 | /* We always use processor focus */ |
482 | ||
1da177e4 LT |
483 | /* |
484 | * Set spurious IRQ vector | |
485 | */ | |
486 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 487 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
488 | |
489 | /* | |
490 | * Set up LVT0, LVT1: | |
491 | * | |
492 | * set up through-local-APIC on the BP's LINT0. This is not | |
493 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
494 | * we delegate interrupts to the 8259A. | |
495 | */ | |
496 | /* | |
497 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
498 | */ | |
499 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 500 | if (!smp_processor_id() && !value) { |
1da177e4 | 501 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
502 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
503 | smp_processor_id()); | |
1da177e4 LT |
504 | } else { |
505 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
506 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
507 | smp_processor_id()); | |
1da177e4 | 508 | } |
11a8e778 | 509 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
510 | |
511 | /* | |
512 | * only the BP should see the LINT1 NMI signal, obviously. | |
513 | */ | |
514 | if (!smp_processor_id()) | |
515 | value = APIC_DM_NMI; | |
516 | else | |
517 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 518 | apic_write(APIC_LVT1, value); |
1da177e4 | 519 | |
61c11341 | 520 | { |
1da177e4 | 521 | unsigned oldvalue; |
37e650c7 | 522 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
523 | oldvalue = apic_read(APIC_ESR); |
524 | value = ERROR_APIC_VECTOR; // enables sending errors | |
11a8e778 | 525 | apic_write(APIC_LVTERR, value); |
1da177e4 LT |
526 | /* |
527 | * spec says clear errors after enabling vector. | |
528 | */ | |
529 | if (maxlvt > 3) | |
530 | apic_write(APIC_ESR, 0); | |
531 | value = apic_read(APIC_ESR); | |
532 | if (value != oldvalue) | |
533 | apic_printk(APIC_VERBOSE, | |
534 | "ESR value after enabling vector: %08x, after %08x\n", | |
535 | oldvalue, value); | |
1da177e4 LT |
536 | } |
537 | ||
538 | nmi_watchdog_default(); | |
f2802e7f | 539 | setup_apic_nmi_watchdog(NULL); |
1da177e4 LT |
540 | apic_pm_activate(); |
541 | } | |
542 | ||
543 | #ifdef CONFIG_PM | |
544 | ||
545 | static struct { | |
546 | /* 'active' is true if the local APIC was enabled by us and | |
547 | not the BIOS; this signifies that we are also responsible | |
548 | for disabling it before entering apm/acpi suspend */ | |
549 | int active; | |
550 | /* r/w apic fields */ | |
551 | unsigned int apic_id; | |
552 | unsigned int apic_taskpri; | |
553 | unsigned int apic_ldr; | |
554 | unsigned int apic_dfr; | |
555 | unsigned int apic_spiv; | |
556 | unsigned int apic_lvtt; | |
557 | unsigned int apic_lvtpc; | |
558 | unsigned int apic_lvt0; | |
559 | unsigned int apic_lvt1; | |
560 | unsigned int apic_lvterr; | |
561 | unsigned int apic_tmict; | |
562 | unsigned int apic_tdcr; | |
563 | unsigned int apic_thmr; | |
564 | } apic_pm_state; | |
565 | ||
0b9c33a7 | 566 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
567 | { |
568 | unsigned long flags; | |
f990fff4 | 569 | int maxlvt; |
1da177e4 LT |
570 | |
571 | if (!apic_pm_state.active) | |
572 | return 0; | |
573 | ||
37e650c7 | 574 | maxlvt = lapic_get_maxlvt(); |
f990fff4 | 575 | |
1da177e4 LT |
576 | apic_pm_state.apic_id = apic_read(APIC_ID); |
577 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); | |
578 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
579 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
580 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
581 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
f990fff4 KW |
582 | if (maxlvt >= 4) |
583 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1da177e4 LT |
584 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); |
585 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
586 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
587 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
588 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
f990fff4 KW |
589 | #ifdef CONFIG_X86_MCE_INTEL |
590 | if (maxlvt >= 5) | |
591 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
592 | #endif | |