Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
ba7eda4c | 27 | #include <linux/clockchips.h> |
70a20025 | 28 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 29 | #include <linux/module.h> |
6e1cb38a | 30 | #include <linux/dmar.h> |
1da177e4 LT |
31 | |
32 | #include <asm/atomic.h> | |
33 | #include <asm/smp.h> | |
34 | #include <asm/mtrr.h> | |
35 | #include <asm/mpspec.h> | |
e83a5fdc | 36 | #include <asm/hpet.h> |
1da177e4 | 37 | #include <asm/pgalloc.h> |
75152114 | 38 | #include <asm/nmi.h> |
95833c83 | 39 | #include <asm/idle.h> |
73dea47f AK |
40 | #include <asm/proto.h> |
41 | #include <asm/timex.h> | |
2c8c0e6b | 42 | #include <asm/apic.h> |
6e1cb38a | 43 | #include <asm/i8259.h> |
1da177e4 | 44 | |
5af5573e | 45 | #include <mach_ipi.h> |
dd46e3ca | 46 | #include <mach_apic.h> |
5af5573e | 47 | |
36fef094 | 48 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ |
aa276e1c | 49 | static int disable_apic_timer __cpuinitdata; |
bc1d99c1 | 50 | static int apic_calibrate_pmtmr __initdata; |
0e078e2f | 51 | int disable_apic; |
6e1cb38a | 52 | int disable_x2apic; |
89027d35 | 53 | int x2apic; |
1da177e4 | 54 | |
6e1cb38a SS |
55 | /* x2apic enabled before OS handover */ |
56 | int x2apic_preenabled; | |
57 | ||
e83a5fdc | 58 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
59 | int local_apic_timer_c2_ok; |
60 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
61 | ||
e83a5fdc HS |
62 | /* |
63 | * Debug level, exported for io_apic.c | |
64 | */ | |
baa13188 | 65 | unsigned int apic_verbosity; |
e83a5fdc | 66 | |
bab4b27c AS |
67 | /* Have we found an MP table */ |
68 | int smp_found_config; | |
69 | ||
39928722 AD |
70 | static struct resource lapic_resource = { |
71 | .name = "Local APIC", | |
72 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
73 | }; | |
74 | ||
d03030e9 TG |
75 | static unsigned int calibration_result; |
76 | ||
ba7eda4c TG |
77 | static int lapic_next_event(unsigned long delta, |
78 | struct clock_event_device *evt); | |
79 | static void lapic_timer_setup(enum clock_event_mode mode, | |
80 | struct clock_event_device *evt); | |
ba7eda4c | 81 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 82 | static void apic_pm_activate(void); |
ba7eda4c | 83 | |
274cfe59 CG |
84 | /* |
85 | * The local apic timer can be used for any function which is CPU local. | |
86 | */ | |
ba7eda4c TG |
87 | static struct clock_event_device lapic_clockevent = { |
88 | .name = "lapic", | |
89 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
90 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
91 | .shift = 32, | |
92 | .set_mode = lapic_timer_setup, | |
93 | .set_next_event = lapic_next_event, | |
94 | .broadcast = lapic_timer_broadcast, | |
95 | .rating = 100, | |
96 | .irq = -1, | |
97 | }; | |
98 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
99 | ||
d3432896 | 100 | static unsigned long apic_phys; |
b6c80513 | 101 | unsigned int __cpuinitdata maxcpus = NR_CPUS; |
d3432896 | 102 | |
3f530709 AS |
103 | unsigned long mp_lapic_addr; |
104 | ||
0e078e2f TG |
105 | /* |
106 | * Get the LAPIC version | |
107 | */ | |
108 | static inline int lapic_get_version(void) | |
ba7eda4c | 109 | { |
0e078e2f | 110 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
111 | } |
112 | ||
0e078e2f | 113 | /* |
9c803869 | 114 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
115 | */ |
116 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 117 | { |
9c803869 | 118 | #ifdef CONFIG_X86_64 |
0e078e2f | 119 | return 1; |
9c803869 CG |
120 | #else |
121 | return APIC_INTEGRATED(lapic_get_version()); | |
122 | #endif | |
ba7eda4c TG |
123 | } |
124 | ||
125 | /* | |
0e078e2f | 126 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 127 | */ |
0e078e2f | 128 | static int modern_apic(void) |
ba7eda4c | 129 | { |
0e078e2f TG |
130 | /* AMD systems use old APIC versions, so check the CPU */ |
131 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
132 | boot_cpu_data.x86 >= 0xf) | |
133 | return 1; | |
134 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
135 | } |
136 | ||
274cfe59 CG |
137 | /* |
138 | * Paravirt kernels also might be using these below ops. So we still | |
139 | * use generic apic_read()/apic_write(), which might be pointing to different | |
140 | * ops in PARAVIRT case. | |
141 | */ | |
1b374e4d | 142 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
143 | { |
144 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
145 | cpu_relax(); | |
146 | } | |
147 | ||
1b374e4d | 148 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 149 | { |
3c6bb07a | 150 | u32 send_status; |
8339e9fb FLV |
151 | int timeout; |
152 | ||
153 | timeout = 0; | |
154 | do { | |
155 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
156 | if (!send_status) | |
157 | break; | |
158 | udelay(100); | |
159 | } while (timeout++ < 1000); | |
160 | ||
161 | return send_status; | |
162 | } | |
163 | ||
1b374e4d SS |
164 | void xapic_icr_write(u32 low, u32 id) |
165 | { | |
ed4e5ec1 | 166 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
167 | apic_write(APIC_ICR, low); |
168 | } | |
169 | ||
170 | u64 xapic_icr_read(void) | |
171 | { | |
172 | u32 icr1, icr2; | |
173 | ||
174 | icr2 = apic_read(APIC_ICR2); | |
175 | icr1 = apic_read(APIC_ICR); | |
176 | ||
cf9768d7 | 177 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
178 | } |
179 | ||
180 | static struct apic_ops xapic_ops = { | |
181 | .read = native_apic_mem_read, | |
182 | .write = native_apic_mem_write, | |
1b374e4d SS |
183 | .icr_read = xapic_icr_read, |
184 | .icr_write = xapic_icr_write, | |
185 | .wait_icr_idle = xapic_wait_icr_idle, | |
186 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
187 | }; | |
188 | ||
189 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
190 | EXPORT_SYMBOL_GPL(apic_ops); |
191 | ||
13c88fb5 SS |
192 | static void x2apic_wait_icr_idle(void) |
193 | { | |
194 | /* no need to wait for icr idle in x2apic */ | |
195 | return; | |
196 | } | |
197 | ||
198 | static u32 safe_x2apic_wait_icr_idle(void) | |
199 | { | |
200 | /* no need to wait for icr idle in x2apic */ | |
201 | return 0; | |
202 | } | |
203 | ||
204 | void x2apic_icr_write(u32 low, u32 id) | |
205 | { | |
206 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
207 | } | |
208 | ||
209 | u64 x2apic_icr_read(void) | |
210 | { | |
211 | unsigned long val; | |
212 | ||
213 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
214 | return val; | |
215 | } | |
216 | ||
217 | static struct apic_ops x2apic_ops = { | |
218 | .read = native_apic_msr_read, | |
219 | .write = native_apic_msr_write, | |
13c88fb5 SS |
220 | .icr_read = x2apic_icr_read, |
221 | .icr_write = x2apic_icr_write, | |
222 | .wait_icr_idle = x2apic_wait_icr_idle, | |
223 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
224 | }; | |
225 | ||
0e078e2f TG |
226 | /** |
227 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
228 | */ | |
e9427101 | 229 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 230 | { |
11a8e778 | 231 | unsigned int v; |
6935d1f9 TG |
232 | |
233 | /* unmask and set to NMI */ | |
234 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
235 | |
236 | /* Level triggered for 82489DX (32bit mode) */ | |
237 | if (!lapic_is_integrated()) | |
238 | v |= APIC_LVT_LEVEL_TRIGGER; | |
239 | ||
11a8e778 | 240 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
241 | } |
242 | ||
0e078e2f TG |
243 | /** |
244 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
245 | */ | |
37e650c7 | 246 | int lapic_get_maxlvt(void) |
1da177e4 | 247 | { |
36a028de | 248 | unsigned int v; |
1da177e4 LT |
249 | |
250 | v = apic_read(APIC_LVR); | |
36a028de CG |
251 | /* |
252 | * - we always have APIC integrated on 64bit mode | |
253 | * - 82489DXs do not report # of LVT entries | |
254 | */ | |
255 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
256 | } |
257 | ||
274cfe59 CG |
258 | /* |
259 | * Local APIC timer | |
260 | */ | |
261 | ||
c40aaec6 CG |
262 | /* Clock divisor */ |
263 | #ifdef CONFG_X86_64 | |
f07f4f90 | 264 | #define APIC_DIVISOR 1 |
c40aaec6 CG |
265 | #else |
266 | #define APIC_DIVISOR 16 | |
267 | #endif | |
f07f4f90 | 268 | |
0e078e2f TG |
269 | /* |
270 | * This function sets up the local APIC timer, with a timeout of | |
271 | * 'clocks' APIC bus clock. During calibration we actually call | |
272 | * this function twice on the boot CPU, once with a bogus timeout | |
273 | * value, second time for real. The other (noncalibrating) CPUs | |
274 | * call this function only once, with the real, calibrated value. | |
275 | * | |
276 | * We do reads before writes even if unnecessary, to get around the | |
277 | * P5 APIC double write bug. | |
278 | */ | |
0e078e2f | 279 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 280 | { |
0e078e2f | 281 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 282 | |
0e078e2f TG |
283 | lvtt_value = LOCAL_TIMER_VECTOR; |
284 | if (!oneshot) | |
285 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
286 | if (!lapic_is_integrated()) |
287 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
288 | ||
0e078e2f TG |
289 | if (!irqen) |
290 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 291 | |
0e078e2f | 292 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
293 | |
294 | /* | |
0e078e2f | 295 | * Divide PICLK by 16 |
1da177e4 | 296 | */ |
0e078e2f | 297 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
298 | apic_write(APIC_TDCR, |
299 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
300 | APIC_TDR_DIV_16); | |
0e078e2f TG |
301 | |
302 | if (!oneshot) | |
f07f4f90 | 303 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
304 | } |
305 | ||
0e078e2f | 306 | /* |
7b83dae7 RR |
307 | * Setup extended LVT, AMD specific (K8, family 10h) |
308 | * | |
309 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
310 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
0e078e2f | 311 | */ |
7b83dae7 RR |
312 | |
313 | #define APIC_EILVT_LVTOFF_MCE 0 | |
314 | #define APIC_EILVT_LVTOFF_IBS 1 | |
315 | ||
316 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 317 | { |
7b83dae7 | 318 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 319 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 320 | |
0e078e2f | 321 | apic_write(reg, v); |
1da177e4 LT |
322 | } |
323 | ||
7b83dae7 RR |
324 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
325 | { | |
326 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
327 | return APIC_EILVT_LVTOFF_MCE; | |
328 | } | |
329 | ||
330 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
331 | { | |
332 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
333 | return APIC_EILVT_LVTOFF_IBS; | |
334 | } | |
335 | ||
0e078e2f TG |
336 | /* |
337 | * Program the next event, relative to now | |
338 | */ | |
339 | static int lapic_next_event(unsigned long delta, | |
340 | struct clock_event_device *evt) | |
1da177e4 | 341 | { |
0e078e2f TG |
342 | apic_write(APIC_TMICT, delta); |
343 | return 0; | |
1da177e4 LT |
344 | } |
345 | ||
0e078e2f TG |
346 | /* |
347 | * Setup the lapic timer in periodic or oneshot mode | |
348 | */ | |
349 | static void lapic_timer_setup(enum clock_event_mode mode, | |
350 | struct clock_event_device *evt) | |
9b7711f0 HS |
351 | { |
352 | unsigned long flags; | |
0e078e2f | 353 | unsigned int v; |
9b7711f0 | 354 | |
0e078e2f TG |
355 | /* Lapic used as dummy for broadcast ? */ |
356 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
357 | return; |
358 | ||
359 | local_irq_save(flags); | |
360 | ||
0e078e2f TG |
361 | switch (mode) { |
362 | case CLOCK_EVT_MODE_PERIODIC: | |
363 | case CLOCK_EVT_MODE_ONESHOT: | |
364 | __setup_APIC_LVTT(calibration_result, | |
365 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
366 | break; | |
367 | case CLOCK_EVT_MODE_UNUSED: | |
368 | case CLOCK_EVT_MODE_SHUTDOWN: | |
369 | v = apic_read(APIC_LVTT); | |
370 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
371 | apic_write(APIC_LVTT, v); | |
372 | break; | |
373 | case CLOCK_EVT_MODE_RESUME: | |
374 | /* Nothing to do here */ | |
375 | break; | |
376 | } | |
9b7711f0 HS |
377 | |
378 | local_irq_restore(flags); | |
379 | } | |
380 | ||
1da177e4 | 381 | /* |
0e078e2f | 382 | * Local APIC timer broadcast function |
1da177e4 | 383 | */ |
0e078e2f | 384 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 385 | { |
0e078e2f TG |
386 | #ifdef CONFIG_SMP |
387 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
388 | #endif | |
389 | } | |
1da177e4 | 390 | |
0e078e2f TG |
391 | /* |
392 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
393 | * of the boot CPU and register the clock event in the framework. | |
394 | */ | |
395 | static void setup_APIC_timer(void) | |
396 | { | |
397 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 398 | |
0e078e2f TG |
399 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
400 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 401 | |
0e078e2f TG |
402 | clockevents_register_device(levt); |
403 | } | |
1da177e4 | 404 | |
0e078e2f TG |
405 | /* |
406 | * In this function we calibrate APIC bus clocks to the external | |
407 | * timer. Unfortunately we cannot use jiffies and the timer irq | |
408 | * to calibrate, since some later bootup code depends on getting | |
409 | * the first irq? Ugh. | |
410 | * | |
411 | * We want to do the calibration only once since we | |
412 | * want to have local timer irqs syncron. CPUs connected | |
413 | * by the same APIC bus have the very same bus frequency. | |
414 | * And we want to have irqs off anyways, no accidental | |
415 | * APIC irq that way. | |
416 | */ | |
417 | ||
418 | #define TICK_COUNT 100000000 | |
419 | ||
89b3b1f4 | 420 | static int __init calibrate_APIC_clock(void) |
0e078e2f TG |
421 | { |
422 | unsigned apic, apic_start; | |
423 | unsigned long tsc, tsc_start; | |
424 | int result; | |
425 | ||
426 | local_irq_disable(); | |
427 | ||
428 | /* | |
429 | * Put whatever arbitrary (but long enough) timeout | |
430 | * value into the APIC clock, we just want to get the | |
431 | * counter running for calibration. | |
432 | * | |
433 | * No interrupt enable ! | |
434 | */ | |
435 | __setup_APIC_LVTT(250000000, 0, 0); | |
436 | ||
437 | apic_start = apic_read(APIC_TMCCT); | |
438 | #ifdef CONFIG_X86_PM_TIMER | |
439 | if (apic_calibrate_pmtmr && pmtmr_ioport) { | |
440 | pmtimer_wait(5000); /* 5ms wait */ | |
441 | apic = apic_read(APIC_TMCCT); | |
442 | result = (apic_start - apic) * 1000L / 5; | |
443 | } else | |
444 | #endif | |
445 | { | |
446 | rdtscll(tsc_start); | |
447 | ||
448 | do { | |
449 | apic = apic_read(APIC_TMCCT); | |
450 | rdtscll(tsc); | |
451 | } while ((tsc - tsc_start) < TICK_COUNT && | |
452 | (apic_start - apic) < TICK_COUNT); | |
453 | ||
454 | result = (apic_start - apic) * 1000L * tsc_khz / | |
455 | (tsc - tsc_start); | |
456 | } | |
457 | ||
458 | local_irq_enable(); | |
459 | ||
460 | printk(KERN_DEBUG "APIC timer calibration result %d\n", result); | |
461 | ||
462 | printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n", | |
463 | result / 1000 / 1000, result / 1000 % 1000); | |
464 | ||
465 | /* Calculate the scaled math multiplication factor */ | |
877084fb AM |
466 | lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, |
467 | lapic_clockevent.shift); | |
0e078e2f TG |
468 | lapic_clockevent.max_delta_ns = |
469 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
470 | lapic_clockevent.min_delta_ns = | |
471 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
472 | ||
f07f4f90 | 473 | calibration_result = (result * APIC_DIVISOR) / HZ; |
89b3b1f4 CG |
474 | |
475 | /* | |
476 | * Do a sanity check on the APIC calibration result | |
477 | */ | |
478 | if (calibration_result < (1000000 / HZ)) { | |
479 | printk(KERN_WARNING | |
480 | "APIC frequency too slow, disabling apic timer\n"); | |
481 | return -1; | |
482 | } | |
483 | ||
484 | return 0; | |
0e078e2f TG |
485 | } |
486 | ||
e83a5fdc HS |
487 | /* |
488 | * Setup the boot APIC | |
489 | * | |
490 | * Calibrate and verify the result. | |
491 | */ | |
0e078e2f TG |
492 | void __init setup_boot_APIC_clock(void) |
493 | { | |
494 | /* | |
274cfe59 CG |
495 | * The local apic timer can be disabled via the kernel |
496 | * commandline or from the CPU detection code. Register the lapic | |
497 | * timer as a dummy clock event source on SMP systems, so the | |
498 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
499 | */ |
500 | if (disable_apic_timer) { | |
501 | printk(KERN_INFO "Disabling APIC timer\n"); | |
502 | /* No broadcast on UP ! */ | |
9d09951d TG |
503 | if (num_possible_cpus() > 1) { |
504 | lapic_clockevent.mult = 1; | |
0e078e2f | 505 | setup_APIC_timer(); |
9d09951d | 506 | } |
0e078e2f TG |
507 | return; |
508 | } | |
509 | ||
274cfe59 CG |
510 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
511 | "calibrating APIC timer ...\n"); | |
512 | ||
89b3b1f4 | 513 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
514 | /* No broadcast on UP ! */ |
515 | if (num_possible_cpus() > 1) | |
516 | setup_APIC_timer(); | |
517 | return; | |
518 | } | |
519 | ||
0e078e2f TG |
520 | /* |
521 | * If nmi_watchdog is set to IO_APIC, we need the | |
522 | * PIT/HPET going. Otherwise register lapic as a dummy | |
523 | * device. | |
524 | */ | |
525 | if (nmi_watchdog != NMI_IO_APIC) | |
526 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
527 | else | |
528 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 529 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 530 | |
274cfe59 | 531 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
532 | setup_APIC_timer(); |
533 | } | |
534 | ||
0e078e2f TG |
535 | void __cpuinit setup_secondary_APIC_clock(void) |
536 | { | |
0e078e2f TG |
537 | setup_APIC_timer(); |
538 | } | |
539 | ||
540 | /* | |
541 | * The guts of the apic timer interrupt | |
542 | */ | |
543 | static void local_apic_timer_interrupt(void) | |
544 | { | |
545 | int cpu = smp_processor_id(); | |
546 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
547 | ||
548 | /* | |
549 | * Normally we should not be here till LAPIC has been initialized but | |
550 | * in some cases like kdump, its possible that there is a pending LAPIC | |
551 | * timer interrupt from previous kernel's context and is delivered in | |
552 | * new kernel the moment interrupts are enabled. | |
553 | * | |
554 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
555 | * its possible that when we get here evt->event_handler is NULL. | |
556 | * Check for event_handler being NULL and discard the interrupt as | |
557 | * spurious. | |
558 | */ | |
559 | if (!evt->event_handler) { | |
560 | printk(KERN_WARNING | |
561 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
562 | /* Switch it off */ | |
563 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
564 | return; | |
565 | } | |
566 | ||
567 | /* | |
568 | * the NMI deadlock-detector uses this. | |
569 | */ | |
570 | add_pda(apic_timer_irqs, 1); | |
571 | ||
572 | evt->event_handler(evt); | |
573 | } | |
574 | ||
575 | /* | |
576 | * Local APIC timer interrupt. This is the most natural way for doing | |
577 | * local interrupts, but local timer interrupts can be emulated by | |
578 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
579 | * | |
580 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
581 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
582 | */ | |
583 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
584 | { | |
585 | struct pt_regs *old_regs = set_irq_regs(regs); | |
586 | ||
587 | /* | |
588 | * NOTE! We'd better ACK the irq immediately, | |
589 | * because timer handling can be slow. | |
590 | */ | |
591 | ack_APIC_irq(); | |
592 | /* | |
593 | * update_process_times() expects us to have done irq_enter(). | |
594 | * Besides, if we don't timer interrupts ignore the global | |
595 | * interrupt lock, which is the WrongThing (tm) to do. | |
596 | */ | |
597 | exit_idle(); | |
598 | irq_enter(); | |
599 | local_apic_timer_interrupt(); | |
600 | irq_exit(); | |
274cfe59 | 601 | |
0e078e2f TG |
602 | set_irq_regs(old_regs); |
603 | } | |
604 | ||
605 | int setup_profiling_timer(unsigned int multiplier) | |
606 | { | |
607 | return -EINVAL; | |
608 | } | |
609 | ||
610 | ||
611 | /* | |
612 | * Local APIC start and shutdown | |
613 | */ | |
614 | ||
615 | /** | |
616 | * clear_local_APIC - shutdown the local APIC | |
617 | * | |
618 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
619 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
620 | * leftovers during boot. | |
621 | */ | |
622 | void clear_local_APIC(void) | |
623 | { | |
2584a82d | 624 | int maxlvt; |
0e078e2f TG |
625 | u32 v; |
626 | ||
d3432896 AK |
627 | /* APIC hasn't been mapped yet */ |
628 | if (!apic_phys) | |
629 | return; | |
630 | ||
631 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
632 | /* |
633 | * Masking an LVT entry can trigger a local APIC error | |
634 | * if the vector is zero. Mask LVTERR first to prevent this. | |
635 | */ | |
636 | if (maxlvt >= 3) { | |
637 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
638 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
639 | } | |
640 | /* | |
641 | * Careful: we have to set masks only first to deassert | |
642 | * any level-triggered sources. | |
643 | */ | |
644 | v = apic_read(APIC_LVTT); | |
645 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
646 | v = apic_read(APIC_LVT0); | |
647 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
648 | v = apic_read(APIC_LVT1); | |
649 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
650 | if (maxlvt >= 4) { | |
651 | v = apic_read(APIC_LVTPC); | |
652 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
653 | } | |
654 | ||
6764014b CG |
655 | /* lets not touch this if we didn't frob it */ |
656 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
657 | if (maxlvt >= 5) { | |
658 | v = apic_read(APIC_LVTTHMR); | |
659 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
660 | } | |
661 | #endif | |
0e078e2f TG |
662 | /* |
663 | * Clean APIC state for other OSs: | |
664 | */ | |
665 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
666 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
667 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
668 | if (maxlvt >= 3) | |
669 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
670 | if (maxlvt >= 4) | |
671 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
672 | |
673 | /* Integrated APIC (!82489DX) ? */ | |
674 | if (lapic_is_integrated()) { | |
675 | if (maxlvt > 3) | |
676 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
677 | apic_write(APIC_ESR, 0); | |
678 | apic_read(APIC_ESR); | |
679 | } | |
0e078e2f TG |
680 | } |
681 | ||
682 | /** | |
683 | * disable_local_APIC - clear and disable the local APIC | |
684 | */ | |
685 | void disable_local_APIC(void) | |
686 | { | |
687 | unsigned int value; | |
688 | ||
689 | clear_local_APIC(); | |
690 | ||
691 | /* | |
692 | * Disable APIC (implies clearing of registers | |
693 | * for 82489DX!). | |
694 | */ | |
695 | value = apic_read(APIC_SPIV); | |
696 | value &= ~APIC_SPIV_APIC_ENABLED; | |
697 | apic_write(APIC_SPIV, value); | |
990b183e CG |
698 | |
699 | #ifdef CONFIG_X86_32 | |
700 | /* | |
701 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
702 | * restore the disabled state. | |
703 | */ | |
704 | if (enabled_via_apicbase) { | |
705 | unsigned int l, h; | |
706 | ||
707 | rdmsr(MSR_IA32_APICBASE, l, h); | |
708 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
709 | wrmsr(MSR_IA32_APICBASE, l, h); | |
710 | } | |
711 | #endif | |
0e078e2f TG |
712 | } |
713 | ||
fe4024dc CG |
714 | /* |
715 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
716 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
717 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
718 | * for the case where Linux didn't enable the LAPIC. | |
719 | */ | |
0e078e2f TG |
720 | void lapic_shutdown(void) |
721 | { | |
722 | unsigned long flags; | |
723 | ||
724 | if (!cpu_has_apic) | |
725 | return; | |
726 | ||
727 | local_irq_save(flags); | |
728 | ||
fe4024dc CG |
729 | #ifdef CONFIG_X86_32 |
730 | if (!enabled_via_apicbase) | |
731 | clear_local_APIC(); | |
732 | else | |
733 | #endif | |
734 | disable_local_APIC(); | |
735 | ||
0e078e2f TG |
736 | |
737 | local_irq_restore(flags); | |
738 | } | |
739 | ||
740 | /* | |
741 | * This is to verify that we're looking at a real local APIC. | |
742 | * Check these against your board if the CPUs aren't getting | |
743 | * started for no apparent reason. | |
744 | */ | |
745 | int __init verify_local_APIC(void) | |
746 | { | |
747 | unsigned int reg0, reg1; | |
748 | ||
749 | /* | |
750 | * The version register is read-only in a real APIC. | |
751 | */ | |
752 | reg0 = apic_read(APIC_LVR); | |
753 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
754 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
755 | reg1 = apic_read(APIC_LVR); | |
756 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
757 | ||
758 | /* | |
759 | * The two version reads above should print the same | |
760 | * numbers. If the second one is different, then we | |
761 | * poke at a non-APIC. | |
762 | */ | |
763 | if (reg1 != reg0) | |
764 | return 0; | |
765 | ||
766 | /* | |
767 | * Check if the version looks reasonably. | |
768 | */ | |
769 | reg1 = GET_APIC_VERSION(reg0); | |
770 | if (reg1 == 0x00 || reg1 == 0xff) | |
771 | return 0; | |
772 | reg1 = lapic_get_maxlvt(); | |
773 | if (reg1 < 0x02 || reg1 == 0xff) | |
774 | return 0; | |
775 | ||
776 | /* | |
777 | * The ID register is read/write in a real APIC. | |
778 | */ | |
2d7a66d0 | 779 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
780 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
781 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 782 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
783 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
784 | apic_write(APIC_ID, reg0); | |
785 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
786 | return 0; | |
787 | ||
788 | /* | |
1da177e4 LT |
789 | * The next two are just to see if we have sane values. |
790 | * They're only really relevant if we're in Virtual Wire | |
791 | * compatibility mode, but most boxes are anymore. | |
792 | */ | |
793 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 794 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
795 | reg1 = apic_read(APIC_LVT1); |
796 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
797 | ||
798 | return 1; | |
799 | } | |
800 | ||
0e078e2f TG |
801 | /** |
802 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
803 | */ | |
1da177e4 LT |
804 | void __init sync_Arb_IDs(void) |
805 | { | |
296cb951 CG |
806 | /* |
807 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
808 | * needed on AMD. | |
809 | */ | |
810 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
811 | return; |
812 | ||
813 | /* | |
814 | * Wait for idle. | |
815 | */ | |
816 | apic_wait_icr_idle(); | |
817 | ||
818 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
819 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
820 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
821 | } |
822 | ||
1da177e4 LT |
823 | /* |
824 | * An initial setup of the virtual wire mode. | |
825 | */ | |
826 | void __init init_bsp_APIC(void) | |
827 | { | |
11a8e778 | 828 | unsigned int value; |
1da177e4 LT |
829 | |
830 | /* | |
831 | * Don't do the setup now if we have a SMP BIOS as the | |
832 | * through-I/O-APIC virtual wire mode might be active. | |
833 | */ | |
834 | if (smp_found_config || !cpu_has_apic) | |
835 | return; | |
836 | ||
1da177e4 LT |
837 | /* |
838 | * Do not trust the local APIC being empty at bootup. | |
839 | */ | |
840 | clear_local_APIC(); | |
841 | ||
842 | /* | |
843 | * Enable APIC. | |
844 | */ | |
845 | value = apic_read(APIC_SPIV); | |
846 | value &= ~APIC_VECTOR_MASK; | |
847 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
848 | |
849 | #ifdef CONFIG_X86_32 | |
850 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
851 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
852 | (boot_cpu_data.x86 == 15)) | |
853 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
854 | else | |
855 | #endif | |
856 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 857 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 858 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
859 | |
860 | /* | |
861 | * Set up the virtual wire mode. | |
862 | */ | |
11a8e778 | 863 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 864 | value = APIC_DM_NMI; |
638c0411 CG |
865 | if (!lapic_is_integrated()) /* 82489DX */ |
866 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 867 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
868 | } |
869 | ||
c43da2f5 CG |
870 | static void __cpuinit lapic_setup_esr(void) |
871 | { | |
872 | unsigned long oldvalue, value, maxlvt; | |
873 | if (lapic_is_integrated() && !esr_disable) { | |
874 | if (esr_disable) { | |
875 | /* | |
876 | * Something untraceable is creating bad interrupts on | |
877 | * secondary quads ... for the moment, just leave the | |
878 | * ESR disabled - we can't do anything useful with the | |
879 | * errors anyway - mbligh | |
880 | */ | |
881 | printk(KERN_INFO "Leaving ESR disabled.\n"); | |
882 | return; | |
883 | } | |
884 | /* !82489DX */ | |
885 | maxlvt = lapic_get_maxlvt(); | |
886 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
887 | apic_write(APIC_ESR, 0); | |
888 | oldvalue = apic_read(APIC_ESR); | |
889 | ||
890 | /* enables sending errors */ | |
891 | value = ERROR_APIC_VECTOR; | |
892 | apic_write(APIC_LVTERR, value); | |
893 | /* | |
894 | * spec says clear errors after enabling vector. | |
895 | */ | |
896 | if (maxlvt > 3) | |
897 | apic_write(APIC_ESR, 0); | |
898 | value = apic_read(APIC_ESR); | |
899 | if (value != oldvalue) | |
900 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
901 | "vector: 0x%08lx after: 0x%08lx\n", | |
902 | oldvalue, value); | |
903 | } else { | |
904 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
905 | } | |
906 | } | |
907 | ||
908 | ||
0e078e2f TG |
909 | /** |
910 | * setup_local_APIC - setup the local APIC | |
911 | */ | |
912 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 913 | { |
739f33b3 | 914 | unsigned int value; |
da7ed9f9 | 915 | int i, j; |
1da177e4 | 916 | |
ac23d4ee | 917 | preempt_disable(); |
1da177e4 | 918 | value = apic_read(APIC_LVR); |
1da177e4 | 919 | |
fe7414a2 | 920 | BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f); |
1da177e4 LT |
921 | |
922 | /* | |
923 | * Double-check whether this APIC is really registered. | |
924 | * This is meaningless in clustered apic mode, so we skip it. | |
925 | */ | |
926 | if (!apic_id_registered()) | |
927 | BUG(); | |
928 | ||
929 | /* | |
930 | * Intel recommends to set DFR, LDR and TPR before enabling | |
931 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
932 | * document number 292116). So here it goes... | |
933 | */ | |
934 | init_apic_ldr(); | |
935 | ||
936 | /* | |
937 | * Set Task Priority to 'accept all'. We never change this | |
938 | * later on. | |
939 | */ | |
940 | value = apic_read(APIC_TASKPRI); | |
941 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 942 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 943 | |
da7ed9f9 VG |
944 | /* |
945 | * After a crash, we no longer service the interrupts and a pending | |
946 | * interrupt from previous kernel might still have ISR bit set. | |
947 | * | |
948 | * Most probably by now CPU has serviced that pending interrupt and | |
949 | * it might not have done the ack_APIC_irq() because it thought, | |
950 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
951 | * does not clear the ISR bit and cpu thinks it has already serivced | |
952 | * the interrupt. Hence a vector might get locked. It was noticed | |
953 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
954 | */ | |
955 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
956 | value = apic_read(APIC_ISR + i*0x10); | |
957 | for (j = 31; j >= 0; j--) { | |
958 | if (value & (1<<j)) | |
959 | ack_APIC_irq(); | |
960 | } | |
961 | } | |
962 | ||
1da177e4 LT |
963 | /* |
964 | * Now that we are all set up, enable the APIC | |
965 | */ | |
966 | value = apic_read(APIC_SPIV); | |
967 | value &= ~APIC_VECTOR_MASK; | |
968 | /* | |
969 | * Enable APIC | |
970 | */ | |
971 | value |= APIC_SPIV_APIC_ENABLED; | |
972 | ||
3f14c746 AK |
973 | /* We always use processor focus */ |
974 | ||
1da177e4 LT |
975 | /* |
976 | * Set spurious IRQ vector | |
977 | */ | |
978 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 979 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
980 | |
981 | /* | |
982 | * Set up LVT0, LVT1: | |
983 | * | |
984 | * set up through-local-APIC on the BP's LINT0. This is not | |
985 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
986 | * we delegate interrupts to the 8259A. | |
987 | */ | |
988 | /* | |
989 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
990 | */ | |
991 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
a8fcf1a2 | 992 | if (!smp_processor_id() && !value) { |
1da177e4 | 993 | value = APIC_DM_EXTINT; |
bc1d99c1 CW |
994 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
995 | smp_processor_id()); | |
1da177e4 LT |
996 | } else { |
997 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 CW |
998 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
999 | smp_processor_id()); | |
1da177e4 | 1000 | } |
11a8e778 | 1001 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1002 | |
1003 | /* | |
1004 | * only the BP should see the LINT1 NMI signal, obviously. | |
1005 | */ | |
1006 | if (!smp_processor_id()) | |
1007 | value = APIC_DM_NMI; | |
1008 | else | |
1009 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
11a8e778 | 1010 | apic_write(APIC_LVT1, value); |
ac23d4ee | 1011 | preempt_enable(); |
739f33b3 | 1012 | } |
1da177e4 | 1013 | |
739f33b3 AK |
1014 | void __cpuinit end_local_APIC_setup(void) |
1015 | { | |
1016 | lapic_setup_esr(); | |
f2802e7f | 1017 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1018 | apic_pm_activate(); |
1da177e4 | 1019 | } |
1da177e4 | 1020 | |
6e1cb38a SS |
1021 | void check_x2apic(void) |
1022 | { | |
1023 | int msr, msr2; | |
1024 | ||
1025 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1026 | ||
1027 | if (msr & X2APIC_ENABLE) { | |
1028 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1029 | x2apic_preenabled = x2apic = 1; | |
1030 | apic_ops = &x2apic_ops; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | void enable_x2apic(void) | |
1035 | { | |
1036 | int msr, msr2; | |
1037 | ||
1038 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1039 | if (!(msr & X2APIC_ENABLE)) { | |
1040 | printk("Enabling x2apic\n"); | |
1041 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | void enable_IR_x2apic(void) | |
1046 | { | |
1047 | #ifdef CONFIG_INTR_REMAP | |
1048 | int ret; | |
1049 | unsigned long flags; | |
1050 | ||
1051 | if (!cpu_has_x2apic) | |
1052 | return; | |
1053 | ||
1054 | if (!x2apic_preenabled && disable_x2apic) { | |
1055 | printk(KERN_INFO | |
1056 | "Skipped enabling x2apic and Interrupt-remapping " | |
1057 | "because of nox2apic\n"); | |
1058 | return; | |
1059 | } | |
1060 | ||
1061 | if (x2apic_preenabled && disable_x2apic) | |
1062 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1063 | ||
1064 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1065 | printk(KERN_INFO | |
1066 | "Skipped enabling x2apic and Interrupt-remapping " | |
1067 | "because of skipping io-apic setup\n"); | |
1068 | return; | |
1069 | } | |
1070 | ||
1071 | ret = dmar_table_init(); | |
1072 | if (ret) { | |
1073 | printk(KERN_INFO | |
1074 | "dmar_table_init() failed with %d:\n", ret); | |
1075 | ||
1076 | if (x2apic_preenabled) | |
1077 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1078 | else | |
1079 | printk(KERN_INFO | |
1080 | "Not enabling x2apic,Intr-remapping\n"); | |
1081 | return; | |
1082 | } | |
1083 | ||
1084 | local_irq_save(flags); | |
1085 | mask_8259A(); | |
1086 | save_mask_IO_APIC_setup(); | |
1087 | ||
1088 | ret = enable_intr_remapping(1); | |
1089 | ||
1090 | if (ret && x2apic_preenabled) { | |
1091 | local_irq_restore(flags); | |
1092 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1093 | } | |
1094 | ||
1095 | if (ret) | |
1096 | goto end; | |
1097 | ||
1098 | if (!x2apic) { | |
1099 | x2apic = 1; | |
1100 | apic_ops = &x2apic_ops; | |
1101 | enable_x2apic(); | |
1102 | } | |
1103 | end: | |
1104 | if (ret) | |
1105 | /* | |
1106 | * IR enabling failed | |
1107 | */ | |
1108 | restore_IO_APIC_setup(); | |
1109 | else | |
1110 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1111 | ||
1112 | unmask_8259A(); | |
1113 | local_irq_restore(flags); | |
1114 | ||
1115 | if (!ret) { | |
1116 | if (!x2apic_preenabled) | |
1117 | printk(KERN_INFO | |
1118 | "Enabled x2apic and interrupt-remapping\n"); | |
1119 | else | |
1120 | printk(KERN_INFO | |
1121 | "Enabled Interrupt-remapping\n"); | |
1122 | } else | |
1123 | printk(KERN_ERR | |
1124 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1125 | #else | |
1126 | if (!cpu_has_x2apic) | |
1127 | return; | |
1128 | ||
1129 | if (x2apic_preenabled) | |
1130 | panic("x2apic enabled prior OS handover," | |
1131 | " enable CONFIG_INTR_REMAP"); | |
1132 | ||
1133 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1134 | " and x2apic\n"); | |
1135 | #endif | |
1136 | ||
1137 | return; | |
1138 | } | |
1139 | ||
1da177e4 LT |
1140 | /* |
1141 | * Detect and enable local APICs on non-SMP boards. | |
1142 | * Original code written by Keir Fraser. | |
1143 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1144 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1145 | */ |
0e078e2f | 1146 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1147 | { |
1148 | if (!cpu_has_apic) { | |
1149 | printk(KERN_INFO "No local APIC present\n"); | |
1150 | return -1; | |
1151 | } | |
1152 | ||
1153 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1154 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1155 | return 0; |
1156 | } | |
1157 | ||
8643f9d0 YL |
1158 | void __init early_init_lapic_mapping(void) |
1159 | { | |
431ee79d | 1160 | unsigned long phys_addr; |
8643f9d0 YL |
1161 | |
1162 | /* | |
1163 | * If no local APIC can be found then go out | |
1164 | * : it means there is no mpatable and MADT | |
1165 | */ | |
1166 | if (!smp_found_config) | |
1167 | return; | |
1168 | ||
431ee79d | 1169 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1170 | |
431ee79d | 1171 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1172 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1173 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1174 | |
1175 | /* | |
1176 | * Fetch the APIC ID of the BSP in case we have a | |
1177 | * default configuration (or the MP table is broken). | |
1178 | */ | |
4c9961d5 | 1179 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 YL |
1180 | } |
1181 | ||
0e078e2f TG |
1182 | /** |
1183 | * init_apic_mappings - initialize APIC mappings | |
1184 | */ | |
1da177e4 LT |
1185 | void __init init_apic_mappings(void) |
1186 | { | |
6e1cb38a | 1187 | if (x2apic) { |
4c9961d5 | 1188 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1189 | return; |
1190 | } | |
1191 | ||
1da177e4 LT |
1192 | /* |
1193 | * If no local APIC can be found then set up a fake all | |
1194 | * zeroes page to simulate the local APIC and another | |
1195 | * one for the IO-APIC. | |
1196 | */ | |
1197 | if (!smp_found_config && detect_init_APIC()) { | |
1198 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1199 | apic_phys = __pa(apic_phys); | |
1200 | } else | |
1201 | apic_phys = mp_lapic_addr; | |
1202 | ||
1203 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
7ffeeb1e YL |
1204 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
1205 | APIC_BASE, apic_phys); | |
1da177e4 LT |
1206 | |
1207 | /* | |
1208 | * Fetch the APIC ID of the BSP in case we have a | |
1209 | * default configuration (or the MP table is broken). | |
1210 | */ | |
4c9961d5 | 1211 | boot_cpu_physical_apicid = read_apic_id(); |
1da177e4 LT |
1212 | } |
1213 | ||
1214 | /* | |
0e078e2f TG |
1215 | * This initializes the IO-APIC and APIC hardware if this is |
1216 | * a UP kernel. | |
1da177e4 | 1217 | */ |
1b313f4a CG |
1218 | int apic_version[MAX_APICS]; |
1219 | ||
0e078e2f | 1220 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1221 | { |
0e078e2f TG |
1222 | if (disable_apic) { |
1223 | printk(KERN_INFO "Apic disabled\n"); | |
1224 | return -1; | |
1225 | } | |
1226 | if (!cpu_has_apic) { | |
1227 | disable_apic = 1; | |
1228 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1229 | return -1; | |
1230 | } | |
1da177e4 | 1231 | |
6e1cb38a SS |
1232 | enable_IR_x2apic(); |
1233 | setup_apic_routing(); | |
1234 | ||
0e078e2f | 1235 | verify_local_APIC(); |
1da177e4 | 1236 | |
b5841765 GC |
1237 | connect_bsp_APIC(); |
1238 | ||
b6df1b8b | 1239 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
c70dcb74 | 1240 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
1da177e4 | 1241 | |
0e078e2f | 1242 | setup_local_APIC(); |
1da177e4 | 1243 | |
739f33b3 AK |
1244 | /* |
1245 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1246 | * We need clear_IO_APIC before enabling vector on BP | |
1247 | */ | |
1248 | if (!skip_ioapic_setup && nr_ioapics) | |
1249 | enable_IO_APIC(); | |
1250 | ||
acae7d90 MR |
1251 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
1252 | localise_nmi_watchdog(); | |
739f33b3 AK |
1253 | end_local_APIC_setup(); |
1254 | ||
0e078e2f TG |
1255 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1256 | setup_IO_APIC(); | |
1257 | else | |
1258 | nr_ioapics = 0; | |
1259 | setup_boot_APIC_clock(); | |
1260 | check_nmi_watchdog(); | |
1261 | return 0; | |
1da177e4 LT |
1262 | } |
1263 | ||
1264 | /* | |
0e078e2f | 1265 | * Local APIC interrupts |
1da177e4 LT |
1266 | */ |
1267 | ||
0e078e2f TG |
1268 | /* |
1269 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1270 | */ | |
1271 | asmlinkage void smp_spurious_interrupt(void) | |
1da177e4 | 1272 | { |
0e078e2f TG |
1273 | unsigned int v; |
1274 | exit_idle(); | |
1275 | irq_enter(); | |
1da177e4 | 1276 | /* |
0e078e2f TG |
1277 | * Check if this really is a spurious interrupt and ACK it |
1278 | * if it is a vectored one. Just in case... | |
1279 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1280 | */ |
0e078e2f TG |
1281 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1282 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1283 | ack_APIC_irq(); | |
c4d58cbd | 1284 | |
0e078e2f TG |
1285 | add_pda(irq_spurious_count, 1); |
1286 | irq_exit(); | |
1287 | } | |
1da177e4 | 1288 | |
0e078e2f TG |
1289 | /* |
1290 | * This interrupt should never happen with our APIC/SMP architecture | |
1291 | */ | |
1292 | asmlinkage void smp_error_interrupt(void) | |
1293 | { | |
1294 | unsigned int v, v1; | |
1da177e4 | 1295 | |
0e078e2f TG |
1296 | exit_idle(); |
1297 | irq_enter(); | |
1298 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1299 | v = apic_read(APIC_ESR); | |
1300 | apic_write(APIC_ESR, 0); | |
1301 | v1 = apic_read(APIC_ESR); | |
1302 | ack_APIC_irq(); | |
1303 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1304 | |
0e078e2f TG |
1305 | /* Here is what the APIC error bits mean: |
1306 | 0: Send CS error | |
1307 | 1: Receive CS error | |
1308 | 2: Send accept error | |
1309 | 3: Receive accept error | |
1310 | 4: Reserved | |
1311 | 5: Send illegal vector | |
1312 | 6: Received illegal vector | |
1313 | 7: Illegal register address | |
1314 | */ | |
1315 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1316 | smp_processor_id(), v , v1); | |
1317 | irq_exit(); | |
1da177e4 LT |
1318 | } |
1319 | ||
b5841765 | 1320 | /** |
36c9d674 CG |
1321 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1322 | */ | |
b5841765 GC |
1323 | void __init connect_bsp_APIC(void) |
1324 | { | |
36c9d674 CG |
1325 | #ifdef CONFIG_X86_32 |
1326 | if (pic_mode) { | |
1327 | /* | |
1328 | * Do not trust the local APIC being empty at bootup. | |
1329 | */ | |
1330 | clear_local_APIC(); | |
1331 | /* | |
1332 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1333 | * local APIC to INT and NMI lines. | |
1334 | */ | |
1335 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1336 | "enabling APIC mode.\n"); | |
1337 | outb(0x70, 0x22); | |
1338 | outb(0x01, 0x23); | |
1339 | } | |
1340 | #endif | |
b5841765 GC |
1341 | enable_apic_mode(); |
1342 | } | |
1343 | ||
274cfe59 CG |
1344 | /** |
1345 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1346 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1347 | * | |
1348 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1349 | * APIC is disabled. | |
1350 | */ | |
0e078e2f | 1351 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1352 | { |
c177b0bc CG |
1353 | #ifdef CONFIG_X86_32 |
1354 | if (pic_mode) { | |
1355 | /* | |
1356 | * Put the board back into PIC mode (has an effect only on | |
1357 | * certain older boards). Note that APIC interrupts, including | |
1358 | * IPIs, won't work beyond this point! The only exception are | |
1359 | * INIT IPIs. | |
1360 | */ | |
1361 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1362 | "entering PIC mode.\n"); | |
1363 | outb(0x70, 0x22); | |
1364 | outb(0x00, 0x23); | |
1365 | return; | |
1366 | } | |
1367 | #endif | |
1368 | ||
0e078e2f | 1369 | /* Go back to Virtual Wire compatibility mode */ |
c177b0bc | 1370 | unsigned int value; |
1da177e4 | 1371 | |
0e078e2f TG |
1372 | /* For the spurious interrupt use vector F, and enable it */ |
1373 | value = apic_read(APIC_SPIV); | |
1374 | value &= ~APIC_VECTOR_MASK; | |
1375 | value |= APIC_SPIV_APIC_ENABLED; | |
1376 | value |= 0xf; | |
1377 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1378 | |
0e078e2f TG |
1379 | if (!virt_wire_setup) { |
1380 | /* | |
1381 | * For LVT0 make it edge triggered, active high, | |
1382 | * external and enabled | |
1383 | */ | |
1384 | value = apic_read(APIC_LVT0); | |
1385 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1386 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1387 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1388 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1389 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1390 | apic_write(APIC_LVT0, value); | |
1391 | } else { | |
1392 | /* Disable LVT0 */ | |
1393 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1394 | } | |
b8ce3359 | 1395 | |
c177b0bc CG |
1396 | /* |
1397 | * For LVT1 make it edge triggered, active high, | |
1398 | * nmi and enabled | |
1399 | */ | |
0e078e2f TG |
1400 | value = apic_read(APIC_LVT1); |
1401 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1402 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1403 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1404 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1405 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1406 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1407 | } |
1408 | ||
be8a5685 AS |
1409 | void __cpuinit generic_processor_info(int apicid, int version) |
1410 | { | |
1411 | int cpu; | |
1412 | cpumask_t tmp_map; | |
1413 | ||
1b313f4a CG |
1414 | /* |
1415 | * Validate version | |
1416 | */ | |
1417 | if (version == 0x0) { | |
1418 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1419 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1420 | version); | |
1421 | version = 0x10; | |
1422 | } | |
1423 | apic_version[apicid] = version; | |
1424 | ||
be8a5685 AS |
1425 | if (num_processors >= NR_CPUS) { |
1426 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1427 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1428 | return; |
1429 | } | |
1430 | ||
1431 | if (num_processors >= maxcpus) { | |
1432 | printk(KERN_WARNING "WARNING: maxcpus limit of %i reached." | |
1b313f4a | 1433 | " Processor ignored.\n", maxcpus); |
be8a5685 AS |
1434 | return; |
1435 | } | |
1436 | ||
1437 | num_processors++; | |
1438 | cpus_complement(tmp_map, cpu_present_map); | |
1439 | cpu = first_cpu(tmp_map); | |
1440 | ||
1441 | physid_set(apicid, phys_cpu_present_map); | |
1442 | if (apicid == boot_cpu_physical_apicid) { | |
1443 | /* | |
1444 | * x86_bios_cpu_apicid is required to have processors listed | |
1445 | * in same order as logical cpu numbers. Hence the first | |
1446 | * entry is BSP, and so on. | |
1447 | */ | |
1448 | cpu = 0; | |
1449 | } | |
e0da3364 YL |
1450 | if (apicid > max_physical_apicid) |
1451 | max_physical_apicid = apicid; | |
1452 | ||
1b313f4a CG |
1453 | #ifdef CONFIG_X86_32 |
1454 | /* | |
1455 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1456 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1457 | * before this can be done without some confusion. | |
1458 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1459 | * - Ashok Raj <ashok.raj@intel.com> | |
1460 | */ | |
1461 | if (max_physical_apicid >= 8) { | |
1462 | switch (boot_cpu_data.x86_vendor) { | |
1463 | case X86_VENDOR_INTEL: | |
1464 | if (!APIC_XAPIC(version)) { | |
1465 | def_to_bigsmp = 0; | |
1466 | break; | |
1467 | } | |
1468 | /* If P4 and above fall through */ | |
1469 | case X86_VENDOR_AMD: | |
1470 | def_to_bigsmp = 1; | |
1471 | } | |
1472 | } | |
1473 | #endif | |
1474 | ||
1475 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1476 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1477 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1478 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1479 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1480 | |
1481 | cpu_to_apicid[cpu] = apicid; | |
1482 | bios_cpu_apicid[cpu] = apicid; | |
1483 | } else { | |
1484 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1485 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1486 | } | |
1b313f4a | 1487 | #endif |
be8a5685 AS |
1488 | |
1489 | cpu_set(cpu, cpu_possible_map); | |
1490 | cpu_set(cpu, cpu_present_map); | |
1491 | } | |
1492 | ||
0c81c746 SS |
1493 | int hard_smp_processor_id(void) |
1494 | { | |
1495 | return read_apic_id(); | |
1496 | } | |
1497 | ||
89039b37 | 1498 | /* |
0e078e2f | 1499 | * Power management |
89039b37 | 1500 | */ |
0e078e2f TG |
1501 | #ifdef CONFIG_PM |
1502 | ||
1503 | static struct { | |
274cfe59 CG |
1504 | /* |
1505 | * 'active' is true if the local APIC was enabled by us and | |
1506 | * not the BIOS; this signifies that we are also responsible | |
1507 | * for disabling it before entering apm/acpi suspend | |
1508 | */ | |
0e078e2f TG |
1509 | int active; |
1510 | /* r/w apic fields */ | |
1511 | unsigned int apic_id; | |
1512 | unsigned int apic_taskpri; | |
1513 | unsigned int apic_ldr; | |
1514 | unsigned int apic_dfr; | |
1515 | unsigned int apic_spiv; | |
1516 | unsigned int apic_lvtt; | |
1517 | unsigned int apic_lvtpc; | |
1518 | unsigned int apic_lvt0; | |
1519 | unsigned int apic_lvt1; | |
1520 | unsigned int apic_lvterr; | |
1521 | unsigned int apic_tmict; | |
1522 | unsigned int apic_tdcr; | |
1523 | unsigned int apic_thmr; | |
1524 | } apic_pm_state; | |
1525 | ||
1526 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1527 | { | |
1528 | unsigned long flags; | |
1529 | int maxlvt; | |
89039b37 | 1530 | |
0e078e2f TG |
1531 | if (!apic_pm_state.active) |
1532 | return 0; | |
89039b37 | 1533 | |
0e078e2f | 1534 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1535 | |
2d7a66d0 | 1536 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1537 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1538 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1539 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1540 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1541 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1542 | if (maxlvt >= 4) | |
1543 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1544 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1545 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1546 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1547 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1548 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1549 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1550 | if (maxlvt >= 5) |
1551 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1552 | #endif | |
24968cfd | 1553 | |
0e078e2f TG |
1554 | local_irq_save(flags); |
1555 | disable_local_APIC(); | |
1556 | local_irq_restore(flags); | |
1557 | return 0; | |
1da177e4 LT |
1558 | } |
1559 | ||
0e078e2f | 1560 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1561 | { |
0e078e2f TG |
1562 | unsigned int l, h; |
1563 | unsigned long flags; | |
1564 | int maxlvt; | |
1da177e4 | 1565 | |
0e078e2f TG |
1566 | if (!apic_pm_state.active) |
1567 | return 0; | |
89b831ef | 1568 | |
0e078e2f | 1569 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1570 | |
0e078e2f | 1571 | local_irq_save(flags); |
92206c90 CG |
1572 | |
1573 | #ifdef CONFIG_X86_64 | |
1574 | if (x2apic) | |
1575 | enable_x2apic(); | |
1576 | else | |
1577 | #endif | |
d5e629a6 | 1578 | { |
92206c90 CG |
1579 | /* |
1580 | * Make sure the APICBASE points to the right address | |
1581 | * | |
1582 | * FIXME! This will be wrong if we ever support suspend on | |
1583 | * SMP! We'll need to do this as part of the CPU restore! | |
1584 | */ | |
6e1cb38a SS |
1585 | rdmsr(MSR_IA32_APICBASE, l, h); |
1586 | l &= ~MSR_IA32_APICBASE_BASE; | |
1587 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1588 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1589 | } |
6e1cb38a | 1590 | |
0e078e2f TG |
1591 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1592 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1593 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1594 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1595 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1596 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1597 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1598 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1599 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1600 | if (maxlvt >= 5) |
1601 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1602 | #endif | |
1603 | if (maxlvt >= 4) | |
1604 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
1605 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
1606 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
1607 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
1608 | apic_write(APIC_ESR, 0); | |
1609 | apic_read(APIC_ESR); | |
1610 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
1611 | apic_write(APIC_ESR, 0); | |
1612 | apic_read(APIC_ESR); | |
92206c90 | 1613 | |
0e078e2f | 1614 | local_irq_restore(flags); |
92206c90 | 1615 | |
0e078e2f TG |
1616 | return 0; |
1617 | } | |
b8ce3359 | 1618 | |
274cfe59 CG |
1619 | /* |
1620 | * This device has no shutdown method - fully functioning local APICs | |
1621 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
1622 | */ | |
1623 | ||
0e078e2f TG |
1624 | static struct sysdev_class lapic_sysclass = { |
1625 | .name = "lapic", | |
1626 | .resume = lapic_resume, | |
1627 | .suspend = lapic_suspend, | |
1628 | }; | |
b8ce3359 | 1629 | |
0e078e2f | 1630 | static struct sys_device device_lapic = { |
e83a5fdc HS |
1631 | .id = 0, |
1632 | .cls = &lapic_sysclass, | |
0e078e2f | 1633 | }; |
b8ce3359 | 1634 | |
0e078e2f TG |
1635 | static void __cpuinit apic_pm_activate(void) |
1636 | { | |
1637 | apic_pm_state.active = 1; | |
1da177e4 LT |
1638 | } |
1639 | ||
0e078e2f | 1640 | static int __init init_lapic_sysfs(void) |
1da177e4 | 1641 | { |
0e078e2f | 1642 | int error; |
e83a5fdc | 1643 | |
0e078e2f TG |
1644 | if (!cpu_has_apic) |
1645 | return 0; | |
1646 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 1647 | |
0e078e2f TG |
1648 | error = sysdev_class_register(&lapic_sysclass); |
1649 | if (!error) | |
1650 | error = sysdev_register(&device_lapic); | |
1651 | return error; | |
1da177e4 | 1652 | } |
0e078e2f TG |
1653 | device_initcall(init_lapic_sysfs); |
1654 | ||
1655 | #else /* CONFIG_PM */ | |
1656 | ||
1657 | static void apic_pm_activate(void) { } | |
1658 | ||
1659 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
1660 | |
1661 | /* | |
f8bf3c65 | 1662 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
1663 | * |
1664 | * Thus far, the major user of this is IBM's Summit2 series: | |
1665 | * | |
637029c6 | 1666 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
1667 | * multi-chassis. Use available data to take a good guess. |
1668 | * If in doubt, go HPET. | |
1669 | */ | |
f8bf3c65 | 1670 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
1671 | { |
1672 | int i, clusters, zeros; | |
1673 | unsigned id; | |
322850af | 1674 | u16 *bios_cpu_apicid; |
1da177e4 LT |
1675 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
1676 | ||
322850af YL |
1677 | /* |
1678 | * there is not this kind of box with AMD CPU yet. | |
1679 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
1680 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 1681 | * vsmp box still need checking... |
322850af | 1682 | */ |
1cb68487 | 1683 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
1684 | return 0; |
1685 | ||
23ca4bba | 1686 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 1687 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
1688 | |
1689 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 1690 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
1691 | if (bios_cpu_apicid) { |
1692 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 1693 | } |
1694 | else if (i < nr_cpu_ids) { | |
1695 | if (cpu_present(i)) | |
1696 | id = per_cpu(x86_bios_cpu_apicid, i); | |
1697 | else | |
1698 | continue; | |
1699 | } | |
1700 | else | |
1701 | break; | |
1702 | ||
1da177e4 LT |
1703 | if (id != BAD_APICID) |
1704 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
1705 | } | |
1706 | ||
1707 | /* Problem: Partially populated chassis may not have CPUs in some of | |
1708 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 1709 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
1710 | * Since clusters are allocated sequentially, count zeros only if | |
1711 | * they are bounded by ones. | |
1da177e4 LT |
1712 | */ |
1713 | clusters = 0; | |
1714 | zeros = 0; | |
1715 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
1716 | if (test_bit(i, clustermap)) { | |
1717 | clusters += 1 + zeros; | |
1718 | zeros = 0; | |
1719 | } else | |
1720 | ++zeros; | |
1721 | } | |
1722 | ||
1cb68487 RT |
1723 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
1724 | * not guaranteed to be synced between boards | |
1725 | */ | |
1726 | if (is_vsmp_box() && clusters > 1) | |
1727 | return 1; | |
1728 | ||
1da177e4 | 1729 | /* |
f8bf3c65 | 1730 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
1731 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
1732 | * out, but AFAIK this will work even for them. | |
1733 | */ | |
1734 | return (clusters > 2); | |
1735 | } | |
1736 | ||
6e1cb38a SS |
1737 | static __init int setup_nox2apic(char *str) |
1738 | { | |
1739 | disable_x2apic = 1; | |
1740 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC); | |
1741 | return 0; | |
1742 | } | |
1743 | early_param("nox2apic", setup_nox2apic); | |
1744 | ||
1745 | ||
1da177e4 | 1746 | /* |
0e078e2f | 1747 | * APIC command line parameters |
1da177e4 | 1748 | */ |
0e078e2f | 1749 | static int __init apic_set_verbosity(char *str) |
1da177e4 | 1750 | { |
0e078e2f TG |
1751 | if (str == NULL) { |
1752 | skip_ioapic_setup = 0; | |
1753 | ioapic_force = 1; | |
1754 | return 0; | |
1da177e4 | 1755 | } |
0e078e2f TG |
1756 | if (strcmp("debug", str) == 0) |
1757 | apic_verbosity = APIC_DEBUG; | |
1758 | else if (strcmp("verbose", str) == 0) | |
1759 | apic_verbosity = APIC_VERBOSE; | |
1760 | else { | |
1761 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
1762 | " use apic=verbose or apic=debug\n", str); | |
1763 | return -EINVAL; | |
1da177e4 LT |
1764 | } |
1765 | ||
1da177e4 LT |
1766 | return 0; |
1767 | } | |
0e078e2f | 1768 | early_param("apic", apic_set_verbosity); |
1da177e4 | 1769 | |
6935d1f9 TG |
1770 | static __init int setup_disableapic(char *str) |
1771 | { | |
1da177e4 | 1772 | disable_apic = 1; |
9175fc06 | 1773 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
1774 | return 0; |
1775 | } | |
1776 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 1777 | |
2c8c0e6b | 1778 | /* same as disableapic, for compatibility */ |
6935d1f9 TG |
1779 | static __init int setup_nolapic(char *str) |
1780 | { | |
2c8c0e6b | 1781 | return setup_disableapic(str); |
6935d1f9 | 1782 | } |
2c8c0e6b | 1783 | early_param("nolapic", setup_nolapic); |
1da177e4 | 1784 | |
2e7c2838 LT |
1785 | static int __init parse_lapic_timer_c2_ok(char *arg) |
1786 | { | |
1787 | local_apic_timer_c2_ok = 1; | |
1788 | return 0; | |
1789 | } | |
1790 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
1791 | ||
36fef094 | 1792 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 1793 | { |
1da177e4 | 1794 | disable_apic_timer = 1; |
36fef094 CG |
1795 | return 0; |
1796 | } | |
1797 | early_param("noapictimer", parse_disable_apic_timer); | |
1798 | ||
1799 | static int __init parse_nolapic_timer(char *arg) | |
1800 | { | |
1801 | disable_apic_timer = 1; | |
1802 | return 0; | |
6935d1f9 | 1803 | } |
36fef094 | 1804 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 1805 | |
0c3749c4 AK |
1806 | static __init int setup_apicpmtimer(char *s) |
1807 | { | |
1808 | apic_calibrate_pmtmr = 1; | |
7fd67843 | 1809 | notsc_setup(NULL); |
b8ce3359 | 1810 | return 0; |
0c3749c4 AK |
1811 | } |
1812 | __setup("apicpmtimer", setup_apicpmtimer); | |
1813 | ||
1e934dda YL |
1814 | static int __init lapic_insert_resource(void) |
1815 | { | |
1816 | if (!apic_phys) | |
1817 | return -1; | |
1818 | ||
1819 | /* Put local APIC into the resource map. */ | |
1820 | lapic_resource.start = apic_phys; | |
1821 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
1822 | insert_resource(&iomem_resource, &lapic_resource); | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | /* | |
1828 | * need call insert after e820_reserve_resources() | |
1829 | * that is using request_resource | |
1830 | */ | |
1831 | late_initcall(lapic_insert_resource); |