Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
8f47e163 | 4 | * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
1da177e4 LT |
5 | * |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 | 17 | #include <linux/kernel_stat.h> |
d1de36f5 | 18 | #include <linux/mc146818rtc.h> |
70a20025 | 19 | #include <linux/acpi_pmtmr.h> |
d1de36f5 IM |
20 | #include <linux/clockchips.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/bootmem.h> | |
23 | #include <linux/ftrace.h> | |
24 | #include <linux/ioport.h> | |
e83a5fdc | 25 | #include <linux/module.h> |
d1de36f5 IM |
26 | #include <linux/sysdev.h> |
27 | #include <linux/delay.h> | |
28 | #include <linux/timex.h> | |
6e1cb38a | 29 | #include <linux/dmar.h> |
d1de36f5 IM |
30 | #include <linux/init.h> |
31 | #include <linux/cpu.h> | |
32 | #include <linux/dmi.h> | |
e423e33e | 33 | #include <linux/nmi.h> |
d1de36f5 IM |
34 | #include <linux/smp.h> |
35 | #include <linux/mm.h> | |
1da177e4 | 36 | |
773763df | 37 | #include <asm/arch_hooks.h> |
1da177e4 | 38 | #include <asm/pgalloc.h> |
d1de36f5 IM |
39 | #include <asm/genapic.h> |
40 | #include <asm/atomic.h> | |
41 | #include <asm/mpspec.h> | |
773763df | 42 | #include <asm/i8253.h> |
d1de36f5 | 43 | #include <asm/i8259.h> |
73dea47f | 44 | #include <asm/proto.h> |
2c8c0e6b | 45 | #include <asm/apic.h> |
d1de36f5 IM |
46 | #include <asm/desc.h> |
47 | #include <asm/hpet.h> | |
48 | #include <asm/idle.h> | |
49 | #include <asm/mtrr.h> | |
2bc13797 | 50 | #include <asm/smp.h> |
1da177e4 | 51 | |
ec70de8b | 52 | unsigned int num_processors; |
fdbecd9f | 53 | |
ec70de8b | 54 | unsigned disabled_cpus __cpuinitdata; |
fdbecd9f | 55 | |
ec70de8b BG |
56 | /* Processor that is doing the boot up */ |
57 | unsigned int boot_cpu_physical_apicid = -1U; | |
5af5573e | 58 | |
80e5609c | 59 | /* |
fdbecd9f IM |
60 | * The highest APIC ID seen during enumeration. |
61 | * | |
62 | * This determines the messaging protocol we can use: if all APIC IDs | |
63 | * are in the 0 ... 7 range, then we can use logical addressing which | |
64 | * has some performance advantages (better broadcasting). | |
65 | * | |
66 | * If there's an APIC ID above 8, we use physical addressing. | |
80e5609c | 67 | */ |
ec70de8b BG |
68 | unsigned int max_physical_apicid; |
69 | ||
fdbecd9f IM |
70 | /* |
71 | * Bitmask of physically existing CPUs: | |
72 | */ | |
ec70de8b BG |
73 | physid_mask_t phys_cpu_present_map; |
74 | ||
75 | /* | |
76 | * Map cpu index to physical APIC ID | |
77 | */ | |
78 | DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); | |
79 | DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); | |
80 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
81 | EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
80e5609c | 82 | |
b3c51170 YL |
83 | #ifdef CONFIG_X86_32 |
84 | /* | |
85 | * Knob to control our willingness to enable the local APIC. | |
86 | * | |
87 | * +1=force-enable | |
88 | */ | |
89 | static int force_enable_local_apic; | |
90 | /* | |
91 | * APIC command line parameters | |
92 | */ | |
93 | static int __init parse_lapic(char *arg) | |
94 | { | |
95 | force_enable_local_apic = 1; | |
96 | return 0; | |
97 | } | |
98 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
99 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
100 | static int enabled_via_apicbase; | |
101 | ||
b3c51170 YL |
102 | #endif |
103 | ||
104 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 105 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
106 | static __init int setup_apicpmtimer(char *s) |
107 | { | |
108 | apic_calibrate_pmtmr = 1; | |
109 | notsc_setup(NULL); | |
110 | return 0; | |
111 | } | |
112 | __setup("apicpmtimer", setup_apicpmtimer); | |
113 | #endif | |
114 | ||
49899eac YL |
115 | #ifdef CONFIG_X86_64 |
116 | #define HAVE_X2APIC | |
117 | #endif | |
118 | ||
119 | #ifdef HAVE_X2APIC | |
89027d35 | 120 | int x2apic; |
6e1cb38a | 121 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
122 | static int x2apic_preenabled; |
123 | static int disable_x2apic; | |
49899eac YL |
124 | static __init int setup_nox2apic(char *str) |
125 | { | |
126 | disable_x2apic = 1; | |
127 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
128 | return 0; | |
129 | } | |
130 | early_param("nox2apic", setup_nox2apic); | |
131 | #endif | |
1da177e4 | 132 | |
b3c51170 YL |
133 | unsigned long mp_lapic_addr; |
134 | int disable_apic; | |
135 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
136 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 137 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
138 | int local_apic_timer_c2_ok; |
139 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
140 | ||
efa2559f YL |
141 | int first_system_vector = 0xfe; |
142 | ||
e83a5fdc HS |
143 | /* |
144 | * Debug level, exported for io_apic.c | |
145 | */ | |
baa13188 | 146 | unsigned int apic_verbosity; |
e83a5fdc | 147 | |
89c38c28 CG |
148 | int pic_mode; |
149 | ||
bab4b27c AS |
150 | /* Have we found an MP table */ |
151 | int smp_found_config; | |
152 | ||
39928722 AD |
153 | static struct resource lapic_resource = { |
154 | .name = "Local APIC", | |
155 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
156 | }; | |
157 | ||
d03030e9 TG |
158 | static unsigned int calibration_result; |
159 | ||
ba7eda4c TG |
160 | static int lapic_next_event(unsigned long delta, |
161 | struct clock_event_device *evt); | |
162 | static void lapic_timer_setup(enum clock_event_mode mode, | |
163 | struct clock_event_device *evt); | |
9628937d | 164 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 165 | static void apic_pm_activate(void); |
ba7eda4c | 166 | |
274cfe59 CG |
167 | /* |
168 | * The local apic timer can be used for any function which is CPU local. | |
169 | */ | |
ba7eda4c TG |
170 | static struct clock_event_device lapic_clockevent = { |
171 | .name = "lapic", | |
172 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
173 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
174 | .shift = 32, | |
175 | .set_mode = lapic_timer_setup, | |
176 | .set_next_event = lapic_next_event, | |
177 | .broadcast = lapic_timer_broadcast, | |
178 | .rating = 100, | |
179 | .irq = -1, | |
180 | }; | |
181 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
182 | ||
d3432896 AK |
183 | static unsigned long apic_phys; |
184 | ||
0e078e2f TG |
185 | /* |
186 | * Get the LAPIC version | |
187 | */ | |
188 | static inline int lapic_get_version(void) | |
ba7eda4c | 189 | { |
0e078e2f | 190 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
191 | } |
192 | ||
0e078e2f | 193 | /* |
9c803869 | 194 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
195 | */ |
196 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 197 | { |
9c803869 | 198 | #ifdef CONFIG_X86_64 |
0e078e2f | 199 | return 1; |
9c803869 CG |
200 | #else |
201 | return APIC_INTEGRATED(lapic_get_version()); | |
202 | #endif | |
ba7eda4c TG |
203 | } |
204 | ||
205 | /* | |
0e078e2f | 206 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 207 | */ |
0e078e2f | 208 | static int modern_apic(void) |
ba7eda4c | 209 | { |
0e078e2f TG |
210 | /* AMD systems use old APIC versions, so check the CPU */ |
211 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
212 | boot_cpu_data.x86 >= 0xf) | |
213 | return 1; | |
214 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
215 | } |
216 | ||
274cfe59 CG |
217 | /* |
218 | * Paravirt kernels also might be using these below ops. So we still | |
219 | * use generic apic_read()/apic_write(), which might be pointing to different | |
220 | * ops in PARAVIRT case. | |
221 | */ | |
1b374e4d | 222 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
223 | { |
224 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
225 | cpu_relax(); | |
226 | } | |
227 | ||
1b374e4d | 228 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 229 | { |
3c6bb07a | 230 | u32 send_status; |
8339e9fb FLV |
231 | int timeout; |
232 | ||
233 | timeout = 0; | |
234 | do { | |
235 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
236 | if (!send_status) | |
237 | break; | |
238 | udelay(100); | |
239 | } while (timeout++ < 1000); | |
240 | ||
241 | return send_status; | |
242 | } | |
243 | ||
1b374e4d SS |
244 | void xapic_icr_write(u32 low, u32 id) |
245 | { | |
ed4e5ec1 | 246 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
247 | apic_write(APIC_ICR, low); |
248 | } | |
249 | ||
ec8c842a | 250 | static u64 xapic_icr_read(void) |
1b374e4d SS |
251 | { |
252 | u32 icr1, icr2; | |
253 | ||
254 | icr2 = apic_read(APIC_ICR2); | |
255 | icr1 = apic_read(APIC_ICR); | |
256 | ||
cf9768d7 | 257 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
258 | } |
259 | ||
260 | static struct apic_ops xapic_ops = { | |
261 | .read = native_apic_mem_read, | |
262 | .write = native_apic_mem_write, | |
1b374e4d SS |
263 | .icr_read = xapic_icr_read, |
264 | .icr_write = xapic_icr_write, | |
265 | .wait_icr_idle = xapic_wait_icr_idle, | |
266 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
267 | }; | |
268 | ||
269 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
270 | EXPORT_SYMBOL_GPL(apic_ops); |
271 | ||
49899eac | 272 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
273 | static void x2apic_wait_icr_idle(void) |
274 | { | |
275 | /* no need to wait for icr idle in x2apic */ | |
276 | return; | |
277 | } | |
278 | ||
279 | static u32 safe_x2apic_wait_icr_idle(void) | |
280 | { | |
281 | /* no need to wait for icr idle in x2apic */ | |
282 | return 0; | |
283 | } | |
284 | ||
285 | void x2apic_icr_write(u32 low, u32 id) | |
286 | { | |
287 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
288 | } | |
289 | ||
ec8c842a | 290 | static u64 x2apic_icr_read(void) |
13c88fb5 SS |
291 | { |
292 | unsigned long val; | |
293 | ||
294 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
295 | return val; | |
296 | } | |
297 | ||
298 | static struct apic_ops x2apic_ops = { | |
299 | .read = native_apic_msr_read, | |
300 | .write = native_apic_msr_write, | |
13c88fb5 SS |
301 | .icr_read = x2apic_icr_read, |
302 | .icr_write = x2apic_icr_write, | |
303 | .wait_icr_idle = x2apic_wait_icr_idle, | |
304 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
305 | }; | |
49899eac | 306 | #endif |
13c88fb5 | 307 | |
0e078e2f TG |
308 | /** |
309 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
310 | */ | |
e9427101 | 311 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 312 | { |
11a8e778 | 313 | unsigned int v; |
6935d1f9 TG |
314 | |
315 | /* unmask and set to NMI */ | |
316 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
317 | |
318 | /* Level triggered for 82489DX (32bit mode) */ | |
319 | if (!lapic_is_integrated()) | |
320 | v |= APIC_LVT_LEVEL_TRIGGER; | |
321 | ||
11a8e778 | 322 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
323 | } |
324 | ||
7c37e48b CG |
325 | #ifdef CONFIG_X86_32 |
326 | /** | |
327 | * get_physical_broadcast - Get number of physical broadcast IDs | |
328 | */ | |
329 | int get_physical_broadcast(void) | |
330 | { | |
331 | return modern_apic() ? 0xff : 0xf; | |
332 | } | |
333 | #endif | |
334 | ||
0e078e2f TG |
335 | /** |
336 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
337 | */ | |
37e650c7 | 338 | int lapic_get_maxlvt(void) |
1da177e4 | 339 | { |
36a028de | 340 | unsigned int v; |
1da177e4 LT |
341 | |
342 | v = apic_read(APIC_LVR); | |
36a028de CG |
343 | /* |
344 | * - we always have APIC integrated on 64bit mode | |
345 | * - 82489DXs do not report # of LVT entries | |
346 | */ | |
347 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
348 | } |
349 | ||
274cfe59 CG |
350 | /* |
351 | * Local APIC timer | |
352 | */ | |
353 | ||
c40aaec6 | 354 | /* Clock divisor */ |
c40aaec6 | 355 | #define APIC_DIVISOR 16 |
f07f4f90 | 356 | |
0e078e2f TG |
357 | /* |
358 | * This function sets up the local APIC timer, with a timeout of | |
359 | * 'clocks' APIC bus clock. During calibration we actually call | |
360 | * this function twice on the boot CPU, once with a bogus timeout | |
361 | * value, second time for real. The other (noncalibrating) CPUs | |
362 | * call this function only once, with the real, calibrated value. | |
363 | * | |
364 | * We do reads before writes even if unnecessary, to get around the | |
365 | * P5 APIC double write bug. | |
366 | */ | |
0e078e2f | 367 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 368 | { |
0e078e2f | 369 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 370 | |
0e078e2f TG |
371 | lvtt_value = LOCAL_TIMER_VECTOR; |
372 | if (!oneshot) | |
373 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
374 | if (!lapic_is_integrated()) |
375 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
376 | ||
0e078e2f TG |
377 | if (!irqen) |
378 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 379 | |
0e078e2f | 380 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
381 | |
382 | /* | |
0e078e2f | 383 | * Divide PICLK by 16 |
1da177e4 | 384 | */ |
0e078e2f | 385 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
386 | apic_write(APIC_TDCR, |
387 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
388 | APIC_TDR_DIV_16); | |
0e078e2f TG |
389 | |
390 | if (!oneshot) | |
f07f4f90 | 391 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
392 | } |
393 | ||
0e078e2f | 394 | /* |
7b83dae7 RR |
395 | * Setup extended LVT, AMD specific (K8, family 10h) |
396 | * | |
397 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
398 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
399 | * |
400 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
401 | * enables the vector. See also the BKDGs. | |
0e078e2f | 402 | */ |
7b83dae7 RR |
403 | |
404 | #define APIC_EILVT_LVTOFF_MCE 0 | |
405 | #define APIC_EILVT_LVTOFF_IBS 1 | |
406 | ||
407 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 408 | { |
7b83dae7 | 409 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 410 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 411 | |
0e078e2f | 412 | apic_write(reg, v); |
1da177e4 LT |
413 | } |
414 | ||
7b83dae7 RR |
415 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
416 | { | |
417 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
418 | return APIC_EILVT_LVTOFF_MCE; | |
419 | } | |
420 | ||
421 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
422 | { | |
423 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
424 | return APIC_EILVT_LVTOFF_IBS; | |
425 | } | |
6aa360e6 | 426 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 427 | |
0e078e2f TG |
428 | /* |
429 | * Program the next event, relative to now | |
430 | */ | |
431 | static int lapic_next_event(unsigned long delta, | |
432 | struct clock_event_device *evt) | |
1da177e4 | 433 | { |
0e078e2f TG |
434 | apic_write(APIC_TMICT, delta); |
435 | return 0; | |
1da177e4 LT |
436 | } |
437 | ||
0e078e2f TG |
438 | /* |
439 | * Setup the lapic timer in periodic or oneshot mode | |
440 | */ | |
441 | static void lapic_timer_setup(enum clock_event_mode mode, | |
442 | struct clock_event_device *evt) | |
9b7711f0 HS |
443 | { |
444 | unsigned long flags; | |
0e078e2f | 445 | unsigned int v; |
9b7711f0 | 446 | |
0e078e2f TG |
447 | /* Lapic used as dummy for broadcast ? */ |
448 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
449 | return; |
450 | ||
451 | local_irq_save(flags); | |
452 | ||
0e078e2f TG |
453 | switch (mode) { |
454 | case CLOCK_EVT_MODE_PERIODIC: | |
455 | case CLOCK_EVT_MODE_ONESHOT: | |
456 | __setup_APIC_LVTT(calibration_result, | |
457 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
458 | break; | |
459 | case CLOCK_EVT_MODE_UNUSED: | |
460 | case CLOCK_EVT_MODE_SHUTDOWN: | |
461 | v = apic_read(APIC_LVTT); | |
462 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
463 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 464 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
465 | break; |
466 | case CLOCK_EVT_MODE_RESUME: | |
467 | /* Nothing to do here */ | |
468 | break; | |
469 | } | |
9b7711f0 HS |
470 | |
471 | local_irq_restore(flags); | |
472 | } | |
473 | ||
1da177e4 | 474 | /* |
0e078e2f | 475 | * Local APIC timer broadcast function |
1da177e4 | 476 | */ |
9628937d | 477 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 478 | { |
0e078e2f | 479 | #ifdef CONFIG_SMP |
dac5f412 | 480 | apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); |
0e078e2f TG |
481 | #endif |
482 | } | |
1da177e4 | 483 | |
0e078e2f TG |
484 | /* |
485 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
486 | * of the boot CPU and register the clock event in the framework. | |
487 | */ | |
db4b5525 | 488 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
489 | { |
490 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 491 | |
0e078e2f | 492 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 493 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 494 | |
0e078e2f TG |
495 | clockevents_register_device(levt); |
496 | } | |
1da177e4 | 497 | |
2f04fa88 YL |
498 | /* |
499 | * In this functions we calibrate APIC bus clocks to the external timer. | |
500 | * | |
501 | * We want to do the calibration only once since we want to have local timer | |
502 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
503 | * frequency. | |
504 | * | |
505 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
506 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
507 | * readout is broken, so it never gets out of the wait loop again. This was | |
508 | * also reported by others. | |
509 | * | |
510 | * Monitoring the jiffies value is inaccurate and the clockevents | |
511 | * infrastructure allows us to do a simple substitution of the interrupt | |
512 | * handler. | |
513 | * | |
514 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
515 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
516 | * back to normal later in the boot process). | |
517 | */ | |
518 | ||
519 | #define LAPIC_CAL_LOOPS (HZ/10) | |
520 | ||
521 | static __initdata int lapic_cal_loops = -1; | |
522 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
523 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
524 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
525 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
526 | ||
527 | /* | |
528 | * Temporary interrupt handler. | |
529 | */ | |
530 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
531 | { | |
532 | unsigned long long tsc = 0; | |
533 | long tapic = apic_read(APIC_TMCCT); | |
534 | unsigned long pm = acpi_pm_read_early(); | |
535 | ||
536 | if (cpu_has_tsc) | |
537 | rdtscll(tsc); | |
538 | ||
539 | switch (lapic_cal_loops++) { | |
540 | case 0: | |
541 | lapic_cal_t1 = tapic; | |
542 | lapic_cal_tsc1 = tsc; | |
543 | lapic_cal_pm1 = pm; | |
544 | lapic_cal_j1 = jiffies; | |
545 | break; | |
546 | ||
547 | case LAPIC_CAL_LOOPS: | |
548 | lapic_cal_t2 = tapic; | |
549 | lapic_cal_tsc2 = tsc; | |
550 | if (pm < lapic_cal_pm1) | |
551 | pm += ACPI_PM_OVRRUN; | |
552 | lapic_cal_pm2 = pm; | |
553 | lapic_cal_j2 = jiffies; | |
554 | break; | |
555 | } | |
556 | } | |
557 | ||
754ef0cd YI |
558 | static int __init |
559 | calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) | |
b189892d CG |
560 | { |
561 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
562 | const long pm_thresh = pm_100ms / 100; | |
563 | unsigned long mult; | |
564 | u64 res; | |
565 | ||
566 | #ifndef CONFIG_X86_PM_TIMER | |
567 | return -1; | |
568 | #endif | |
569 | ||
39ba5d43 | 570 | apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); |
b189892d CG |
571 | |
572 | /* Check, if the PM timer is available */ | |
573 | if (!deltapm) | |
574 | return -1; | |
575 | ||
576 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
577 | ||
578 | if (deltapm > (pm_100ms - pm_thresh) && | |
579 | deltapm < (pm_100ms + pm_thresh)) { | |
39ba5d43 | 580 | apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); |
754ef0cd YI |
581 | return 0; |
582 | } | |
583 | ||
584 | res = (((u64)deltapm) * mult) >> 22; | |
585 | do_div(res, 1000000); | |
586 | pr_warning("APIC calibration not consistent " | |
39ba5d43 | 587 | "with PM-Timer: %ldms instead of 100ms\n",(long)res); |
754ef0cd YI |
588 | |
589 | /* Correct the lapic counter value */ | |
590 | res = (((u64)(*delta)) * pm_100ms); | |
591 | do_div(res, deltapm); | |
592 | pr_info("APIC delta adjusted to PM-Timer: " | |
593 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
594 | *delta = (long)res; | |
595 | ||
596 | /* Correct the tsc counter value */ | |
597 | if (cpu_has_tsc) { | |
598 | res = (((u64)(*deltatsc)) * pm_100ms); | |
b189892d | 599 | do_div(res, deltapm); |
754ef0cd YI |
600 | apic_printk(APIC_VERBOSE, "TSC delta adjusted to " |
601 | "PM-Timer: %lu (%ld) \n", | |
602 | (unsigned long)res, *deltatsc); | |
603 | *deltatsc = (long)res; | |
b189892d CG |
604 | } |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
2f04fa88 YL |
609 | static int __init calibrate_APIC_clock(void) |
610 | { | |
611 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
612 | void (*real_handler)(struct clock_event_device *dev); |
613 | unsigned long deltaj; | |
754ef0cd | 614 | long delta, deltatsc; |
2f04fa88 YL |
615 | int pm_referenced = 0; |
616 | ||
617 | local_irq_disable(); | |
618 | ||
619 | /* Replace the global interrupt handler */ | |
620 | real_handler = global_clock_event->event_handler; | |
621 | global_clock_event->event_handler = lapic_cal_handler; | |
622 | ||
623 | /* | |
81608f3c | 624 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
625 | * can underflow in the 100ms detection time frame |
626 | */ | |
81608f3c | 627 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
628 | |
629 | /* Let the interrupts run */ | |
630 | local_irq_enable(); | |
631 | ||
632 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
633 | cpu_relax(); | |
634 | ||
635 | local_irq_disable(); | |
636 | ||
637 | /* Restore the real event handler */ | |
638 | global_clock_event->event_handler = real_handler; | |
639 | ||
640 | /* Build delta t1-t2 as apic timer counts down */ | |
641 | delta = lapic_cal_t1 - lapic_cal_t2; | |
642 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
643 | ||
754ef0cd YI |
644 | deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); |
645 | ||
b189892d CG |
646 | /* we trust the PM based calibration if possible */ |
647 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
754ef0cd | 648 | &delta, &deltatsc); |
2f04fa88 YL |
649 | |
650 | /* Calculate the scaled math multiplication factor */ | |
651 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
652 | lapic_clockevent.shift); | |
653 | lapic_clockevent.max_delta_ns = | |
654 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
655 | lapic_clockevent.min_delta_ns = | |
656 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
657 | ||
658 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
659 | ||
660 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
661 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
662 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
663 | calibration_result); | |
664 | ||
665 | if (cpu_has_tsc) { | |
2f04fa88 YL |
666 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " |
667 | "%ld.%04ld MHz.\n", | |
754ef0cd YI |
668 | (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), |
669 | (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
2f04fa88 YL |
670 | } |
671 | ||
672 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
673 | "%u.%04u MHz.\n", | |
674 | calibration_result / (1000000 / HZ), | |
675 | calibration_result % (1000000 / HZ)); | |
676 | ||
677 | /* | |
678 | * Do a sanity check on the APIC calibration result | |
679 | */ | |
680 | if (calibration_result < (1000000 / HZ)) { | |
681 | local_irq_enable(); | |
ba21ebb6 | 682 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
683 | return -1; |
684 | } | |
685 | ||
686 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
687 | ||
b189892d CG |
688 | /* |
689 | * PM timer calibration failed or not turned on | |
690 | * so lets try APIC timer based calibration | |
691 | */ | |
2f04fa88 YL |
692 | if (!pm_referenced) { |
693 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
694 | ||
695 | /* | |
696 | * Setup the apic timer manually | |
697 | */ | |
698 | levt->event_handler = lapic_cal_handler; | |
699 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
700 | lapic_cal_loops = -1; | |
701 | ||
702 | /* Let the interrupts run */ | |
703 | local_irq_enable(); | |
704 | ||
705 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
706 | cpu_relax(); | |
707 | ||
2f04fa88 YL |
708 | /* Stop the lapic timer */ |
709 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
710 | ||
2f04fa88 YL |
711 | /* Jiffies delta */ |
712 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
713 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
714 | ||
715 | /* Check, if the jiffies result is consistent */ | |
716 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
717 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
718 | else | |
719 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
720 | } else | |
721 | local_irq_enable(); | |
722 | ||
723 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
e423e33e | 724 | pr_warning("APIC timer disabled due to verification failure\n"); |
2f04fa88 YL |
725 | return -1; |
726 | } | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
e83a5fdc HS |
731 | /* |
732 | * Setup the boot APIC | |
733 | * | |
734 | * Calibrate and verify the result. | |
735 | */ | |
0e078e2f TG |
736 | void __init setup_boot_APIC_clock(void) |
737 | { | |
738 | /* | |
274cfe59 CG |
739 | * The local apic timer can be disabled via the kernel |
740 | * commandline or from the CPU detection code. Register the lapic | |
741 | * timer as a dummy clock event source on SMP systems, so the | |
742 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
743 | */ |
744 | if (disable_apic_timer) { | |
ba21ebb6 | 745 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 746 | /* No broadcast on UP ! */ |
9d09951d TG |
747 | if (num_possible_cpus() > 1) { |
748 | lapic_clockevent.mult = 1; | |
0e078e2f | 749 | setup_APIC_timer(); |
9d09951d | 750 | } |
0e078e2f TG |
751 | return; |
752 | } | |
753 | ||
274cfe59 CG |
754 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
755 | "calibrating APIC timer ...\n"); | |
756 | ||
89b3b1f4 | 757 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
758 | /* No broadcast on UP ! */ |
759 | if (num_possible_cpus() > 1) | |
760 | setup_APIC_timer(); | |
761 | return; | |
762 | } | |
763 | ||
0e078e2f TG |
764 | /* |
765 | * If nmi_watchdog is set to IO_APIC, we need the | |
766 | * PIT/HPET going. Otherwise register lapic as a dummy | |
767 | * device. | |
768 | */ | |
769 | if (nmi_watchdog != NMI_IO_APIC) | |
770 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
771 | else | |
ba21ebb6 | 772 | pr_warning("APIC timer registered as dummy," |
116f570e | 773 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 774 | |
274cfe59 | 775 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
776 | setup_APIC_timer(); |
777 | } | |
778 | ||
0e078e2f TG |
779 | void __cpuinit setup_secondary_APIC_clock(void) |
780 | { | |
0e078e2f TG |
781 | setup_APIC_timer(); |
782 | } | |
783 | ||
784 | /* | |
785 | * The guts of the apic timer interrupt | |
786 | */ | |
787 | static void local_apic_timer_interrupt(void) | |
788 | { | |
789 | int cpu = smp_processor_id(); | |
790 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
791 | ||
792 | /* | |
793 | * Normally we should not be here till LAPIC has been initialized but | |
794 | * in some cases like kdump, its possible that there is a pending LAPIC | |
795 | * timer interrupt from previous kernel's context and is delivered in | |
796 | * new kernel the moment interrupts are enabled. | |
797 | * | |
798 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
799 | * its possible that when we get here evt->event_handler is NULL. | |
800 | * Check for event_handler being NULL and discard the interrupt as | |
801 | * spurious. | |
802 | */ | |
803 | if (!evt->event_handler) { | |
ba21ebb6 | 804 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
805 | /* Switch it off */ |
806 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
807 | return; | |
808 | } | |
809 | ||
810 | /* | |
811 | * the NMI deadlock-detector uses this. | |
812 | */ | |
915b0d01 | 813 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
814 | |
815 | evt->event_handler(evt); | |
816 | } | |
817 | ||
818 | /* | |
819 | * Local APIC timer interrupt. This is the most natural way for doing | |
820 | * local interrupts, but local timer interrupts can be emulated by | |
821 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
822 | * | |
823 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
824 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
825 | */ | |
bcbc4f20 | 826 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
827 | { |
828 | struct pt_regs *old_regs = set_irq_regs(regs); | |
829 | ||
830 | /* | |
831 | * NOTE! We'd better ACK the irq immediately, | |
832 | * because timer handling can be slow. | |
833 | */ | |
834 | ack_APIC_irq(); | |
835 | /* | |
836 | * update_process_times() expects us to have done irq_enter(). | |
837 | * Besides, if we don't timer interrupts ignore the global | |
838 | * interrupt lock, which is the WrongThing (tm) to do. | |
839 | */ | |
840 | exit_idle(); | |
841 | irq_enter(); | |
842 | local_apic_timer_interrupt(); | |
843 | irq_exit(); | |
274cfe59 | 844 | |
0e078e2f TG |
845 | set_irq_regs(old_regs); |
846 | } | |
847 | ||
848 | int setup_profiling_timer(unsigned int multiplier) | |
849 | { | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
0e078e2f TG |
853 | /* |
854 | * Local APIC start and shutdown | |
855 | */ | |
856 | ||
857 | /** | |
858 | * clear_local_APIC - shutdown the local APIC | |
859 | * | |
860 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
861 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
862 | * leftovers during boot. | |
863 | */ | |
864 | void clear_local_APIC(void) | |
865 | { | |
2584a82d | 866 | int maxlvt; |
0e078e2f TG |
867 | u32 v; |
868 | ||
d3432896 AK |
869 | /* APIC hasn't been mapped yet */ |
870 | if (!apic_phys) | |
871 | return; | |
872 | ||
873 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
874 | /* |
875 | * Masking an LVT entry can trigger a local APIC error | |
876 | * if the vector is zero. Mask LVTERR first to prevent this. | |
877 | */ | |
878 | if (maxlvt >= 3) { | |
879 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
880 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
881 | } | |
882 | /* | |
883 | * Careful: we have to set masks only first to deassert | |
884 | * any level-triggered sources. | |
885 | */ | |
886 | v = apic_read(APIC_LVTT); | |
887 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
888 | v = apic_read(APIC_LVT0); | |
889 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
890 | v = apic_read(APIC_LVT1); | |
891 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
892 | if (maxlvt >= 4) { | |
893 | v = apic_read(APIC_LVTPC); | |
894 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
895 | } | |
896 | ||
6764014b CG |
897 | /* lets not touch this if we didn't frob it */ |
898 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
899 | if (maxlvt >= 5) { | |
900 | v = apic_read(APIC_LVTTHMR); | |
901 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
902 | } | |
903 | #endif | |
0e078e2f TG |
904 | /* |
905 | * Clean APIC state for other OSs: | |
906 | */ | |
907 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
908 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
909 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
910 | if (maxlvt >= 3) | |
911 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
912 | if (maxlvt >= 4) | |
913 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
914 | |
915 | /* Integrated APIC (!82489DX) ? */ | |
916 | if (lapic_is_integrated()) { | |
917 | if (maxlvt > 3) | |
918 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
919 | apic_write(APIC_ESR, 0); | |
920 | apic_read(APIC_ESR); | |
921 | } | |
0e078e2f TG |
922 | } |
923 | ||
924 | /** | |
925 | * disable_local_APIC - clear and disable the local APIC | |
926 | */ | |
927 | void disable_local_APIC(void) | |
928 | { | |
929 | unsigned int value; | |
930 | ||
4a13ad0b JB |
931 | /* APIC hasn't been mapped yet */ |
932 | if (!apic_phys) | |
933 | return; | |
934 | ||
0e078e2f TG |
935 | clear_local_APIC(); |
936 | ||
937 | /* | |
938 | * Disable APIC (implies clearing of registers | |
939 | * for 82489DX!). | |
940 | */ | |
941 | value = apic_read(APIC_SPIV); | |
942 | value &= ~APIC_SPIV_APIC_ENABLED; | |
943 | apic_write(APIC_SPIV, value); | |
990b183e CG |
944 | |
945 | #ifdef CONFIG_X86_32 | |
946 | /* | |
947 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
948 | * restore the disabled state. | |
949 | */ | |
950 | if (enabled_via_apicbase) { | |
951 | unsigned int l, h; | |
952 | ||
953 | rdmsr(MSR_IA32_APICBASE, l, h); | |
954 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
955 | wrmsr(MSR_IA32_APICBASE, l, h); | |
956 | } | |
957 | #endif | |
0e078e2f TG |
958 | } |
959 | ||
fe4024dc CG |
960 | /* |
961 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
962 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
963 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
964 | * for the case where Linux didn't enable the LAPIC. | |
965 | */ | |
0e078e2f TG |
966 | void lapic_shutdown(void) |
967 | { | |
968 | unsigned long flags; | |
969 | ||
970 | if (!cpu_has_apic) | |
971 | return; | |
972 | ||
973 | local_irq_save(flags); | |
974 | ||
fe4024dc CG |
975 | #ifdef CONFIG_X86_32 |
976 | if (!enabled_via_apicbase) | |
977 | clear_local_APIC(); | |
978 | else | |
979 | #endif | |
980 | disable_local_APIC(); | |
981 | ||
0e078e2f TG |
982 | |
983 | local_irq_restore(flags); | |
984 | } | |
985 | ||
986 | /* | |
987 | * This is to verify that we're looking at a real local APIC. | |
988 | * Check these against your board if the CPUs aren't getting | |
989 | * started for no apparent reason. | |
990 | */ | |
991 | int __init verify_local_APIC(void) | |
992 | { | |
993 | unsigned int reg0, reg1; | |
994 | ||
995 | /* | |
996 | * The version register is read-only in a real APIC. | |
997 | */ | |
998 | reg0 = apic_read(APIC_LVR); | |
999 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
1000 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
1001 | reg1 = apic_read(APIC_LVR); | |
1002 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
1003 | ||
1004 | /* | |
1005 | * The two version reads above should print the same | |
1006 | * numbers. If the second one is different, then we | |
1007 | * poke at a non-APIC. | |
1008 | */ | |
1009 | if (reg1 != reg0) | |
1010 | return 0; | |
1011 | ||
1012 | /* | |
1013 | * Check if the version looks reasonably. | |
1014 | */ | |
1015 | reg1 = GET_APIC_VERSION(reg0); | |
1016 | if (reg1 == 0x00 || reg1 == 0xff) | |
1017 | return 0; | |
1018 | reg1 = lapic_get_maxlvt(); | |
1019 | if (reg1 < 0x02 || reg1 == 0xff) | |
1020 | return 0; | |
1021 | ||
1022 | /* | |
1023 | * The ID register is read/write in a real APIC. | |
1024 | */ | |
2d7a66d0 | 1025 | reg0 = apic_read(APIC_ID); |
0e078e2f | 1026 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
5b812727 | 1027 | apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); |
2d7a66d0 | 1028 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1029 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1030 | apic_write(APIC_ID, reg0); | |
5b812727 | 1031 | if (reg1 != (reg0 ^ apic->apic_id_mask)) |
0e078e2f TG |
1032 | return 0; |
1033 | ||
1034 | /* | |
1da177e4 LT |
1035 | * The next two are just to see if we have sane values. |
1036 | * They're only really relevant if we're in Virtual Wire | |
1037 | * compatibility mode, but most boxes are anymore. | |
1038 | */ | |
1039 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1040 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1041 | reg1 = apic_read(APIC_LVT1); |
1042 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1043 | ||
1044 | return 1; | |
1045 | } | |
1046 | ||
0e078e2f TG |
1047 | /** |
1048 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1049 | */ | |
1da177e4 LT |
1050 | void __init sync_Arb_IDs(void) |
1051 | { | |
296cb951 CG |
1052 | /* |
1053 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1054 | * needed on AMD. | |
1055 | */ | |
1056 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1057 | return; |
1058 | ||
1059 | /* | |
1060 | * Wait for idle. | |
1061 | */ | |
1062 | apic_wait_icr_idle(); | |
1063 | ||
1064 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1065 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1066 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1067 | } |
1068 | ||
1da177e4 LT |
1069 | /* |
1070 | * An initial setup of the virtual wire mode. | |
1071 | */ | |
1072 | void __init init_bsp_APIC(void) | |
1073 | { | |
11a8e778 | 1074 | unsigned int value; |
1da177e4 LT |
1075 | |
1076 | /* | |
1077 | * Don't do the setup now if we have a SMP BIOS as the | |
1078 | * through-I/O-APIC virtual wire mode might be active. | |
1079 | */ | |
1080 | if (smp_found_config || !cpu_has_apic) | |
1081 | return; | |
1082 | ||
1da177e4 LT |
1083 | /* |
1084 | * Do not trust the local APIC being empty at bootup. | |
1085 | */ | |
1086 | clear_local_APIC(); | |
1087 | ||
1088 | /* | |
1089 | * Enable APIC. | |
1090 | */ | |
1091 | value = apic_read(APIC_SPIV); | |
1092 | value &= ~APIC_VECTOR_MASK; | |
1093 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1094 | |
1095 | #ifdef CONFIG_X86_32 | |
1096 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1097 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1098 | (boot_cpu_data.x86 == 15)) | |
1099 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1100 | else | |
1101 | #endif | |
1102 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1103 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1104 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1105 | |
1106 | /* | |
1107 | * Set up the virtual wire mode. | |
1108 | */ | |
11a8e778 | 1109 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1110 | value = APIC_DM_NMI; |
638c0411 CG |
1111 | if (!lapic_is_integrated()) /* 82489DX */ |
1112 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1113 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1114 | } |
1115 | ||
c43da2f5 CG |
1116 | static void __cpuinit lapic_setup_esr(void) |
1117 | { | |
9df08f10 CG |
1118 | unsigned int oldvalue, value, maxlvt; |
1119 | ||
1120 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1121 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1122 | return; |
1123 | } | |
c43da2f5 | 1124 | |
08125d3e | 1125 | if (apic->disable_esr) { |
c43da2f5 | 1126 | /* |
9df08f10 CG |
1127 | * Something untraceable is creating bad interrupts on |
1128 | * secondary quads ... for the moment, just leave the | |
1129 | * ESR disabled - we can't do anything useful with the | |
1130 | * errors anyway - mbligh | |
c43da2f5 | 1131 | */ |
ba21ebb6 | 1132 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1133 | return; |
c43da2f5 | 1134 | } |
9df08f10 CG |
1135 | |
1136 | maxlvt = lapic_get_maxlvt(); | |
1137 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1138 | apic_write(APIC_ESR, 0); | |
1139 | oldvalue = apic_read(APIC_ESR); | |
1140 | ||
1141 | /* enables sending errors */ | |
1142 | value = ERROR_APIC_VECTOR; | |
1143 | apic_write(APIC_LVTERR, value); | |
1144 | ||
1145 | /* | |
1146 | * spec says clear errors after enabling vector. | |
1147 | */ | |
1148 | if (maxlvt > 3) | |
1149 | apic_write(APIC_ESR, 0); | |
1150 | value = apic_read(APIC_ESR); | |
1151 | if (value != oldvalue) | |
1152 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1153 | "vector: 0x%08x after: 0x%08x\n", | |
1154 | oldvalue, value); | |
c43da2f5 CG |
1155 | } |
1156 | ||
1157 | ||
0e078e2f TG |
1158 | /** |
1159 | * setup_local_APIC - setup the local APIC | |
1160 | */ | |
1161 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1162 | { |
739f33b3 | 1163 | unsigned int value; |
da7ed9f9 | 1164 | int i, j; |
1da177e4 | 1165 | |
f1182638 | 1166 | if (disable_apic) { |
65a4e574 | 1167 | arch_disable_smp_support(); |
f1182638 JB |
1168 | return; |
1169 | } | |
1170 | ||
89c38c28 CG |
1171 | #ifdef CONFIG_X86_32 |
1172 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08125d3e | 1173 | if (lapic_is_integrated() && apic->disable_esr) { |
89c38c28 CG |
1174 | apic_write(APIC_ESR, 0); |
1175 | apic_write(APIC_ESR, 0); | |
1176 | apic_write(APIC_ESR, 0); | |
1177 | apic_write(APIC_ESR, 0); | |
1178 | } | |
1179 | #endif | |
1180 | ||
ac23d4ee | 1181 | preempt_disable(); |
1da177e4 | 1182 | |
1da177e4 LT |
1183 | /* |
1184 | * Double-check whether this APIC is really registered. | |
1185 | * This is meaningless in clustered apic mode, so we skip it. | |
1186 | */ | |
7ed248da | 1187 | if (!apic->apic_id_registered()) |
1da177e4 LT |
1188 | BUG(); |
1189 | ||
1190 | /* | |
1191 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1192 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1193 | * document number 292116). So here it goes... | |
1194 | */ | |
a5c43296 | 1195 | apic->init_apic_ldr(); |
1da177e4 LT |
1196 | |
1197 | /* | |
1198 | * Set Task Priority to 'accept all'. We never change this | |
1199 | * later on. | |
1200 | */ | |
1201 | value = apic_read(APIC_TASKPRI); | |
1202 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1203 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1204 | |
da7ed9f9 VG |
1205 | /* |
1206 | * After a crash, we no longer service the interrupts and a pending | |
1207 | * interrupt from previous kernel might still have ISR bit set. | |
1208 | * | |
1209 | * Most probably by now CPU has serviced that pending interrupt and | |
1210 | * it might not have done the ack_APIC_irq() because it thought, | |
1211 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1212 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1213 | * the interrupt. Hence a vector might get locked. It was noticed | |
1214 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1215 | */ | |
1216 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1217 | value = apic_read(APIC_ISR + i*0x10); | |
1218 | for (j = 31; j >= 0; j--) { | |
1219 | if (value & (1<<j)) | |
1220 | ack_APIC_irq(); | |
1221 | } | |
1222 | } | |
1223 | ||
1da177e4 LT |
1224 | /* |
1225 | * Now that we are all set up, enable the APIC | |
1226 | */ | |
1227 | value = apic_read(APIC_SPIV); | |
1228 | value &= ~APIC_VECTOR_MASK; | |
1229 | /* | |
1230 | * Enable APIC | |
1231 | */ | |
1232 | value |= APIC_SPIV_APIC_ENABLED; | |
1233 | ||
89c38c28 CG |
1234 | #ifdef CONFIG_X86_32 |
1235 | /* | |
1236 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1237 | * certain networking cards. If high frequency interrupts are | |
1238 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1239 | * entry is masked/unmasked at a high rate as well then sooner or | |
1240 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1241 | * from the device. If focus CPU is disabled then the hang goes | |
1242 | * away, oh well :-( | |
1243 | * | |
1244 | * [ This bug can be reproduced easily with a level-triggered | |
1245 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1246 | * BX chipset. ] | |
1247 | */ | |
1248 | /* | |
1249 | * Actually disabling the focus CPU check just makes the hang less | |
1250 | * frequent as it makes the interrupt distributon model be more | |
1251 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1252 | * See also the comment in end_level_ioapic_irq(). --macro | |
1253 | */ | |
1254 | ||
1255 | /* | |
1256 | * - enable focus processor (bit==0) | |
1257 | * - 64bit mode always use processor focus | |
1258 | * so no need to set it | |
1259 | */ | |
1260 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1261 | #endif | |
3f14c746 | 1262 | |
1da177e4 LT |
1263 | /* |
1264 | * Set spurious IRQ vector | |
1265 | */ | |
1266 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1267 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1268 | |
1269 | /* | |
1270 | * Set up LVT0, LVT1: | |
1271 | * | |
1272 | * set up through-local-APIC on the BP's LINT0. This is not | |
1273 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1274 | * we delegate interrupts to the 8259A. | |
1275 | */ | |
1276 | /* | |
1277 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1278 | */ | |
1279 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1280 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1281 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1282 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1283 | smp_processor_id()); |
1da177e4 LT |
1284 | } else { |
1285 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1286 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1287 | smp_processor_id()); |
1da177e4 | 1288 | } |
11a8e778 | 1289 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1290 | |
1291 | /* | |
1292 | * only the BP should see the LINT1 NMI signal, obviously. | |
1293 | */ | |
1294 | if (!smp_processor_id()) | |
1295 | value = APIC_DM_NMI; | |
1296 | else | |
1297 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1298 | if (!lapic_is_integrated()) /* 82489DX */ |
1299 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1300 | apic_write(APIC_LVT1, value); |
89c38c28 | 1301 | |
ac23d4ee | 1302 | preempt_enable(); |
739f33b3 | 1303 | } |
1da177e4 | 1304 | |
739f33b3 AK |
1305 | void __cpuinit end_local_APIC_setup(void) |
1306 | { | |
1307 | lapic_setup_esr(); | |
fa6b95fc CG |
1308 | |
1309 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1310 | { |
1311 | unsigned int value; | |
1312 | /* Disable the local apic timer */ | |
1313 | value = apic_read(APIC_LVTT); | |
1314 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1315 | apic_write(APIC_LVTT, value); | |
1316 | } | |
fa6b95fc CG |
1317 | #endif |
1318 | ||
f2802e7f | 1319 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1320 | apic_pm_activate(); |
1da177e4 | 1321 | } |
1da177e4 | 1322 | |
49899eac | 1323 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1324 | void check_x2apic(void) |
1325 | { | |
1326 | int msr, msr2; | |
1327 | ||
1328 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1329 | ||
1330 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1331 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1332 | x2apic_preenabled = x2apic = 1; |
1333 | apic_ops = &x2apic_ops; | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | void enable_x2apic(void) | |
1338 | { | |
1339 | int msr, msr2; | |
1340 | ||
1341 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1342 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1343 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1344 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1345 | } | |
1346 | } | |
1347 | ||
2236d252 | 1348 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1349 | { |
1350 | #ifdef CONFIG_INTR_REMAP | |
1351 | int ret; | |
1352 | unsigned long flags; | |
1353 | ||
1354 | if (!cpu_has_x2apic) | |
1355 | return; | |
1356 | ||
1357 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1358 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1359 | "because of nox2apic\n"); | |
6e1cb38a SS |
1360 | return; |
1361 | } | |
1362 | ||
1363 | if (x2apic_preenabled && disable_x2apic) | |
1364 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1365 | ||
1366 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1367 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1368 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1369 | return; |
1370 | } | |
1371 | ||
1372 | ret = dmar_table_init(); | |
1373 | if (ret) { | |
ba21ebb6 | 1374 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1375 | |
1376 | if (x2apic_preenabled) | |
1377 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1378 | else | |
ba21ebb6 | 1379 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1380 | return; |
1381 | } | |
1382 | ||
1383 | local_irq_save(flags); | |
1384 | mask_8259A(); | |
5ffa4eb2 CG |
1385 | |
1386 | ret = save_mask_IO_APIC_setup(); | |
1387 | if (ret) { | |
ba21ebb6 | 1388 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1389 | goto end; |
1390 | } | |
6e1cb38a SS |
1391 | |
1392 | ret = enable_intr_remapping(1); | |
1393 | ||
1394 | if (ret && x2apic_preenabled) { | |
1395 | local_irq_restore(flags); | |
1396 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1397 | } | |
1398 | ||
1399 | if (ret) | |
5ffa4eb2 | 1400 | goto end_restore; |
6e1cb38a SS |
1401 | |
1402 | if (!x2apic) { | |
1403 | x2apic = 1; | |
1404 | apic_ops = &x2apic_ops; | |
1405 | enable_x2apic(); | |
1406 | } | |
5ffa4eb2 CG |
1407 | |
1408 | end_restore: | |
6e1cb38a SS |
1409 | if (ret) |
1410 | /* | |
1411 | * IR enabling failed | |
1412 | */ | |
1413 | restore_IO_APIC_setup(); | |
1414 | else | |
1415 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1416 | ||
5ffa4eb2 | 1417 | end: |
6e1cb38a SS |
1418 | unmask_8259A(); |
1419 | local_irq_restore(flags); | |
1420 | ||
1421 | if (!ret) { | |
1422 | if (!x2apic_preenabled) | |
ba21ebb6 | 1423 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1424 | else |
ba21ebb6 | 1425 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1426 | } else |
ba21ebb6 | 1427 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1428 | #else |
1429 | if (!cpu_has_x2apic) | |
1430 | return; | |
1431 | ||
1432 | if (x2apic_preenabled) | |
1433 | panic("x2apic enabled prior OS handover," | |
1434 | " enable CONFIG_INTR_REMAP"); | |
1435 | ||
ba21ebb6 CG |
1436 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1437 | " and x2apic\n"); | |
6e1cb38a SS |
1438 | #endif |
1439 | ||
1440 | return; | |
1441 | } | |
49899eac | 1442 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1443 | |
be7a656f | 1444 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1445 | /* |
1446 | * Detect and enable local APICs on non-SMP boards. | |
1447 | * Original code written by Keir Fraser. | |
1448 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1449 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1450 | */ |
0e078e2f | 1451 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1452 | { |
1453 | if (!cpu_has_apic) { | |
ba21ebb6 | 1454 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1455 | return -1; |
1456 | } | |
1457 | ||
1458 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1459 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1460 | return 0; |
1461 | } | |
be7a656f YL |
1462 | #else |
1463 | /* | |
1464 | * Detect and initialize APIC | |
1465 | */ | |
1466 | static int __init detect_init_APIC(void) | |
1467 | { | |
1468 | u32 h, l, features; | |
1469 | ||
1470 | /* Disabled by kernel option? */ | |
1471 | if (disable_apic) | |
1472 | return -1; | |
1473 | ||
1474 | switch (boot_cpu_data.x86_vendor) { | |
1475 | case X86_VENDOR_AMD: | |
1476 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
85877061 | 1477 | (boot_cpu_data.x86 >= 15)) |
be7a656f YL |
1478 | break; |
1479 | goto no_apic; | |
1480 | case X86_VENDOR_INTEL: | |
1481 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1482 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1483 | break; | |
1484 | goto no_apic; | |
1485 | default: | |
1486 | goto no_apic; | |
1487 | } | |
1488 | ||
1489 | if (!cpu_has_apic) { | |
1490 | /* | |
1491 | * Over-ride BIOS and try to enable the local APIC only if | |
1492 | * "lapic" specified. | |
1493 | */ | |
1494 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1495 | pr_info("Local APIC disabled by BIOS -- " |
1496 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1497 | return -1; |
1498 | } | |
1499 | /* | |
1500 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1501 | * MSR. This can only be done in software for Intel P6 or later | |
1502 | * and AMD K7 (Model > 1) or later. | |
1503 | */ | |
1504 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1505 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1506 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1507 | l &= ~MSR_IA32_APICBASE_BASE; |
1508 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1509 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1510 | enabled_via_apicbase = 1; | |
1511 | } | |
1512 | } | |
1513 | /* | |
1514 | * The APIC feature bit should now be enabled | |
1515 | * in `cpuid' | |
1516 | */ | |
1517 | features = cpuid_edx(1); | |
1518 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1519 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1520 | return -1; |
1521 | } | |
1522 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1523 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1524 | ||
1525 | /* The BIOS may have set up the APIC at some other address */ | |
1526 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1527 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1528 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1529 | ||
ba21ebb6 | 1530 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1531 | |
1532 | apic_pm_activate(); | |
1533 | ||
1534 | return 0; | |
1535 | ||
1536 | no_apic: | |
ba21ebb6 | 1537 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1538 | return -1; |
1539 | } | |
1540 | #endif | |
1da177e4 | 1541 | |
f28c0ae2 | 1542 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1543 | void __init early_init_lapic_mapping(void) |
1544 | { | |
431ee79d | 1545 | unsigned long phys_addr; |
8643f9d0 YL |
1546 | |
1547 | /* | |
1548 | * If no local APIC can be found then go out | |
1549 | * : it means there is no mpatable and MADT | |
1550 | */ | |
1551 | if (!smp_found_config) | |
1552 | return; | |
1553 | ||
431ee79d | 1554 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1555 | |
431ee79d | 1556 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1557 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1558 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1559 | |
1560 | /* | |
1561 | * Fetch the APIC ID of the BSP in case we have a | |
1562 | * default configuration (or the MP table is broken). | |
1563 | */ | |
4c9961d5 | 1564 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1565 | } |
f28c0ae2 | 1566 | #endif |
8643f9d0 | 1567 | |
0e078e2f TG |
1568 | /** |
1569 | * init_apic_mappings - initialize APIC mappings | |
1570 | */ | |
1da177e4 LT |
1571 | void __init init_apic_mappings(void) |
1572 | { | |
49899eac | 1573 | #ifdef HAVE_X2APIC |
6e1cb38a | 1574 | if (x2apic) { |
4c9961d5 | 1575 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1576 | return; |
1577 | } | |
49899eac | 1578 | #endif |
6e1cb38a | 1579 | |
1da177e4 LT |
1580 | /* |
1581 | * If no local APIC can be found then set up a fake all | |
1582 | * zeroes page to simulate the local APIC and another | |
1583 | * one for the IO-APIC. | |
1584 | */ | |
1585 | if (!smp_found_config && detect_init_APIC()) { | |
1586 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1587 | apic_phys = __pa(apic_phys); | |
1588 | } else | |
1589 | apic_phys = mp_lapic_addr; | |
1590 | ||
1591 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1592 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1593 | APIC_BASE, apic_phys); |
1da177e4 LT |
1594 | |
1595 | /* | |
1596 | * Fetch the APIC ID of the BSP in case we have a | |
1597 | * default configuration (or the MP table is broken). | |
1598 | */ | |
f28c0ae2 YL |
1599 | if (boot_cpu_physical_apicid == -1U) |
1600 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1601 | } |
1602 | ||
1603 | /* | |
0e078e2f TG |
1604 | * This initializes the IO-APIC and APIC hardware if this is |
1605 | * a UP kernel. | |
1da177e4 | 1606 | */ |
1b313f4a CG |
1607 | int apic_version[MAX_APICS]; |
1608 | ||
0e078e2f | 1609 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1610 | { |
0e078e2f | 1611 | if (disable_apic) { |
ba21ebb6 | 1612 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1613 | return -1; |
1614 | } | |
f1182638 | 1615 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1616 | if (!cpu_has_apic) { |
1617 | disable_apic = 1; | |
ba21ebb6 | 1618 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1619 | return -1; |
1620 | } | |
fa2bd35a YL |
1621 | #else |
1622 | if (!smp_found_config && !cpu_has_apic) | |
1623 | return -1; | |
1624 | ||
1625 | /* | |
1626 | * Complain if the BIOS pretends there is one. | |
1627 | */ | |
1628 | if (!cpu_has_apic && | |
1629 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1630 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1631 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1632 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1633 | return -1; | |
1634 | } | |
1635 | #endif | |
1636 | ||
49899eac | 1637 | #ifdef HAVE_X2APIC |
6e1cb38a | 1638 | enable_IR_x2apic(); |
49899eac | 1639 | #endif |
fa2bd35a | 1640 | #ifdef CONFIG_X86_64 |
72ce0165 | 1641 | default_setup_apic_routing(); |
fa2bd35a | 1642 | #endif |
6e1cb38a | 1643 | |
0e078e2f | 1644 | verify_local_APIC(); |
b5841765 GC |
1645 | connect_bsp_APIC(); |
1646 | ||
fa2bd35a | 1647 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1648 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1649 | #else |
1650 | /* | |
1651 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1652 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1653 | * might be zero if read from MP tables. Get it from LAPIC. | |
1654 | */ | |
1655 | # ifdef CONFIG_CRASH_DUMP | |
1656 | boot_cpu_physical_apicid = read_apic_id(); | |
1657 | # endif | |
1658 | #endif | |
1659 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1660 | setup_local_APIC(); |
1da177e4 | 1661 | |
88d0f550 | 1662 | #ifdef CONFIG_X86_IO_APIC |
739f33b3 AK |
1663 | /* |
1664 | * Now enable IO-APICs, actually call clear_IO_APIC | |
98c061b6 | 1665 | * We need clear_IO_APIC before enabling error vector |
739f33b3 AK |
1666 | */ |
1667 | if (!skip_ioapic_setup && nr_ioapics) | |
1668 | enable_IO_APIC(); | |
fa2bd35a | 1669 | #endif |
739f33b3 AK |
1670 | |
1671 | end_local_APIC_setup(); | |
1672 | ||
fa2bd35a | 1673 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1674 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1675 | setup_IO_APIC(); | |
98c061b6 | 1676 | else { |
0e078e2f | 1677 | nr_ioapics = 0; |
98c061b6 YL |
1678 | localise_nmi_watchdog(); |
1679 | } | |
1680 | #else | |
1681 | localise_nmi_watchdog(); | |
fa2bd35a YL |
1682 | #endif |
1683 | ||
98c061b6 | 1684 | setup_boot_clock(); |
fa2bd35a | 1685 | #ifdef CONFIG_X86_64 |
0e078e2f | 1686 | check_nmi_watchdog(); |
fa2bd35a YL |
1687 | #endif |
1688 | ||
0e078e2f | 1689 | return 0; |
1da177e4 LT |
1690 | } |
1691 | ||
1692 | /* | |
0e078e2f | 1693 | * Local APIC interrupts |
1da177e4 LT |
1694 | */ |
1695 | ||
0e078e2f TG |
1696 | /* |
1697 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1698 | */ | |
dc1528dd | 1699 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1700 | { |
dc1528dd YL |
1701 | u32 v; |
1702 | ||
0e078e2f TG |
1703 | exit_idle(); |
1704 | irq_enter(); | |
1da177e4 | 1705 | /* |
0e078e2f TG |
1706 | * Check if this really is a spurious interrupt and ACK it |
1707 | * if it is a vectored one. Just in case... | |
1708 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1709 | */ |
0e078e2f TG |
1710 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1711 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1712 | ack_APIC_irq(); | |
c4d58cbd | 1713 | |
915b0d01 HS |
1714 | inc_irq_stat(irq_spurious_count); |
1715 | ||
dc1528dd | 1716 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1717 | pr_info("spurious APIC interrupt on CPU#%d, " |
1718 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1719 | irq_exit(); |
1720 | } | |
1da177e4 | 1721 | |
0e078e2f TG |
1722 | /* |
1723 | * This interrupt should never happen with our APIC/SMP architecture | |
1724 | */ | |
dc1528dd | 1725 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1726 | { |
dc1528dd | 1727 | u32 v, v1; |
1da177e4 | 1728 | |
0e078e2f TG |
1729 | exit_idle(); |
1730 | irq_enter(); | |
1731 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1732 | v = apic_read(APIC_ESR); | |
1733 | apic_write(APIC_ESR, 0); | |
1734 | v1 = apic_read(APIC_ESR); | |
1735 | ack_APIC_irq(); | |
1736 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1737 | |
ba21ebb6 CG |
1738 | /* |
1739 | * Here is what the APIC error bits mean: | |
1740 | * 0: Send CS error | |
1741 | * 1: Receive CS error | |
1742 | * 2: Send accept error | |
1743 | * 3: Receive accept error | |
1744 | * 4: Reserved | |
1745 | * 5: Send illegal vector | |
1746 | * 6: Received illegal vector | |
1747 | * 7: Illegal register address | |
1748 | */ | |
1749 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1750 | smp_processor_id(), v , v1); |
1751 | irq_exit(); | |
1da177e4 LT |
1752 | } |
1753 | ||
b5841765 | 1754 | /** |
36c9d674 CG |
1755 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1756 | */ | |
b5841765 GC |
1757 | void __init connect_bsp_APIC(void) |
1758 | { | |
36c9d674 CG |
1759 | #ifdef CONFIG_X86_32 |
1760 | if (pic_mode) { | |
1761 | /* | |
1762 | * Do not trust the local APIC being empty at bootup. | |
1763 | */ | |
1764 | clear_local_APIC(); | |
1765 | /* | |
1766 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1767 | * local APIC to INT and NMI lines. | |
1768 | */ | |
1769 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1770 | "enabling APIC mode.\n"); | |
1771 | outb(0x70, 0x22); | |
1772 | outb(0x01, 0x23); | |
1773 | } | |
1774 | #endif | |
49040333 IM |
1775 | if (apic->enable_apic_mode) |
1776 | apic->enable_apic_mode(); | |
b5841765 GC |
1777 | } |
1778 | ||
274cfe59 CG |
1779 | /** |
1780 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1781 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1782 | * | |
1783 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1784 | * APIC is disabled. | |
1785 | */ | |
0e078e2f | 1786 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1787 | { |
1b4ee4e4 CG |
1788 | unsigned int value; |
1789 | ||
c177b0bc CG |
1790 | #ifdef CONFIG_X86_32 |
1791 | if (pic_mode) { | |
1792 | /* | |
1793 | * Put the board back into PIC mode (has an effect only on | |
1794 | * certain older boards). Note that APIC interrupts, including | |
1795 | * IPIs, won't work beyond this point! The only exception are | |
1796 | * INIT IPIs. | |
1797 | */ | |
1798 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1799 | "entering PIC mode.\n"); | |
1800 | outb(0x70, 0x22); | |
1801 | outb(0x00, 0x23); | |
1802 | return; | |
1803 | } | |
1804 | #endif | |
1805 | ||
0e078e2f | 1806 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1807 | |
0e078e2f TG |
1808 | /* For the spurious interrupt use vector F, and enable it */ |
1809 | value = apic_read(APIC_SPIV); | |
1810 | value &= ~APIC_VECTOR_MASK; | |
1811 | value |= APIC_SPIV_APIC_ENABLED; | |
1812 | value |= 0xf; | |
1813 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1814 | |
0e078e2f TG |
1815 | if (!virt_wire_setup) { |
1816 | /* | |
1817 | * For LVT0 make it edge triggered, active high, | |
1818 | * external and enabled | |
1819 | */ | |
1820 | value = apic_read(APIC_LVT0); | |
1821 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1822 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1823 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1824 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1825 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1826 | apic_write(APIC_LVT0, value); | |
1827 | } else { | |
1828 | /* Disable LVT0 */ | |
1829 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1830 | } | |
b8ce3359 | 1831 | |
c177b0bc CG |
1832 | /* |
1833 | * For LVT1 make it edge triggered, active high, | |
1834 | * nmi and enabled | |
1835 | */ | |
0e078e2f TG |
1836 | value = apic_read(APIC_LVT1); |
1837 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1838 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1839 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1840 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1841 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1842 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1843 | } |
1844 | ||
be8a5685 AS |
1845 | void __cpuinit generic_processor_info(int apicid, int version) |
1846 | { | |
1847 | int cpu; | |
be8a5685 | 1848 | |
1b313f4a CG |
1849 | /* |
1850 | * Validate version | |
1851 | */ | |
1852 | if (version == 0x0) { | |
ba21ebb6 | 1853 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1854 | "fixing up to 0x10. (tell your hw vendor)\n", |
1855 | version); | |
1b313f4a | 1856 | version = 0x10; |
be8a5685 | 1857 | } |
1b313f4a | 1858 | apic_version[apicid] = version; |
be8a5685 | 1859 | |
3b11ce7f MT |
1860 | if (num_processors >= nr_cpu_ids) { |
1861 | int max = nr_cpu_ids; | |
1862 | int thiscpu = max + disabled_cpus; | |
1863 | ||
1864 | pr_warning( | |
1865 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1866 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1867 | ||
1868 | disabled_cpus++; | |
be8a5685 AS |
1869 | return; |
1870 | } | |
1871 | ||
1872 | num_processors++; | |
3b11ce7f | 1873 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 | 1874 | |
b2b815d8 MT |
1875 | if (version != apic_version[boot_cpu_physical_apicid]) |
1876 | WARN_ONCE(1, | |
1877 | "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", | |
1878 | apic_version[boot_cpu_physical_apicid], cpu, version); | |
1879 | ||
be8a5685 AS |
1880 | physid_set(apicid, phys_cpu_present_map); |
1881 | if (apicid == boot_cpu_physical_apicid) { | |
1882 | /* | |
1883 | * x86_bios_cpu_apicid is required to have processors listed | |
1884 | * in same order as logical cpu numbers. Hence the first | |
1885 | * entry is BSP, and so on. | |
1886 | */ | |
1887 | cpu = 0; | |
1888 | } | |
e0da3364 YL |
1889 | if (apicid > max_physical_apicid) |
1890 | max_physical_apicid = apicid; | |
1891 | ||
1b313f4a CG |
1892 | #ifdef CONFIG_X86_32 |
1893 | /* | |
1894 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1895 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1896 | * before this can be done without some confusion. | |
1897 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1898 | * - Ashok Raj <ashok.raj@intel.com> | |
1899 | */ | |
1900 | if (max_physical_apicid >= 8) { | |
1901 | switch (boot_cpu_data.x86_vendor) { | |
1902 | case X86_VENDOR_INTEL: | |
1903 | if (!APIC_XAPIC(version)) { | |
1904 | def_to_bigsmp = 0; | |
1905 | break; | |
1906 | } | |
1907 | /* If P4 and above fall through */ | |
1908 | case X86_VENDOR_AMD: | |
1909 | def_to_bigsmp = 1; | |
1910 | } | |
1911 | } | |
1912 | #endif | |
1913 | ||
3e5095d1 | 1914 | #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) |
f10fcd47 TH |
1915 | early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; |
1916 | early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1b313f4a | 1917 | #endif |
be8a5685 | 1918 | |
1de88cd4 MT |
1919 | set_cpu_possible(cpu, true); |
1920 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1921 | } |
1922 | ||
0c81c746 SS |
1923 | int hard_smp_processor_id(void) |
1924 | { | |
1925 | return read_apic_id(); | |
1926 | } | |
1dcdd3d1 IM |
1927 | |
1928 | void default_init_apic_ldr(void) | |
1929 | { | |
1930 | unsigned long val; | |
1931 | ||
1932 | apic_write(APIC_DFR, APIC_DFR_VALUE); | |
1933 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
1934 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
1935 | apic_write(APIC_LDR, val); | |
1936 | } | |
1937 | ||
1938 | #ifdef CONFIG_X86_32 | |
1939 | int default_apicid_to_node(int logical_apicid) | |
1940 | { | |
1941 | #ifdef CONFIG_SMP | |
1942 | return apicid_2_node[hard_smp_processor_id()]; | |
1943 | #else | |
1944 | return 0; | |
1945 | #endif | |
1946 | } | |
3491998d | 1947 | #endif |
0c81c746 | 1948 | |
89039b37 | 1949 | /* |
0e078e2f | 1950 | * Power management |
89039b37 | 1951 | */ |
0e078e2f TG |
1952 | #ifdef CONFIG_PM |
1953 | ||
1954 | static struct { | |
274cfe59 CG |
1955 | /* |
1956 | * 'active' is true if the local APIC was enabled by us and | |
1957 | * not the BIOS; this signifies that we are also responsible | |
1958 | * for disabling it before entering apm/acpi suspend | |
1959 | */ | |
0e078e2f TG |
1960 | int active; |
1961 | /* r/w apic fields */ | |
1962 | unsigned int apic_id; | |
1963 | unsigned int apic_taskpri; | |
1964 | unsigned int apic_ldr; | |
1965 | unsigned int apic_dfr; | |
1966 | unsigned int apic_spiv; | |
1967 | unsigned int apic_lvtt; | |
1968 | unsigned int apic_lvtpc; | |
1969 | unsigned int apic_lvt0; | |
1970 | unsigned int apic_lvt1; | |
1971 | unsigned int apic_lvterr; | |
1972 | unsigned int apic_tmict; | |
1973 | unsigned int apic_tdcr; | |
1974 | unsigned int apic_thmr; | |
1975 | } apic_pm_state; | |
1976 | ||
1977 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1978 | { | |
1979 | unsigned long flags; | |
1980 | int maxlvt; | |
89039b37 | 1981 | |
0e078e2f TG |
1982 | if (!apic_pm_state.active) |
1983 | return 0; | |
89039b37 | 1984 | |
0e078e2f | 1985 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1986 | |
2d7a66d0 | 1987 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1988 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1989 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1990 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1991 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1992 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1993 | if (maxlvt >= 4) | |
1994 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1995 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1996 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1997 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1998 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1999 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 2000 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2001 | if (maxlvt >= 5) |
2002 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
2003 | #endif | |
24968cfd | 2004 | |
0e078e2f TG |
2005 | local_irq_save(flags); |
2006 | disable_local_APIC(); | |
2007 | local_irq_restore(flags); | |
2008 | return 0; | |
1da177e4 LT |
2009 | } |
2010 | ||
0e078e2f | 2011 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 2012 | { |
0e078e2f TG |
2013 | unsigned int l, h; |
2014 | unsigned long flags; | |
2015 | int maxlvt; | |
1da177e4 | 2016 | |
0e078e2f TG |
2017 | if (!apic_pm_state.active) |
2018 | return 0; | |
89b831ef | 2019 | |
0e078e2f | 2020 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 2021 | |
0e078e2f | 2022 | local_irq_save(flags); |
92206c90 | 2023 | |
49899eac | 2024 | #ifdef HAVE_X2APIC |
92206c90 CG |
2025 | if (x2apic) |
2026 | enable_x2apic(); | |
2027 | else | |
2028 | #endif | |
d5e629a6 | 2029 | { |
92206c90 CG |
2030 | /* |
2031 | * Make sure the APICBASE points to the right address | |
2032 | * | |
2033 | * FIXME! This will be wrong if we ever support suspend on | |
2034 | * SMP! We'll need to do this as part of the CPU restore! | |
2035 | */ | |
6e1cb38a SS |
2036 | rdmsr(MSR_IA32_APICBASE, l, h); |
2037 | l &= ~MSR_IA32_APICBASE_BASE; | |
2038 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2039 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2040 | } |
6e1cb38a | 2041 | |
0e078e2f TG |
2042 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2043 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2044 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2045 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2046 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2047 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2048 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2049 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2050 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2051 | if (maxlvt >= 5) |
2052 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2053 | #endif | |
2054 | if (maxlvt >= 4) | |
2055 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2056 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2057 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2058 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2059 | apic_write(APIC_ESR, 0); | |
2060 | apic_read(APIC_ESR); | |
2061 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2062 | apic_write(APIC_ESR, 0); | |
2063 | apic_read(APIC_ESR); | |
92206c90 | 2064 | |
0e078e2f | 2065 | local_irq_restore(flags); |
92206c90 | 2066 | |
0e078e2f TG |
2067 | return 0; |
2068 | } | |
b8ce3359 | 2069 | |
274cfe59 CG |
2070 | /* |
2071 | * This device has no shutdown method - fully functioning local APICs | |
2072 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2073 | */ | |
2074 | ||
0e078e2f TG |
2075 | static struct sysdev_class lapic_sysclass = { |
2076 | .name = "lapic", | |
2077 | .resume = lapic_resume, | |
2078 | .suspend = lapic_suspend, | |
2079 | }; | |
b8ce3359 | 2080 | |
0e078e2f | 2081 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2082 | .id = 0, |
2083 | .cls = &lapic_sysclass, | |
0e078e2f | 2084 | }; |
b8ce3359 | 2085 | |
0e078e2f TG |
2086 | static void __cpuinit apic_pm_activate(void) |
2087 | { | |
2088 | apic_pm_state.active = 1; | |
1da177e4 LT |
2089 | } |
2090 | ||
0e078e2f | 2091 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2092 | { |
0e078e2f | 2093 | int error; |
e83a5fdc | 2094 | |
0e078e2f TG |
2095 | if (!cpu_has_apic) |
2096 | return 0; | |
2097 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2098 | |
0e078e2f TG |
2099 | error = sysdev_class_register(&lapic_sysclass); |
2100 | if (!error) | |
2101 | error = sysdev_register(&device_lapic); | |
2102 | return error; | |
1da177e4 | 2103 | } |
0e078e2f TG |
2104 | device_initcall(init_lapic_sysfs); |
2105 | ||
2106 | #else /* CONFIG_PM */ | |
2107 | ||
2108 | static void apic_pm_activate(void) { } | |
2109 | ||
2110 | #endif /* CONFIG_PM */ | |
1da177e4 | 2111 | |
f28c0ae2 | 2112 | #ifdef CONFIG_X86_64 |
1da177e4 | 2113 | /* |
f8bf3c65 | 2114 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2115 | * |
2116 | * Thus far, the major user of this is IBM's Summit2 series: | |
2117 | * | |
637029c6 | 2118 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2119 | * multi-chassis. Use available data to take a good guess. |
2120 | * If in doubt, go HPET. | |
2121 | */ | |
f8bf3c65 | 2122 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2123 | { |
2124 | int i, clusters, zeros; | |
2125 | unsigned id; | |
322850af | 2126 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2127 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2128 | ||
322850af YL |
2129 | /* |
2130 | * there is not this kind of box with AMD CPU yet. | |
2131 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2132 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2133 | * vsmp box still need checking... |
322850af | 2134 | */ |
1cb68487 | 2135 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2136 | return 0; |
2137 | ||
23ca4bba | 2138 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2139 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2140 | |
168ef543 | 2141 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2142 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2143 | if (bios_cpu_apicid) { |
2144 | id = bios_cpu_apicid[i]; | |
e423e33e | 2145 | } else if (i < nr_cpu_ids) { |
e8c10ef9 | 2146 | if (cpu_present(i)) |
2147 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2148 | else | |
2149 | continue; | |
e423e33e | 2150 | } else |
e8c10ef9 | 2151 | break; |
2152 | ||
1da177e4 LT |
2153 | if (id != BAD_APICID) |
2154 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2155 | } | |
2156 | ||
2157 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2158 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2159 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2160 | * Since clusters are allocated sequentially, count zeros only if | |
2161 | * they are bounded by ones. | |
1da177e4 LT |
2162 | */ |
2163 | clusters = 0; | |
2164 | zeros = 0; | |
2165 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2166 | if (test_bit(i, clustermap)) { | |
2167 | clusters += 1 + zeros; | |
2168 | zeros = 0; | |
2169 | } else | |
2170 | ++zeros; | |
2171 | } | |
2172 | ||
1cb68487 RT |
2173 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2174 | * not guaranteed to be synced between boards | |
2175 | */ | |
2176 | if (is_vsmp_box() && clusters > 1) | |
2177 | return 1; | |
2178 | ||
1da177e4 | 2179 | /* |
f8bf3c65 | 2180 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2181 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2182 | * out, but AFAIK this will work even for them. | |
2183 | */ | |
2184 | return (clusters > 2); | |
2185 | } | |
f28c0ae2 | 2186 | #endif |
1da177e4 LT |
2187 | |
2188 | /* | |
0e078e2f | 2189 | * APIC command line parameters |
1da177e4 | 2190 | */ |
789fa735 | 2191 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2192 | { |
1da177e4 | 2193 | disable_apic = 1; |
9175fc06 | 2194 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2195 | return 0; |
2196 | } | |
2197 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2198 | |
2c8c0e6b | 2199 | /* same as disableapic, for compatibility */ |
789fa735 | 2200 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2201 | { |
789fa735 | 2202 | return setup_disableapic(arg); |
6935d1f9 | 2203 | } |
2c8c0e6b | 2204 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2205 | |
2e7c2838 LT |
2206 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2207 | { | |
2208 | local_apic_timer_c2_ok = 1; | |
2209 | return 0; | |
2210 | } | |
2211 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2212 | ||
36fef094 | 2213 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2214 | { |
1da177e4 | 2215 | disable_apic_timer = 1; |
36fef094 | 2216 | return 0; |
6935d1f9 | 2217 | } |
36fef094 CG |
2218 | early_param("noapictimer", parse_disable_apic_timer); |
2219 | ||
2220 | static int __init parse_nolapic_timer(char *arg) | |
2221 | { | |
2222 | disable_apic_timer = 1; | |
2223 | return 0; | |
6935d1f9 | 2224 | } |
36fef094 | 2225 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2226 | |
79af9bec CG |
2227 | static int __init apic_set_verbosity(char *arg) |
2228 | { | |
2229 | if (!arg) { | |
2230 | #ifdef CONFIG_X86_64 | |
2231 | skip_ioapic_setup = 0; | |
79af9bec CG |
2232 | return 0; |
2233 | #endif | |
2234 | return -EINVAL; | |
2235 | } | |
2236 | ||
2237 | if (strcmp("debug", arg) == 0) | |
2238 | apic_verbosity = APIC_DEBUG; | |
2239 | else if (strcmp("verbose", arg) == 0) | |
2240 | apic_verbosity = APIC_VERBOSE; | |
2241 | else { | |
ba21ebb6 | 2242 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2243 | " use apic=verbose or apic=debug\n", arg); |
2244 | return -EINVAL; | |
2245 | } | |
2246 | ||
2247 | return 0; | |
2248 | } | |
2249 | early_param("apic", apic_set_verbosity); | |
2250 | ||
1e934dda YL |
2251 | static int __init lapic_insert_resource(void) |
2252 | { | |
2253 | if (!apic_phys) | |
2254 | return -1; | |
2255 | ||
2256 | /* Put local APIC into the resource map. */ | |
2257 | lapic_resource.start = apic_phys; | |
2258 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2259 | insert_resource(&iomem_resource, &lapic_resource); | |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
2264 | /* | |
2265 | * need call insert after e820_reserve_resources() | |
2266 | * that is using request_resource | |
2267 | */ | |
2268 | late_initcall(lapic_insert_resource); |