Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
1da177e4 LT |
33 | |
34 | #include <asm/atomic.h> | |
35 | #include <asm/smp.h> | |
36 | #include <asm/mtrr.h> | |
37 | #include <asm/mpspec.h> | |
efa2559f | 38 | #include <asm/desc.h> |
773763df | 39 | #include <asm/arch_hooks.h> |
e83a5fdc | 40 | #include <asm/hpet.h> |
1da177e4 | 41 | #include <asm/pgalloc.h> |
773763df | 42 | #include <asm/i8253.h> |
75152114 | 43 | #include <asm/nmi.h> |
95833c83 | 44 | #include <asm/idle.h> |
73dea47f AK |
45 | #include <asm/proto.h> |
46 | #include <asm/timex.h> | |
2c8c0e6b | 47 | #include <asm/apic.h> |
6e1cb38a | 48 | #include <asm/i8259.h> |
1da177e4 | 49 | |
dd46e3ca | 50 | #include <mach_apic.h> |
773763df YL |
51 | #include <mach_apicdef.h> |
52 | #include <mach_ipi.h> | |
5af5573e | 53 | |
80e5609c CG |
54 | /* |
55 | * Sanity check | |
56 | */ | |
57 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
58 | # error SPURIOUS_APIC_VECTOR definition error | |
59 | #endif | |
60 | ||
b3c51170 YL |
61 | #ifdef CONFIG_X86_32 |
62 | /* | |
63 | * Knob to control our willingness to enable the local APIC. | |
64 | * | |
65 | * +1=force-enable | |
66 | */ | |
67 | static int force_enable_local_apic; | |
68 | /* | |
69 | * APIC command line parameters | |
70 | */ | |
71 | static int __init parse_lapic(char *arg) | |
72 | { | |
73 | force_enable_local_apic = 1; | |
74 | return 0; | |
75 | } | |
76 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
77 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
78 | static int enabled_via_apicbase; | |
79 | ||
b3c51170 YL |
80 | #endif |
81 | ||
82 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 83 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
84 | static __init int setup_apicpmtimer(char *s) |
85 | { | |
86 | apic_calibrate_pmtmr = 1; | |
87 | notsc_setup(NULL); | |
88 | return 0; | |
89 | } | |
90 | __setup("apicpmtimer", setup_apicpmtimer); | |
91 | #endif | |
92 | ||
49899eac YL |
93 | #ifdef CONFIG_X86_64 |
94 | #define HAVE_X2APIC | |
95 | #endif | |
96 | ||
97 | #ifdef HAVE_X2APIC | |
89027d35 | 98 | int x2apic; |
6e1cb38a SS |
99 | /* x2apic enabled before OS handover */ |
100 | int x2apic_preenabled; | |
49899eac YL |
101 | int disable_x2apic; |
102 | static __init int setup_nox2apic(char *str) | |
103 | { | |
104 | disable_x2apic = 1; | |
105 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
106 | return 0; | |
107 | } | |
108 | early_param("nox2apic", setup_nox2apic); | |
109 | #endif | |
1da177e4 | 110 | |
b3c51170 YL |
111 | unsigned long mp_lapic_addr; |
112 | int disable_apic; | |
113 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
114 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 115 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
116 | int local_apic_timer_c2_ok; |
117 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
118 | ||
efa2559f YL |
119 | int first_system_vector = 0xfe; |
120 | ||
121 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
122 | ||
e83a5fdc HS |
123 | /* |
124 | * Debug level, exported for io_apic.c | |
125 | */ | |
baa13188 | 126 | unsigned int apic_verbosity; |
e83a5fdc | 127 | |
89c38c28 CG |
128 | int pic_mode; |
129 | ||
bab4b27c AS |
130 | /* Have we found an MP table */ |
131 | int smp_found_config; | |
132 | ||
39928722 AD |
133 | static struct resource lapic_resource = { |
134 | .name = "Local APIC", | |
135 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
136 | }; | |
137 | ||
d03030e9 TG |
138 | static unsigned int calibration_result; |
139 | ||
ba7eda4c TG |
140 | static int lapic_next_event(unsigned long delta, |
141 | struct clock_event_device *evt); | |
142 | static void lapic_timer_setup(enum clock_event_mode mode, | |
143 | struct clock_event_device *evt); | |
ba7eda4c | 144 | static void lapic_timer_broadcast(cpumask_t mask); |
0e078e2f | 145 | static void apic_pm_activate(void); |
ba7eda4c | 146 | |
274cfe59 CG |
147 | /* |
148 | * The local apic timer can be used for any function which is CPU local. | |
149 | */ | |
ba7eda4c TG |
150 | static struct clock_event_device lapic_clockevent = { |
151 | .name = "lapic", | |
152 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
153 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
154 | .shift = 32, | |
155 | .set_mode = lapic_timer_setup, | |
156 | .set_next_event = lapic_next_event, | |
157 | .broadcast = lapic_timer_broadcast, | |
158 | .rating = 100, | |
159 | .irq = -1, | |
160 | }; | |
161 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
162 | ||
d3432896 AK |
163 | static unsigned long apic_phys; |
164 | ||
0e078e2f TG |
165 | /* |
166 | * Get the LAPIC version | |
167 | */ | |
168 | static inline int lapic_get_version(void) | |
ba7eda4c | 169 | { |
0e078e2f | 170 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
171 | } |
172 | ||
0e078e2f | 173 | /* |
9c803869 | 174 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
175 | */ |
176 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 177 | { |
9c803869 | 178 | #ifdef CONFIG_X86_64 |
0e078e2f | 179 | return 1; |
9c803869 CG |
180 | #else |
181 | return APIC_INTEGRATED(lapic_get_version()); | |
182 | #endif | |
ba7eda4c TG |
183 | } |
184 | ||
185 | /* | |
0e078e2f | 186 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 187 | */ |
0e078e2f | 188 | static int modern_apic(void) |
ba7eda4c | 189 | { |
0e078e2f TG |
190 | /* AMD systems use old APIC versions, so check the CPU */ |
191 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
192 | boot_cpu_data.x86 >= 0xf) | |
193 | return 1; | |
194 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
195 | } |
196 | ||
274cfe59 CG |
197 | /* |
198 | * Paravirt kernels also might be using these below ops. So we still | |
199 | * use generic apic_read()/apic_write(), which might be pointing to different | |
200 | * ops in PARAVIRT case. | |
201 | */ | |
1b374e4d | 202 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
203 | { |
204 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
205 | cpu_relax(); | |
206 | } | |
207 | ||
1b374e4d | 208 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 209 | { |
3c6bb07a | 210 | u32 send_status; |
8339e9fb FLV |
211 | int timeout; |
212 | ||
213 | timeout = 0; | |
214 | do { | |
215 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
216 | if (!send_status) | |
217 | break; | |
218 | udelay(100); | |
219 | } while (timeout++ < 1000); | |
220 | ||
221 | return send_status; | |
222 | } | |
223 | ||
1b374e4d SS |
224 | void xapic_icr_write(u32 low, u32 id) |
225 | { | |
ed4e5ec1 | 226 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
227 | apic_write(APIC_ICR, low); |
228 | } | |
229 | ||
230 | u64 xapic_icr_read(void) | |
231 | { | |
232 | u32 icr1, icr2; | |
233 | ||
234 | icr2 = apic_read(APIC_ICR2); | |
235 | icr1 = apic_read(APIC_ICR); | |
236 | ||
cf9768d7 | 237 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
238 | } |
239 | ||
240 | static struct apic_ops xapic_ops = { | |
241 | .read = native_apic_mem_read, | |
242 | .write = native_apic_mem_write, | |
1b374e4d SS |
243 | .icr_read = xapic_icr_read, |
244 | .icr_write = xapic_icr_write, | |
245 | .wait_icr_idle = xapic_wait_icr_idle, | |
246 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
247 | }; | |
248 | ||
249 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
250 | EXPORT_SYMBOL_GPL(apic_ops); |
251 | ||
49899eac | 252 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
253 | static void x2apic_wait_icr_idle(void) |
254 | { | |
255 | /* no need to wait for icr idle in x2apic */ | |
256 | return; | |
257 | } | |
258 | ||
259 | static u32 safe_x2apic_wait_icr_idle(void) | |
260 | { | |
261 | /* no need to wait for icr idle in x2apic */ | |
262 | return 0; | |
263 | } | |
264 | ||
265 | void x2apic_icr_write(u32 low, u32 id) | |
266 | { | |
267 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
268 | } | |
269 | ||
270 | u64 x2apic_icr_read(void) | |
271 | { | |
272 | unsigned long val; | |
273 | ||
274 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
275 | return val; | |
276 | } | |
277 | ||
278 | static struct apic_ops x2apic_ops = { | |
279 | .read = native_apic_msr_read, | |
280 | .write = native_apic_msr_write, | |
13c88fb5 SS |
281 | .icr_read = x2apic_icr_read, |
282 | .icr_write = x2apic_icr_write, | |
283 | .wait_icr_idle = x2apic_wait_icr_idle, | |
284 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
285 | }; | |
49899eac | 286 | #endif |
13c88fb5 | 287 | |
0e078e2f TG |
288 | /** |
289 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
290 | */ | |
e9427101 | 291 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 292 | { |
11a8e778 | 293 | unsigned int v; |
6935d1f9 TG |
294 | |
295 | /* unmask and set to NMI */ | |
296 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
297 | |
298 | /* Level triggered for 82489DX (32bit mode) */ | |
299 | if (!lapic_is_integrated()) | |
300 | v |= APIC_LVT_LEVEL_TRIGGER; | |
301 | ||
11a8e778 | 302 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
303 | } |
304 | ||
7c37e48b CG |
305 | #ifdef CONFIG_X86_32 |
306 | /** | |
307 | * get_physical_broadcast - Get number of physical broadcast IDs | |
308 | */ | |
309 | int get_physical_broadcast(void) | |
310 | { | |
311 | return modern_apic() ? 0xff : 0xf; | |
312 | } | |
313 | #endif | |
314 | ||
0e078e2f TG |
315 | /** |
316 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
317 | */ | |
37e650c7 | 318 | int lapic_get_maxlvt(void) |
1da177e4 | 319 | { |
36a028de | 320 | unsigned int v; |
1da177e4 LT |
321 | |
322 | v = apic_read(APIC_LVR); | |
36a028de CG |
323 | /* |
324 | * - we always have APIC integrated on 64bit mode | |
325 | * - 82489DXs do not report # of LVT entries | |
326 | */ | |
327 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
328 | } |
329 | ||
274cfe59 CG |
330 | /* |
331 | * Local APIC timer | |
332 | */ | |
333 | ||
c40aaec6 | 334 | /* Clock divisor */ |
c40aaec6 | 335 | #define APIC_DIVISOR 16 |
f07f4f90 | 336 | |
0e078e2f TG |
337 | /* |
338 | * This function sets up the local APIC timer, with a timeout of | |
339 | * 'clocks' APIC bus clock. During calibration we actually call | |
340 | * this function twice on the boot CPU, once with a bogus timeout | |
341 | * value, second time for real. The other (noncalibrating) CPUs | |
342 | * call this function only once, with the real, calibrated value. | |
343 | * | |
344 | * We do reads before writes even if unnecessary, to get around the | |
345 | * P5 APIC double write bug. | |
346 | */ | |
0e078e2f | 347 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 348 | { |
0e078e2f | 349 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 350 | |
0e078e2f TG |
351 | lvtt_value = LOCAL_TIMER_VECTOR; |
352 | if (!oneshot) | |
353 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
354 | if (!lapic_is_integrated()) |
355 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
356 | ||
0e078e2f TG |
357 | if (!irqen) |
358 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 359 | |
0e078e2f | 360 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
361 | |
362 | /* | |
0e078e2f | 363 | * Divide PICLK by 16 |
1da177e4 | 364 | */ |
0e078e2f | 365 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
366 | apic_write(APIC_TDCR, |
367 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
368 | APIC_TDR_DIV_16); | |
0e078e2f TG |
369 | |
370 | if (!oneshot) | |
f07f4f90 | 371 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
372 | } |
373 | ||
0e078e2f | 374 | /* |
7b83dae7 RR |
375 | * Setup extended LVT, AMD specific (K8, family 10h) |
376 | * | |
377 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
378 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
379 | * |
380 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
381 | * enables the vector. See also the BKDGs. | |
0e078e2f | 382 | */ |
7b83dae7 RR |
383 | |
384 | #define APIC_EILVT_LVTOFF_MCE 0 | |
385 | #define APIC_EILVT_LVTOFF_IBS 1 | |
386 | ||
387 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 388 | { |
7b83dae7 | 389 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 390 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 391 | |
0e078e2f | 392 | apic_write(reg, v); |
1da177e4 LT |
393 | } |
394 | ||
7b83dae7 RR |
395 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
396 | { | |
397 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
398 | return APIC_EILVT_LVTOFF_MCE; | |
399 | } | |
400 | ||
401 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
402 | { | |
403 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
404 | return APIC_EILVT_LVTOFF_IBS; | |
405 | } | |
6aa360e6 | 406 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 407 | |
0e078e2f TG |
408 | /* |
409 | * Program the next event, relative to now | |
410 | */ | |
411 | static int lapic_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
1da177e4 | 413 | { |
0e078e2f TG |
414 | apic_write(APIC_TMICT, delta); |
415 | return 0; | |
1da177e4 LT |
416 | } |
417 | ||
0e078e2f TG |
418 | /* |
419 | * Setup the lapic timer in periodic or oneshot mode | |
420 | */ | |
421 | static void lapic_timer_setup(enum clock_event_mode mode, | |
422 | struct clock_event_device *evt) | |
9b7711f0 HS |
423 | { |
424 | unsigned long flags; | |
0e078e2f | 425 | unsigned int v; |
9b7711f0 | 426 | |
0e078e2f TG |
427 | /* Lapic used as dummy for broadcast ? */ |
428 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
429 | return; |
430 | ||
431 | local_irq_save(flags); | |
432 | ||
0e078e2f TG |
433 | switch (mode) { |
434 | case CLOCK_EVT_MODE_PERIODIC: | |
435 | case CLOCK_EVT_MODE_ONESHOT: | |
436 | __setup_APIC_LVTT(calibration_result, | |
437 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
438 | break; | |
439 | case CLOCK_EVT_MODE_UNUSED: | |
440 | case CLOCK_EVT_MODE_SHUTDOWN: | |
441 | v = apic_read(APIC_LVTT); | |
442 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
443 | apic_write(APIC_LVTT, v); | |
444 | break; | |
445 | case CLOCK_EVT_MODE_RESUME: | |
446 | /* Nothing to do here */ | |
447 | break; | |
448 | } | |
9b7711f0 HS |
449 | |
450 | local_irq_restore(flags); | |
451 | } | |
452 | ||
1da177e4 | 453 | /* |
0e078e2f | 454 | * Local APIC timer broadcast function |
1da177e4 | 455 | */ |
0e078e2f | 456 | static void lapic_timer_broadcast(cpumask_t mask) |
1da177e4 | 457 | { |
0e078e2f TG |
458 | #ifdef CONFIG_SMP |
459 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
460 | #endif | |
461 | } | |
1da177e4 | 462 | |
0e078e2f TG |
463 | /* |
464 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
465 | * of the boot CPU and register the clock event in the framework. | |
466 | */ | |
db4b5525 | 467 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
468 | { |
469 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 470 | |
0e078e2f TG |
471 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
472 | levt->cpumask = cpumask_of_cpu(smp_processor_id()); | |
1da177e4 | 473 | |
0e078e2f TG |
474 | clockevents_register_device(levt); |
475 | } | |
1da177e4 | 476 | |
2f04fa88 YL |
477 | /* |
478 | * In this functions we calibrate APIC bus clocks to the external timer. | |
479 | * | |
480 | * We want to do the calibration only once since we want to have local timer | |
481 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
482 | * frequency. | |
483 | * | |
484 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
485 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
486 | * readout is broken, so it never gets out of the wait loop again. This was | |
487 | * also reported by others. | |
488 | * | |
489 | * Monitoring the jiffies value is inaccurate and the clockevents | |
490 | * infrastructure allows us to do a simple substitution of the interrupt | |
491 | * handler. | |
492 | * | |
493 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
494 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
495 | * back to normal later in the boot process). | |
496 | */ | |
497 | ||
498 | #define LAPIC_CAL_LOOPS (HZ/10) | |
499 | ||
500 | static __initdata int lapic_cal_loops = -1; | |
501 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
502 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
503 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
504 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
505 | ||
506 | /* | |
507 | * Temporary interrupt handler. | |
508 | */ | |
509 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
510 | { | |
511 | unsigned long long tsc = 0; | |
512 | long tapic = apic_read(APIC_TMCCT); | |
513 | unsigned long pm = acpi_pm_read_early(); | |
514 | ||
515 | if (cpu_has_tsc) | |
516 | rdtscll(tsc); | |
517 | ||
518 | switch (lapic_cal_loops++) { | |
519 | case 0: | |
520 | lapic_cal_t1 = tapic; | |
521 | lapic_cal_tsc1 = tsc; | |
522 | lapic_cal_pm1 = pm; | |
523 | lapic_cal_j1 = jiffies; | |
524 | break; | |
525 | ||
526 | case LAPIC_CAL_LOOPS: | |
527 | lapic_cal_t2 = tapic; | |
528 | lapic_cal_tsc2 = tsc; | |
529 | if (pm < lapic_cal_pm1) | |
530 | pm += ACPI_PM_OVRRUN; | |
531 | lapic_cal_pm2 = pm; | |
532 | lapic_cal_j2 = jiffies; | |
533 | break; | |
534 | } | |
535 | } | |
536 | ||
b189892d CG |
537 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
538 | { | |
539 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
540 | const long pm_thresh = pm_100ms / 100; | |
541 | unsigned long mult; | |
542 | u64 res; | |
543 | ||
544 | #ifndef CONFIG_X86_PM_TIMER | |
545 | return -1; | |
546 | #endif | |
547 | ||
548 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
549 | ||
550 | /* Check, if the PM timer is available */ | |
551 | if (!deltapm) | |
552 | return -1; | |
553 | ||
554 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
555 | ||
556 | if (deltapm > (pm_100ms - pm_thresh) && | |
557 | deltapm < (pm_100ms + pm_thresh)) { | |
558 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
559 | } else { | |
560 | res = (((u64)deltapm) * mult) >> 22; | |
561 | do_div(res, 1000000); | |
562 | printk(KERN_WARNING "APIC calibration not consistent " | |
563 | "with PM Timer: %ldms instead of 100ms\n", | |
564 | (long)res); | |
565 | /* Correct the lapic counter value */ | |
566 | res = (((u64)(*delta)) * pm_100ms); | |
567 | do_div(res, deltapm); | |
568 | printk(KERN_INFO "APIC delta adjusted to PM-Timer: " | |
569 | "%lu (%ld)\n", (unsigned long)res, *delta); | |
570 | *delta = (long)res; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
2f04fa88 YL |
576 | static int __init calibrate_APIC_clock(void) |
577 | { | |
578 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
579 | void (*real_handler)(struct clock_event_device *dev); |
580 | unsigned long deltaj; | |
b189892d | 581 | long delta; |
2f04fa88 YL |
582 | int pm_referenced = 0; |
583 | ||
584 | local_irq_disable(); | |
585 | ||
586 | /* Replace the global interrupt handler */ | |
587 | real_handler = global_clock_event->event_handler; | |
588 | global_clock_event->event_handler = lapic_cal_handler; | |
589 | ||
590 | /* | |
81608f3c | 591 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
592 | * can underflow in the 100ms detection time frame |
593 | */ | |
81608f3c | 594 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
595 | |
596 | /* Let the interrupts run */ | |
597 | local_irq_enable(); | |
598 | ||
599 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
600 | cpu_relax(); | |
601 | ||
602 | local_irq_disable(); | |
603 | ||
604 | /* Restore the real event handler */ | |
605 | global_clock_event->event_handler = real_handler; | |
606 | ||
607 | /* Build delta t1-t2 as apic timer counts down */ | |
608 | delta = lapic_cal_t1 - lapic_cal_t2; | |
609 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
610 | ||
b189892d CG |
611 | /* we trust the PM based calibration if possible */ |
612 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
613 | &delta); | |
2f04fa88 YL |
614 | |
615 | /* Calculate the scaled math multiplication factor */ | |
616 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
617 | lapic_clockevent.shift); | |
618 | lapic_clockevent.max_delta_ns = | |
619 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
620 | lapic_clockevent.min_delta_ns = | |
621 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
622 | ||
623 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
624 | ||
625 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
626 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
627 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
628 | calibration_result); | |
629 | ||
630 | if (cpu_has_tsc) { | |
631 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
632 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
633 | "%ld.%04ld MHz.\n", | |
634 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
635 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
636 | } | |
637 | ||
638 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
639 | "%u.%04u MHz.\n", | |
640 | calibration_result / (1000000 / HZ), | |
641 | calibration_result % (1000000 / HZ)); | |
642 | ||
643 | /* | |
644 | * Do a sanity check on the APIC calibration result | |
645 | */ | |
646 | if (calibration_result < (1000000 / HZ)) { | |
647 | local_irq_enable(); | |
648 | printk(KERN_WARNING | |
649 | "APIC frequency too slow, disabling apic timer\n"); | |
650 | return -1; | |
651 | } | |
652 | ||
653 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
654 | ||
b189892d CG |
655 | /* |
656 | * PM timer calibration failed or not turned on | |
657 | * so lets try APIC timer based calibration | |
658 | */ | |
2f04fa88 YL |
659 | if (!pm_referenced) { |
660 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
661 | ||
662 | /* | |
663 | * Setup the apic timer manually | |
664 | */ | |
665 | levt->event_handler = lapic_cal_handler; | |
666 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
667 | lapic_cal_loops = -1; | |
668 | ||
669 | /* Let the interrupts run */ | |
670 | local_irq_enable(); | |
671 | ||
672 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
673 | cpu_relax(); | |
674 | ||
2f04fa88 YL |
675 | /* Stop the lapic timer */ |
676 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
677 | ||
2f04fa88 YL |
678 | /* Jiffies delta */ |
679 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
680 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
681 | ||
682 | /* Check, if the jiffies result is consistent */ | |
683 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
684 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
685 | else | |
686 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
687 | } else | |
688 | local_irq_enable(); | |
689 | ||
690 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
691 | printk(KERN_WARNING | |
692 | "APIC timer disabled due to verification failure.\n"); | |
693 | return -1; | |
694 | } | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
e83a5fdc HS |
699 | /* |
700 | * Setup the boot APIC | |
701 | * | |
702 | * Calibrate and verify the result. | |
703 | */ | |
0e078e2f TG |
704 | void __init setup_boot_APIC_clock(void) |
705 | { | |
706 | /* | |
274cfe59 CG |
707 | * The local apic timer can be disabled via the kernel |
708 | * commandline or from the CPU detection code. Register the lapic | |
709 | * timer as a dummy clock event source on SMP systems, so the | |
710 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
711 | */ |
712 | if (disable_apic_timer) { | |
713 | printk(KERN_INFO "Disabling APIC timer\n"); | |
714 | /* No broadcast on UP ! */ | |
9d09951d TG |
715 | if (num_possible_cpus() > 1) { |
716 | lapic_clockevent.mult = 1; | |
0e078e2f | 717 | setup_APIC_timer(); |
9d09951d | 718 | } |
0e078e2f TG |
719 | return; |
720 | } | |
721 | ||
274cfe59 CG |
722 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
723 | "calibrating APIC timer ...\n"); | |
724 | ||
89b3b1f4 | 725 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
726 | /* No broadcast on UP ! */ |
727 | if (num_possible_cpus() > 1) | |
728 | setup_APIC_timer(); | |
729 | return; | |
730 | } | |
731 | ||
0e078e2f TG |
732 | /* |
733 | * If nmi_watchdog is set to IO_APIC, we need the | |
734 | * PIT/HPET going. Otherwise register lapic as a dummy | |
735 | * device. | |
736 | */ | |
737 | if (nmi_watchdog != NMI_IO_APIC) | |
738 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
739 | else | |
740 | printk(KERN_WARNING "APIC timer registered as dummy," | |
116f570e | 741 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 742 | |
274cfe59 | 743 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
744 | setup_APIC_timer(); |
745 | } | |
746 | ||
0e078e2f TG |
747 | void __cpuinit setup_secondary_APIC_clock(void) |
748 | { | |
0e078e2f TG |
749 | setup_APIC_timer(); |
750 | } | |
751 | ||
752 | /* | |
753 | * The guts of the apic timer interrupt | |
754 | */ | |
755 | static void local_apic_timer_interrupt(void) | |
756 | { | |
757 | int cpu = smp_processor_id(); | |
758 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
759 | ||
760 | /* | |
761 | * Normally we should not be here till LAPIC has been initialized but | |
762 | * in some cases like kdump, its possible that there is a pending LAPIC | |
763 | * timer interrupt from previous kernel's context and is delivered in | |
764 | * new kernel the moment interrupts are enabled. | |
765 | * | |
766 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
767 | * its possible that when we get here evt->event_handler is NULL. | |
768 | * Check for event_handler being NULL and discard the interrupt as | |
769 | * spurious. | |
770 | */ | |
771 | if (!evt->event_handler) { | |
772 | printk(KERN_WARNING | |
773 | "Spurious LAPIC timer interrupt on cpu %d\n", cpu); | |
774 | /* Switch it off */ | |
775 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
776 | return; | |
777 | } | |
778 | ||
779 | /* | |
780 | * the NMI deadlock-detector uses this. | |
781 | */ | |
0b23e8cf | 782 | #ifdef CONFIG_X86_64 |
0e078e2f | 783 | add_pda(apic_timer_irqs, 1); |
0b23e8cf CG |
784 | #else |
785 | per_cpu(irq_stat, cpu).apic_timer_irqs++; | |
786 | #endif | |
0e078e2f TG |
787 | |
788 | evt->event_handler(evt); | |
789 | } | |
790 | ||
791 | /* | |
792 | * Local APIC timer interrupt. This is the most natural way for doing | |
793 | * local interrupts, but local timer interrupts can be emulated by | |
794 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
795 | * | |
796 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
797 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
798 | */ | |
799 | void smp_apic_timer_interrupt(struct pt_regs *regs) | |
800 | { | |
801 | struct pt_regs *old_regs = set_irq_regs(regs); | |
802 | ||
803 | /* | |
804 | * NOTE! We'd better ACK the irq immediately, | |
805 | * because timer handling can be slow. | |
806 | */ | |
807 | ack_APIC_irq(); | |
808 | /* | |
809 | * update_process_times() expects us to have done irq_enter(). | |
810 | * Besides, if we don't timer interrupts ignore the global | |
811 | * interrupt lock, which is the WrongThing (tm) to do. | |
812 | */ | |
6460bc73 | 813 | #ifdef CONFIG_X86_64 |
0e078e2f | 814 | exit_idle(); |
6460bc73 | 815 | #endif |
0e078e2f TG |
816 | irq_enter(); |
817 | local_apic_timer_interrupt(); | |
818 | irq_exit(); | |
274cfe59 | 819 | |
0e078e2f TG |
820 | set_irq_regs(old_regs); |
821 | } | |
822 | ||
823 | int setup_profiling_timer(unsigned int multiplier) | |
824 | { | |
825 | return -EINVAL; | |
826 | } | |
827 | ||
0e078e2f TG |
828 | /* |
829 | * Local APIC start and shutdown | |
830 | */ | |
831 | ||
832 | /** | |
833 | * clear_local_APIC - shutdown the local APIC | |
834 | * | |
835 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
836 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
837 | * leftovers during boot. | |
838 | */ | |
839 | void clear_local_APIC(void) | |
840 | { | |
2584a82d | 841 | int maxlvt; |
0e078e2f TG |
842 | u32 v; |
843 | ||
d3432896 AK |
844 | /* APIC hasn't been mapped yet */ |
845 | if (!apic_phys) | |
846 | return; | |
847 | ||
848 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
849 | /* |
850 | * Masking an LVT entry can trigger a local APIC error | |
851 | * if the vector is zero. Mask LVTERR first to prevent this. | |
852 | */ | |
853 | if (maxlvt >= 3) { | |
854 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
855 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
856 | } | |
857 | /* | |
858 | * Careful: we have to set masks only first to deassert | |
859 | * any level-triggered sources. | |
860 | */ | |
861 | v = apic_read(APIC_LVTT); | |
862 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
863 | v = apic_read(APIC_LVT0); | |
864 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
865 | v = apic_read(APIC_LVT1); | |
866 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
867 | if (maxlvt >= 4) { | |
868 | v = apic_read(APIC_LVTPC); | |
869 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
870 | } | |
871 | ||
6764014b CG |
872 | /* lets not touch this if we didn't frob it */ |
873 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
874 | if (maxlvt >= 5) { | |
875 | v = apic_read(APIC_LVTTHMR); | |
876 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
877 | } | |
878 | #endif | |
0e078e2f TG |
879 | /* |
880 | * Clean APIC state for other OSs: | |
881 | */ | |
882 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
883 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
884 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
885 | if (maxlvt >= 3) | |
886 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
887 | if (maxlvt >= 4) | |
888 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
889 | |
890 | /* Integrated APIC (!82489DX) ? */ | |
891 | if (lapic_is_integrated()) { | |
892 | if (maxlvt > 3) | |
893 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
894 | apic_write(APIC_ESR, 0); | |
895 | apic_read(APIC_ESR); | |
896 | } | |
0e078e2f TG |
897 | } |
898 | ||
899 | /** | |
900 | * disable_local_APIC - clear and disable the local APIC | |
901 | */ | |
902 | void disable_local_APIC(void) | |
903 | { | |
904 | unsigned int value; | |
905 | ||
906 | clear_local_APIC(); | |
907 | ||
908 | /* | |
909 | * Disable APIC (implies clearing of registers | |
910 | * for 82489DX!). | |
911 | */ | |
912 | value = apic_read(APIC_SPIV); | |
913 | value &= ~APIC_SPIV_APIC_ENABLED; | |
914 | apic_write(APIC_SPIV, value); | |
990b183e CG |
915 | |
916 | #ifdef CONFIG_X86_32 | |
917 | /* | |
918 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
919 | * restore the disabled state. | |
920 | */ | |
921 | if (enabled_via_apicbase) { | |
922 | unsigned int l, h; | |
923 | ||
924 | rdmsr(MSR_IA32_APICBASE, l, h); | |
925 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
926 | wrmsr(MSR_IA32_APICBASE, l, h); | |
927 | } | |
928 | #endif | |
0e078e2f TG |
929 | } |
930 | ||
fe4024dc CG |
931 | /* |
932 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
933 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
934 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
935 | * for the case where Linux didn't enable the LAPIC. | |
936 | */ | |
0e078e2f TG |
937 | void lapic_shutdown(void) |
938 | { | |
939 | unsigned long flags; | |
940 | ||
941 | if (!cpu_has_apic) | |
942 | return; | |
943 | ||
944 | local_irq_save(flags); | |
945 | ||
fe4024dc CG |
946 | #ifdef CONFIG_X86_32 |
947 | if (!enabled_via_apicbase) | |
948 | clear_local_APIC(); | |
949 | else | |
950 | #endif | |
951 | disable_local_APIC(); | |
952 | ||
0e078e2f TG |
953 | |
954 | local_irq_restore(flags); | |
955 | } | |
956 | ||
957 | /* | |
958 | * This is to verify that we're looking at a real local APIC. | |
959 | * Check these against your board if the CPUs aren't getting | |
960 | * started for no apparent reason. | |
961 | */ | |
962 | int __init verify_local_APIC(void) | |
963 | { | |
964 | unsigned int reg0, reg1; | |
965 | ||
966 | /* | |
967 | * The version register is read-only in a real APIC. | |
968 | */ | |
969 | reg0 = apic_read(APIC_LVR); | |
970 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
971 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
972 | reg1 = apic_read(APIC_LVR); | |
973 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
974 | ||
975 | /* | |
976 | * The two version reads above should print the same | |
977 | * numbers. If the second one is different, then we | |
978 | * poke at a non-APIC. | |
979 | */ | |
980 | if (reg1 != reg0) | |
981 | return 0; | |
982 | ||
983 | /* | |
984 | * Check if the version looks reasonably. | |
985 | */ | |
986 | reg1 = GET_APIC_VERSION(reg0); | |
987 | if (reg1 == 0x00 || reg1 == 0xff) | |
988 | return 0; | |
989 | reg1 = lapic_get_maxlvt(); | |
990 | if (reg1 < 0x02 || reg1 == 0xff) | |
991 | return 0; | |
992 | ||
993 | /* | |
994 | * The ID register is read/write in a real APIC. | |
995 | */ | |
2d7a66d0 | 996 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
997 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
998 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 999 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
1000 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
1001 | apic_write(APIC_ID, reg0); | |
1002 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
1003 | return 0; | |
1004 | ||
1005 | /* | |
1da177e4 LT |
1006 | * The next two are just to see if we have sane values. |
1007 | * They're only really relevant if we're in Virtual Wire | |
1008 | * compatibility mode, but most boxes are anymore. | |
1009 | */ | |
1010 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1011 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1012 | reg1 = apic_read(APIC_LVT1); |
1013 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1014 | ||
1015 | return 1; | |
1016 | } | |
1017 | ||
0e078e2f TG |
1018 | /** |
1019 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1020 | */ | |
1da177e4 LT |
1021 | void __init sync_Arb_IDs(void) |
1022 | { | |
296cb951 CG |
1023 | /* |
1024 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1025 | * needed on AMD. | |
1026 | */ | |
1027 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1028 | return; |
1029 | ||
1030 | /* | |
1031 | * Wait for idle. | |
1032 | */ | |
1033 | apic_wait_icr_idle(); | |
1034 | ||
1035 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1036 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1037 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1038 | } |
1039 | ||
1da177e4 LT |
1040 | /* |
1041 | * An initial setup of the virtual wire mode. | |
1042 | */ | |
1043 | void __init init_bsp_APIC(void) | |
1044 | { | |
11a8e778 | 1045 | unsigned int value; |
1da177e4 LT |
1046 | |
1047 | /* | |
1048 | * Don't do the setup now if we have a SMP BIOS as the | |
1049 | * through-I/O-APIC virtual wire mode might be active. | |
1050 | */ | |
1051 | if (smp_found_config || !cpu_has_apic) | |
1052 | return; | |
1053 | ||
1da177e4 LT |
1054 | /* |
1055 | * Do not trust the local APIC being empty at bootup. | |
1056 | */ | |
1057 | clear_local_APIC(); | |
1058 | ||
1059 | /* | |
1060 | * Enable APIC. | |
1061 | */ | |
1062 | value = apic_read(APIC_SPIV); | |
1063 | value &= ~APIC_VECTOR_MASK; | |
1064 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1065 | |
1066 | #ifdef CONFIG_X86_32 | |
1067 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1068 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1069 | (boot_cpu_data.x86 == 15)) | |
1070 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1071 | else | |
1072 | #endif | |
1073 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1074 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1075 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1076 | |
1077 | /* | |
1078 | * Set up the virtual wire mode. | |
1079 | */ | |
11a8e778 | 1080 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1081 | value = APIC_DM_NMI; |
638c0411 CG |
1082 | if (!lapic_is_integrated()) /* 82489DX */ |
1083 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1084 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1085 | } |
1086 | ||
c43da2f5 CG |
1087 | static void __cpuinit lapic_setup_esr(void) |
1088 | { | |
9df08f10 CG |
1089 | unsigned int oldvalue, value, maxlvt; |
1090 | ||
1091 | if (!lapic_is_integrated()) { | |
1092 | printk(KERN_INFO "No ESR for 82489DX.\n"); | |
1093 | return; | |
1094 | } | |
c43da2f5 | 1095 | |
9df08f10 | 1096 | if (esr_disable) { |
c43da2f5 | 1097 | /* |
9df08f10 CG |
1098 | * Something untraceable is creating bad interrupts on |
1099 | * secondary quads ... for the moment, just leave the | |
1100 | * ESR disabled - we can't do anything useful with the | |
1101 | * errors anyway - mbligh | |
c43da2f5 | 1102 | */ |
9df08f10 CG |
1103 | printk(KERN_INFO "Leaving ESR disabled.\n"); |
1104 | return; | |
c43da2f5 | 1105 | } |
9df08f10 CG |
1106 | |
1107 | maxlvt = lapic_get_maxlvt(); | |
1108 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1109 | apic_write(APIC_ESR, 0); | |
1110 | oldvalue = apic_read(APIC_ESR); | |
1111 | ||
1112 | /* enables sending errors */ | |
1113 | value = ERROR_APIC_VECTOR; | |
1114 | apic_write(APIC_LVTERR, value); | |
1115 | ||
1116 | /* | |
1117 | * spec says clear errors after enabling vector. | |
1118 | */ | |
1119 | if (maxlvt > 3) | |
1120 | apic_write(APIC_ESR, 0); | |
1121 | value = apic_read(APIC_ESR); | |
1122 | if (value != oldvalue) | |
1123 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1124 | "vector: 0x%08x after: 0x%08x\n", | |
1125 | oldvalue, value); | |
c43da2f5 CG |
1126 | } |
1127 | ||
1128 | ||
0e078e2f TG |
1129 | /** |
1130 | * setup_local_APIC - setup the local APIC | |
1131 | */ | |
1132 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1133 | { |
739f33b3 | 1134 | unsigned int value; |
da7ed9f9 | 1135 | int i, j; |
1da177e4 | 1136 | |
89c38c28 CG |
1137 | #ifdef CONFIG_X86_32 |
1138 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08ad776e | 1139 | if (lapic_is_integrated() && esr_disable) { |
89c38c28 CG |
1140 | apic_write(APIC_ESR, 0); |
1141 | apic_write(APIC_ESR, 0); | |
1142 | apic_write(APIC_ESR, 0); | |
1143 | apic_write(APIC_ESR, 0); | |
1144 | } | |
1145 | #endif | |
1146 | ||
ac23d4ee | 1147 | preempt_disable(); |
1da177e4 | 1148 | |
1da177e4 LT |
1149 | /* |
1150 | * Double-check whether this APIC is really registered. | |
1151 | * This is meaningless in clustered apic mode, so we skip it. | |
1152 | */ | |
1153 | if (!apic_id_registered()) | |
1154 | BUG(); | |
1155 | ||
1156 | /* | |
1157 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1158 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1159 | * document number 292116). So here it goes... | |
1160 | */ | |
1161 | init_apic_ldr(); | |
1162 | ||
1163 | /* | |
1164 | * Set Task Priority to 'accept all'. We never change this | |
1165 | * later on. | |
1166 | */ | |
1167 | value = apic_read(APIC_TASKPRI); | |
1168 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1169 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1170 | |
da7ed9f9 VG |
1171 | /* |
1172 | * After a crash, we no longer service the interrupts and a pending | |
1173 | * interrupt from previous kernel might still have ISR bit set. | |
1174 | * | |
1175 | * Most probably by now CPU has serviced that pending interrupt and | |
1176 | * it might not have done the ack_APIC_irq() because it thought, | |
1177 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1178 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1179 | * the interrupt. Hence a vector might get locked. It was noticed | |
1180 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1181 | */ | |
1182 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1183 | value = apic_read(APIC_ISR + i*0x10); | |
1184 | for (j = 31; j >= 0; j--) { | |
1185 | if (value & (1<<j)) | |
1186 | ack_APIC_irq(); | |
1187 | } | |
1188 | } | |
1189 | ||
1da177e4 LT |
1190 | /* |
1191 | * Now that we are all set up, enable the APIC | |
1192 | */ | |
1193 | value = apic_read(APIC_SPIV); | |
1194 | value &= ~APIC_VECTOR_MASK; | |
1195 | /* | |
1196 | * Enable APIC | |
1197 | */ | |
1198 | value |= APIC_SPIV_APIC_ENABLED; | |
1199 | ||
89c38c28 CG |
1200 | #ifdef CONFIG_X86_32 |
1201 | /* | |
1202 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1203 | * certain networking cards. If high frequency interrupts are | |
1204 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1205 | * entry is masked/unmasked at a high rate as well then sooner or | |
1206 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1207 | * from the device. If focus CPU is disabled then the hang goes | |
1208 | * away, oh well :-( | |
1209 | * | |
1210 | * [ This bug can be reproduced easily with a level-triggered | |
1211 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1212 | * BX chipset. ] | |
1213 | */ | |
1214 | /* | |
1215 | * Actually disabling the focus CPU check just makes the hang less | |
1216 | * frequent as it makes the interrupt distributon model be more | |
1217 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1218 | * See also the comment in end_level_ioapic_irq(). --macro | |
1219 | */ | |
1220 | ||
1221 | /* | |
1222 | * - enable focus processor (bit==0) | |
1223 | * - 64bit mode always use processor focus | |
1224 | * so no need to set it | |
1225 | */ | |
1226 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1227 | #endif | |
3f14c746 | 1228 | |
1da177e4 LT |
1229 | /* |
1230 | * Set spurious IRQ vector | |
1231 | */ | |
1232 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1233 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1234 | |
1235 | /* | |
1236 | * Set up LVT0, LVT1: | |
1237 | * | |
1238 | * set up through-local-APIC on the BP's LINT0. This is not | |
1239 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1240 | * we delegate interrupts to the 8259A. | |
1241 | */ | |
1242 | /* | |
1243 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1244 | */ | |
1245 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1246 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1247 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1248 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1249 | smp_processor_id()); |
1da177e4 LT |
1250 | } else { |
1251 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1252 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1253 | smp_processor_id()); |
1da177e4 | 1254 | } |
11a8e778 | 1255 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1256 | |
1257 | /* | |
1258 | * only the BP should see the LINT1 NMI signal, obviously. | |
1259 | */ | |
1260 | if (!smp_processor_id()) | |
1261 | value = APIC_DM_NMI; | |
1262 | else | |
1263 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1264 | if (!lapic_is_integrated()) /* 82489DX */ |
1265 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1266 | apic_write(APIC_LVT1, value); |
89c38c28 | 1267 | |
ac23d4ee | 1268 | preempt_enable(); |
739f33b3 | 1269 | } |
1da177e4 | 1270 | |
739f33b3 AK |
1271 | void __cpuinit end_local_APIC_setup(void) |
1272 | { | |
1273 | lapic_setup_esr(); | |
fa6b95fc CG |
1274 | |
1275 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1276 | { |
1277 | unsigned int value; | |
1278 | /* Disable the local apic timer */ | |
1279 | value = apic_read(APIC_LVTT); | |
1280 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1281 | apic_write(APIC_LVTT, value); | |
1282 | } | |
fa6b95fc CG |
1283 | #endif |
1284 | ||
f2802e7f | 1285 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1286 | apic_pm_activate(); |
1da177e4 | 1287 | } |
1da177e4 | 1288 | |
49899eac | 1289 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1290 | void check_x2apic(void) |
1291 | { | |
1292 | int msr, msr2; | |
1293 | ||
1294 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1295 | ||
1296 | if (msr & X2APIC_ENABLE) { | |
1297 | printk("x2apic enabled by BIOS, switching to x2apic ops\n"); | |
1298 | x2apic_preenabled = x2apic = 1; | |
1299 | apic_ops = &x2apic_ops; | |
1300 | } | |
1301 | } | |
1302 | ||
1303 | void enable_x2apic(void) | |
1304 | { | |
1305 | int msr, msr2; | |
1306 | ||
1307 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1308 | if (!(msr & X2APIC_ENABLE)) { | |
1309 | printk("Enabling x2apic\n"); | |
1310 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | void enable_IR_x2apic(void) | |
1315 | { | |
1316 | #ifdef CONFIG_INTR_REMAP | |
1317 | int ret; | |
1318 | unsigned long flags; | |
1319 | ||
1320 | if (!cpu_has_x2apic) | |
1321 | return; | |
1322 | ||
1323 | if (!x2apic_preenabled && disable_x2apic) { | |
1324 | printk(KERN_INFO | |
1325 | "Skipped enabling x2apic and Interrupt-remapping " | |
1326 | "because of nox2apic\n"); | |
1327 | return; | |
1328 | } | |
1329 | ||
1330 | if (x2apic_preenabled && disable_x2apic) | |
1331 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1332 | ||
1333 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
1334 | printk(KERN_INFO | |
1335 | "Skipped enabling x2apic and Interrupt-remapping " | |
1336 | "because of skipping io-apic setup\n"); | |
1337 | return; | |
1338 | } | |
1339 | ||
1340 | ret = dmar_table_init(); | |
1341 | if (ret) { | |
1342 | printk(KERN_INFO | |
1343 | "dmar_table_init() failed with %d:\n", ret); | |
1344 | ||
1345 | if (x2apic_preenabled) | |
1346 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1347 | else | |
1348 | printk(KERN_INFO | |
1349 | "Not enabling x2apic,Intr-remapping\n"); | |
1350 | return; | |
1351 | } | |
1352 | ||
1353 | local_irq_save(flags); | |
1354 | mask_8259A(); | |
5ffa4eb2 CG |
1355 | |
1356 | ret = save_mask_IO_APIC_setup(); | |
1357 | if (ret) { | |
1358 | printk(KERN_INFO "Saving IO-APIC state failed: %d\n", ret); | |
1359 | goto end; | |
1360 | } | |
6e1cb38a SS |
1361 | |
1362 | ret = enable_intr_remapping(1); | |
1363 | ||
1364 | if (ret && x2apic_preenabled) { | |
1365 | local_irq_restore(flags); | |
1366 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1367 | } | |
1368 | ||
1369 | if (ret) | |
5ffa4eb2 | 1370 | goto end_restore; |
6e1cb38a SS |
1371 | |
1372 | if (!x2apic) { | |
1373 | x2apic = 1; | |
1374 | apic_ops = &x2apic_ops; | |
1375 | enable_x2apic(); | |
1376 | } | |
5ffa4eb2 CG |
1377 | |
1378 | end_restore: | |
6e1cb38a SS |
1379 | if (ret) |
1380 | /* | |
1381 | * IR enabling failed | |
1382 | */ | |
1383 | restore_IO_APIC_setup(); | |
1384 | else | |
1385 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1386 | ||
5ffa4eb2 | 1387 | end: |
6e1cb38a SS |
1388 | unmask_8259A(); |
1389 | local_irq_restore(flags); | |
1390 | ||
1391 | if (!ret) { | |
1392 | if (!x2apic_preenabled) | |
1393 | printk(KERN_INFO | |
1394 | "Enabled x2apic and interrupt-remapping\n"); | |
1395 | else | |
1396 | printk(KERN_INFO | |
1397 | "Enabled Interrupt-remapping\n"); | |
1398 | } else | |
1399 | printk(KERN_ERR | |
1400 | "Failed to enable Interrupt-remapping and x2apic\n"); | |
1401 | #else | |
1402 | if (!cpu_has_x2apic) | |
1403 | return; | |
1404 | ||
1405 | if (x2apic_preenabled) | |
1406 | panic("x2apic enabled prior OS handover," | |
1407 | " enable CONFIG_INTR_REMAP"); | |
1408 | ||
1409 | printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping " | |
1410 | " and x2apic\n"); | |
1411 | #endif | |
1412 | ||
1413 | return; | |
1414 | } | |
49899eac | 1415 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1416 | |
be7a656f | 1417 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1418 | /* |
1419 | * Detect and enable local APICs on non-SMP boards. | |
1420 | * Original code written by Keir Fraser. | |
1421 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1422 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1423 | */ |
0e078e2f | 1424 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1425 | { |
1426 | if (!cpu_has_apic) { | |
1427 | printk(KERN_INFO "No local APIC present\n"); | |
1428 | return -1; | |
1429 | } | |
1430 | ||
1431 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1432 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1433 | return 0; |
1434 | } | |
be7a656f YL |
1435 | #else |
1436 | /* | |
1437 | * Detect and initialize APIC | |
1438 | */ | |
1439 | static int __init detect_init_APIC(void) | |
1440 | { | |
1441 | u32 h, l, features; | |
1442 | ||
1443 | /* Disabled by kernel option? */ | |
1444 | if (disable_apic) | |
1445 | return -1; | |
1446 | ||
1447 | switch (boot_cpu_data.x86_vendor) { | |
1448 | case X86_VENDOR_AMD: | |
1449 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1450 | (boot_cpu_data.x86 == 15)) | |
1451 | break; | |
1452 | goto no_apic; | |
1453 | case X86_VENDOR_INTEL: | |
1454 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1455 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1456 | break; | |
1457 | goto no_apic; | |
1458 | default: | |
1459 | goto no_apic; | |
1460 | } | |
1461 | ||
1462 | if (!cpu_has_apic) { | |
1463 | /* | |
1464 | * Over-ride BIOS and try to enable the local APIC only if | |
1465 | * "lapic" specified. | |
1466 | */ | |
1467 | if (!force_enable_local_apic) { | |
1468 | printk(KERN_INFO "Local APIC disabled by BIOS -- " | |
1469 | "you can enable it with \"lapic\"\n"); | |
1470 | return -1; | |
1471 | } | |
1472 | /* | |
1473 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1474 | * MSR. This can only be done in software for Intel P6 or later | |
1475 | * and AMD K7 (Model > 1) or later. | |
1476 | */ | |
1477 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1478 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
1479 | printk(KERN_INFO | |
1480 | "Local APIC disabled by BIOS -- reenabling.\n"); | |
1481 | l &= ~MSR_IA32_APICBASE_BASE; | |
1482 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1483 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1484 | enabled_via_apicbase = 1; | |
1485 | } | |
1486 | } | |
1487 | /* | |
1488 | * The APIC feature bit should now be enabled | |
1489 | * in `cpuid' | |
1490 | */ | |
1491 | features = cpuid_edx(1); | |
1492 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
1493 | printk(KERN_WARNING "Could not enable APIC!\n"); | |
1494 | return -1; | |
1495 | } | |
1496 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1497 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1498 | ||
1499 | /* The BIOS may have set up the APIC at some other address */ | |
1500 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1501 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1502 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1503 | ||
1504 | printk(KERN_INFO "Found and enabled local APIC!\n"); | |
1505 | ||
1506 | apic_pm_activate(); | |
1507 | ||
1508 | return 0; | |
1509 | ||
1510 | no_apic: | |
1511 | printk(KERN_INFO "No local APIC present or hardware disabled\n"); | |
1512 | return -1; | |
1513 | } | |
1514 | #endif | |
1da177e4 | 1515 | |
f28c0ae2 | 1516 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1517 | void __init early_init_lapic_mapping(void) |
1518 | { | |
431ee79d | 1519 | unsigned long phys_addr; |
8643f9d0 YL |
1520 | |
1521 | /* | |
1522 | * If no local APIC can be found then go out | |
1523 | * : it means there is no mpatable and MADT | |
1524 | */ | |
1525 | if (!smp_found_config) | |
1526 | return; | |
1527 | ||
431ee79d | 1528 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1529 | |
431ee79d | 1530 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1531 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1532 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1533 | |
1534 | /* | |
1535 | * Fetch the APIC ID of the BSP in case we have a | |
1536 | * default configuration (or the MP table is broken). | |
1537 | */ | |
4c9961d5 | 1538 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1539 | } |
f28c0ae2 | 1540 | #endif |
8643f9d0 | 1541 | |
0e078e2f TG |
1542 | /** |
1543 | * init_apic_mappings - initialize APIC mappings | |
1544 | */ | |
1da177e4 LT |
1545 | void __init init_apic_mappings(void) |
1546 | { | |
49899eac | 1547 | #ifdef HAVE_X2APIC |
6e1cb38a | 1548 | if (x2apic) { |
4c9961d5 | 1549 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1550 | return; |
1551 | } | |
49899eac | 1552 | #endif |
6e1cb38a | 1553 | |
1da177e4 LT |
1554 | /* |
1555 | * If no local APIC can be found then set up a fake all | |
1556 | * zeroes page to simulate the local APIC and another | |
1557 | * one for the IO-APIC. | |
1558 | */ | |
1559 | if (!smp_found_config && detect_init_APIC()) { | |
1560 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1561 | apic_phys = __pa(apic_phys); | |
1562 | } else | |
1563 | apic_phys = mp_lapic_addr; | |
1564 | ||
1565 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1566 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1567 | APIC_BASE, apic_phys); |
1da177e4 LT |
1568 | |
1569 | /* | |
1570 | * Fetch the APIC ID of the BSP in case we have a | |
1571 | * default configuration (or the MP table is broken). | |
1572 | */ | |
f28c0ae2 YL |
1573 | if (boot_cpu_physical_apicid == -1U) |
1574 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1575 | } |
1576 | ||
1577 | /* | |
0e078e2f TG |
1578 | * This initializes the IO-APIC and APIC hardware if this is |
1579 | * a UP kernel. | |
1da177e4 | 1580 | */ |
1b313f4a CG |
1581 | int apic_version[MAX_APICS]; |
1582 | ||
0e078e2f | 1583 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1584 | { |
fa2bd35a | 1585 | #ifdef CONFIG_X86_64 |
0e078e2f TG |
1586 | if (disable_apic) { |
1587 | printk(KERN_INFO "Apic disabled\n"); | |
1588 | return -1; | |
1589 | } | |
1590 | if (!cpu_has_apic) { | |
1591 | disable_apic = 1; | |
1592 | printk(KERN_INFO "Apic disabled by BIOS\n"); | |
1593 | return -1; | |
1594 | } | |
fa2bd35a YL |
1595 | #else |
1596 | if (!smp_found_config && !cpu_has_apic) | |
1597 | return -1; | |
1598 | ||
1599 | /* | |
1600 | * Complain if the BIOS pretends there is one. | |
1601 | */ | |
1602 | if (!cpu_has_apic && | |
1603 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
823b259b | 1604 | printk(KERN_ERR "BIOS bug, local APIC 0x%x not detected!...\n", |
fa2bd35a YL |
1605 | boot_cpu_physical_apicid); |
1606 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1607 | return -1; | |
1608 | } | |
1609 | #endif | |
1610 | ||
49899eac | 1611 | #ifdef HAVE_X2APIC |
6e1cb38a | 1612 | enable_IR_x2apic(); |
49899eac | 1613 | #endif |
fa2bd35a | 1614 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1615 | setup_apic_routing(); |
fa2bd35a | 1616 | #endif |
6e1cb38a | 1617 | |
0e078e2f | 1618 | verify_local_APIC(); |
b5841765 GC |
1619 | connect_bsp_APIC(); |
1620 | ||
fa2bd35a | 1621 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1622 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1623 | #else |
1624 | /* | |
1625 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1626 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1627 | * might be zero if read from MP tables. Get it from LAPIC. | |
1628 | */ | |
1629 | # ifdef CONFIG_CRASH_DUMP | |
1630 | boot_cpu_physical_apicid = read_apic_id(); | |
1631 | # endif | |
1632 | #endif | |
1633 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1634 | setup_local_APIC(); |
1da177e4 | 1635 | |
fa2bd35a | 1636 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1637 | /* |
1638 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1639 | * We need clear_IO_APIC before enabling vector on BP | |
1640 | */ | |
1641 | if (!skip_ioapic_setup && nr_ioapics) | |
1642 | enable_IO_APIC(); | |
fa2bd35a | 1643 | #endif |
739f33b3 | 1644 | |
fa2bd35a | 1645 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1646 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1647 | #endif |
acae7d90 | 1648 | localise_nmi_watchdog(); |
739f33b3 AK |
1649 | end_local_APIC_setup(); |
1650 | ||
fa2bd35a | 1651 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1652 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1653 | setup_IO_APIC(); | |
fa2bd35a | 1654 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1655 | else |
1656 | nr_ioapics = 0; | |
fa2bd35a YL |
1657 | # endif |
1658 | #endif | |
1659 | ||
1660 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1661 | setup_boot_APIC_clock(); |
1662 | check_nmi_watchdog(); | |
fa2bd35a YL |
1663 | #else |
1664 | setup_boot_clock(); | |
1665 | #endif | |
1666 | ||
0e078e2f | 1667 | return 0; |
1da177e4 LT |
1668 | } |
1669 | ||
1670 | /* | |
0e078e2f | 1671 | * Local APIC interrupts |
1da177e4 LT |
1672 | */ |
1673 | ||
0e078e2f TG |
1674 | /* |
1675 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1676 | */ | |
dc1528dd | 1677 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1678 | { |
dc1528dd YL |
1679 | u32 v; |
1680 | ||
1681 | #ifdef CONFIG_X86_64 | |
0e078e2f | 1682 | exit_idle(); |
dc1528dd | 1683 | #endif |
0e078e2f | 1684 | irq_enter(); |
1da177e4 | 1685 | /* |
0e078e2f TG |
1686 | * Check if this really is a spurious interrupt and ACK it |
1687 | * if it is a vectored one. Just in case... | |
1688 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1689 | */ |
0e078e2f TG |
1690 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1691 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1692 | ack_APIC_irq(); | |
c4d58cbd | 1693 | |
dc1528dd | 1694 | #ifdef CONFIG_X86_64 |
0e078e2f | 1695 | add_pda(irq_spurious_count, 1); |
dc1528dd YL |
1696 | #else |
1697 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ | |
1698 | printk(KERN_INFO "spurious APIC interrupt on CPU#%d, " | |
1699 | "should never happen.\n", smp_processor_id()); | |
1700 | __get_cpu_var(irq_stat).irq_spurious_count++; | |
1701 | #endif | |
0e078e2f TG |
1702 | irq_exit(); |
1703 | } | |
1da177e4 | 1704 | |
0e078e2f TG |
1705 | /* |
1706 | * This interrupt should never happen with our APIC/SMP architecture | |
1707 | */ | |
dc1528dd | 1708 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1709 | { |
dc1528dd | 1710 | u32 v, v1; |
1da177e4 | 1711 | |
dc1528dd | 1712 | #ifdef CONFIG_X86_64 |
0e078e2f | 1713 | exit_idle(); |
dc1528dd | 1714 | #endif |
0e078e2f TG |
1715 | irq_enter(); |
1716 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1717 | v = apic_read(APIC_ESR); | |
1718 | apic_write(APIC_ESR, 0); | |
1719 | v1 = apic_read(APIC_ESR); | |
1720 | ack_APIC_irq(); | |
1721 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1722 | |
0e078e2f TG |
1723 | /* Here is what the APIC error bits mean: |
1724 | 0: Send CS error | |
1725 | 1: Receive CS error | |
1726 | 2: Send accept error | |
1727 | 3: Receive accept error | |
1728 | 4: Reserved | |
1729 | 5: Send illegal vector | |
1730 | 6: Received illegal vector | |
1731 | 7: Illegal register address | |
1732 | */ | |
1733 | printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n", | |
1734 | smp_processor_id(), v , v1); | |
1735 | irq_exit(); | |
1da177e4 LT |
1736 | } |
1737 | ||
b5841765 | 1738 | /** |
36c9d674 CG |
1739 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1740 | */ | |
b5841765 GC |
1741 | void __init connect_bsp_APIC(void) |
1742 | { | |
36c9d674 CG |
1743 | #ifdef CONFIG_X86_32 |
1744 | if (pic_mode) { | |
1745 | /* | |
1746 | * Do not trust the local APIC being empty at bootup. | |
1747 | */ | |
1748 | clear_local_APIC(); | |
1749 | /* | |
1750 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1751 | * local APIC to INT and NMI lines. | |
1752 | */ | |
1753 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1754 | "enabling APIC mode.\n"); | |
1755 | outb(0x70, 0x22); | |
1756 | outb(0x01, 0x23); | |
1757 | } | |
1758 | #endif | |
b5841765 GC |
1759 | enable_apic_mode(); |
1760 | } | |
1761 | ||
274cfe59 CG |
1762 | /** |
1763 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1764 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1765 | * | |
1766 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1767 | * APIC is disabled. | |
1768 | */ | |
0e078e2f | 1769 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1770 | { |
1b4ee4e4 CG |
1771 | unsigned int value; |
1772 | ||
c177b0bc CG |
1773 | #ifdef CONFIG_X86_32 |
1774 | if (pic_mode) { | |
1775 | /* | |
1776 | * Put the board back into PIC mode (has an effect only on | |
1777 | * certain older boards). Note that APIC interrupts, including | |
1778 | * IPIs, won't work beyond this point! The only exception are | |
1779 | * INIT IPIs. | |
1780 | */ | |
1781 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1782 | "entering PIC mode.\n"); | |
1783 | outb(0x70, 0x22); | |
1784 | outb(0x00, 0x23); | |
1785 | return; | |
1786 | } | |
1787 | #endif | |
1788 | ||
0e078e2f | 1789 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1790 | |
0e078e2f TG |
1791 | /* For the spurious interrupt use vector F, and enable it */ |
1792 | value = apic_read(APIC_SPIV); | |
1793 | value &= ~APIC_VECTOR_MASK; | |
1794 | value |= APIC_SPIV_APIC_ENABLED; | |
1795 | value |= 0xf; | |
1796 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1797 | |
0e078e2f TG |
1798 | if (!virt_wire_setup) { |
1799 | /* | |
1800 | * For LVT0 make it edge triggered, active high, | |
1801 | * external and enabled | |
1802 | */ | |
1803 | value = apic_read(APIC_LVT0); | |
1804 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1805 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1806 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1807 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1808 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1809 | apic_write(APIC_LVT0, value); | |
1810 | } else { | |
1811 | /* Disable LVT0 */ | |
1812 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1813 | } | |
b8ce3359 | 1814 | |
c177b0bc CG |
1815 | /* |
1816 | * For LVT1 make it edge triggered, active high, | |
1817 | * nmi and enabled | |
1818 | */ | |
0e078e2f TG |
1819 | value = apic_read(APIC_LVT1); |
1820 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1821 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1822 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1823 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1824 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1825 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1826 | } |
1827 | ||
be8a5685 AS |
1828 | void __cpuinit generic_processor_info(int apicid, int version) |
1829 | { | |
1830 | int cpu; | |
1831 | cpumask_t tmp_map; | |
1832 | ||
1b313f4a CG |
1833 | /* |
1834 | * Validate version | |
1835 | */ | |
1836 | if (version == 0x0) { | |
1837 | printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! " | |
1838 | "fixing up to 0x10. (tell your hw vendor)\n", | |
1839 | version); | |
1840 | version = 0x10; | |
be8a5685 | 1841 | } |
1b313f4a | 1842 | apic_version[apicid] = version; |
be8a5685 | 1843 | |
be8a5685 AS |
1844 | if (num_processors >= NR_CPUS) { |
1845 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
1b313f4a | 1846 | " Processor ignored.\n", NR_CPUS); |
be8a5685 AS |
1847 | return; |
1848 | } | |
1849 | ||
1850 | num_processors++; | |
1851 | cpus_complement(tmp_map, cpu_present_map); | |
1852 | cpu = first_cpu(tmp_map); | |
1853 | ||
1854 | physid_set(apicid, phys_cpu_present_map); | |
1855 | if (apicid == boot_cpu_physical_apicid) { | |
1856 | /* | |
1857 | * x86_bios_cpu_apicid is required to have processors listed | |
1858 | * in same order as logical cpu numbers. Hence the first | |
1859 | * entry is BSP, and so on. | |
1860 | */ | |
1861 | cpu = 0; | |
1862 | } | |
e0da3364 YL |
1863 | if (apicid > max_physical_apicid) |
1864 | max_physical_apicid = apicid; | |
1865 | ||
1b313f4a CG |
1866 | #ifdef CONFIG_X86_32 |
1867 | /* | |
1868 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1869 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1870 | * before this can be done without some confusion. | |
1871 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1872 | * - Ashok Raj <ashok.raj@intel.com> | |
1873 | */ | |
1874 | if (max_physical_apicid >= 8) { | |
1875 | switch (boot_cpu_data.x86_vendor) { | |
1876 | case X86_VENDOR_INTEL: | |
1877 | if (!APIC_XAPIC(version)) { | |
1878 | def_to_bigsmp = 0; | |
1879 | break; | |
1880 | } | |
1881 | /* If P4 and above fall through */ | |
1882 | case X86_VENDOR_AMD: | |
1883 | def_to_bigsmp = 1; | |
1884 | } | |
1885 | } | |
1886 | #endif | |
1887 | ||
1888 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1889 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1890 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1891 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1892 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1893 | |
1894 | cpu_to_apicid[cpu] = apicid; | |
1895 | bios_cpu_apicid[cpu] = apicid; | |
1896 | } else { | |
1897 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1898 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1899 | } | |
1b313f4a | 1900 | #endif |
be8a5685 AS |
1901 | |
1902 | cpu_set(cpu, cpu_possible_map); | |
1903 | cpu_set(cpu, cpu_present_map); | |
1904 | } | |
1905 | ||
3491998d | 1906 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1907 | int hard_smp_processor_id(void) |
1908 | { | |
1909 | return read_apic_id(); | |
1910 | } | |
3491998d | 1911 | #endif |
0c81c746 | 1912 | |
89039b37 | 1913 | /* |
0e078e2f | 1914 | * Power management |
89039b37 | 1915 | */ |
0e078e2f TG |
1916 | #ifdef CONFIG_PM |
1917 | ||
1918 | static struct { | |
274cfe59 CG |
1919 | /* |
1920 | * 'active' is true if the local APIC was enabled by us and | |
1921 | * not the BIOS; this signifies that we are also responsible | |
1922 | * for disabling it before entering apm/acpi suspend | |
1923 | */ | |
0e078e2f TG |
1924 | int active; |
1925 | /* r/w apic fields */ | |
1926 | unsigned int apic_id; | |
1927 | unsigned int apic_taskpri; | |
1928 | unsigned int apic_ldr; | |
1929 | unsigned int apic_dfr; | |
1930 | unsigned int apic_spiv; | |
1931 | unsigned int apic_lvtt; | |
1932 | unsigned int apic_lvtpc; | |
1933 | unsigned int apic_lvt0; | |
1934 | unsigned int apic_lvt1; | |
1935 | unsigned int apic_lvterr; | |
1936 | unsigned int apic_tmict; | |
1937 | unsigned int apic_tdcr; | |
1938 | unsigned int apic_thmr; | |
1939 | } apic_pm_state; | |
1940 | ||
1941 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1942 | { | |
1943 | unsigned long flags; | |
1944 | int maxlvt; | |
89039b37 | 1945 | |
0e078e2f TG |
1946 | if (!apic_pm_state.active) |
1947 | return 0; | |
89039b37 | 1948 | |
0e078e2f | 1949 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1950 | |
2d7a66d0 | 1951 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1952 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1953 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1954 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1955 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1956 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1957 | if (maxlvt >= 4) | |
1958 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1959 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1960 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1961 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1962 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1963 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1964 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1965 | if (maxlvt >= 5) |
1966 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1967 | #endif | |
24968cfd | 1968 | |
0e078e2f TG |
1969 | local_irq_save(flags); |
1970 | disable_local_APIC(); | |
1971 | local_irq_restore(flags); | |
1972 | return 0; | |
1da177e4 LT |
1973 | } |
1974 | ||
0e078e2f | 1975 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1976 | { |
0e078e2f TG |
1977 | unsigned int l, h; |
1978 | unsigned long flags; | |
1979 | int maxlvt; | |
1da177e4 | 1980 | |
0e078e2f TG |
1981 | if (!apic_pm_state.active) |
1982 | return 0; | |
89b831ef | 1983 | |
0e078e2f | 1984 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1985 | |
0e078e2f | 1986 | local_irq_save(flags); |
92206c90 | 1987 | |
49899eac | 1988 | #ifdef HAVE_X2APIC |
92206c90 CG |
1989 | if (x2apic) |
1990 | enable_x2apic(); | |
1991 | else | |
1992 | #endif | |
d5e629a6 | 1993 | { |
92206c90 CG |
1994 | /* |
1995 | * Make sure the APICBASE points to the right address | |
1996 | * | |
1997 | * FIXME! This will be wrong if we ever support suspend on | |
1998 | * SMP! We'll need to do this as part of the CPU restore! | |
1999 | */ | |
6e1cb38a SS |
2000 | rdmsr(MSR_IA32_APICBASE, l, h); |
2001 | l &= ~MSR_IA32_APICBASE_BASE; | |
2002 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
2003 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 2004 | } |
6e1cb38a | 2005 | |
0e078e2f TG |
2006 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
2007 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
2008 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
2009 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
2010 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
2011 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
2012 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
2013 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 2014 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
2015 | if (maxlvt >= 5) |
2016 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
2017 | #endif | |
2018 | if (maxlvt >= 4) | |
2019 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2020 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2021 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2022 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2023 | apic_write(APIC_ESR, 0); | |
2024 | apic_read(APIC_ESR); | |
2025 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2026 | apic_write(APIC_ESR, 0); | |
2027 | apic_read(APIC_ESR); | |
92206c90 | 2028 | |
0e078e2f | 2029 | local_irq_restore(flags); |
92206c90 | 2030 | |
0e078e2f TG |
2031 | return 0; |
2032 | } | |
b8ce3359 | 2033 | |
274cfe59 CG |
2034 | /* |
2035 | * This device has no shutdown method - fully functioning local APICs | |
2036 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2037 | */ | |
2038 | ||
0e078e2f TG |
2039 | static struct sysdev_class lapic_sysclass = { |
2040 | .name = "lapic", | |
2041 | .resume = lapic_resume, | |
2042 | .suspend = lapic_suspend, | |
2043 | }; | |
b8ce3359 | 2044 | |
0e078e2f | 2045 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2046 | .id = 0, |
2047 | .cls = &lapic_sysclass, | |
0e078e2f | 2048 | }; |
b8ce3359 | 2049 | |
0e078e2f TG |
2050 | static void __cpuinit apic_pm_activate(void) |
2051 | { | |
2052 | apic_pm_state.active = 1; | |
1da177e4 LT |
2053 | } |
2054 | ||
0e078e2f | 2055 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2056 | { |
0e078e2f | 2057 | int error; |
e83a5fdc | 2058 | |
0e078e2f TG |
2059 | if (!cpu_has_apic) |
2060 | return 0; | |
2061 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2062 | |
0e078e2f TG |
2063 | error = sysdev_class_register(&lapic_sysclass); |
2064 | if (!error) | |
2065 | error = sysdev_register(&device_lapic); | |
2066 | return error; | |
1da177e4 | 2067 | } |
0e078e2f TG |
2068 | device_initcall(init_lapic_sysfs); |
2069 | ||
2070 | #else /* CONFIG_PM */ | |
2071 | ||
2072 | static void apic_pm_activate(void) { } | |
2073 | ||
2074 | #endif /* CONFIG_PM */ | |
1da177e4 | 2075 | |
f28c0ae2 | 2076 | #ifdef CONFIG_X86_64 |
1da177e4 | 2077 | /* |
f8bf3c65 | 2078 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2079 | * |
2080 | * Thus far, the major user of this is IBM's Summit2 series: | |
2081 | * | |
637029c6 | 2082 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2083 | * multi-chassis. Use available data to take a good guess. |
2084 | * If in doubt, go HPET. | |
2085 | */ | |
f8bf3c65 | 2086 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2087 | { |
2088 | int i, clusters, zeros; | |
2089 | unsigned id; | |
322850af | 2090 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2091 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2092 | ||
322850af YL |
2093 | /* |
2094 | * there is not this kind of box with AMD CPU yet. | |
2095 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2096 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2097 | * vsmp box still need checking... |
322850af | 2098 | */ |
1cb68487 | 2099 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2100 | return 0; |
2101 | ||
23ca4bba | 2102 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2103 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 LT |
2104 | |
2105 | for (i = 0; i < NR_CPUS; i++) { | |
e8c10ef9 | 2106 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2107 | if (bios_cpu_apicid) { |
2108 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 2109 | } |
2110 | else if (i < nr_cpu_ids) { | |
2111 | if (cpu_present(i)) | |
2112 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2113 | else | |
2114 | continue; | |
2115 | } | |
2116 | else | |
2117 | break; | |
2118 | ||
1da177e4 LT |
2119 | if (id != BAD_APICID) |
2120 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2121 | } | |
2122 | ||
2123 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2124 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2125 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2126 | * Since clusters are allocated sequentially, count zeros only if | |
2127 | * they are bounded by ones. | |
1da177e4 LT |
2128 | */ |
2129 | clusters = 0; | |
2130 | zeros = 0; | |
2131 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2132 | if (test_bit(i, clustermap)) { | |
2133 | clusters += 1 + zeros; | |
2134 | zeros = 0; | |
2135 | } else | |
2136 | ++zeros; | |
2137 | } | |
2138 | ||
1cb68487 RT |
2139 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2140 | * not guaranteed to be synced between boards | |
2141 | */ | |
2142 | if (is_vsmp_box() && clusters > 1) | |
2143 | return 1; | |
2144 | ||
1da177e4 | 2145 | /* |
f8bf3c65 | 2146 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2147 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2148 | * out, but AFAIK this will work even for them. | |
2149 | */ | |
2150 | return (clusters > 2); | |
2151 | } | |
f28c0ae2 | 2152 | #endif |
1da177e4 LT |
2153 | |
2154 | /* | |
0e078e2f | 2155 | * APIC command line parameters |
1da177e4 | 2156 | */ |
789fa735 | 2157 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2158 | { |
1da177e4 | 2159 | disable_apic = 1; |
9175fc06 | 2160 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2161 | return 0; |
2162 | } | |
2163 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2164 | |
2c8c0e6b | 2165 | /* same as disableapic, for compatibility */ |
789fa735 | 2166 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2167 | { |
789fa735 | 2168 | return setup_disableapic(arg); |
6935d1f9 | 2169 | } |
2c8c0e6b | 2170 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2171 | |
2e7c2838 LT |
2172 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2173 | { | |
2174 | local_apic_timer_c2_ok = 1; | |
2175 | return 0; | |
2176 | } | |
2177 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2178 | ||
36fef094 | 2179 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2180 | { |
1da177e4 | 2181 | disable_apic_timer = 1; |
36fef094 | 2182 | return 0; |
6935d1f9 | 2183 | } |
36fef094 CG |
2184 | early_param("noapictimer", parse_disable_apic_timer); |
2185 | ||
2186 | static int __init parse_nolapic_timer(char *arg) | |
2187 | { | |
2188 | disable_apic_timer = 1; | |
2189 | return 0; | |
6935d1f9 | 2190 | } |
36fef094 | 2191 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2192 | |
79af9bec CG |
2193 | static int __init apic_set_verbosity(char *arg) |
2194 | { | |
2195 | if (!arg) { | |
2196 | #ifdef CONFIG_X86_64 | |
2197 | skip_ioapic_setup = 0; | |
79af9bec CG |
2198 | return 0; |
2199 | #endif | |
2200 | return -EINVAL; | |
2201 | } | |
2202 | ||
2203 | if (strcmp("debug", arg) == 0) | |
2204 | apic_verbosity = APIC_DEBUG; | |
2205 | else if (strcmp("verbose", arg) == 0) | |
2206 | apic_verbosity = APIC_VERBOSE; | |
2207 | else { | |
2208 | printk(KERN_WARNING "APIC Verbosity level %s not recognised" | |
2209 | " use apic=verbose or apic=debug\n", arg); | |
2210 | return -EINVAL; | |
2211 | } | |
2212 | ||
2213 | return 0; | |
2214 | } | |
2215 | early_param("apic", apic_set_verbosity); | |
2216 | ||
1e934dda YL |
2217 | static int __init lapic_insert_resource(void) |
2218 | { | |
2219 | if (!apic_phys) | |
2220 | return -1; | |
2221 | ||
2222 | /* Put local APIC into the resource map. */ | |
2223 | lapic_resource.start = apic_phys; | |
2224 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2225 | insert_resource(&iomem_resource, &lapic_resource); | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
2230 | /* | |
2231 | * need call insert after e820_reserve_resources() | |
2232 | * that is using request_resource | |
2233 | */ | |
2234 | late_initcall(lapic_insert_resource); |