Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Local APIC handling, local APIC timers | |
3 | * | |
4 | * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes | |
7 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
8 | * thanks to Eric Gilmore | |
9 | * and Rolf G. Tews | |
10 | * for testing these extensively. | |
11 | * Maciej W. Rozycki : Various updates and fixes. | |
12 | * Mikael Pettersson : Power Management for UP-APIC. | |
13 | * Pavel Machek and | |
14 | * Mikael Pettersson : PM converted to driver model. | |
15 | */ | |
16 | ||
1da177e4 LT |
17 | #include <linux/init.h> |
18 | ||
19 | #include <linux/mm.h> | |
1da177e4 LT |
20 | #include <linux/delay.h> |
21 | #include <linux/bootmem.h> | |
1da177e4 LT |
22 | #include <linux/interrupt.h> |
23 | #include <linux/mc146818rtc.h> | |
24 | #include <linux/kernel_stat.h> | |
25 | #include <linux/sysdev.h> | |
39928722 | 26 | #include <linux/ioport.h> |
773763df | 27 | #include <linux/cpu.h> |
ba7eda4c | 28 | #include <linux/clockchips.h> |
70a20025 | 29 | #include <linux/acpi_pmtmr.h> |
e83a5fdc | 30 | #include <linux/module.h> |
773763df | 31 | #include <linux/dmi.h> |
6e1cb38a | 32 | #include <linux/dmar.h> |
bcbc4f20 | 33 | #include <linux/ftrace.h> |
1da177e4 LT |
34 | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/smp.h> | |
37 | #include <asm/mtrr.h> | |
38 | #include <asm/mpspec.h> | |
efa2559f | 39 | #include <asm/desc.h> |
773763df | 40 | #include <asm/arch_hooks.h> |
e83a5fdc | 41 | #include <asm/hpet.h> |
1da177e4 | 42 | #include <asm/pgalloc.h> |
773763df | 43 | #include <asm/i8253.h> |
75152114 | 44 | #include <asm/nmi.h> |
95833c83 | 45 | #include <asm/idle.h> |
73dea47f AK |
46 | #include <asm/proto.h> |
47 | #include <asm/timex.h> | |
2c8c0e6b | 48 | #include <asm/apic.h> |
6e1cb38a | 49 | #include <asm/i8259.h> |
1da177e4 | 50 | |
dd46e3ca | 51 | #include <mach_apic.h> |
773763df YL |
52 | #include <mach_apicdef.h> |
53 | #include <mach_ipi.h> | |
5af5573e | 54 | |
80e5609c CG |
55 | /* |
56 | * Sanity check | |
57 | */ | |
58 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
59 | # error SPURIOUS_APIC_VECTOR definition error | |
60 | #endif | |
61 | ||
b3c51170 YL |
62 | #ifdef CONFIG_X86_32 |
63 | /* | |
64 | * Knob to control our willingness to enable the local APIC. | |
65 | * | |
66 | * +1=force-enable | |
67 | */ | |
68 | static int force_enable_local_apic; | |
69 | /* | |
70 | * APIC command line parameters | |
71 | */ | |
72 | static int __init parse_lapic(char *arg) | |
73 | { | |
74 | force_enable_local_apic = 1; | |
75 | return 0; | |
76 | } | |
77 | early_param("lapic", parse_lapic); | |
f28c0ae2 YL |
78 | /* Local APIC was disabled by the BIOS and enabled by the kernel */ |
79 | static int enabled_via_apicbase; | |
80 | ||
b3c51170 YL |
81 | #endif |
82 | ||
83 | #ifdef CONFIG_X86_64 | |
bc1d99c1 | 84 | static int apic_calibrate_pmtmr __initdata; |
b3c51170 YL |
85 | static __init int setup_apicpmtimer(char *s) |
86 | { | |
87 | apic_calibrate_pmtmr = 1; | |
88 | notsc_setup(NULL); | |
89 | return 0; | |
90 | } | |
91 | __setup("apicpmtimer", setup_apicpmtimer); | |
92 | #endif | |
93 | ||
49899eac YL |
94 | #ifdef CONFIG_X86_64 |
95 | #define HAVE_X2APIC | |
96 | #endif | |
97 | ||
98 | #ifdef HAVE_X2APIC | |
89027d35 | 99 | int x2apic; |
6e1cb38a | 100 | /* x2apic enabled before OS handover */ |
b6b301aa JS |
101 | static int x2apic_preenabled; |
102 | static int disable_x2apic; | |
49899eac YL |
103 | static __init int setup_nox2apic(char *str) |
104 | { | |
105 | disable_x2apic = 1; | |
106 | setup_clear_cpu_cap(X86_FEATURE_X2APIC); | |
107 | return 0; | |
108 | } | |
109 | early_param("nox2apic", setup_nox2apic); | |
110 | #endif | |
1da177e4 | 111 | |
b3c51170 YL |
112 | unsigned long mp_lapic_addr; |
113 | int disable_apic; | |
114 | /* Disable local APIC timer from the kernel commandline or via dmi quirk */ | |
115 | static int disable_apic_timer __cpuinitdata; | |
e83a5fdc | 116 | /* Local APIC timer works in C2 */ |
2e7c2838 LT |
117 | int local_apic_timer_c2_ok; |
118 | EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); | |
119 | ||
efa2559f YL |
120 | int first_system_vector = 0xfe; |
121 | ||
e83a5fdc HS |
122 | /* |
123 | * Debug level, exported for io_apic.c | |
124 | */ | |
baa13188 | 125 | unsigned int apic_verbosity; |
e83a5fdc | 126 | |
89c38c28 CG |
127 | int pic_mode; |
128 | ||
bab4b27c AS |
129 | /* Have we found an MP table */ |
130 | int smp_found_config; | |
131 | ||
39928722 AD |
132 | static struct resource lapic_resource = { |
133 | .name = "Local APIC", | |
134 | .flags = IORESOURCE_MEM | IORESOURCE_BUSY, | |
135 | }; | |
136 | ||
d03030e9 TG |
137 | static unsigned int calibration_result; |
138 | ||
ba7eda4c TG |
139 | static int lapic_next_event(unsigned long delta, |
140 | struct clock_event_device *evt); | |
141 | static void lapic_timer_setup(enum clock_event_mode mode, | |
142 | struct clock_event_device *evt); | |
9628937d | 143 | static void lapic_timer_broadcast(const struct cpumask *mask); |
0e078e2f | 144 | static void apic_pm_activate(void); |
ba7eda4c | 145 | |
274cfe59 CG |
146 | /* |
147 | * The local apic timer can be used for any function which is CPU local. | |
148 | */ | |
ba7eda4c TG |
149 | static struct clock_event_device lapic_clockevent = { |
150 | .name = "lapic", | |
151 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
152 | | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, | |
153 | .shift = 32, | |
154 | .set_mode = lapic_timer_setup, | |
155 | .set_next_event = lapic_next_event, | |
156 | .broadcast = lapic_timer_broadcast, | |
157 | .rating = 100, | |
158 | .irq = -1, | |
159 | }; | |
160 | static DEFINE_PER_CPU(struct clock_event_device, lapic_events); | |
161 | ||
d3432896 AK |
162 | static unsigned long apic_phys; |
163 | ||
0e078e2f TG |
164 | /* |
165 | * Get the LAPIC version | |
166 | */ | |
167 | static inline int lapic_get_version(void) | |
ba7eda4c | 168 | { |
0e078e2f | 169 | return GET_APIC_VERSION(apic_read(APIC_LVR)); |
ba7eda4c TG |
170 | } |
171 | ||
0e078e2f | 172 | /* |
9c803869 | 173 | * Check, if the APIC is integrated or a separate chip |
0e078e2f TG |
174 | */ |
175 | static inline int lapic_is_integrated(void) | |
ba7eda4c | 176 | { |
9c803869 | 177 | #ifdef CONFIG_X86_64 |
0e078e2f | 178 | return 1; |
9c803869 CG |
179 | #else |
180 | return APIC_INTEGRATED(lapic_get_version()); | |
181 | #endif | |
ba7eda4c TG |
182 | } |
183 | ||
184 | /* | |
0e078e2f | 185 | * Check, whether this is a modern or a first generation APIC |
ba7eda4c | 186 | */ |
0e078e2f | 187 | static int modern_apic(void) |
ba7eda4c | 188 | { |
0e078e2f TG |
189 | /* AMD systems use old APIC versions, so check the CPU */ |
190 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | |
191 | boot_cpu_data.x86 >= 0xf) | |
192 | return 1; | |
193 | return lapic_get_version() >= 0x14; | |
ba7eda4c TG |
194 | } |
195 | ||
274cfe59 CG |
196 | /* |
197 | * Paravirt kernels also might be using these below ops. So we still | |
198 | * use generic apic_read()/apic_write(), which might be pointing to different | |
199 | * ops in PARAVIRT case. | |
200 | */ | |
1b374e4d | 201 | void xapic_wait_icr_idle(void) |
8339e9fb FLV |
202 | { |
203 | while (apic_read(APIC_ICR) & APIC_ICR_BUSY) | |
204 | cpu_relax(); | |
205 | } | |
206 | ||
1b374e4d | 207 | u32 safe_xapic_wait_icr_idle(void) |
8339e9fb | 208 | { |
3c6bb07a | 209 | u32 send_status; |
8339e9fb FLV |
210 | int timeout; |
211 | ||
212 | timeout = 0; | |
213 | do { | |
214 | send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; | |
215 | if (!send_status) | |
216 | break; | |
217 | udelay(100); | |
218 | } while (timeout++ < 1000); | |
219 | ||
220 | return send_status; | |
221 | } | |
222 | ||
1b374e4d SS |
223 | void xapic_icr_write(u32 low, u32 id) |
224 | { | |
ed4e5ec1 | 225 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); |
1b374e4d SS |
226 | apic_write(APIC_ICR, low); |
227 | } | |
228 | ||
ec8c842a | 229 | static u64 xapic_icr_read(void) |
1b374e4d SS |
230 | { |
231 | u32 icr1, icr2; | |
232 | ||
233 | icr2 = apic_read(APIC_ICR2); | |
234 | icr1 = apic_read(APIC_ICR); | |
235 | ||
cf9768d7 | 236 | return icr1 | ((u64)icr2 << 32); |
1b374e4d SS |
237 | } |
238 | ||
239 | static struct apic_ops xapic_ops = { | |
240 | .read = native_apic_mem_read, | |
241 | .write = native_apic_mem_write, | |
1b374e4d SS |
242 | .icr_read = xapic_icr_read, |
243 | .icr_write = xapic_icr_write, | |
244 | .wait_icr_idle = xapic_wait_icr_idle, | |
245 | .safe_wait_icr_idle = safe_xapic_wait_icr_idle, | |
246 | }; | |
247 | ||
248 | struct apic_ops __read_mostly *apic_ops = &xapic_ops; | |
1b374e4d SS |
249 | EXPORT_SYMBOL_GPL(apic_ops); |
250 | ||
49899eac | 251 | #ifdef HAVE_X2APIC |
13c88fb5 SS |
252 | static void x2apic_wait_icr_idle(void) |
253 | { | |
254 | /* no need to wait for icr idle in x2apic */ | |
255 | return; | |
256 | } | |
257 | ||
258 | static u32 safe_x2apic_wait_icr_idle(void) | |
259 | { | |
260 | /* no need to wait for icr idle in x2apic */ | |
261 | return 0; | |
262 | } | |
263 | ||
264 | void x2apic_icr_write(u32 low, u32 id) | |
265 | { | |
266 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
267 | } | |
268 | ||
ec8c842a | 269 | static u64 x2apic_icr_read(void) |
13c88fb5 SS |
270 | { |
271 | unsigned long val; | |
272 | ||
273 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
274 | return val; | |
275 | } | |
276 | ||
277 | static struct apic_ops x2apic_ops = { | |
278 | .read = native_apic_msr_read, | |
279 | .write = native_apic_msr_write, | |
13c88fb5 SS |
280 | .icr_read = x2apic_icr_read, |
281 | .icr_write = x2apic_icr_write, | |
282 | .wait_icr_idle = x2apic_wait_icr_idle, | |
283 | .safe_wait_icr_idle = safe_x2apic_wait_icr_idle, | |
284 | }; | |
49899eac | 285 | #endif |
13c88fb5 | 286 | |
0e078e2f TG |
287 | /** |
288 | * enable_NMI_through_LVT0 - enable NMI through local vector table 0 | |
289 | */ | |
e9427101 | 290 | void __cpuinit enable_NMI_through_LVT0(void) |
1da177e4 | 291 | { |
11a8e778 | 292 | unsigned int v; |
6935d1f9 TG |
293 | |
294 | /* unmask and set to NMI */ | |
295 | v = APIC_DM_NMI; | |
d4c63ec0 CG |
296 | |
297 | /* Level triggered for 82489DX (32bit mode) */ | |
298 | if (!lapic_is_integrated()) | |
299 | v |= APIC_LVT_LEVEL_TRIGGER; | |
300 | ||
11a8e778 | 301 | apic_write(APIC_LVT0, v); |
1da177e4 LT |
302 | } |
303 | ||
7c37e48b CG |
304 | #ifdef CONFIG_X86_32 |
305 | /** | |
306 | * get_physical_broadcast - Get number of physical broadcast IDs | |
307 | */ | |
308 | int get_physical_broadcast(void) | |
309 | { | |
310 | return modern_apic() ? 0xff : 0xf; | |
311 | } | |
312 | #endif | |
313 | ||
0e078e2f TG |
314 | /** |
315 | * lapic_get_maxlvt - get the maximum number of local vector table entries | |
316 | */ | |
37e650c7 | 317 | int lapic_get_maxlvt(void) |
1da177e4 | 318 | { |
36a028de | 319 | unsigned int v; |
1da177e4 LT |
320 | |
321 | v = apic_read(APIC_LVR); | |
36a028de CG |
322 | /* |
323 | * - we always have APIC integrated on 64bit mode | |
324 | * - 82489DXs do not report # of LVT entries | |
325 | */ | |
326 | return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; | |
1da177e4 LT |
327 | } |
328 | ||
274cfe59 CG |
329 | /* |
330 | * Local APIC timer | |
331 | */ | |
332 | ||
c40aaec6 | 333 | /* Clock divisor */ |
c40aaec6 | 334 | #define APIC_DIVISOR 16 |
f07f4f90 | 335 | |
0e078e2f TG |
336 | /* |
337 | * This function sets up the local APIC timer, with a timeout of | |
338 | * 'clocks' APIC bus clock. During calibration we actually call | |
339 | * this function twice on the boot CPU, once with a bogus timeout | |
340 | * value, second time for real. The other (noncalibrating) CPUs | |
341 | * call this function only once, with the real, calibrated value. | |
342 | * | |
343 | * We do reads before writes even if unnecessary, to get around the | |
344 | * P5 APIC double write bug. | |
345 | */ | |
0e078e2f | 346 | static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) |
1da177e4 | 347 | { |
0e078e2f | 348 | unsigned int lvtt_value, tmp_value; |
1da177e4 | 349 | |
0e078e2f TG |
350 | lvtt_value = LOCAL_TIMER_VECTOR; |
351 | if (!oneshot) | |
352 | lvtt_value |= APIC_LVT_TIMER_PERIODIC; | |
f07f4f90 CG |
353 | if (!lapic_is_integrated()) |
354 | lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); | |
355 | ||
0e078e2f TG |
356 | if (!irqen) |
357 | lvtt_value |= APIC_LVT_MASKED; | |
1da177e4 | 358 | |
0e078e2f | 359 | apic_write(APIC_LVTT, lvtt_value); |
1da177e4 LT |
360 | |
361 | /* | |
0e078e2f | 362 | * Divide PICLK by 16 |
1da177e4 | 363 | */ |
0e078e2f | 364 | tmp_value = apic_read(APIC_TDCR); |
c40aaec6 CG |
365 | apic_write(APIC_TDCR, |
366 | (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | | |
367 | APIC_TDR_DIV_16); | |
0e078e2f TG |
368 | |
369 | if (!oneshot) | |
f07f4f90 | 370 | apic_write(APIC_TMICT, clocks / APIC_DIVISOR); |
1da177e4 LT |
371 | } |
372 | ||
0e078e2f | 373 | /* |
7b83dae7 RR |
374 | * Setup extended LVT, AMD specific (K8, family 10h) |
375 | * | |
376 | * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and | |
377 | * MCE interrupts are supported. Thus MCE offset must be set to 0. | |
286f5718 RR |
378 | * |
379 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | |
380 | * enables the vector. See also the BKDGs. | |
0e078e2f | 381 | */ |
7b83dae7 RR |
382 | |
383 | #define APIC_EILVT_LVTOFF_MCE 0 | |
384 | #define APIC_EILVT_LVTOFF_IBS 1 | |
385 | ||
386 | static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) | |
1da177e4 | 387 | { |
7b83dae7 | 388 | unsigned long reg = (lvt_off << 4) + APIC_EILVT0; |
0e078e2f | 389 | unsigned int v = (mask << 16) | (msg_type << 8) | vector; |
a8fcf1a2 | 390 | |
0e078e2f | 391 | apic_write(reg, v); |
1da177e4 LT |
392 | } |
393 | ||
7b83dae7 RR |
394 | u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) |
395 | { | |
396 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); | |
397 | return APIC_EILVT_LVTOFF_MCE; | |
398 | } | |
399 | ||
400 | u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) | |
401 | { | |
402 | setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); | |
403 | return APIC_EILVT_LVTOFF_IBS; | |
404 | } | |
6aa360e6 | 405 | EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); |
7b83dae7 | 406 | |
0e078e2f TG |
407 | /* |
408 | * Program the next event, relative to now | |
409 | */ | |
410 | static int lapic_next_event(unsigned long delta, | |
411 | struct clock_event_device *evt) | |
1da177e4 | 412 | { |
0e078e2f TG |
413 | apic_write(APIC_TMICT, delta); |
414 | return 0; | |
1da177e4 LT |
415 | } |
416 | ||
0e078e2f TG |
417 | /* |
418 | * Setup the lapic timer in periodic or oneshot mode | |
419 | */ | |
420 | static void lapic_timer_setup(enum clock_event_mode mode, | |
421 | struct clock_event_device *evt) | |
9b7711f0 HS |
422 | { |
423 | unsigned long flags; | |
0e078e2f | 424 | unsigned int v; |
9b7711f0 | 425 | |
0e078e2f TG |
426 | /* Lapic used as dummy for broadcast ? */ |
427 | if (evt->features & CLOCK_EVT_FEAT_DUMMY) | |
9b7711f0 HS |
428 | return; |
429 | ||
430 | local_irq_save(flags); | |
431 | ||
0e078e2f TG |
432 | switch (mode) { |
433 | case CLOCK_EVT_MODE_PERIODIC: | |
434 | case CLOCK_EVT_MODE_ONESHOT: | |
435 | __setup_APIC_LVTT(calibration_result, | |
436 | mode != CLOCK_EVT_MODE_PERIODIC, 1); | |
437 | break; | |
438 | case CLOCK_EVT_MODE_UNUSED: | |
439 | case CLOCK_EVT_MODE_SHUTDOWN: | |
440 | v = apic_read(APIC_LVTT); | |
441 | v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
442 | apic_write(APIC_LVTT, v); | |
a98f8fd2 | 443 | apic_write(APIC_TMICT, 0xffffffff); |
0e078e2f TG |
444 | break; |
445 | case CLOCK_EVT_MODE_RESUME: | |
446 | /* Nothing to do here */ | |
447 | break; | |
448 | } | |
9b7711f0 HS |
449 | |
450 | local_irq_restore(flags); | |
451 | } | |
452 | ||
1da177e4 | 453 | /* |
0e078e2f | 454 | * Local APIC timer broadcast function |
1da177e4 | 455 | */ |
9628937d | 456 | static void lapic_timer_broadcast(const struct cpumask *mask) |
1da177e4 | 457 | { |
0e078e2f TG |
458 | #ifdef CONFIG_SMP |
459 | send_IPI_mask(mask, LOCAL_TIMER_VECTOR); | |
460 | #endif | |
461 | } | |
1da177e4 | 462 | |
0e078e2f TG |
463 | /* |
464 | * Setup the local APIC timer for this CPU. Copy the initilized values | |
465 | * of the boot CPU and register the clock event in the framework. | |
466 | */ | |
db4b5525 | 467 | static void __cpuinit setup_APIC_timer(void) |
0e078e2f TG |
468 | { |
469 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
1da177e4 | 470 | |
0e078e2f | 471 | memcpy(levt, &lapic_clockevent, sizeof(*levt)); |
320ab2b0 | 472 | levt->cpumask = cpumask_of(smp_processor_id()); |
1da177e4 | 473 | |
0e078e2f TG |
474 | clockevents_register_device(levt); |
475 | } | |
1da177e4 | 476 | |
2f04fa88 YL |
477 | /* |
478 | * In this functions we calibrate APIC bus clocks to the external timer. | |
479 | * | |
480 | * We want to do the calibration only once since we want to have local timer | |
481 | * irqs syncron. CPUs connected by the same APIC bus have the very same bus | |
482 | * frequency. | |
483 | * | |
484 | * This was previously done by reading the PIT/HPET and waiting for a wrap | |
485 | * around to find out, that a tick has elapsed. I have a box, where the PIT | |
486 | * readout is broken, so it never gets out of the wait loop again. This was | |
487 | * also reported by others. | |
488 | * | |
489 | * Monitoring the jiffies value is inaccurate and the clockevents | |
490 | * infrastructure allows us to do a simple substitution of the interrupt | |
491 | * handler. | |
492 | * | |
493 | * The calibration routine also uses the pm_timer when possible, as the PIT | |
494 | * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes | |
495 | * back to normal later in the boot process). | |
496 | */ | |
497 | ||
498 | #define LAPIC_CAL_LOOPS (HZ/10) | |
499 | ||
500 | static __initdata int lapic_cal_loops = -1; | |
501 | static __initdata long lapic_cal_t1, lapic_cal_t2; | |
502 | static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; | |
503 | static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; | |
504 | static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; | |
505 | ||
506 | /* | |
507 | * Temporary interrupt handler. | |
508 | */ | |
509 | static void __init lapic_cal_handler(struct clock_event_device *dev) | |
510 | { | |
511 | unsigned long long tsc = 0; | |
512 | long tapic = apic_read(APIC_TMCCT); | |
513 | unsigned long pm = acpi_pm_read_early(); | |
514 | ||
515 | if (cpu_has_tsc) | |
516 | rdtscll(tsc); | |
517 | ||
518 | switch (lapic_cal_loops++) { | |
519 | case 0: | |
520 | lapic_cal_t1 = tapic; | |
521 | lapic_cal_tsc1 = tsc; | |
522 | lapic_cal_pm1 = pm; | |
523 | lapic_cal_j1 = jiffies; | |
524 | break; | |
525 | ||
526 | case LAPIC_CAL_LOOPS: | |
527 | lapic_cal_t2 = tapic; | |
528 | lapic_cal_tsc2 = tsc; | |
529 | if (pm < lapic_cal_pm1) | |
530 | pm += ACPI_PM_OVRRUN; | |
531 | lapic_cal_pm2 = pm; | |
532 | lapic_cal_j2 = jiffies; | |
533 | break; | |
534 | } | |
535 | } | |
536 | ||
b189892d CG |
537 | static int __init calibrate_by_pmtimer(long deltapm, long *delta) |
538 | { | |
539 | const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; | |
540 | const long pm_thresh = pm_100ms / 100; | |
541 | unsigned long mult; | |
542 | u64 res; | |
543 | ||
544 | #ifndef CONFIG_X86_PM_TIMER | |
545 | return -1; | |
546 | #endif | |
547 | ||
548 | apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm); | |
549 | ||
550 | /* Check, if the PM timer is available */ | |
551 | if (!deltapm) | |
552 | return -1; | |
553 | ||
554 | mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); | |
555 | ||
556 | if (deltapm > (pm_100ms - pm_thresh) && | |
557 | deltapm < (pm_100ms + pm_thresh)) { | |
558 | apic_printk(APIC_VERBOSE, "... PM timer result ok\n"); | |
559 | } else { | |
560 | res = (((u64)deltapm) * mult) >> 22; | |
561 | do_div(res, 1000000); | |
ba21ebb6 | 562 | pr_warning("APIC calibration not consistent " |
b189892d CG |
563 | "with PM Timer: %ldms instead of 100ms\n", |
564 | (long)res); | |
565 | /* Correct the lapic counter value */ | |
566 | res = (((u64)(*delta)) * pm_100ms); | |
567 | do_div(res, deltapm); | |
ba21ebb6 | 568 | pr_info("APIC delta adjusted to PM-Timer: " |
b189892d CG |
569 | "%lu (%ld)\n", (unsigned long)res, *delta); |
570 | *delta = (long)res; | |
571 | } | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
2f04fa88 YL |
576 | static int __init calibrate_APIC_clock(void) |
577 | { | |
578 | struct clock_event_device *levt = &__get_cpu_var(lapic_events); | |
2f04fa88 YL |
579 | void (*real_handler)(struct clock_event_device *dev); |
580 | unsigned long deltaj; | |
b189892d | 581 | long delta; |
2f04fa88 YL |
582 | int pm_referenced = 0; |
583 | ||
584 | local_irq_disable(); | |
585 | ||
586 | /* Replace the global interrupt handler */ | |
587 | real_handler = global_clock_event->event_handler; | |
588 | global_clock_event->event_handler = lapic_cal_handler; | |
589 | ||
590 | /* | |
81608f3c | 591 | * Setup the APIC counter to maximum. There is no way the lapic |
2f04fa88 YL |
592 | * can underflow in the 100ms detection time frame |
593 | */ | |
81608f3c | 594 | __setup_APIC_LVTT(0xffffffff, 0, 0); |
2f04fa88 YL |
595 | |
596 | /* Let the interrupts run */ | |
597 | local_irq_enable(); | |
598 | ||
599 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
600 | cpu_relax(); | |
601 | ||
602 | local_irq_disable(); | |
603 | ||
604 | /* Restore the real event handler */ | |
605 | global_clock_event->event_handler = real_handler; | |
606 | ||
607 | /* Build delta t1-t2 as apic timer counts down */ | |
608 | delta = lapic_cal_t1 - lapic_cal_t2; | |
609 | apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); | |
610 | ||
b189892d CG |
611 | /* we trust the PM based calibration if possible */ |
612 | pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, | |
613 | &delta); | |
2f04fa88 YL |
614 | |
615 | /* Calculate the scaled math multiplication factor */ | |
616 | lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, | |
617 | lapic_clockevent.shift); | |
618 | lapic_clockevent.max_delta_ns = | |
619 | clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); | |
620 | lapic_clockevent.min_delta_ns = | |
621 | clockevent_delta2ns(0xF, &lapic_clockevent); | |
622 | ||
623 | calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; | |
624 | ||
625 | apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); | |
626 | apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); | |
627 | apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", | |
628 | calibration_result); | |
629 | ||
630 | if (cpu_has_tsc) { | |
631 | delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); | |
632 | apic_printk(APIC_VERBOSE, "..... CPU clock speed is " | |
633 | "%ld.%04ld MHz.\n", | |
634 | (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ), | |
635 | (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ)); | |
636 | } | |
637 | ||
638 | apic_printk(APIC_VERBOSE, "..... host bus clock speed is " | |
639 | "%u.%04u MHz.\n", | |
640 | calibration_result / (1000000 / HZ), | |
641 | calibration_result % (1000000 / HZ)); | |
642 | ||
643 | /* | |
644 | * Do a sanity check on the APIC calibration result | |
645 | */ | |
646 | if (calibration_result < (1000000 / HZ)) { | |
647 | local_irq_enable(); | |
ba21ebb6 | 648 | pr_warning("APIC frequency too slow, disabling apic timer\n"); |
2f04fa88 YL |
649 | return -1; |
650 | } | |
651 | ||
652 | levt->features &= ~CLOCK_EVT_FEAT_DUMMY; | |
653 | ||
b189892d CG |
654 | /* |
655 | * PM timer calibration failed or not turned on | |
656 | * so lets try APIC timer based calibration | |
657 | */ | |
2f04fa88 YL |
658 | if (!pm_referenced) { |
659 | apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); | |
660 | ||
661 | /* | |
662 | * Setup the apic timer manually | |
663 | */ | |
664 | levt->event_handler = lapic_cal_handler; | |
665 | lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); | |
666 | lapic_cal_loops = -1; | |
667 | ||
668 | /* Let the interrupts run */ | |
669 | local_irq_enable(); | |
670 | ||
671 | while (lapic_cal_loops <= LAPIC_CAL_LOOPS) | |
672 | cpu_relax(); | |
673 | ||
2f04fa88 YL |
674 | /* Stop the lapic timer */ |
675 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); | |
676 | ||
2f04fa88 YL |
677 | /* Jiffies delta */ |
678 | deltaj = lapic_cal_j2 - lapic_cal_j1; | |
679 | apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); | |
680 | ||
681 | /* Check, if the jiffies result is consistent */ | |
682 | if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) | |
683 | apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); | |
684 | else | |
685 | levt->features |= CLOCK_EVT_FEAT_DUMMY; | |
686 | } else | |
687 | local_irq_enable(); | |
688 | ||
689 | if (levt->features & CLOCK_EVT_FEAT_DUMMY) { | |
ba21ebb6 | 690 | pr_warning("APIC timer disabled due to verification failure.\n"); |
2f04fa88 YL |
691 | return -1; |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
e83a5fdc HS |
697 | /* |
698 | * Setup the boot APIC | |
699 | * | |
700 | * Calibrate and verify the result. | |
701 | */ | |
0e078e2f TG |
702 | void __init setup_boot_APIC_clock(void) |
703 | { | |
704 | /* | |
274cfe59 CG |
705 | * The local apic timer can be disabled via the kernel |
706 | * commandline or from the CPU detection code. Register the lapic | |
707 | * timer as a dummy clock event source on SMP systems, so the | |
708 | * broadcast mechanism is used. On UP systems simply ignore it. | |
0e078e2f TG |
709 | */ |
710 | if (disable_apic_timer) { | |
ba21ebb6 | 711 | pr_info("Disabling APIC timer\n"); |
0e078e2f | 712 | /* No broadcast on UP ! */ |
9d09951d TG |
713 | if (num_possible_cpus() > 1) { |
714 | lapic_clockevent.mult = 1; | |
0e078e2f | 715 | setup_APIC_timer(); |
9d09951d | 716 | } |
0e078e2f TG |
717 | return; |
718 | } | |
719 | ||
274cfe59 CG |
720 | apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" |
721 | "calibrating APIC timer ...\n"); | |
722 | ||
89b3b1f4 | 723 | if (calibrate_APIC_clock()) { |
c2b84b30 TG |
724 | /* No broadcast on UP ! */ |
725 | if (num_possible_cpus() > 1) | |
726 | setup_APIC_timer(); | |
727 | return; | |
728 | } | |
729 | ||
0e078e2f TG |
730 | /* |
731 | * If nmi_watchdog is set to IO_APIC, we need the | |
732 | * PIT/HPET going. Otherwise register lapic as a dummy | |
733 | * device. | |
734 | */ | |
735 | if (nmi_watchdog != NMI_IO_APIC) | |
736 | lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; | |
737 | else | |
ba21ebb6 | 738 | pr_warning("APIC timer registered as dummy," |
116f570e | 739 | " due to nmi_watchdog=%d!\n", nmi_watchdog); |
0e078e2f | 740 | |
274cfe59 | 741 | /* Setup the lapic or request the broadcast */ |
0e078e2f TG |
742 | setup_APIC_timer(); |
743 | } | |
744 | ||
0e078e2f TG |
745 | void __cpuinit setup_secondary_APIC_clock(void) |
746 | { | |
0e078e2f TG |
747 | setup_APIC_timer(); |
748 | } | |
749 | ||
750 | /* | |
751 | * The guts of the apic timer interrupt | |
752 | */ | |
753 | static void local_apic_timer_interrupt(void) | |
754 | { | |
755 | int cpu = smp_processor_id(); | |
756 | struct clock_event_device *evt = &per_cpu(lapic_events, cpu); | |
757 | ||
758 | /* | |
759 | * Normally we should not be here till LAPIC has been initialized but | |
760 | * in some cases like kdump, its possible that there is a pending LAPIC | |
761 | * timer interrupt from previous kernel's context and is delivered in | |
762 | * new kernel the moment interrupts are enabled. | |
763 | * | |
764 | * Interrupts are enabled early and LAPIC is setup much later, hence | |
765 | * its possible that when we get here evt->event_handler is NULL. | |
766 | * Check for event_handler being NULL and discard the interrupt as | |
767 | * spurious. | |
768 | */ | |
769 | if (!evt->event_handler) { | |
ba21ebb6 | 770 | pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); |
0e078e2f TG |
771 | /* Switch it off */ |
772 | lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); | |
773 | return; | |
774 | } | |
775 | ||
776 | /* | |
777 | * the NMI deadlock-detector uses this. | |
778 | */ | |
915b0d01 | 779 | inc_irq_stat(apic_timer_irqs); |
0e078e2f TG |
780 | |
781 | evt->event_handler(evt); | |
782 | } | |
783 | ||
784 | /* | |
785 | * Local APIC timer interrupt. This is the most natural way for doing | |
786 | * local interrupts, but local timer interrupts can be emulated by | |
787 | * broadcast interrupts too. [in case the hw doesn't support APIC timers] | |
788 | * | |
789 | * [ if a single-CPU system runs an SMP kernel then we call the local | |
790 | * interrupt as well. Thus we cannot inline the local irq ... ] | |
791 | */ | |
bcbc4f20 | 792 | void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) |
0e078e2f TG |
793 | { |
794 | struct pt_regs *old_regs = set_irq_regs(regs); | |
795 | ||
796 | /* | |
797 | * NOTE! We'd better ACK the irq immediately, | |
798 | * because timer handling can be slow. | |
799 | */ | |
800 | ack_APIC_irq(); | |
801 | /* | |
802 | * update_process_times() expects us to have done irq_enter(). | |
803 | * Besides, if we don't timer interrupts ignore the global | |
804 | * interrupt lock, which is the WrongThing (tm) to do. | |
805 | */ | |
806 | exit_idle(); | |
807 | irq_enter(); | |
808 | local_apic_timer_interrupt(); | |
809 | irq_exit(); | |
274cfe59 | 810 | |
0e078e2f TG |
811 | set_irq_regs(old_regs); |
812 | } | |
813 | ||
814 | int setup_profiling_timer(unsigned int multiplier) | |
815 | { | |
816 | return -EINVAL; | |
817 | } | |
818 | ||
0e078e2f TG |
819 | /* |
820 | * Local APIC start and shutdown | |
821 | */ | |
822 | ||
823 | /** | |
824 | * clear_local_APIC - shutdown the local APIC | |
825 | * | |
826 | * This is called, when a CPU is disabled and before rebooting, so the state of | |
827 | * the local APIC has no dangling leftovers. Also used to cleanout any BIOS | |
828 | * leftovers during boot. | |
829 | */ | |
830 | void clear_local_APIC(void) | |
831 | { | |
2584a82d | 832 | int maxlvt; |
0e078e2f TG |
833 | u32 v; |
834 | ||
d3432896 AK |
835 | /* APIC hasn't been mapped yet */ |
836 | if (!apic_phys) | |
837 | return; | |
838 | ||
839 | maxlvt = lapic_get_maxlvt(); | |
0e078e2f TG |
840 | /* |
841 | * Masking an LVT entry can trigger a local APIC error | |
842 | * if the vector is zero. Mask LVTERR first to prevent this. | |
843 | */ | |
844 | if (maxlvt >= 3) { | |
845 | v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ | |
846 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
847 | } | |
848 | /* | |
849 | * Careful: we have to set masks only first to deassert | |
850 | * any level-triggered sources. | |
851 | */ | |
852 | v = apic_read(APIC_LVTT); | |
853 | apic_write(APIC_LVTT, v | APIC_LVT_MASKED); | |
854 | v = apic_read(APIC_LVT0); | |
855 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); | |
856 | v = apic_read(APIC_LVT1); | |
857 | apic_write(APIC_LVT1, v | APIC_LVT_MASKED); | |
858 | if (maxlvt >= 4) { | |
859 | v = apic_read(APIC_LVTPC); | |
860 | apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); | |
861 | } | |
862 | ||
6764014b CG |
863 | /* lets not touch this if we didn't frob it */ |
864 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) | |
865 | if (maxlvt >= 5) { | |
866 | v = apic_read(APIC_LVTTHMR); | |
867 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | |
868 | } | |
869 | #endif | |
0e078e2f TG |
870 | /* |
871 | * Clean APIC state for other OSs: | |
872 | */ | |
873 | apic_write(APIC_LVTT, APIC_LVT_MASKED); | |
874 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
875 | apic_write(APIC_LVT1, APIC_LVT_MASKED); | |
876 | if (maxlvt >= 3) | |
877 | apic_write(APIC_LVTERR, APIC_LVT_MASKED); | |
878 | if (maxlvt >= 4) | |
879 | apic_write(APIC_LVTPC, APIC_LVT_MASKED); | |
6764014b CG |
880 | |
881 | /* Integrated APIC (!82489DX) ? */ | |
882 | if (lapic_is_integrated()) { | |
883 | if (maxlvt > 3) | |
884 | /* Clear ESR due to Pentium errata 3AP and 11AP */ | |
885 | apic_write(APIC_ESR, 0); | |
886 | apic_read(APIC_ESR); | |
887 | } | |
0e078e2f TG |
888 | } |
889 | ||
890 | /** | |
891 | * disable_local_APIC - clear and disable the local APIC | |
892 | */ | |
893 | void disable_local_APIC(void) | |
894 | { | |
895 | unsigned int value; | |
896 | ||
897 | clear_local_APIC(); | |
898 | ||
899 | /* | |
900 | * Disable APIC (implies clearing of registers | |
901 | * for 82489DX!). | |
902 | */ | |
903 | value = apic_read(APIC_SPIV); | |
904 | value &= ~APIC_SPIV_APIC_ENABLED; | |
905 | apic_write(APIC_SPIV, value); | |
990b183e CG |
906 | |
907 | #ifdef CONFIG_X86_32 | |
908 | /* | |
909 | * When LAPIC was disabled by the BIOS and enabled by the kernel, | |
910 | * restore the disabled state. | |
911 | */ | |
912 | if (enabled_via_apicbase) { | |
913 | unsigned int l, h; | |
914 | ||
915 | rdmsr(MSR_IA32_APICBASE, l, h); | |
916 | l &= ~MSR_IA32_APICBASE_ENABLE; | |
917 | wrmsr(MSR_IA32_APICBASE, l, h); | |
918 | } | |
919 | #endif | |
0e078e2f TG |
920 | } |
921 | ||
fe4024dc CG |
922 | /* |
923 | * If Linux enabled the LAPIC against the BIOS default disable it down before | |
924 | * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and | |
925 | * not power-off. Additionally clear all LVT entries before disable_local_APIC | |
926 | * for the case where Linux didn't enable the LAPIC. | |
927 | */ | |
0e078e2f TG |
928 | void lapic_shutdown(void) |
929 | { | |
930 | unsigned long flags; | |
931 | ||
932 | if (!cpu_has_apic) | |
933 | return; | |
934 | ||
935 | local_irq_save(flags); | |
936 | ||
fe4024dc CG |
937 | #ifdef CONFIG_X86_32 |
938 | if (!enabled_via_apicbase) | |
939 | clear_local_APIC(); | |
940 | else | |
941 | #endif | |
942 | disable_local_APIC(); | |
943 | ||
0e078e2f TG |
944 | |
945 | local_irq_restore(flags); | |
946 | } | |
947 | ||
948 | /* | |
949 | * This is to verify that we're looking at a real local APIC. | |
950 | * Check these against your board if the CPUs aren't getting | |
951 | * started for no apparent reason. | |
952 | */ | |
953 | int __init verify_local_APIC(void) | |
954 | { | |
955 | unsigned int reg0, reg1; | |
956 | ||
957 | /* | |
958 | * The version register is read-only in a real APIC. | |
959 | */ | |
960 | reg0 = apic_read(APIC_LVR); | |
961 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); | |
962 | apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); | |
963 | reg1 = apic_read(APIC_LVR); | |
964 | apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); | |
965 | ||
966 | /* | |
967 | * The two version reads above should print the same | |
968 | * numbers. If the second one is different, then we | |
969 | * poke at a non-APIC. | |
970 | */ | |
971 | if (reg1 != reg0) | |
972 | return 0; | |
973 | ||
974 | /* | |
975 | * Check if the version looks reasonably. | |
976 | */ | |
977 | reg1 = GET_APIC_VERSION(reg0); | |
978 | if (reg1 == 0x00 || reg1 == 0xff) | |
979 | return 0; | |
980 | reg1 = lapic_get_maxlvt(); | |
981 | if (reg1 < 0x02 || reg1 == 0xff) | |
982 | return 0; | |
983 | ||
984 | /* | |
985 | * The ID register is read/write in a real APIC. | |
986 | */ | |
2d7a66d0 | 987 | reg0 = apic_read(APIC_ID); |
0e078e2f TG |
988 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); |
989 | apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); | |
2d7a66d0 | 990 | reg1 = apic_read(APIC_ID); |
0e078e2f TG |
991 | apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); |
992 | apic_write(APIC_ID, reg0); | |
993 | if (reg1 != (reg0 ^ APIC_ID_MASK)) | |
994 | return 0; | |
995 | ||
996 | /* | |
1da177e4 LT |
997 | * The next two are just to see if we have sane values. |
998 | * They're only really relevant if we're in Virtual Wire | |
999 | * compatibility mode, but most boxes are anymore. | |
1000 | */ | |
1001 | reg0 = apic_read(APIC_LVT0); | |
0e078e2f | 1002 | apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); |
1da177e4 LT |
1003 | reg1 = apic_read(APIC_LVT1); |
1004 | apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); | |
1005 | ||
1006 | return 1; | |
1007 | } | |
1008 | ||
0e078e2f TG |
1009 | /** |
1010 | * sync_Arb_IDs - synchronize APIC bus arbitration IDs | |
1011 | */ | |
1da177e4 LT |
1012 | void __init sync_Arb_IDs(void) |
1013 | { | |
296cb951 CG |
1014 | /* |
1015 | * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not | |
1016 | * needed on AMD. | |
1017 | */ | |
1018 | if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
1da177e4 LT |
1019 | return; |
1020 | ||
1021 | /* | |
1022 | * Wait for idle. | |
1023 | */ | |
1024 | apic_wait_icr_idle(); | |
1025 | ||
1026 | apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); | |
6f6da97f CG |
1027 | apic_write(APIC_ICR, APIC_DEST_ALLINC | |
1028 | APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
1da177e4 LT |
1029 | } |
1030 | ||
1da177e4 LT |
1031 | /* |
1032 | * An initial setup of the virtual wire mode. | |
1033 | */ | |
1034 | void __init init_bsp_APIC(void) | |
1035 | { | |
11a8e778 | 1036 | unsigned int value; |
1da177e4 LT |
1037 | |
1038 | /* | |
1039 | * Don't do the setup now if we have a SMP BIOS as the | |
1040 | * through-I/O-APIC virtual wire mode might be active. | |
1041 | */ | |
1042 | if (smp_found_config || !cpu_has_apic) | |
1043 | return; | |
1044 | ||
1da177e4 LT |
1045 | /* |
1046 | * Do not trust the local APIC being empty at bootup. | |
1047 | */ | |
1048 | clear_local_APIC(); | |
1049 | ||
1050 | /* | |
1051 | * Enable APIC. | |
1052 | */ | |
1053 | value = apic_read(APIC_SPIV); | |
1054 | value &= ~APIC_VECTOR_MASK; | |
1055 | value |= APIC_SPIV_APIC_ENABLED; | |
638c0411 CG |
1056 | |
1057 | #ifdef CONFIG_X86_32 | |
1058 | /* This bit is reserved on P4/Xeon and should be cleared */ | |
1059 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
1060 | (boot_cpu_data.x86 == 15)) | |
1061 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1062 | else | |
1063 | #endif | |
1064 | value |= APIC_SPIV_FOCUS_DISABLED; | |
1da177e4 | 1065 | value |= SPURIOUS_APIC_VECTOR; |
11a8e778 | 1066 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1067 | |
1068 | /* | |
1069 | * Set up the virtual wire mode. | |
1070 | */ | |
11a8e778 | 1071 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 | 1072 | value = APIC_DM_NMI; |
638c0411 CG |
1073 | if (!lapic_is_integrated()) /* 82489DX */ |
1074 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1075 | apic_write(APIC_LVT1, value); |
1da177e4 LT |
1076 | } |
1077 | ||
c43da2f5 CG |
1078 | static void __cpuinit lapic_setup_esr(void) |
1079 | { | |
9df08f10 CG |
1080 | unsigned int oldvalue, value, maxlvt; |
1081 | ||
1082 | if (!lapic_is_integrated()) { | |
ba21ebb6 | 1083 | pr_info("No ESR for 82489DX.\n"); |
9df08f10 CG |
1084 | return; |
1085 | } | |
c43da2f5 | 1086 | |
9df08f10 | 1087 | if (esr_disable) { |
c43da2f5 | 1088 | /* |
9df08f10 CG |
1089 | * Something untraceable is creating bad interrupts on |
1090 | * secondary quads ... for the moment, just leave the | |
1091 | * ESR disabled - we can't do anything useful with the | |
1092 | * errors anyway - mbligh | |
c43da2f5 | 1093 | */ |
ba21ebb6 | 1094 | pr_info("Leaving ESR disabled.\n"); |
9df08f10 | 1095 | return; |
c43da2f5 | 1096 | } |
9df08f10 CG |
1097 | |
1098 | maxlvt = lapic_get_maxlvt(); | |
1099 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1100 | apic_write(APIC_ESR, 0); | |
1101 | oldvalue = apic_read(APIC_ESR); | |
1102 | ||
1103 | /* enables sending errors */ | |
1104 | value = ERROR_APIC_VECTOR; | |
1105 | apic_write(APIC_LVTERR, value); | |
1106 | ||
1107 | /* | |
1108 | * spec says clear errors after enabling vector. | |
1109 | */ | |
1110 | if (maxlvt > 3) | |
1111 | apic_write(APIC_ESR, 0); | |
1112 | value = apic_read(APIC_ESR); | |
1113 | if (value != oldvalue) | |
1114 | apic_printk(APIC_VERBOSE, "ESR value before enabling " | |
1115 | "vector: 0x%08x after: 0x%08x\n", | |
1116 | oldvalue, value); | |
c43da2f5 CG |
1117 | } |
1118 | ||
1119 | ||
0e078e2f TG |
1120 | /** |
1121 | * setup_local_APIC - setup the local APIC | |
1122 | */ | |
1123 | void __cpuinit setup_local_APIC(void) | |
1da177e4 | 1124 | { |
739f33b3 | 1125 | unsigned int value; |
da7ed9f9 | 1126 | int i, j; |
1da177e4 | 1127 | |
89c38c28 CG |
1128 | #ifdef CONFIG_X86_32 |
1129 | /* Pound the ESR really hard over the head with a big hammer - mbligh */ | |
08ad776e | 1130 | if (lapic_is_integrated() && esr_disable) { |
89c38c28 CG |
1131 | apic_write(APIC_ESR, 0); |
1132 | apic_write(APIC_ESR, 0); | |
1133 | apic_write(APIC_ESR, 0); | |
1134 | apic_write(APIC_ESR, 0); | |
1135 | } | |
1136 | #endif | |
1137 | ||
ac23d4ee | 1138 | preempt_disable(); |
1da177e4 | 1139 | |
1da177e4 LT |
1140 | /* |
1141 | * Double-check whether this APIC is really registered. | |
1142 | * This is meaningless in clustered apic mode, so we skip it. | |
1143 | */ | |
1144 | if (!apic_id_registered()) | |
1145 | BUG(); | |
1146 | ||
1147 | /* | |
1148 | * Intel recommends to set DFR, LDR and TPR before enabling | |
1149 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
1150 | * document number 292116). So here it goes... | |
1151 | */ | |
1152 | init_apic_ldr(); | |
1153 | ||
1154 | /* | |
1155 | * Set Task Priority to 'accept all'. We never change this | |
1156 | * later on. | |
1157 | */ | |
1158 | value = apic_read(APIC_TASKPRI); | |
1159 | value &= ~APIC_TPRI_MASK; | |
11a8e778 | 1160 | apic_write(APIC_TASKPRI, value); |
1da177e4 | 1161 | |
da7ed9f9 VG |
1162 | /* |
1163 | * After a crash, we no longer service the interrupts and a pending | |
1164 | * interrupt from previous kernel might still have ISR bit set. | |
1165 | * | |
1166 | * Most probably by now CPU has serviced that pending interrupt and | |
1167 | * it might not have done the ack_APIC_irq() because it thought, | |
1168 | * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it | |
1169 | * does not clear the ISR bit and cpu thinks it has already serivced | |
1170 | * the interrupt. Hence a vector might get locked. It was noticed | |
1171 | * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. | |
1172 | */ | |
1173 | for (i = APIC_ISR_NR - 1; i >= 0; i--) { | |
1174 | value = apic_read(APIC_ISR + i*0x10); | |
1175 | for (j = 31; j >= 0; j--) { | |
1176 | if (value & (1<<j)) | |
1177 | ack_APIC_irq(); | |
1178 | } | |
1179 | } | |
1180 | ||
1da177e4 LT |
1181 | /* |
1182 | * Now that we are all set up, enable the APIC | |
1183 | */ | |
1184 | value = apic_read(APIC_SPIV); | |
1185 | value &= ~APIC_VECTOR_MASK; | |
1186 | /* | |
1187 | * Enable APIC | |
1188 | */ | |
1189 | value |= APIC_SPIV_APIC_ENABLED; | |
1190 | ||
89c38c28 CG |
1191 | #ifdef CONFIG_X86_32 |
1192 | /* | |
1193 | * Some unknown Intel IO/APIC (or APIC) errata is biting us with | |
1194 | * certain networking cards. If high frequency interrupts are | |
1195 | * happening on a particular IOAPIC pin, plus the IOAPIC routing | |
1196 | * entry is masked/unmasked at a high rate as well then sooner or | |
1197 | * later IOAPIC line gets 'stuck', no more interrupts are received | |
1198 | * from the device. If focus CPU is disabled then the hang goes | |
1199 | * away, oh well :-( | |
1200 | * | |
1201 | * [ This bug can be reproduced easily with a level-triggered | |
1202 | * PCI Ne2000 networking cards and PII/PIII processors, dual | |
1203 | * BX chipset. ] | |
1204 | */ | |
1205 | /* | |
1206 | * Actually disabling the focus CPU check just makes the hang less | |
1207 | * frequent as it makes the interrupt distributon model be more | |
1208 | * like LRU than MRU (the short-term load is more even across CPUs). | |
1209 | * See also the comment in end_level_ioapic_irq(). --macro | |
1210 | */ | |
1211 | ||
1212 | /* | |
1213 | * - enable focus processor (bit==0) | |
1214 | * - 64bit mode always use processor focus | |
1215 | * so no need to set it | |
1216 | */ | |
1217 | value &= ~APIC_SPIV_FOCUS_DISABLED; | |
1218 | #endif | |
3f14c746 | 1219 | |
1da177e4 LT |
1220 | /* |
1221 | * Set spurious IRQ vector | |
1222 | */ | |
1223 | value |= SPURIOUS_APIC_VECTOR; | |
11a8e778 | 1224 | apic_write(APIC_SPIV, value); |
1da177e4 LT |
1225 | |
1226 | /* | |
1227 | * Set up LVT0, LVT1: | |
1228 | * | |
1229 | * set up through-local-APIC on the BP's LINT0. This is not | |
1230 | * strictly necessary in pure symmetric-IO mode, but sometimes | |
1231 | * we delegate interrupts to the 8259A. | |
1232 | */ | |
1233 | /* | |
1234 | * TODO: set up through-local-APIC from through-I/O-APIC? --macro | |
1235 | */ | |
1236 | value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; | |
89c38c28 | 1237 | if (!smp_processor_id() && (pic_mode || !value)) { |
1da177e4 | 1238 | value = APIC_DM_EXTINT; |
bc1d99c1 | 1239 | apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", |
89c38c28 | 1240 | smp_processor_id()); |
1da177e4 LT |
1241 | } else { |
1242 | value = APIC_DM_EXTINT | APIC_LVT_MASKED; | |
bc1d99c1 | 1243 | apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", |
89c38c28 | 1244 | smp_processor_id()); |
1da177e4 | 1245 | } |
11a8e778 | 1246 | apic_write(APIC_LVT0, value); |
1da177e4 LT |
1247 | |
1248 | /* | |
1249 | * only the BP should see the LINT1 NMI signal, obviously. | |
1250 | */ | |
1251 | if (!smp_processor_id()) | |
1252 | value = APIC_DM_NMI; | |
1253 | else | |
1254 | value = APIC_DM_NMI | APIC_LVT_MASKED; | |
89c38c28 CG |
1255 | if (!lapic_is_integrated()) /* 82489DX */ |
1256 | value |= APIC_LVT_LEVEL_TRIGGER; | |
11a8e778 | 1257 | apic_write(APIC_LVT1, value); |
89c38c28 | 1258 | |
ac23d4ee | 1259 | preempt_enable(); |
739f33b3 | 1260 | } |
1da177e4 | 1261 | |
739f33b3 AK |
1262 | void __cpuinit end_local_APIC_setup(void) |
1263 | { | |
1264 | lapic_setup_esr(); | |
fa6b95fc CG |
1265 | |
1266 | #ifdef CONFIG_X86_32 | |
1b4ee4e4 CG |
1267 | { |
1268 | unsigned int value; | |
1269 | /* Disable the local apic timer */ | |
1270 | value = apic_read(APIC_LVTT); | |
1271 | value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); | |
1272 | apic_write(APIC_LVTT, value); | |
1273 | } | |
fa6b95fc CG |
1274 | #endif |
1275 | ||
f2802e7f | 1276 | setup_apic_nmi_watchdog(NULL); |
0e078e2f | 1277 | apic_pm_activate(); |
1da177e4 | 1278 | } |
1da177e4 | 1279 | |
49899eac | 1280 | #ifdef HAVE_X2APIC |
6e1cb38a SS |
1281 | void check_x2apic(void) |
1282 | { | |
1283 | int msr, msr2; | |
1284 | ||
1285 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1286 | ||
1287 | if (msr & X2APIC_ENABLE) { | |
ba21ebb6 | 1288 | pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); |
6e1cb38a SS |
1289 | x2apic_preenabled = x2apic = 1; |
1290 | apic_ops = &x2apic_ops; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | void enable_x2apic(void) | |
1295 | { | |
1296 | int msr, msr2; | |
1297 | ||
1298 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
1299 | if (!(msr & X2APIC_ENABLE)) { | |
ba21ebb6 | 1300 | pr_info("Enabling x2apic\n"); |
6e1cb38a SS |
1301 | wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); |
1302 | } | |
1303 | } | |
1304 | ||
2236d252 | 1305 | void __init enable_IR_x2apic(void) |
6e1cb38a SS |
1306 | { |
1307 | #ifdef CONFIG_INTR_REMAP | |
1308 | int ret; | |
1309 | unsigned long flags; | |
1310 | ||
1311 | if (!cpu_has_x2apic) | |
1312 | return; | |
1313 | ||
1314 | if (!x2apic_preenabled && disable_x2apic) { | |
ba21ebb6 CG |
1315 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1316 | "because of nox2apic\n"); | |
6e1cb38a SS |
1317 | return; |
1318 | } | |
1319 | ||
1320 | if (x2apic_preenabled && disable_x2apic) | |
1321 | panic("Bios already enabled x2apic, can't enforce nox2apic"); | |
1322 | ||
1323 | if (!x2apic_preenabled && skip_ioapic_setup) { | |
ba21ebb6 CG |
1324 | pr_info("Skipped enabling x2apic and Interrupt-remapping " |
1325 | "because of skipping io-apic setup\n"); | |
6e1cb38a SS |
1326 | return; |
1327 | } | |
1328 | ||
1329 | ret = dmar_table_init(); | |
1330 | if (ret) { | |
ba21ebb6 | 1331 | pr_info("dmar_table_init() failed with %d:\n", ret); |
6e1cb38a SS |
1332 | |
1333 | if (x2apic_preenabled) | |
1334 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1335 | else | |
ba21ebb6 | 1336 | pr_info("Not enabling x2apic,Intr-remapping\n"); |
6e1cb38a SS |
1337 | return; |
1338 | } | |
1339 | ||
1340 | local_irq_save(flags); | |
1341 | mask_8259A(); | |
5ffa4eb2 CG |
1342 | |
1343 | ret = save_mask_IO_APIC_setup(); | |
1344 | if (ret) { | |
ba21ebb6 | 1345 | pr_info("Saving IO-APIC state failed: %d\n", ret); |
5ffa4eb2 CG |
1346 | goto end; |
1347 | } | |
6e1cb38a SS |
1348 | |
1349 | ret = enable_intr_remapping(1); | |
1350 | ||
1351 | if (ret && x2apic_preenabled) { | |
1352 | local_irq_restore(flags); | |
1353 | panic("x2apic enabled by bios. But IR enabling failed"); | |
1354 | } | |
1355 | ||
1356 | if (ret) | |
5ffa4eb2 | 1357 | goto end_restore; |
6e1cb38a SS |
1358 | |
1359 | if (!x2apic) { | |
1360 | x2apic = 1; | |
1361 | apic_ops = &x2apic_ops; | |
1362 | enable_x2apic(); | |
1363 | } | |
5ffa4eb2 CG |
1364 | |
1365 | end_restore: | |
6e1cb38a SS |
1366 | if (ret) |
1367 | /* | |
1368 | * IR enabling failed | |
1369 | */ | |
1370 | restore_IO_APIC_setup(); | |
1371 | else | |
1372 | reinit_intr_remapped_IO_APIC(x2apic_preenabled); | |
1373 | ||
5ffa4eb2 | 1374 | end: |
6e1cb38a SS |
1375 | unmask_8259A(); |
1376 | local_irq_restore(flags); | |
1377 | ||
1378 | if (!ret) { | |
1379 | if (!x2apic_preenabled) | |
ba21ebb6 | 1380 | pr_info("Enabled x2apic and interrupt-remapping\n"); |
6e1cb38a | 1381 | else |
ba21ebb6 | 1382 | pr_info("Enabled Interrupt-remapping\n"); |
6e1cb38a | 1383 | } else |
ba21ebb6 | 1384 | pr_err("Failed to enable Interrupt-remapping and x2apic\n"); |
6e1cb38a SS |
1385 | #else |
1386 | if (!cpu_has_x2apic) | |
1387 | return; | |
1388 | ||
1389 | if (x2apic_preenabled) | |
1390 | panic("x2apic enabled prior OS handover," | |
1391 | " enable CONFIG_INTR_REMAP"); | |
1392 | ||
ba21ebb6 CG |
1393 | pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " |
1394 | " and x2apic\n"); | |
6e1cb38a SS |
1395 | #endif |
1396 | ||
1397 | return; | |
1398 | } | |
49899eac | 1399 | #endif /* HAVE_X2APIC */ |
6e1cb38a | 1400 | |
be7a656f | 1401 | #ifdef CONFIG_X86_64 |
1da177e4 LT |
1402 | /* |
1403 | * Detect and enable local APICs on non-SMP boards. | |
1404 | * Original code written by Keir Fraser. | |
1405 | * On AMD64 we trust the BIOS - if it says no APIC it is likely | |
6935d1f9 | 1406 | * not correctly set up (usually the APIC timer won't work etc.) |
1da177e4 | 1407 | */ |
0e078e2f | 1408 | static int __init detect_init_APIC(void) |
1da177e4 LT |
1409 | { |
1410 | if (!cpu_has_apic) { | |
ba21ebb6 | 1411 | pr_info("No local APIC present\n"); |
1da177e4 LT |
1412 | return -1; |
1413 | } | |
1414 | ||
1415 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
c70dcb74 | 1416 | boot_cpu_physical_apicid = 0; |
1da177e4 LT |
1417 | return 0; |
1418 | } | |
be7a656f YL |
1419 | #else |
1420 | /* | |
1421 | * Detect and initialize APIC | |
1422 | */ | |
1423 | static int __init detect_init_APIC(void) | |
1424 | { | |
1425 | u32 h, l, features; | |
1426 | ||
1427 | /* Disabled by kernel option? */ | |
1428 | if (disable_apic) | |
1429 | return -1; | |
1430 | ||
1431 | switch (boot_cpu_data.x86_vendor) { | |
1432 | case X86_VENDOR_AMD: | |
1433 | if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || | |
1434 | (boot_cpu_data.x86 == 15)) | |
1435 | break; | |
1436 | goto no_apic; | |
1437 | case X86_VENDOR_INTEL: | |
1438 | if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || | |
1439 | (boot_cpu_data.x86 == 5 && cpu_has_apic)) | |
1440 | break; | |
1441 | goto no_apic; | |
1442 | default: | |
1443 | goto no_apic; | |
1444 | } | |
1445 | ||
1446 | if (!cpu_has_apic) { | |
1447 | /* | |
1448 | * Over-ride BIOS and try to enable the local APIC only if | |
1449 | * "lapic" specified. | |
1450 | */ | |
1451 | if (!force_enable_local_apic) { | |
ba21ebb6 CG |
1452 | pr_info("Local APIC disabled by BIOS -- " |
1453 | "you can enable it with \"lapic\"\n"); | |
be7a656f YL |
1454 | return -1; |
1455 | } | |
1456 | /* | |
1457 | * Some BIOSes disable the local APIC in the APIC_BASE | |
1458 | * MSR. This can only be done in software for Intel P6 or later | |
1459 | * and AMD K7 (Model > 1) or later. | |
1460 | */ | |
1461 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1462 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | |
ba21ebb6 | 1463 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
be7a656f YL |
1464 | l &= ~MSR_IA32_APICBASE_BASE; |
1465 | l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; | |
1466 | wrmsr(MSR_IA32_APICBASE, l, h); | |
1467 | enabled_via_apicbase = 1; | |
1468 | } | |
1469 | } | |
1470 | /* | |
1471 | * The APIC feature bit should now be enabled | |
1472 | * in `cpuid' | |
1473 | */ | |
1474 | features = cpuid_edx(1); | |
1475 | if (!(features & (1 << X86_FEATURE_APIC))) { | |
ba21ebb6 | 1476 | pr_warning("Could not enable APIC!\n"); |
be7a656f YL |
1477 | return -1; |
1478 | } | |
1479 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); | |
1480 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
1481 | ||
1482 | /* The BIOS may have set up the APIC at some other address */ | |
1483 | rdmsr(MSR_IA32_APICBASE, l, h); | |
1484 | if (l & MSR_IA32_APICBASE_ENABLE) | |
1485 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | |
1486 | ||
ba21ebb6 | 1487 | pr_info("Found and enabled local APIC!\n"); |
be7a656f YL |
1488 | |
1489 | apic_pm_activate(); | |
1490 | ||
1491 | return 0; | |
1492 | ||
1493 | no_apic: | |
ba21ebb6 | 1494 | pr_info("No local APIC present or hardware disabled\n"); |
be7a656f YL |
1495 | return -1; |
1496 | } | |
1497 | #endif | |
1da177e4 | 1498 | |
f28c0ae2 | 1499 | #ifdef CONFIG_X86_64 |
8643f9d0 YL |
1500 | void __init early_init_lapic_mapping(void) |
1501 | { | |
431ee79d | 1502 | unsigned long phys_addr; |
8643f9d0 YL |
1503 | |
1504 | /* | |
1505 | * If no local APIC can be found then go out | |
1506 | * : it means there is no mpatable and MADT | |
1507 | */ | |
1508 | if (!smp_found_config) | |
1509 | return; | |
1510 | ||
431ee79d | 1511 | phys_addr = mp_lapic_addr; |
8643f9d0 | 1512 | |
431ee79d | 1513 | set_fixmap_nocache(FIX_APIC_BASE, phys_addr); |
8643f9d0 | 1514 | apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", |
431ee79d | 1515 | APIC_BASE, phys_addr); |
8643f9d0 YL |
1516 | |
1517 | /* | |
1518 | * Fetch the APIC ID of the BSP in case we have a | |
1519 | * default configuration (or the MP table is broken). | |
1520 | */ | |
4c9961d5 | 1521 | boot_cpu_physical_apicid = read_apic_id(); |
8643f9d0 | 1522 | } |
f28c0ae2 | 1523 | #endif |
8643f9d0 | 1524 | |
0e078e2f TG |
1525 | /** |
1526 | * init_apic_mappings - initialize APIC mappings | |
1527 | */ | |
1da177e4 LT |
1528 | void __init init_apic_mappings(void) |
1529 | { | |
49899eac | 1530 | #ifdef HAVE_X2APIC |
6e1cb38a | 1531 | if (x2apic) { |
4c9961d5 | 1532 | boot_cpu_physical_apicid = read_apic_id(); |
6e1cb38a SS |
1533 | return; |
1534 | } | |
49899eac | 1535 | #endif |
6e1cb38a | 1536 | |
1da177e4 LT |
1537 | /* |
1538 | * If no local APIC can be found then set up a fake all | |
1539 | * zeroes page to simulate the local APIC and another | |
1540 | * one for the IO-APIC. | |
1541 | */ | |
1542 | if (!smp_found_config && detect_init_APIC()) { | |
1543 | apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); | |
1544 | apic_phys = __pa(apic_phys); | |
1545 | } else | |
1546 | apic_phys = mp_lapic_addr; | |
1547 | ||
1548 | set_fixmap_nocache(FIX_APIC_BASE, apic_phys); | |
79c09698 | 1549 | apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", |
7ffeeb1e | 1550 | APIC_BASE, apic_phys); |
1da177e4 LT |
1551 | |
1552 | /* | |
1553 | * Fetch the APIC ID of the BSP in case we have a | |
1554 | * default configuration (or the MP table is broken). | |
1555 | */ | |
f28c0ae2 YL |
1556 | if (boot_cpu_physical_apicid == -1U) |
1557 | boot_cpu_physical_apicid = read_apic_id(); | |
1da177e4 LT |
1558 | } |
1559 | ||
1560 | /* | |
0e078e2f TG |
1561 | * This initializes the IO-APIC and APIC hardware if this is |
1562 | * a UP kernel. | |
1da177e4 | 1563 | */ |
1b313f4a CG |
1564 | int apic_version[MAX_APICS]; |
1565 | ||
0e078e2f | 1566 | int __init APIC_init_uniprocessor(void) |
1da177e4 | 1567 | { |
fa2bd35a | 1568 | #ifdef CONFIG_X86_64 |
0e078e2f | 1569 | if (disable_apic) { |
ba21ebb6 | 1570 | pr_info("Apic disabled\n"); |
0e078e2f TG |
1571 | return -1; |
1572 | } | |
1573 | if (!cpu_has_apic) { | |
1574 | disable_apic = 1; | |
ba21ebb6 | 1575 | pr_info("Apic disabled by BIOS\n"); |
0e078e2f TG |
1576 | return -1; |
1577 | } | |
fa2bd35a YL |
1578 | #else |
1579 | if (!smp_found_config && !cpu_has_apic) | |
1580 | return -1; | |
1581 | ||
1582 | /* | |
1583 | * Complain if the BIOS pretends there is one. | |
1584 | */ | |
1585 | if (!cpu_has_apic && | |
1586 | APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
ba21ebb6 CG |
1587 | pr_err("BIOS bug, local APIC 0x%x not detected!...\n", |
1588 | boot_cpu_physical_apicid); | |
fa2bd35a YL |
1589 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); |
1590 | return -1; | |
1591 | } | |
1592 | #endif | |
1593 | ||
49899eac | 1594 | #ifdef HAVE_X2APIC |
6e1cb38a | 1595 | enable_IR_x2apic(); |
49899eac | 1596 | #endif |
fa2bd35a | 1597 | #ifdef CONFIG_X86_64 |
6e1cb38a | 1598 | setup_apic_routing(); |
fa2bd35a | 1599 | #endif |
6e1cb38a | 1600 | |
0e078e2f | 1601 | verify_local_APIC(); |
b5841765 GC |
1602 | connect_bsp_APIC(); |
1603 | ||
fa2bd35a | 1604 | #ifdef CONFIG_X86_64 |
c70dcb74 | 1605 | apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); |
fa2bd35a YL |
1606 | #else |
1607 | /* | |
1608 | * Hack: In case of kdump, after a crash, kernel might be booting | |
1609 | * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid | |
1610 | * might be zero if read from MP tables. Get it from LAPIC. | |
1611 | */ | |
1612 | # ifdef CONFIG_CRASH_DUMP | |
1613 | boot_cpu_physical_apicid = read_apic_id(); | |
1614 | # endif | |
1615 | #endif | |
1616 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); | |
0e078e2f | 1617 | setup_local_APIC(); |
1da177e4 | 1618 | |
fa2bd35a | 1619 | #ifdef CONFIG_X86_64 |
739f33b3 AK |
1620 | /* |
1621 | * Now enable IO-APICs, actually call clear_IO_APIC | |
1622 | * We need clear_IO_APIC before enabling vector on BP | |
1623 | */ | |
1624 | if (!skip_ioapic_setup && nr_ioapics) | |
1625 | enable_IO_APIC(); | |
fa2bd35a | 1626 | #endif |
739f33b3 | 1627 | |
fa2bd35a | 1628 | #ifdef CONFIG_X86_IO_APIC |
acae7d90 | 1629 | if (!smp_found_config || skip_ioapic_setup || !nr_ioapics) |
fa2bd35a | 1630 | #endif |
acae7d90 | 1631 | localise_nmi_watchdog(); |
739f33b3 AK |
1632 | end_local_APIC_setup(); |
1633 | ||
fa2bd35a | 1634 | #ifdef CONFIG_X86_IO_APIC |
0e078e2f TG |
1635 | if (smp_found_config && !skip_ioapic_setup && nr_ioapics) |
1636 | setup_IO_APIC(); | |
fa2bd35a | 1637 | # ifdef CONFIG_X86_64 |
0e078e2f TG |
1638 | else |
1639 | nr_ioapics = 0; | |
fa2bd35a YL |
1640 | # endif |
1641 | #endif | |
1642 | ||
1643 | #ifdef CONFIG_X86_64 | |
0e078e2f TG |
1644 | setup_boot_APIC_clock(); |
1645 | check_nmi_watchdog(); | |
fa2bd35a YL |
1646 | #else |
1647 | setup_boot_clock(); | |
1648 | #endif | |
1649 | ||
0e078e2f | 1650 | return 0; |
1da177e4 LT |
1651 | } |
1652 | ||
1653 | /* | |
0e078e2f | 1654 | * Local APIC interrupts |
1da177e4 LT |
1655 | */ |
1656 | ||
0e078e2f TG |
1657 | /* |
1658 | * This interrupt should _never_ happen with our APIC/SMP architecture | |
1659 | */ | |
dc1528dd | 1660 | void smp_spurious_interrupt(struct pt_regs *regs) |
1da177e4 | 1661 | { |
dc1528dd YL |
1662 | u32 v; |
1663 | ||
0e078e2f TG |
1664 | exit_idle(); |
1665 | irq_enter(); | |
1da177e4 | 1666 | /* |
0e078e2f TG |
1667 | * Check if this really is a spurious interrupt and ACK it |
1668 | * if it is a vectored one. Just in case... | |
1669 | * Spurious interrupts should not be ACKed. | |
1da177e4 | 1670 | */ |
0e078e2f TG |
1671 | v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); |
1672 | if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) | |
1673 | ack_APIC_irq(); | |
c4d58cbd | 1674 | |
915b0d01 HS |
1675 | inc_irq_stat(irq_spurious_count); |
1676 | ||
dc1528dd | 1677 | /* see sw-dev-man vol 3, chapter 7.4.13.5 */ |
ba21ebb6 CG |
1678 | pr_info("spurious APIC interrupt on CPU#%d, " |
1679 | "should never happen.\n", smp_processor_id()); | |
0e078e2f TG |
1680 | irq_exit(); |
1681 | } | |
1da177e4 | 1682 | |
0e078e2f TG |
1683 | /* |
1684 | * This interrupt should never happen with our APIC/SMP architecture | |
1685 | */ | |
dc1528dd | 1686 | void smp_error_interrupt(struct pt_regs *regs) |
0e078e2f | 1687 | { |
dc1528dd | 1688 | u32 v, v1; |
1da177e4 | 1689 | |
0e078e2f TG |
1690 | exit_idle(); |
1691 | irq_enter(); | |
1692 | /* First tickle the hardware, only then report what went on. -- REW */ | |
1693 | v = apic_read(APIC_ESR); | |
1694 | apic_write(APIC_ESR, 0); | |
1695 | v1 = apic_read(APIC_ESR); | |
1696 | ack_APIC_irq(); | |
1697 | atomic_inc(&irq_err_count); | |
ba7eda4c | 1698 | |
ba21ebb6 CG |
1699 | /* |
1700 | * Here is what the APIC error bits mean: | |
1701 | * 0: Send CS error | |
1702 | * 1: Receive CS error | |
1703 | * 2: Send accept error | |
1704 | * 3: Receive accept error | |
1705 | * 4: Reserved | |
1706 | * 5: Send illegal vector | |
1707 | * 6: Received illegal vector | |
1708 | * 7: Illegal register address | |
1709 | */ | |
1710 | pr_debug("APIC error on CPU%d: %02x(%02x)\n", | |
0e078e2f TG |
1711 | smp_processor_id(), v , v1); |
1712 | irq_exit(); | |
1da177e4 LT |
1713 | } |
1714 | ||
b5841765 | 1715 | /** |
36c9d674 CG |
1716 | * connect_bsp_APIC - attach the APIC to the interrupt system |
1717 | */ | |
b5841765 GC |
1718 | void __init connect_bsp_APIC(void) |
1719 | { | |
36c9d674 CG |
1720 | #ifdef CONFIG_X86_32 |
1721 | if (pic_mode) { | |
1722 | /* | |
1723 | * Do not trust the local APIC being empty at bootup. | |
1724 | */ | |
1725 | clear_local_APIC(); | |
1726 | /* | |
1727 | * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's | |
1728 | * local APIC to INT and NMI lines. | |
1729 | */ | |
1730 | apic_printk(APIC_VERBOSE, "leaving PIC mode, " | |
1731 | "enabling APIC mode.\n"); | |
1732 | outb(0x70, 0x22); | |
1733 | outb(0x01, 0x23); | |
1734 | } | |
1735 | #endif | |
b5841765 GC |
1736 | enable_apic_mode(); |
1737 | } | |
1738 | ||
274cfe59 CG |
1739 | /** |
1740 | * disconnect_bsp_APIC - detach the APIC from the interrupt system | |
1741 | * @virt_wire_setup: indicates, whether virtual wire mode is selected | |
1742 | * | |
1743 | * Virtual wire mode is necessary to deliver legacy interrupts even when the | |
1744 | * APIC is disabled. | |
1745 | */ | |
0e078e2f | 1746 | void disconnect_bsp_APIC(int virt_wire_setup) |
1da177e4 | 1747 | { |
1b4ee4e4 CG |
1748 | unsigned int value; |
1749 | ||
c177b0bc CG |
1750 | #ifdef CONFIG_X86_32 |
1751 | if (pic_mode) { | |
1752 | /* | |
1753 | * Put the board back into PIC mode (has an effect only on | |
1754 | * certain older boards). Note that APIC interrupts, including | |
1755 | * IPIs, won't work beyond this point! The only exception are | |
1756 | * INIT IPIs. | |
1757 | */ | |
1758 | apic_printk(APIC_VERBOSE, "disabling APIC mode, " | |
1759 | "entering PIC mode.\n"); | |
1760 | outb(0x70, 0x22); | |
1761 | outb(0x00, 0x23); | |
1762 | return; | |
1763 | } | |
1764 | #endif | |
1765 | ||
0e078e2f | 1766 | /* Go back to Virtual Wire compatibility mode */ |
1da177e4 | 1767 | |
0e078e2f TG |
1768 | /* For the spurious interrupt use vector F, and enable it */ |
1769 | value = apic_read(APIC_SPIV); | |
1770 | value &= ~APIC_VECTOR_MASK; | |
1771 | value |= APIC_SPIV_APIC_ENABLED; | |
1772 | value |= 0xf; | |
1773 | apic_write(APIC_SPIV, value); | |
b8ce3359 | 1774 | |
0e078e2f TG |
1775 | if (!virt_wire_setup) { |
1776 | /* | |
1777 | * For LVT0 make it edge triggered, active high, | |
1778 | * external and enabled | |
1779 | */ | |
1780 | value = apic_read(APIC_LVT0); | |
1781 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1782 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1783 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1784 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1785 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); | |
1786 | apic_write(APIC_LVT0, value); | |
1787 | } else { | |
1788 | /* Disable LVT0 */ | |
1789 | apic_write(APIC_LVT0, APIC_LVT_MASKED); | |
1790 | } | |
b8ce3359 | 1791 | |
c177b0bc CG |
1792 | /* |
1793 | * For LVT1 make it edge triggered, active high, | |
1794 | * nmi and enabled | |
1795 | */ | |
0e078e2f TG |
1796 | value = apic_read(APIC_LVT1); |
1797 | value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | | |
1798 | APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | | |
1799 | APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); | |
1800 | value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; | |
1801 | value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); | |
1802 | apic_write(APIC_LVT1, value); | |
1da177e4 LT |
1803 | } |
1804 | ||
be8a5685 AS |
1805 | void __cpuinit generic_processor_info(int apicid, int version) |
1806 | { | |
1807 | int cpu; | |
be8a5685 | 1808 | |
1b313f4a CG |
1809 | /* |
1810 | * Validate version | |
1811 | */ | |
1812 | if (version == 0x0) { | |
ba21ebb6 | 1813 | pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " |
3b11ce7f MT |
1814 | "fixing up to 0x10. (tell your hw vendor)\n", |
1815 | version); | |
1b313f4a | 1816 | version = 0x10; |
be8a5685 | 1817 | } |
1b313f4a | 1818 | apic_version[apicid] = version; |
be8a5685 | 1819 | |
3b11ce7f MT |
1820 | if (num_processors >= nr_cpu_ids) { |
1821 | int max = nr_cpu_ids; | |
1822 | int thiscpu = max + disabled_cpus; | |
1823 | ||
1824 | pr_warning( | |
1825 | "ACPI: NR_CPUS/possible_cpus limit of %i reached." | |
1826 | " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); | |
1827 | ||
1828 | disabled_cpus++; | |
be8a5685 AS |
1829 | return; |
1830 | } | |
1831 | ||
1832 | num_processors++; | |
3b11ce7f | 1833 | cpu = cpumask_next_zero(-1, cpu_present_mask); |
be8a5685 AS |
1834 | |
1835 | physid_set(apicid, phys_cpu_present_map); | |
1836 | if (apicid == boot_cpu_physical_apicid) { | |
1837 | /* | |
1838 | * x86_bios_cpu_apicid is required to have processors listed | |
1839 | * in same order as logical cpu numbers. Hence the first | |
1840 | * entry is BSP, and so on. | |
1841 | */ | |
1842 | cpu = 0; | |
1843 | } | |
e0da3364 YL |
1844 | if (apicid > max_physical_apicid) |
1845 | max_physical_apicid = apicid; | |
1846 | ||
1b313f4a CG |
1847 | #ifdef CONFIG_X86_32 |
1848 | /* | |
1849 | * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y | |
1850 | * but we need to work other dependencies like SMP_SUSPEND etc | |
1851 | * before this can be done without some confusion. | |
1852 | * if (CPU_HOTPLUG_ENABLED || num_processors > 8) | |
1853 | * - Ashok Raj <ashok.raj@intel.com> | |
1854 | */ | |
1855 | if (max_physical_apicid >= 8) { | |
1856 | switch (boot_cpu_data.x86_vendor) { | |
1857 | case X86_VENDOR_INTEL: | |
1858 | if (!APIC_XAPIC(version)) { | |
1859 | def_to_bigsmp = 0; | |
1860 | break; | |
1861 | } | |
1862 | /* If P4 and above fall through */ | |
1863 | case X86_VENDOR_AMD: | |
1864 | def_to_bigsmp = 1; | |
1865 | } | |
1866 | } | |
1867 | #endif | |
1868 | ||
1869 | #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64) | |
be8a5685 | 1870 | /* are we being called early in kernel startup? */ |
23ca4bba MT |
1871 | if (early_per_cpu_ptr(x86_cpu_to_apicid)) { |
1872 | u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid); | |
1873 | u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); | |
be8a5685 AS |
1874 | |
1875 | cpu_to_apicid[cpu] = apicid; | |
1876 | bios_cpu_apicid[cpu] = apicid; | |
1877 | } else { | |
1878 | per_cpu(x86_cpu_to_apicid, cpu) = apicid; | |
1879 | per_cpu(x86_bios_cpu_apicid, cpu) = apicid; | |
1880 | } | |
1b313f4a | 1881 | #endif |
be8a5685 | 1882 | |
1de88cd4 MT |
1883 | set_cpu_possible(cpu, true); |
1884 | set_cpu_present(cpu, true); | |
be8a5685 AS |
1885 | } |
1886 | ||
3491998d | 1887 | #ifdef CONFIG_X86_64 |
0c81c746 SS |
1888 | int hard_smp_processor_id(void) |
1889 | { | |
1890 | return read_apic_id(); | |
1891 | } | |
3491998d | 1892 | #endif |
0c81c746 | 1893 | |
89039b37 | 1894 | /* |
0e078e2f | 1895 | * Power management |
89039b37 | 1896 | */ |
0e078e2f TG |
1897 | #ifdef CONFIG_PM |
1898 | ||
1899 | static struct { | |
274cfe59 CG |
1900 | /* |
1901 | * 'active' is true if the local APIC was enabled by us and | |
1902 | * not the BIOS; this signifies that we are also responsible | |
1903 | * for disabling it before entering apm/acpi suspend | |
1904 | */ | |
0e078e2f TG |
1905 | int active; |
1906 | /* r/w apic fields */ | |
1907 | unsigned int apic_id; | |
1908 | unsigned int apic_taskpri; | |
1909 | unsigned int apic_ldr; | |
1910 | unsigned int apic_dfr; | |
1911 | unsigned int apic_spiv; | |
1912 | unsigned int apic_lvtt; | |
1913 | unsigned int apic_lvtpc; | |
1914 | unsigned int apic_lvt0; | |
1915 | unsigned int apic_lvt1; | |
1916 | unsigned int apic_lvterr; | |
1917 | unsigned int apic_tmict; | |
1918 | unsigned int apic_tdcr; | |
1919 | unsigned int apic_thmr; | |
1920 | } apic_pm_state; | |
1921 | ||
1922 | static int lapic_suspend(struct sys_device *dev, pm_message_t state) | |
1923 | { | |
1924 | unsigned long flags; | |
1925 | int maxlvt; | |
89039b37 | 1926 | |
0e078e2f TG |
1927 | if (!apic_pm_state.active) |
1928 | return 0; | |
89039b37 | 1929 | |
0e078e2f | 1930 | maxlvt = lapic_get_maxlvt(); |
89039b37 | 1931 | |
2d7a66d0 | 1932 | apic_pm_state.apic_id = apic_read(APIC_ID); |
0e078e2f TG |
1933 | apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); |
1934 | apic_pm_state.apic_ldr = apic_read(APIC_LDR); | |
1935 | apic_pm_state.apic_dfr = apic_read(APIC_DFR); | |
1936 | apic_pm_state.apic_spiv = apic_read(APIC_SPIV); | |
1937 | apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); | |
1938 | if (maxlvt >= 4) | |
1939 | apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); | |
1940 | apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); | |
1941 | apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); | |
1942 | apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); | |
1943 | apic_pm_state.apic_tmict = apic_read(APIC_TMICT); | |
1944 | apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); | |
24968cfd | 1945 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1946 | if (maxlvt >= 5) |
1947 | apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); | |
1948 | #endif | |
24968cfd | 1949 | |
0e078e2f TG |
1950 | local_irq_save(flags); |
1951 | disable_local_APIC(); | |
1952 | local_irq_restore(flags); | |
1953 | return 0; | |
1da177e4 LT |
1954 | } |
1955 | ||
0e078e2f | 1956 | static int lapic_resume(struct sys_device *dev) |
1da177e4 | 1957 | { |
0e078e2f TG |
1958 | unsigned int l, h; |
1959 | unsigned long flags; | |
1960 | int maxlvt; | |
1da177e4 | 1961 | |
0e078e2f TG |
1962 | if (!apic_pm_state.active) |
1963 | return 0; | |
89b831ef | 1964 | |
0e078e2f | 1965 | maxlvt = lapic_get_maxlvt(); |
1da177e4 | 1966 | |
0e078e2f | 1967 | local_irq_save(flags); |
92206c90 | 1968 | |
49899eac | 1969 | #ifdef HAVE_X2APIC |
92206c90 CG |
1970 | if (x2apic) |
1971 | enable_x2apic(); | |
1972 | else | |
1973 | #endif | |
d5e629a6 | 1974 | { |
92206c90 CG |
1975 | /* |
1976 | * Make sure the APICBASE points to the right address | |
1977 | * | |
1978 | * FIXME! This will be wrong if we ever support suspend on | |
1979 | * SMP! We'll need to do this as part of the CPU restore! | |
1980 | */ | |
6e1cb38a SS |
1981 | rdmsr(MSR_IA32_APICBASE, l, h); |
1982 | l &= ~MSR_IA32_APICBASE_BASE; | |
1983 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | |
1984 | wrmsr(MSR_IA32_APICBASE, l, h); | |
d5e629a6 | 1985 | } |
6e1cb38a | 1986 | |
0e078e2f TG |
1987 | apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); |
1988 | apic_write(APIC_ID, apic_pm_state.apic_id); | |
1989 | apic_write(APIC_DFR, apic_pm_state.apic_dfr); | |
1990 | apic_write(APIC_LDR, apic_pm_state.apic_ldr); | |
1991 | apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); | |
1992 | apic_write(APIC_SPIV, apic_pm_state.apic_spiv); | |
1993 | apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); | |
1994 | apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); | |
92206c90 | 1995 | #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) |
0e078e2f TG |
1996 | if (maxlvt >= 5) |
1997 | apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); | |
1998 | #endif | |
1999 | if (maxlvt >= 4) | |
2000 | apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); | |
2001 | apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); | |
2002 | apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); | |
2003 | apic_write(APIC_TMICT, apic_pm_state.apic_tmict); | |
2004 | apic_write(APIC_ESR, 0); | |
2005 | apic_read(APIC_ESR); | |
2006 | apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); | |
2007 | apic_write(APIC_ESR, 0); | |
2008 | apic_read(APIC_ESR); | |
92206c90 | 2009 | |
0e078e2f | 2010 | local_irq_restore(flags); |
92206c90 | 2011 | |
0e078e2f TG |
2012 | return 0; |
2013 | } | |
b8ce3359 | 2014 | |
274cfe59 CG |
2015 | /* |
2016 | * This device has no shutdown method - fully functioning local APICs | |
2017 | * are needed on every CPU up until machine_halt/restart/poweroff. | |
2018 | */ | |
2019 | ||
0e078e2f TG |
2020 | static struct sysdev_class lapic_sysclass = { |
2021 | .name = "lapic", | |
2022 | .resume = lapic_resume, | |
2023 | .suspend = lapic_suspend, | |
2024 | }; | |
b8ce3359 | 2025 | |
0e078e2f | 2026 | static struct sys_device device_lapic = { |
e83a5fdc HS |
2027 | .id = 0, |
2028 | .cls = &lapic_sysclass, | |
0e078e2f | 2029 | }; |
b8ce3359 | 2030 | |
0e078e2f TG |
2031 | static void __cpuinit apic_pm_activate(void) |
2032 | { | |
2033 | apic_pm_state.active = 1; | |
1da177e4 LT |
2034 | } |
2035 | ||
0e078e2f | 2036 | static int __init init_lapic_sysfs(void) |
1da177e4 | 2037 | { |
0e078e2f | 2038 | int error; |
e83a5fdc | 2039 | |
0e078e2f TG |
2040 | if (!cpu_has_apic) |
2041 | return 0; | |
2042 | /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ | |
e83a5fdc | 2043 | |
0e078e2f TG |
2044 | error = sysdev_class_register(&lapic_sysclass); |
2045 | if (!error) | |
2046 | error = sysdev_register(&device_lapic); | |
2047 | return error; | |
1da177e4 | 2048 | } |
0e078e2f TG |
2049 | device_initcall(init_lapic_sysfs); |
2050 | ||
2051 | #else /* CONFIG_PM */ | |
2052 | ||
2053 | static void apic_pm_activate(void) { } | |
2054 | ||
2055 | #endif /* CONFIG_PM */ | |
1da177e4 | 2056 | |
f28c0ae2 | 2057 | #ifdef CONFIG_X86_64 |
1da177e4 | 2058 | /* |
f8bf3c65 | 2059 | * apic_is_clustered_box() -- Check if we can expect good TSC |
1da177e4 LT |
2060 | * |
2061 | * Thus far, the major user of this is IBM's Summit2 series: | |
2062 | * | |
637029c6 | 2063 | * Clustered boxes may have unsynced TSC problems if they are |
1da177e4 LT |
2064 | * multi-chassis. Use available data to take a good guess. |
2065 | * If in doubt, go HPET. | |
2066 | */ | |
f8bf3c65 | 2067 | __cpuinit int apic_is_clustered_box(void) |
1da177e4 LT |
2068 | { |
2069 | int i, clusters, zeros; | |
2070 | unsigned id; | |
322850af | 2071 | u16 *bios_cpu_apicid; |
1da177e4 LT |
2072 | DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); |
2073 | ||
322850af YL |
2074 | /* |
2075 | * there is not this kind of box with AMD CPU yet. | |
2076 | * Some AMD box with quadcore cpu and 8 sockets apicid | |
2077 | * will be [4, 0x23] or [8, 0x27] could be thought to | |
f8fffa45 | 2078 | * vsmp box still need checking... |
322850af | 2079 | */ |
1cb68487 | 2080 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) |
322850af YL |
2081 | return 0; |
2082 | ||
23ca4bba | 2083 | bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); |
376ec33f | 2084 | bitmap_zero(clustermap, NUM_APIC_CLUSTERS); |
1da177e4 | 2085 | |
168ef543 | 2086 | for (i = 0; i < nr_cpu_ids; i++) { |
e8c10ef9 | 2087 | /* are we being called early in kernel startup? */ |
693e3c56 MT |
2088 | if (bios_cpu_apicid) { |
2089 | id = bios_cpu_apicid[i]; | |
e8c10ef9 | 2090 | } |
2091 | else if (i < nr_cpu_ids) { | |
2092 | if (cpu_present(i)) | |
2093 | id = per_cpu(x86_bios_cpu_apicid, i); | |
2094 | else | |
2095 | continue; | |
2096 | } | |
2097 | else | |
2098 | break; | |
2099 | ||
1da177e4 LT |
2100 | if (id != BAD_APICID) |
2101 | __set_bit(APIC_CLUSTERID(id), clustermap); | |
2102 | } | |
2103 | ||
2104 | /* Problem: Partially populated chassis may not have CPUs in some of | |
2105 | * the APIC clusters they have been allocated. Only present CPUs have | |
602a54a8 | 2106 | * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. |
2107 | * Since clusters are allocated sequentially, count zeros only if | |
2108 | * they are bounded by ones. | |
1da177e4 LT |
2109 | */ |
2110 | clusters = 0; | |
2111 | zeros = 0; | |
2112 | for (i = 0; i < NUM_APIC_CLUSTERS; i++) { | |
2113 | if (test_bit(i, clustermap)) { | |
2114 | clusters += 1 + zeros; | |
2115 | zeros = 0; | |
2116 | } else | |
2117 | ++zeros; | |
2118 | } | |
2119 | ||
1cb68487 RT |
2120 | /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are |
2121 | * not guaranteed to be synced between boards | |
2122 | */ | |
2123 | if (is_vsmp_box() && clusters > 1) | |
2124 | return 1; | |
2125 | ||
1da177e4 | 2126 | /* |
f8bf3c65 | 2127 | * If clusters > 2, then should be multi-chassis. |
1da177e4 LT |
2128 | * May have to revisit this when multi-core + hyperthreaded CPUs come |
2129 | * out, but AFAIK this will work even for them. | |
2130 | */ | |
2131 | return (clusters > 2); | |
2132 | } | |
f28c0ae2 | 2133 | #endif |
1da177e4 LT |
2134 | |
2135 | /* | |
0e078e2f | 2136 | * APIC command line parameters |
1da177e4 | 2137 | */ |
789fa735 | 2138 | static int __init setup_disableapic(char *arg) |
6935d1f9 | 2139 | { |
1da177e4 | 2140 | disable_apic = 1; |
9175fc06 | 2141 | setup_clear_cpu_cap(X86_FEATURE_APIC); |
2c8c0e6b AK |
2142 | return 0; |
2143 | } | |
2144 | early_param("disableapic", setup_disableapic); | |
1da177e4 | 2145 | |
2c8c0e6b | 2146 | /* same as disableapic, for compatibility */ |
789fa735 | 2147 | static int __init setup_nolapic(char *arg) |
6935d1f9 | 2148 | { |
789fa735 | 2149 | return setup_disableapic(arg); |
6935d1f9 | 2150 | } |
2c8c0e6b | 2151 | early_param("nolapic", setup_nolapic); |
1da177e4 | 2152 | |
2e7c2838 LT |
2153 | static int __init parse_lapic_timer_c2_ok(char *arg) |
2154 | { | |
2155 | local_apic_timer_c2_ok = 1; | |
2156 | return 0; | |
2157 | } | |
2158 | early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); | |
2159 | ||
36fef094 | 2160 | static int __init parse_disable_apic_timer(char *arg) |
6935d1f9 | 2161 | { |
1da177e4 | 2162 | disable_apic_timer = 1; |
36fef094 | 2163 | return 0; |
6935d1f9 | 2164 | } |
36fef094 CG |
2165 | early_param("noapictimer", parse_disable_apic_timer); |
2166 | ||
2167 | static int __init parse_nolapic_timer(char *arg) | |
2168 | { | |
2169 | disable_apic_timer = 1; | |
2170 | return 0; | |
6935d1f9 | 2171 | } |
36fef094 | 2172 | early_param("nolapic_timer", parse_nolapic_timer); |
73dea47f | 2173 | |
79af9bec CG |
2174 | static int __init apic_set_verbosity(char *arg) |
2175 | { | |
2176 | if (!arg) { | |
2177 | #ifdef CONFIG_X86_64 | |
2178 | skip_ioapic_setup = 0; | |
79af9bec CG |
2179 | return 0; |
2180 | #endif | |
2181 | return -EINVAL; | |
2182 | } | |
2183 | ||
2184 | if (strcmp("debug", arg) == 0) | |
2185 | apic_verbosity = APIC_DEBUG; | |
2186 | else if (strcmp("verbose", arg) == 0) | |
2187 | apic_verbosity = APIC_VERBOSE; | |
2188 | else { | |
ba21ebb6 | 2189 | pr_warning("APIC Verbosity level %s not recognised" |
79af9bec CG |
2190 | " use apic=verbose or apic=debug\n", arg); |
2191 | return -EINVAL; | |
2192 | } | |
2193 | ||
2194 | return 0; | |
2195 | } | |
2196 | early_param("apic", apic_set_verbosity); | |
2197 | ||
1e934dda YL |
2198 | static int __init lapic_insert_resource(void) |
2199 | { | |
2200 | if (!apic_phys) | |
2201 | return -1; | |
2202 | ||
2203 | /* Put local APIC into the resource map. */ | |
2204 | lapic_resource.start = apic_phys; | |
2205 | lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; | |
2206 | insert_resource(&iomem_resource, &lapic_resource); | |
2207 | ||
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | /* | |
2212 | * need call insert after e820_reserve_resources() | |
2213 | * that is using request_resource | |
2214 | */ | |
2215 | late_initcall(lapic_insert_resource); |