Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
c8f730b1 | 8 | * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
0b1da1c8 | 28 | |
ac23d4ee JS |
29 | #include <asm/uv/uv_mmrs.h> |
30 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
31 | #include <asm/current.h> |
32 | #include <asm/pgtable.h> | |
7019cc2d | 33 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
34 | #include <asm/uv/uv.h> |
35 | #include <asm/apic.h> | |
36 | #include <asm/ipi.h> | |
37 | #include <asm/smp.h> | |
fd12a0d6 | 38 | #include <asm/x86_init.h> |
818987e9 | 39 | #include <asm/emergency-restart.h> |
1d44e828 JS |
40 | #include <asm/nmi.h> |
41 | ||
42 | /* BMC sets a bit this MMR non-zero before sending an NMI */ | |
43 | #define UVH_NMI_MMR UVH_SCRATCH5 | |
44 | #define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8) | |
45 | #define UV_NMI_PENDING_MASK (1UL << 63) | |
46 | DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count); | |
ac23d4ee | 47 | |
510b3725 YL |
48 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
49 | ||
841582ea MT |
50 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
51 | ||
1b9b89e7 | 52 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 53 | static u64 gru_start_paddr, gru_end_paddr; |
c8f730b1 | 54 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
55 | int uv_min_hub_revision_id; |
56 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
57 | unsigned int uv_apicid_hibits; |
58 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
78c06176 | 59 | static DEFINE_SPINLOCK(uv_nmi_lock); |
fd12a0d6 | 60 | |
1a8880a1 SS |
61 | static struct apic apic_x2apic_uv_x; |
62 | ||
e6810413 JS |
63 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
64 | { | |
65 | unsigned long val, *mmr; | |
66 | ||
67 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
68 | val = *mmr; | |
69 | early_iounmap(mmr, sizeof(*mmr)); | |
70 | return val; | |
71 | } | |
72 | ||
eb41c8be | 73 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 74 | { |
ccef0864 | 75 | return start >= gru_start_paddr && end <= gru_end_paddr; |
fd12a0d6 JS |
76 | } |
77 | ||
eb41c8be | 78 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
79 | { |
80 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
81 | } | |
1b9b89e7 | 82 | |
d8850ba4 | 83 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
84 | { |
85 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
86 | union uvh_rh_gam_config_mmr_u m_n_config; |
87 | int pnode; | |
7a1110e8 JS |
88 | |
89 | /* Currently, all blades have same revision number */ | |
e6810413 | 90 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 91 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
92 | uv_min_hub_revision_id = node_id.s.revision; |
93 | ||
2a919596 JS |
94 | if (node_id.s.part_number == UV2_HUB_PART_NUMBER) |
95 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; | |
b495e039 JS |
96 | if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X) |
97 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; | |
2a919596 JS |
98 | |
99 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
d8850ba4 JS |
100 | pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); |
101 | return pnode; | |
27229ca6 JS |
102 | } |
103 | ||
0520bd84 | 104 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 | 105 | { |
e6810413 | 106 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
c8f730b1 RA |
107 | if (!uvh_apicid.v) |
108 | /* | |
109 | * Old bios, use default value | |
110 | */ | |
111 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
112 | } |
113 | ||
8191c9f6 DS |
114 | /* |
115 | * Add an extra bit as dictated by bios to the destination apicid of | |
116 | * interrupts potentially passing through the UV HUB. This prevents | |
117 | * a deadlock between interrupts and IO port operations. | |
118 | */ | |
119 | static void __init uv_set_apicid_hibit(void) | |
120 | { | |
2a919596 | 121 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 122 | |
2a919596 JS |
123 | if (is_uv1_hub()) { |
124 | apicid_mask.v = | |
125 | uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); | |
126 | uv_apicid_hibits = | |
127 | apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
128 | } | |
8191c9f6 DS |
129 | } |
130 | ||
52459ab9 | 131 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 132 | { |
2a919596 | 133 | int pnodeid, is_uv1, is_uv2; |
1d2c867c | 134 | |
2a919596 JS |
135 | is_uv1 = !strcmp(oem_id, "SGI"); |
136 | is_uv2 = !strcmp(oem_id, "SGI2"); | |
137 | if (is_uv1 || is_uv2) { | |
138 | uv_hub_info->hub_revision = | |
139 | is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE; | |
d8850ba4 | 140 | pnodeid = early_get_pnodeid(); |
0520bd84 | 141 | early_get_apic_pnode_shift(); |
fd12a0d6 | 142 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; |
78c06176 | 143 | x86_platform.nmi_init = uv_nmi_init; |
1b9b89e7 YL |
144 | if (!strcmp(oem_table_id, "UVL")) |
145 | uv_system_type = UV_LEGACY_APIC; | |
146 | else if (!strcmp(oem_table_id, "UVX")) | |
147 | uv_system_type = UV_X2APIC; | |
148 | else if (!strcmp(oem_table_id, "UVH")) { | |
0a3aee0d | 149 | __this_cpu_write(x2apic_extra_bits, |
72eb6a79 | 150 | pnodeid << uvh_apicid.s.pnode_shift); |
1b9b89e7 | 151 | uv_system_type = UV_NON_UNIQUE_APIC; |
8191c9f6 | 152 | uv_set_apicid_hibit(); |
1b9b89e7 YL |
153 | return 1; |
154 | } | |
155 | } | |
156 | return 0; | |
157 | } | |
158 | ||
159 | enum uv_system_type get_uv_system_type(void) | |
160 | { | |
161 | return uv_system_type; | |
162 | } | |
163 | ||
164 | int is_uv_system(void) | |
165 | { | |
166 | return uv_system_type != UV_NONE; | |
167 | } | |
8067794b | 168 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 169 | |
ac23d4ee JS |
170 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
171 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
172 | ||
173 | struct uv_blade_info *uv_blade_info; | |
174 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
175 | ||
176 | short *uv_node_to_blade; | |
177 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
178 | ||
179 | short *uv_cpu_to_blade; | |
180 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
181 | ||
182 | short uv_possible_blades; | |
183 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
184 | ||
7019cc2d RA |
185 | unsigned long sn_rtc_cycles_per_second; |
186 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
187 | ||
667c5296 | 188 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee | 189 | { |
0b1da1c8 | 190 | #ifdef CONFIG_SMP |
ac23d4ee | 191 | unsigned long val; |
9f5314fb | 192 | int pnode; |
ac23d4ee | 193 | |
9f5314fb | 194 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 195 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
196 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
197 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 198 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 199 | APIC_DM_INIT; |
9f5314fb | 200 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
201 | |
202 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
203 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 204 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 205 | APIC_DM_STARTUP; |
9f5314fb | 206 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf YL |
207 | |
208 | atomic_set(&init_deasserted, 1); | |
0b1da1c8 | 209 | #endif |
ac23d4ee JS |
210 | return 0; |
211 | } | |
212 | ||
213 | static void uv_send_IPI_one(int cpu, int vector) | |
214 | { | |
66666e50 | 215 | unsigned long apicid; |
9f5314fb | 216 | int pnode; |
ac23d4ee | 217 | |
1e0b5d00 | 218 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 219 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 220 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
221 | } |
222 | ||
bcda016e | 223 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
224 | { |
225 | unsigned int cpu; | |
226 | ||
bcda016e | 227 | for_each_cpu(cpu, mask) |
e7986739 MT |
228 | uv_send_IPI_one(cpu, vector); |
229 | } | |
230 | ||
bcda016e | 231 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 232 | { |
e7986739 | 233 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 234 | unsigned int cpu; |
e7986739 | 235 | |
dac5f412 | 236 | for_each_cpu(cpu, mask) { |
e7986739 | 237 | if (cpu != this_cpu) |
ac23d4ee | 238 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 239 | } |
ac23d4ee JS |
240 | } |
241 | ||
242 | static void uv_send_IPI_allbutself(int vector) | |
243 | { | |
e7986739 | 244 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 245 | unsigned int cpu; |
ac23d4ee | 246 | |
dac5f412 | 247 | for_each_online_cpu(cpu) { |
e7986739 MT |
248 | if (cpu != this_cpu) |
249 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 250 | } |
ac23d4ee JS |
251 | } |
252 | ||
253 | static void uv_send_IPI_all(int vector) | |
254 | { | |
bcda016e | 255 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
256 | } |
257 | ||
b7157acf SP |
258 | static int uv_apic_id_valid(int apicid) |
259 | { | |
260 | return 1; | |
261 | } | |
262 | ||
ac23d4ee JS |
263 | static int uv_apic_id_registered(void) |
264 | { | |
265 | return 1; | |
266 | } | |
267 | ||
277d1f58 | 268 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
269 | { |
270 | } | |
271 | ||
ff164324 AG |
272 | static inline int __uv_cpu_to_apicid(int cpu, unsigned int *apicid) |
273 | { | |
274 | if (likely((unsigned int)cpu < nr_cpu_ids)) { | |
275 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; | |
276 | return 0; | |
277 | } else { | |
278 | return -EINVAL; | |
279 | } | |
280 | } | |
281 | ||
282 | static int | |
283 | uv_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *apicid) | |
ac23d4ee | 284 | { |
ac23d4ee JS |
285 | /* |
286 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
287 | * May as well be the first. | |
288 | */ | |
debccb3e | 289 | int cpu = cpumask_first(cpumask); |
ff164324 | 290 | return __uv_cpu_to_apicid(cpu, apicid); |
ac23d4ee JS |
291 | } |
292 | ||
ff164324 | 293 | static int |
debccb3e | 294 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
295 | const struct cpumask *andmask, |
296 | unsigned int *apicid) | |
95d313cf MT |
297 | { |
298 | int cpu; | |
299 | ||
300 | /* | |
301 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
302 | * May as well be the first. | |
303 | */ | |
debccb3e | 304 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
305 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
306 | break; | |
debccb3e | 307 | } |
ff164324 AG |
308 | |
309 | return __uv_cpu_to_apicid(cpu, apicid); | |
95d313cf MT |
310 | } |
311 | ||
ca6c8ed4 | 312 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
313 | { |
314 | unsigned int id; | |
315 | ||
316 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 317 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
318 | |
319 | return id; | |
320 | } | |
321 | ||
1b9b89e7 | 322 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
323 | { |
324 | unsigned long x; | |
325 | ||
326 | /* maskout x2apic_extra_bits ? */ | |
327 | x = id; | |
328 | return x; | |
329 | } | |
330 | ||
331 | static unsigned int uv_read_apic_id(void) | |
332 | { | |
333 | ||
ca6c8ed4 | 334 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
335 | } |
336 | ||
d4c9a9f3 | 337 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 338 | { |
0c81c746 | 339 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
340 | } |
341 | ||
ac23d4ee JS |
342 | static void uv_send_IPI_self(int vector) |
343 | { | |
344 | apic_write(APIC_SELF_IPI, vector); | |
345 | } | |
ac23d4ee | 346 | |
9ebd680b SS |
347 | static int uv_probe(void) |
348 | { | |
349 | return apic == &apic_x2apic_uv_x; | |
350 | } | |
351 | ||
1a8880a1 | 352 | static struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
353 | |
354 | .name = "UV large system", | |
9ebd680b | 355 | .probe = uv_probe, |
c7967329 | 356 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 357 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
358 | .apic_id_registered = uv_apic_id_registered, |
359 | ||
f8987a10 | 360 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 361 | .irq_dest_mode = 0, /* physical */ |
c7967329 | 362 | |
bf721d3a | 363 | .target_cpus = online_target_cpus, |
08125d3e | 364 | .disable_esr = 0, |
bdb1a9b6 | 365 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 IM |
366 | .check_apicid_used = NULL, |
367 | .check_apicid_present = NULL, | |
368 | ||
9d8e1066 | 369 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
370 | .init_apic_ldr = uv_init_apic_ldr, |
371 | ||
372 | .ioapic_phys_id_map = NULL, | |
373 | .setup_apic_routing = NULL, | |
374 | .multi_timer_check = NULL, | |
a21769a4 | 375 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 IM |
376 | .apicid_to_cpu_present = NULL, |
377 | .setup_portio_remap = NULL, | |
a27a6210 | 378 | .check_phys_apicid_present = default_check_phys_apicid_present, |
c7967329 | 379 | .enable_apic_mode = NULL, |
d4c9a9f3 | 380 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 IM |
381 | .mps_oem_check = NULL, |
382 | ||
ca6c8ed4 | 383 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
384 | .set_apic_id = set_apic_id, |
385 | .apic_id_mask = 0xFFFFFFFFu, | |
386 | ||
387 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | |
388 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | |
389 | ||
390 | .send_IPI_mask = uv_send_IPI_mask, | |
391 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
392 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
393 | .send_IPI_all = uv_send_IPI_all, | |
394 | .send_IPI_self = uv_send_IPI_self, | |
395 | ||
1f5bcabf | 396 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
abfa584c IM |
397 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
398 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
c7967329 IM |
399 | .wait_for_init_deassert = NULL, |
400 | .smp_callin_clear_local_apic = NULL, | |
c7967329 | 401 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
402 | |
403 | .read = native_apic_msr_read, | |
404 | .write = native_apic_msr_write, | |
0ab711ae | 405 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
406 | .icr_read = native_x2apic_icr_read, |
407 | .icr_write = native_x2apic_icr_write, | |
408 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
409 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
410 | }; |
411 | ||
9f5314fb | 412 | static __cpuinit void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 413 | { |
16ee8db6 | 414 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
415 | } |
416 | ||
417 | /* | |
418 | * Called on boot cpu. | |
419 | */ | |
9f5314fb JS |
420 | static __init int boot_pnode_to_blade(int pnode) |
421 | { | |
422 | int blade; | |
423 | ||
424 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
425 | if (pnode == uv_blade_info[blade].pnode) | |
426 | return blade; | |
427 | BUG(); | |
428 | } | |
429 | ||
430 | struct redir_addr { | |
431 | unsigned long redirect; | |
432 | unsigned long alias; | |
433 | }; | |
434 | ||
435 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT | |
436 | ||
437 | static __initdata struct redir_addr redir_addrs[] = { | |
62b0cfc2 JS |
438 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, |
439 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, | |
440 | {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, | |
9f5314fb JS |
441 | }; |
442 | ||
443 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) | |
444 | { | |
62b0cfc2 | 445 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb JS |
446 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
447 | int i; | |
448 | ||
449 | for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { | |
450 | alias.v = uv_read_local_mmr(redir_addrs[i].alias); | |
036ed8ba | 451 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb JS |
452 | *size = (1UL << alias.s.m_alias); |
453 | redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); | |
454 | *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; | |
455 | return; | |
456 | } | |
457 | } | |
036ed8ba | 458 | *base = *size = 0; |
9f5314fb JS |
459 | } |
460 | ||
83f5d894 JS |
461 | enum map_type {map_wb, map_uc}; |
462 | ||
fcfbb2b5 MT |
463 | static __init void map_high(char *id, unsigned long base, int pshift, |
464 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
465 | { |
466 | unsigned long bytes, paddr; | |
467 | ||
fcfbb2b5 MT |
468 | paddr = base << pshift; |
469 | bytes = (1UL << bshift) * (max_pnode + 1); | |
83f5d894 | 470 | printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, |
0b1da1c8 | 471 | paddr + bytes); |
83f5d894 JS |
472 | if (map_type == map_uc) |
473 | init_extra_mapping_uc(paddr, bytes); | |
474 | else | |
475 | init_extra_mapping_wb(paddr, bytes); | |
476 | ||
477 | } | |
478 | static __init void map_gru_high(int max_pnode) | |
479 | { | |
480 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
481 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
482 | ||
483 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
fd12a0d6 | 484 | if (gru.s.enable) { |
fcfbb2b5 | 485 | map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); |
fd12a0d6 JS |
486 | gru_start_paddr = ((u64)gru.s.base << shift); |
487 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); | |
488 | ||
489 | } | |
83f5d894 JS |
490 | } |
491 | ||
daf7b9c9 JS |
492 | static __init void map_mmr_high(int max_pnode) |
493 | { | |
494 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
495 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
496 | ||
497 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
498 | if (mmr.s.enable) | |
fcfbb2b5 | 499 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
daf7b9c9 JS |
500 | } |
501 | ||
83f5d894 JS |
502 | static __init void map_mmioh_high(int max_pnode) |
503 | { | |
504 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
2a919596 | 505 | int shift; |
83f5d894 JS |
506 | |
507 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); | |
2a919596 JS |
508 | if (is_uv1_hub() && mmioh.s1.enable) { |
509 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
510 | map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io, | |
511 | max_pnode, map_uc); | |
512 | } | |
513 | if (is_uv2_hub() && mmioh.s2.enable) { | |
514 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
515 | map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io, | |
fcfbb2b5 | 516 | max_pnode, map_uc); |
2a919596 | 517 | } |
83f5d894 JS |
518 | } |
519 | ||
918bc960 JS |
520 | static __init void map_low_mmrs(void) |
521 | { | |
522 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
523 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
524 | } | |
525 | ||
7019cc2d RA |
526 | static __init void uv_rtc_init(void) |
527 | { | |
922402f1 RA |
528 | long status; |
529 | u64 ticks_per_sec; | |
7019cc2d | 530 | |
922402f1 RA |
531 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
532 | &ticks_per_sec); | |
533 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
534 | printk(KERN_WARNING |
535 | "unable to determine platform RTC clock frequency, " | |
536 | "guessing.\n"); | |
537 | /* BIOS gives wrong value for clock freq. so guess */ | |
538 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
539 | } else | |
540 | sn_rtc_cycles_per_second = ticks_per_sec; | |
541 | } | |
542 | ||
7f1baa06 MT |
543 | /* |
544 | * percpu heartbeat timer | |
545 | */ | |
546 | static void uv_heartbeat(unsigned long ignored) | |
547 | { | |
548 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
549 | unsigned char bits = uv_hub_info->scir.state; | |
550 | ||
551 | /* flip heartbeat bit */ | |
552 | bits ^= SCIR_CPU_HEARTBEAT; | |
553 | ||
69a72a0e MT |
554 | /* is this cpu idle? */ |
555 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
556 | bits &= ~SCIR_CPU_ACTIVITY; |
557 | else | |
558 | bits |= SCIR_CPU_ACTIVITY; | |
559 | ||
560 | /* update system controller interface reg */ | |
561 | uv_set_scir_bits(bits); | |
562 | ||
563 | /* enable next timer period */ | |
5c333864 | 564 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
565 | } |
566 | ||
567 | static void __cpuinit uv_heartbeat_enable(int cpu) | |
568 | { | |
99659a92 | 569 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
570 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
571 | ||
572 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
573 | setup_timer(timer, uv_heartbeat, cpu); | |
574 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
575 | add_timer_on(timer, cpu); | |
576 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 577 | |
99659a92 RK |
578 | /* also ensure that boot cpu is enabled */ |
579 | cpu = 0; | |
580 | } | |
7f1baa06 MT |
581 | } |
582 | ||
77be80e4 | 583 | #ifdef CONFIG_HOTPLUG_CPU |
7f1baa06 MT |
584 | static void __cpuinit uv_heartbeat_disable(int cpu) |
585 | { | |
586 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
587 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
588 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
589 | } | |
590 | uv_set_cpu_scir_bits(cpu, 0xff); | |
591 | } | |
592 | ||
7f1baa06 MT |
593 | /* |
594 | * cpu hotplug notifier | |
595 | */ | |
596 | static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, | |
597 | unsigned long action, void *hcpu) | |
598 | { | |
599 | long cpu = (long)hcpu; | |
600 | ||
601 | switch (action) { | |
602 | case CPU_ONLINE: | |
603 | uv_heartbeat_enable(cpu); | |
604 | break; | |
605 | case CPU_DOWN_PREPARE: | |
606 | uv_heartbeat_disable(cpu); | |
607 | break; | |
608 | default: | |
609 | break; | |
610 | } | |
611 | return NOTIFY_OK; | |
612 | } | |
613 | ||
614 | static __init void uv_scir_register_cpu_notifier(void) | |
615 | { | |
616 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
617 | } | |
618 | ||
619 | #else /* !CONFIG_HOTPLUG_CPU */ | |
620 | ||
621 | static __init void uv_scir_register_cpu_notifier(void) | |
622 | { | |
623 | } | |
624 | ||
625 | static __init int uv_init_heartbeat(void) | |
626 | { | |
627 | int cpu; | |
628 | ||
629 | if (is_uv_system()) | |
630 | for_each_online_cpu(cpu) | |
631 | uv_heartbeat_enable(cpu); | |
632 | return 0; | |
633 | } | |
634 | ||
635 | late_initcall(uv_init_heartbeat); | |
636 | ||
637 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
638 | ||
841582ea MT |
639 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
640 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
7ad35cf2 | 641 | unsigned int command_bits, u32 flags) |
841582ea MT |
642 | { |
643 | int domain, bus, rc; | |
644 | ||
7ad35cf2 DA |
645 | PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", |
646 | pdev->devfn, decode, command_bits, flags); | |
841582ea | 647 | |
7ad35cf2 | 648 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
649 | return 0; |
650 | ||
651 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
652 | return 0; | |
653 | ||
654 | domain = pci_domain_nr(pdev->bus); | |
655 | bus = pdev->bus->number; | |
656 | ||
657 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
658 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
659 | ||
660 | return rc; | |
661 | } | |
662 | ||
8da077d6 JS |
663 | /* |
664 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 665 | * FIXME: hotplug not supported yet |
8da077d6 JS |
666 | */ |
667 | void __cpuinit uv_cpu_init(void) | |
668 | { | |
669 | /* CPU 0 initilization will be done via uv_system_init. */ | |
670 | if (!uv_blade_info) | |
671 | return; | |
672 | ||
673 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
674 | ||
675 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
676 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
677 | } | |
678 | ||
78c06176 RA |
679 | /* |
680 | * When NMI is received, print a stack trace. | |
681 | */ | |
9c48f1c6 | 682 | int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) |
78c06176 | 683 | { |
1d44e828 JS |
684 | unsigned long real_uv_nmi; |
685 | int bid; | |
686 | ||
78c06176 | 687 | /* |
1d44e828 JS |
688 | * Each blade has an MMR that indicates when an NMI has been sent |
689 | * to cpus on the blade. If an NMI is detected, atomically | |
690 | * clear the MMR and update a per-blade NMI count used to | |
691 | * cause each cpu on the blade to notice a new NMI. | |
692 | */ | |
693 | bid = uv_numa_blade_id(); | |
694 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
695 | ||
696 | if (unlikely(real_uv_nmi)) { | |
697 | spin_lock(&uv_blade_info[bid].nmi_lock); | |
698 | real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); | |
699 | if (real_uv_nmi) { | |
700 | uv_blade_info[bid].nmi_count++; | |
701 | uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK); | |
702 | } | |
703 | spin_unlock(&uv_blade_info[bid].nmi_lock); | |
704 | } | |
705 | ||
706 | if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count)) | |
9c48f1c6 | 707 | return NMI_DONE; |
1d44e828 JS |
708 | |
709 | __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count; | |
710 | ||
711 | /* | |
712 | * Use a lock so only one cpu prints at a time. | |
713 | * This prevents intermixed output. | |
78c06176 RA |
714 | */ |
715 | spin_lock(&uv_nmi_lock); | |
1d44e828 | 716 | pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id()); |
78c06176 RA |
717 | dump_stack(); |
718 | spin_unlock(&uv_nmi_lock); | |
719 | ||
9c48f1c6 | 720 | return NMI_HANDLED; |
78c06176 RA |
721 | } |
722 | ||
78c06176 RA |
723 | void uv_register_nmi_notifier(void) |
724 | { | |
9c48f1c6 | 725 | if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) |
78c06176 RA |
726 | printk(KERN_WARNING "UV NMI handler failed to register\n"); |
727 | } | |
728 | ||
729 | void uv_nmi_init(void) | |
730 | { | |
731 | unsigned int value; | |
732 | ||
733 | /* | |
734 | * Unmask NMI on all cpus | |
735 | */ | |
736 | value = apic_read(APIC_LVT1) | APIC_DM_NMI; | |
737 | value &= ~APIC_LVT_MASKED; | |
738 | apic_write(APIC_LVT1, value); | |
739 | } | |
c4bd1fda MS |
740 | |
741 | void __init uv_system_init(void) | |
ac23d4ee | 742 | { |
62b0cfc2 | 743 | union uvh_rh_gam_config_mmr_u m_n_config; |
d8850ba4 | 744 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; |
9f5314fb JS |
745 | union uvh_node_id_u node_id; |
746 | unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; | |
d8850ba4 | 747 | int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io; |
c4ed3f04 | 748 | int gnode_extra, max_pnode = 0; |
6a891a24 | 749 | unsigned long mmr_base, present, paddr; |
d8850ba4 | 750 | unsigned short pnode_mask, pnode_io_mask; |
ac23d4ee | 751 | |
2a919596 | 752 | printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2"); |
918bc960 JS |
753 | map_low_mmrs(); |
754 | ||
62b0cfc2 | 755 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); |
9f5314fb JS |
756 | m_val = m_n_config.s.m_skt; |
757 | n_val = m_n_config.s.n_skt; | |
d8850ba4 | 758 | mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); |
2a919596 | 759 | n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io; |
ac23d4ee JS |
760 | mmr_base = |
761 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
762 | ~UV_MMR_ENABLE; | |
c4ed3f04 | 763 | pnode_mask = (1 << n_val) - 1; |
d8850ba4 JS |
764 | pnode_io_mask = (1 << n_io) - 1; |
765 | ||
c4ed3f04 JS |
766 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); |
767 | gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; | |
768 | gnode_upper = ((unsigned long)gnode_extra << m_val); | |
d8850ba4 JS |
769 | printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n", |
770 | n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask); | |
c4ed3f04 | 771 | |
ac23d4ee JS |
772 | printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); |
773 | ||
9f5314fb JS |
774 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
775 | uv_possible_blades += | |
776 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
da517a08 JS |
777 | |
778 | /* uv_num_possible_blades() is really the hub count */ | |
779 | printk(KERN_INFO "UV: Found %d blades, %d hubs\n", | |
780 | is_uv1_hub() ? uv_num_possible_blades() : | |
781 | (uv_num_possible_blades() + 1) / 2, | |
782 | uv_num_possible_blades()); | |
ac23d4ee JS |
783 | |
784 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
1d44e828 | 785 | uv_blade_info = kzalloc(bytes, GFP_KERNEL); |
9a8709d4 | 786 | BUG_ON(!uv_blade_info); |
1d44e828 | 787 | |
6c7184b7 JS |
788 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
789 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 790 | |
9f5314fb JS |
791 | get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); |
792 | ||
ac23d4ee | 793 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 794 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 795 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
796 | memset(uv_node_to_blade, 255, bytes); |
797 | ||
798 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 799 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 800 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
801 | memset(uv_cpu_to_blade, 255, bytes); |
802 | ||
9f5314fb JS |
803 | blade = 0; |
804 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
805 | present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
806 | for (j = 0; j < 64; j++) { | |
807 | if (!test_bit(j, &present)) | |
808 | continue; | |
d8850ba4 | 809 | pnode = (i * 64 + j) & pnode_mask; |
36ac4b98 | 810 | uv_blade_info[blade].pnode = pnode; |
9f5314fb | 811 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 812 | uv_blade_info[blade].nr_online_cpus = 0; |
1d44e828 | 813 | spin_lock_init(&uv_blade_info[blade].nmi_lock); |
36ac4b98 | 814 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 815 | blade++; |
ac23d4ee | 816 | } |
9f5314fb | 817 | } |
ac23d4ee | 818 | |
7f594232 | 819 | uv_bios_init(); |
b76365a1 RA |
820 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
821 | &sn_region_size, &system_serial_number); | |
7019cc2d RA |
822 | uv_rtc_init(); |
823 | ||
9f5314fb | 824 | for_each_present_cpu(cpu) { |
39d30770 MT |
825 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
826 | ||
9f5314fb | 827 | nid = cpu_to_node(cpu); |
c8f730b1 RA |
828 | /* |
829 | * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); | |
830 | */ | |
d8850ba4 | 831 | uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; |
c8f730b1 | 832 | uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; |
2a919596 JS |
833 | uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; |
834 | ||
6a469e46 JS |
835 | uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; |
836 | uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ? | |
837 | (m_val == 40 ? 40 : 39) : m_val; | |
838 | ||
39d30770 | 839 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
840 | blade = boot_pnode_to_blade(pnode); |
841 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
842 | uv_blade_info[blade].nr_possible_cpus++; | |
843 | ||
6c7184b7 JS |
844 | /* Any node on the blade, else will contain -1. */ |
845 | uv_blade_info[blade].memory_nid = nid; | |
846 | ||
9f5314fb | 847 | uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; |
189f67c4 | 848 | uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; |
9f5314fb | 849 | uv_cpu_hub_info(cpu)->m_val = m_val; |
036ed8ba | 850 | uv_cpu_hub_info(cpu)->n_val = n_val; |
ac23d4ee JS |
851 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
852 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; | |
9f5314fb | 853 | uv_cpu_hub_info(cpu)->pnode = pnode; |
036ed8ba | 854 | uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; |
9f5314fb | 855 | uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; |
c4ed3f04 | 856 | uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; |
ac23d4ee | 857 | uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; |
b0f20989 | 858 | uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; |
39d30770 | 859 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
ac23d4ee JS |
860 | uv_node_to_blade[nid] = blade; |
861 | uv_cpu_to_blade[cpu] = blade; | |
ac23d4ee | 862 | } |
83f5d894 | 863 | |
6a891a24 JS |
864 | /* Add blade/pnode info for nodes without cpus */ |
865 | for_each_online_node(nid) { | |
866 | if (uv_node_to_blade[nid] >= 0) | |
867 | continue; | |
868 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
6a469e46 | 869 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); |
6a891a24 JS |
870 | blade = boot_pnode_to_blade(pnode); |
871 | uv_node_to_blade[nid] = blade; | |
872 | } | |
873 | ||
83f5d894 | 874 | map_gru_high(max_pnode); |
daf7b9c9 | 875 | map_mmr_high(max_pnode); |
d8850ba4 | 876 | map_mmioh_high(max_pnode & pnode_io_mask); |
ac23d4ee | 877 | |
8da077d6 | 878 | uv_cpu_init(); |
7f1baa06 | 879 | uv_scir_register_cpu_notifier(); |
78c06176 | 880 | uv_register_nmi_notifier(); |
a3d732f9 | 881 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
882 | |
883 | /* register Legacy VGA I/O redirection handler */ | |
884 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
885 | |
886 | /* | |
887 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
888 | * EFI is not enabled in the kdump kernel. | |
889 | */ | |
890 | if (is_kdump_kernel()) | |
891 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 892 | } |
107e0e0c SS |
893 | |
894 | apic_driver(apic_x2apic_uv_x); |