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x86/platform/UV: Build GAM reference tables
[linux-2.6-block.git] / arch / x86 / kernel / apic / x2apic_uv_x.c
CommitLineData
ac23d4ee
JS		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
5f40f7d9 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
ac23d4ee 9 */
ac23d4ee 10#include <linux/cpumask.h>
0b1da1c8
IM		 11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
ac23d4ee 16#include <linux/string.h>
ac23d4ee 17#include <linux/ctype.h>
ac23d4ee 18#include <linux/sched.h>
7f1baa06 19#include <linux/timer.h>
5a0e3ad6 20#include <linux/slab.h>
0b1da1c8
IM		 21#include <linux/cpu.h>
22#include <linux/init.h>
27229ca6 23#include <linux/io.h>
841582ea 24#include <linux/pci.h>
78c06176 25#include <linux/kdebug.h>
ca444564 26#include <linux/delay.h>
818987e9 27#include <linux/crash_dump.h>
1b3a5d02 28#include <linux/reboot.h>
0b1da1c8 29
ac23d4ee
JS		 30#include <asm/uv/uv_mmrs.h>
31#include <asm/uv/uv_hub.h>
0b1da1c8
IM		 32#include <asm/current.h>
33#include <asm/pgtable.h>
7019cc2d 34#include <asm/uv/bios.h>
0b1da1c8
IM		 35#include <asm/uv/uv.h>
36#include <asm/apic.h>
37#include <asm/ipi.h>
38#include <asm/smp.h>
fd12a0d6 39#include <asm/x86_init.h>
1d44e828
JS		 40#include <asm/nmi.h>
41
510b3725
YL		 42DEFINE_PER_CPU(int, x2apic_extra_bits);
43
841582ea
MT		 44#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
45
1b9b89e7 46static enum uv_system_type uv_system_type;
fd12a0d6 47static u64 gru_start_paddr, gru_end_paddr;
879d5ad0
DS		 48static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49static u64 gru_dist_lmask, gru_dist_umask;
c8f730b1 50static union uvh_apicid uvh_apicid;
405422d8
MT		 51
52/* info derived from CPUID */
53static struct {
54 unsigned int apicid_shift;
55 unsigned int apicid_mask;
56 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
57 unsigned int pnode_mask;
58 unsigned int gpa_shift;
59} uv_cpuid;
60
7a1110e8
JS		 61int uv_min_hub_revision_id;
62EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
8191c9f6
DS		 63unsigned int uv_apicid_hibits;
64EXPORT_SYMBOL_GPL(uv_apicid_hibits);
fd12a0d6 65
1a8880a1 66static struct apic apic_x2apic_uv_x;
3edcf2ff 67static struct uv_hub_info_s uv_hub_info_node0;
1a8880a1 68
7563421b
MT		 69/* Set this to use hardware error handler instead of kernel panic */
70static int disable_uv_undefined_panic = 1;
71unsigned long uv_undefined(char *str)
72{
73 if (likely(!disable_uv_undefined_panic))
74 panic("UV: error: undefined MMR: %s\n", str);
75 else
76 pr_crit("UV: error: undefined MMR: %s\n", str);
77 return ~0ul; /* cause a machine fault */
78}
79EXPORT_SYMBOL(uv_undefined);
80
e6810413
JS		 81static unsigned long __init uv_early_read_mmr(unsigned long addr)
82{
83 unsigned long val, *mmr;
84
85 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
86 val = *mmr;
87 early_iounmap(mmr, sizeof(*mmr));
88 return val;
89}
90
eb41c8be 91static inline bool is_GRU_range(u64 start, u64 end)
fd12a0d6 92{
879d5ad0
DS		 93 if (gru_dist_base) {
94 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
95 u64 sl = start & gru_dist_lmask; /* base offset bits */
96 u64 eu = end & gru_dist_umask;
97 u64 el = end & gru_dist_lmask;
98
99 /* Must reside completely within a single GRU range */
100 return (sl == gru_dist_base && el == gru_dist_base &&
101 su >= gru_first_node_paddr &&
102 su <= gru_last_node_paddr &&
103 eu == su);
104 } else {
105 return start >= gru_start_paddr && end <= gru_end_paddr;
106 }
fd12a0d6
JS		 107}
108
eb41c8be 109static bool uv_is_untracked_pat_range(u64 start, u64 end)
fd12a0d6
JS		 110{
111 return is_ISA_range(start, end) || is_GRU_range(start, end);
112}
1b9b89e7 113
d8850ba4 114static int __init early_get_pnodeid(void)
27229ca6
JS		 115{
116 union uvh_node_id_u node_id;
d8850ba4
JS		 117 union uvh_rh_gam_config_mmr_u m_n_config;
118 int pnode;
7a1110e8
JS		 119
120 /* Currently, all blades have same revision number */
e6810413 121 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
d8850ba4 122 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
7a1110e8
JS		 123 uv_min_hub_revision_id = node_id.s.revision;
124
b15cc4a1
MT		 125 switch (node_id.s.part_number) {
126 case UV2_HUB_PART_NUMBER:
127 case UV2_HUB_PART_NUMBER_X:
b495e039 128 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
b15cc4a1
MT		 129 break;
130 case UV3_HUB_PART_NUMBER:
131 case UV3_HUB_PART_NUMBER_X:
dd3c9c4b 132 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
b15cc4a1 133 break;
a0ec83f3
MT		 134 case UV4_HUB_PART_NUMBER:
135 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
136 break;
b15cc4a1 137 }
2a919596
JS		 138
139 uv_hub_info->hub_revision = uv_min_hub_revision_id;
405422d8
MT		 140 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
141 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
142 uv_cpuid.gpa_shift = 46; /* default unless changed */
143
144 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
145 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
146 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
d8850ba4 147 return pnode;
27229ca6
JS		 148}
149
405422d8
MT		 150/* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
151#define SMT_LEVEL 0 /* leaf 0xb SMT level */
152#define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */
153#define SMT_TYPE 1
154#define CORE_TYPE 2
155#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
156#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
157
158static void set_x2apic_bits(void)
159{
160 unsigned int eax, ebx, ecx, edx, sub_index;
161 unsigned int sid_shift;
162
163 cpuid(0, &eax, &ebx, &ecx, &edx);
164 if (eax < 0xb) {
165 pr_info("UV: CPU does not have CPUID.11\n");
166 return;
167 }
168 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
169 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
170 pr_info("UV: CPUID.11 not implemented\n");
171 return;
172 }
173 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
174 sub_index = 1;
175 do {
176 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
177 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
178 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
179 break;
180 }
181 sub_index++;
182 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
183 uv_cpuid.apicid_shift = 0;
184 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
185 uv_cpuid.socketid_shift = sid_shift;
186}
187
188static void __init early_get_apic_socketid_shift(void)
c8f730b1 189{
405422d8
MT		 190 if (is_uv2_hub() || is_uv3_hub())
191 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
192
193 set_x2apic_bits();
194
195 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
196 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
197 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
198 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
c8f730b1
RA		 199}
200
8191c9f6
DS		 201/*
202 * Add an extra bit as dictated by bios to the destination apicid of
203 * interrupts potentially passing through the UV HUB. This prevents
204 * a deadlock between interrupts and IO port operations.
205 */
206static void __init uv_set_apicid_hibit(void)
207{
2a919596 208 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
8191c9f6 209
2a919596
JS		 210 if (is_uv1_hub()) {
211 apicid_mask.v =
212 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
213 uv_apicid_hibits =
214 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
215 }
8191c9f6
DS		 216}
217
52459ab9 218static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
1b9b89e7 219{
379b97e2
MT		 220 int pnodeid;
221 int uv_apic;
1d2c867c 222
7a4e0170
MT		 223 if (strncmp(oem_id, "SGI", 3) != 0)
224 return 0;
225
3edcf2ff
MT		 226 /* Setup early hub type field in uv_hub_info for Node 0 */
227 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
228
379b97e2
MT		 229 /*
230 * Determine UV arch type.
231 * SGI: UV100/1000
232 * SGI2: UV2000/3000
233 * SGI3: UV300 (truncated to 4 chars because of different varieties)
a0ec83f3 234 * SGI4: UV400 (truncated to 4 chars because of different varieties)
379b97e2
MT		 235 */
236 uv_hub_info->hub_revision =
a0ec83f3 237 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
379b97e2
MT		 238 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
239 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
240 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
241
242 if (uv_hub_info->hub_revision == 0)
243 goto badbios;
244
245 pnodeid = early_get_pnodeid();
405422d8 246 early_get_apic_socketid_shift();
379b97e2
MT		 247 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
248 x86_platform.nmi_init = uv_nmi_init;
249
250 if (!strcmp(oem_table_id, "UVX")) { /* most common */
251 uv_system_type = UV_X2APIC;
252 uv_apic = 0;
253
254 } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */
255 uv_system_type = UV_NON_UNIQUE_APIC;
256 __this_cpu_write(x2apic_extra_bits,
257 pnodeid << uvh_apicid.s.pnode_shift);
258 uv_set_apicid_hibit();
259 uv_apic = 1;
260
261 } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */
262 uv_system_type = UV_LEGACY_APIC; /* very small systems */
263 uv_apic = 0;
264
265 } else {
266 goto badbios;
1b9b89e7 267 }
379b97e2
MT		 268
269 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n",
270 oem_id, oem_table_id, uv_system_type,
271 uv_min_hub_revision_id, uv_apic);
272
273 return uv_apic;
274
275badbios:
276 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
277 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
278 BUG();
1b9b89e7
YL		 279}
280
281enum uv_system_type get_uv_system_type(void)
282{
283 return uv_system_type;
284}
285
286int is_uv_system(void)
287{
288 return uv_system_type != UV_NONE;
289}
8067794b 290EXPORT_SYMBOL_GPL(is_uv_system);
1b9b89e7 291
3edcf2ff
MT		 292void **__uv_hub_info_list;
293EXPORT_SYMBOL_GPL(__uv_hub_info_list);
ac23d4ee 294
0045ddd2
MT		 295DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
296EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
297
ac23d4ee
JS		 298short uv_possible_blades;
299EXPORT_SYMBOL_GPL(uv_possible_blades);
300
7019cc2d
RA		 301unsigned long sn_rtc_cycles_per_second;
302EXPORT_SYMBOL(sn_rtc_cycles_per_second);
303
1de329c1 304/* the following values are used for the per node hub info struct */
906f3b20 305static __initdata unsigned short *_node_to_pnode;
1de329c1
MT		 306static __initdata unsigned short _min_socket, _max_socket;
307static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
308static __initdata struct uv_gam_range_entry *uv_gre_table;
309static __initdata struct uv_gam_parameters *uv_gp_table;
6e27b91c
MT		 310static __initdata unsigned short *_socket_to_node;
311static __initdata unsigned short *_socket_to_pnode;
312static __initdata unsigned short *_pnode_to_socket;
1de329c1 313#define SOCK_EMPTY ((unsigned short)~0)
906f3b20 314
3edcf2ff
MT		 315extern int uv_hub_info_version(void)
316{
317 return UV_HUB_INFO_VERSION;
318}
319EXPORT_SYMBOL(uv_hub_info_version);
320
148f9bb8 321static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
ac23d4ee
JS		 322{
323 unsigned long val;
9f5314fb 324 int pnode;
ac23d4ee 325
9f5314fb 326 pnode = uv_apicid_to_pnode(phys_apicid);
8191c9f6 327 phys_apicid |= uv_apicid_hibits;
ac23d4ee
JS		 328 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
329 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
2b6163bf 330 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
34d05591 331 APIC_DM_INIT;
9f5314fb 332 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
34d05591
JS		 333
334 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
335 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
2b6163bf 336 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
34d05591 337 APIC_DM_STARTUP;
9f5314fb 338 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
2b6163bf 339
ac23d4ee
JS		 340 return 0;
341}
342
343static void uv_send_IPI_one(int cpu, int vector)
344{
66666e50 345 unsigned long apicid;
9f5314fb 346 int pnode;
ac23d4ee 347
1e0b5d00 348 apicid = per_cpu(x86_cpu_to_apicid, cpu);
9f5314fb 349 pnode = uv_apicid_to_pnode(apicid);
66666e50 350 uv_hub_send_ipi(pnode, apicid, vector);
ac23d4ee
JS		 351}
352
bcda016e 353static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
ac23d4ee
JS		 354{
355 unsigned int cpu;
356
bcda016e 357 for_each_cpu(cpu, mask)
e7986739
MT		 358 uv_send_IPI_one(cpu, vector);
359}
360
bcda016e 361static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
e7986739 362{
e7986739 363 unsigned int this_cpu = smp_processor_id();
dac5f412 364 unsigned int cpu;
e7986739 365
dac5f412 366 for_each_cpu(cpu, mask) {
e7986739 367 if (cpu != this_cpu)
ac23d4ee 368 uv_send_IPI_one(cpu, vector);
dac5f412 369 }
ac23d4ee
JS		 370}
371
372static void uv_send_IPI_allbutself(int vector)
373{
e7986739 374 unsigned int this_cpu = smp_processor_id();
dac5f412 375 unsigned int cpu;
ac23d4ee 376
dac5f412 377 for_each_online_cpu(cpu) {
e7986739
MT		 378 if (cpu != this_cpu)
379 uv_send_IPI_one(cpu, vector);
dac5f412 380 }
ac23d4ee
JS		 381}
382
383static void uv_send_IPI_all(int vector)
384{
bcda016e 385 uv_send_IPI_mask(cpu_online_mask, vector);
ac23d4ee
JS		 386}
387
b7157acf
SP		 388static int uv_apic_id_valid(int apicid)
389{
390 return 1;
391}
392
ac23d4ee
JS		 393static int uv_apic_id_registered(void)
394{
395 return 1;
396}
397
277d1f58 398static void uv_init_apic_ldr(void)
5c520a67
SS		 399{
400}
401
ff164324 402static int
debccb3e 403uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
ff164324
AG		 404 const struct cpumask *andmask,
405 unsigned int *apicid)
95d313cf 406{
ea3807ea 407 int unsigned cpu;
95d313cf
MT		 408
409 /*
410 * We're using fixed IRQ delivery, can only return one phys APIC ID.
411 * May as well be the first.
412 */
debccb3e 413 for_each_cpu_and(cpu, cpumask, andmask) {
a775a38b
MT		 414 if (cpumask_test_cpu(cpu, cpu_online_mask))
415 break;
debccb3e 416 }
ff164324 417
ea3807ea 418 if (likely(cpu < nr_cpu_ids)) {
a5a39156
AG		 419 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
420 return 0;
a5a39156 421 }
ea3807ea
AG		 422
423 return -EINVAL;
95d313cf
MT		 424}
425
ca6c8ed4 426static unsigned int x2apic_get_apic_id(unsigned long x)
0c81c746
SS		 427{
428 unsigned int id;
429
430 WARN_ON(preemptible() && num_online_cpus() > 1);
0a3aee0d 431 id = x | __this_cpu_read(x2apic_extra_bits);
0c81c746
SS		 432
433 return id;
434}
435
1b9b89e7 436static unsigned long set_apic_id(unsigned int id)
f910a9dc
YL		 437{
438 unsigned long x;
439
440 /* maskout x2apic_extra_bits ? */
441 x = id;
442 return x;
443}
444
445static unsigned int uv_read_apic_id(void)
446{
ca6c8ed4 447 return x2apic_get_apic_id(apic_read(APIC_ID));
f910a9dc
YL		 448}
449
d4c9a9f3 450static int uv_phys_pkg_id(int initial_apicid, int index_msb)
ac23d4ee 451{
0c81c746 452 return uv_read_apic_id() >> index_msb;
ac23d4ee
JS		 453}
454
ac23d4ee
JS		 455static void uv_send_IPI_self(int vector)
456{
457 apic_write(APIC_SELF_IPI, vector);
458}
ac23d4ee 459
9ebd680b
SS		 460static int uv_probe(void)
461{
462 return apic == &apic_x2apic_uv_x;
463}
464
1a8880a1 465static struct apic __refdata apic_x2apic_uv_x = {
c7967329
IM		 466
467 .name = "UV large system",
9ebd680b 468 .probe = uv_probe,
c7967329 469 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
b7157acf 470 .apic_id_valid = uv_apic_id_valid,
c7967329
IM		 471 .apic_id_registered = uv_apic_id_registered,
472
f8987a10 473 .irq_delivery_mode = dest_Fixed,
c5997fa8 474 .irq_dest_mode = 0, /* physical */
c7967329 475
bf721d3a 476 .target_cpus = online_target_cpus,
08125d3e 477 .disable_esr = 0,
bdb1a9b6 478 .dest_logical = APIC_DEST_LOGICAL,
c7967329 479 .check_apicid_used = NULL,
c7967329 480
9d8e1066 481 .vector_allocation_domain = default_vector_allocation_domain,
c7967329
IM		 482 .init_apic_ldr = uv_init_apic_ldr,
483
484 .ioapic_phys_id_map = NULL,
485 .setup_apic_routing = NULL,
a21769a4 486 .cpu_present_to_apicid = default_cpu_present_to_apicid,
c7967329 487 .apicid_to_cpu_present = NULL,
a27a6210 488 .check_phys_apicid_present = default_check_phys_apicid_present,
d4c9a9f3 489 .phys_pkg_id = uv_phys_pkg_id,
c7967329 490
ca6c8ed4 491 .get_apic_id = x2apic_get_apic_id,
c7967329
IM		 492 .set_apic_id = set_apic_id,
493 .apic_id_mask = 0xFFFFFFFFu,
494
c7967329
IM		 495 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
496
8642ea95 497 .send_IPI = uv_send_IPI_one,
c7967329
IM		 498 .send_IPI_mask = uv_send_IPI_mask,
499 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
500 .send_IPI_allbutself = uv_send_IPI_allbutself,
501 .send_IPI_all = uv_send_IPI_all,
502 .send_IPI_self = uv_send_IPI_self,
503
1f5bcabf 504 .wakeup_secondary_cpu = uv_wakeup_secondary,
c7967329 505 .inquire_remote_apic = NULL,
c1eeb2de
YL		 506
507 .read = native_apic_msr_read,
508 .write = native_apic_msr_write,
0ab711ae 509 .eoi_write = native_apic_msr_eoi_write,
c1eeb2de
YL		 510 .icr_read = native_x2apic_icr_read,
511 .icr_write = native_x2apic_icr_write,
512 .wait_icr_idle = native_x2apic_wait_icr_idle,
513 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
ac23d4ee
JS		 514};
515
148f9bb8 516static void set_x2apic_extra_bits(int pnode)
ac23d4ee 517{
16ee8db6 518 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
ac23d4ee
JS		 519}
520
c443c03d 521#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
9f5314fb
JS		 522#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
523
9f5314fb
JS		 524static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
525{
62b0cfc2 526 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
9f5314fb 527 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
c443c03d
MT		 528 unsigned long m_redirect;
529 unsigned long m_overlay;
9f5314fb
JS		 530 int i;
531
c443c03d
MT		 532 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
533 switch (i) {
534 case 0:
535 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
536 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
537 break;
538 case 1:
539 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
540 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
541 break;
542 case 2:
543 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
544 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
545 break;
546 }
547 alias.v = uv_read_local_mmr(m_overlay);
036ed8ba 548 if (alias.s.enable && alias.s.base == 0) {
9f5314fb 549 *size = (1UL << alias.s.m_alias);
c443c03d
MT		 550 redirect.v = uv_read_local_mmr(m_redirect);
551 *base = (unsigned long)redirect.s.dest_base
552 << DEST_SHIFT;
9f5314fb
JS		 553 return;
554 }
555 }
036ed8ba 556 *base = *size = 0;
9f5314fb
JS		 557}
558
83f5d894
JS		 559enum map_type {map_wb, map_uc};
560
fcfbb2b5
MT		 561static __init void map_high(char *id, unsigned long base, int pshift,
562 int bshift, int max_pnode, enum map_type map_type)
83f5d894
JS		 563{
564 unsigned long bytes, paddr;
565
fcfbb2b5
MT		 566 paddr = base << pshift;
567 bytes = (1UL << bshift) * (max_pnode + 1);
b15cc4a1
MT		 568 if (!paddr) {
569 pr_info("UV: Map %s_HI base address NULL\n", id);
570 return;
571 }
879d5ad0 572 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
83f5d894
JS		 573 if (map_type == map_uc)
574 init_extra_mapping_uc(paddr, bytes);
575 else
576 init_extra_mapping_wb(paddr, bytes);
83f5d894 577}
b15cc4a1 578
879d5ad0
DS		 579static __init void map_gru_distributed(unsigned long c)
580{
581 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
582 u64 paddr;
583 unsigned long bytes;
584 int nid;
585
586 gru.v = c;
587 /* only base bits 42:28 relevant in dist mode */
588 gru_dist_base = gru.v & 0x000007fff0000000UL;
589 if (!gru_dist_base) {
590 pr_info("UV: Map GRU_DIST base address NULL\n");
591 return;
592 }
593 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
594 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
595 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
596 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
597 for_each_online_node(nid) {
598 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
599 gru_dist_base;
600 init_extra_mapping_wb(paddr, bytes);
601 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
602 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
603 }
604 /* Save upper (63:M) bits of address only for is_GRU_range */
605 gru_first_node_paddr &= gru_dist_umask;
606 gru_last_node_paddr &= gru_dist_umask;
607 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
608 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
609}
610
83f5d894
JS		 611static __init void map_gru_high(int max_pnode)
612{
613 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
614 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
c443c03d
MT		 615 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
616 unsigned long base;
83f5d894
JS		 617
618 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
879d5ad0 619 if (!gru.s.enable) {
b15cc4a1 620 pr_info("UV: GRU disabled\n");
879d5ad0
DS		 621 return;
622 }
623
624 if (is_uv3_hub() && gru.s3.mode) {
625 map_gru_distributed(gru.v);
626 return;
fd12a0d6 627 }
c443c03d
MT		 628 base = (gru.v & mask) >> shift;
629 map_high("GRU", base, shift, shift, max_pnode, map_wb);
630 gru_start_paddr = ((u64)base << shift);
879d5ad0 631 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
83f5d894
JS		 632}
633
daf7b9c9
JS		 634static __init void map_mmr_high(int max_pnode)
635{
636 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
637 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
638
639 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
640 if (mmr.s.enable)
fcfbb2b5 641 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
b15cc4a1
MT		 642 else
643 pr_info("UV: MMR disabled\n");
644}
645
646/*
647 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
648 * and REDIRECT MMR regs are exactly the same on UV3.
649 */
650struct mmioh_config {
651 unsigned long overlay;
652 unsigned long redirect;
653 char *id;
654};
655
656static __initdata struct mmioh_config mmiohs[] = {
657 {
658 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
659 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
660 "MMIOH0"
661 },
662 {
663 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
664 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
665 "MMIOH1"
666 },
667};
668
a2f28e69 669/* UV3 & UV4 have identical MMIOH overlay configs */
b15cc4a1
MT		 670static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
671{
672 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
673 unsigned long mmr;
674 unsigned long base;
675 int i, n, shift, m_io, max_io;
676 int nasid, lnasid, fi, li;
677 char *id;
678
679 id = mmiohs[index].id;
680 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
681 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
682 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
683 if (!overlay.s3.enable) {
684 pr_info("UV: %s disabled\n", id);
685 return;
686 }
687
688 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
689 base = (unsigned long)overlay.s3.base;
690 m_io = overlay.s3.m_io;
691 mmr = mmiohs[index].redirect;
692 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
693 min_pnode *= 2; /* convert to NASID */
694 max_pnode *= 2;
695 max_io = lnasid = fi = li = -1;
696
697 for (i = 0; i < n; i++) {
698 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
699
700 redirect.v = uv_read_local_mmr(mmr + i * 8);
701 nasid = redirect.s3.nasid;
702 if (nasid < min_pnode || max_pnode < nasid)
703 nasid = -1; /* invalid NASID */
704
705 if (nasid == lnasid) {
706 li = i;
707 if (i != n-1) /* last entry check */
708 continue;
709 }
710
711 /* check if we have a cached (or last) redirect to print */
712 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
713 unsigned long addr1, addr2;
714 int f, l;
715
716 if (lnasid == -1) {
717 f = l = i;
718 lnasid = nasid;
719 } else {
720 f = fi;
721 l = li;
722 }
723 addr1 = (base << shift) +
724 f * (unsigned long)(1 << m_io);
725 addr2 = (base << shift) +
726 (l + 1) * (unsigned long)(1 << m_io);
727 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
728 id, fi, li, lnasid, addr1, addr2);
729 if (max_io < l)
730 max_io = l;
731 }
732 fi = li = i;
733 lnasid = nasid;
734 }
735
736 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
737 id, base, shift, m_io, max_io);
738
739 if (max_io >= 0)
740 map_high(id, base, shift, m_io, max_io, map_uc);
daf7b9c9
JS		 741}
742
b15cc4a1 743static __init void map_mmioh_high(int min_pnode, int max_pnode)
83f5d894
JS		 744{
745 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
b15cc4a1
MT		 746 unsigned long mmr, base;
747 int shift, enable, m_io, n_io;
83f5d894 748
a2f28e69 749 if (is_uv3_hub() || is_uv4_hub()) {
b15cc4a1
MT		 750 /* Map both MMIOH Regions */
751 map_mmioh_high_uv3(0, min_pnode, max_pnode);
752 map_mmioh_high_uv3(1, min_pnode, max_pnode);
753 return;
2a919596 754 }
b15cc4a1
MT		 755
756 if (is_uv1_hub()) {
757 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
758 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
759 mmioh.v = uv_read_local_mmr(mmr);
760 enable = !!mmioh.s1.enable;
761 base = mmioh.s1.base;
762 m_io = mmioh.s1.m_io;
763 n_io = mmioh.s1.n_io;
764 } else if (is_uv2_hub()) {
765 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
2a919596 766 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
b15cc4a1
MT		 767 mmioh.v = uv_read_local_mmr(mmr);
768 enable = !!mmioh.s2.enable;
769 base = mmioh.s2.base;
770 m_io = mmioh.s2.m_io;
771 n_io = mmioh.s2.n_io;
772 } else
773 return;
774
775 if (enable) {
776 max_pnode &= (1 << n_io) - 1;
777 pr_info(
778 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
779 base, shift, m_io, n_io, max_pnode);
780 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
781 } else {
782 pr_info("UV: MMIOH disabled\n");
2a919596 783 }
83f5d894
JS		 784}
785
918bc960
JS		 786static __init void map_low_mmrs(void)
787{
788 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
789 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
790}
791
7019cc2d
RA		 792static __init void uv_rtc_init(void)
793{
922402f1
RA		 794 long status;
795 u64 ticks_per_sec;
7019cc2d 796
922402f1
RA		 797 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
798 &ticks_per_sec);
799 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
7019cc2d
RA		 800 printk(KERN_WARNING
801 "unable to determine platform RTC clock frequency, "
802 "guessing.\n");
803 /* BIOS gives wrong value for clock freq. so guess */
804 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
805 } else
806 sn_rtc_cycles_per_second = ticks_per_sec;
807}
808
7f1baa06
MT		 809/*
810 * percpu heartbeat timer
811 */
812static void uv_heartbeat(unsigned long ignored)
813{
d38bb135
MT		 814 struct timer_list *timer = &uv_scir_info->timer;
815 unsigned char bits = uv_scir_info->state;
7f1baa06
MT		 816
817 /* flip heartbeat bit */
818 bits ^= SCIR_CPU_HEARTBEAT;
819
69a72a0e
MT		 820 /* is this cpu idle? */
821 if (idle_cpu(raw_smp_processor_id()))
7f1baa06
MT		 822 bits &= ~SCIR_CPU_ACTIVITY;
823 else
824 bits |= SCIR_CPU_ACTIVITY;
825
826 /* update system controller interface reg */
827 uv_set_scir_bits(bits);
828
829 /* enable next timer period */
5c333864 830 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
7f1baa06
MT		 831}
832
148f9bb8 833static void uv_heartbeat_enable(int cpu)
7f1baa06 834{
d38bb135
MT		 835 while (!uv_cpu_scir_info(cpu)->enabled) {
836 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
7f1baa06
MT		 837
838 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
839 setup_timer(timer, uv_heartbeat, cpu);
840 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
841 add_timer_on(timer, cpu);
d38bb135 842 uv_cpu_scir_info(cpu)->enabled = 1;
7f1baa06 843
99659a92
RK		 844 /* also ensure that boot cpu is enabled */
845 cpu = 0;
846 }
7f1baa06
MT		 847}
848
77be80e4 849#ifdef CONFIG_HOTPLUG_CPU
148f9bb8 850static void uv_heartbeat_disable(int cpu)
7f1baa06 851{
d38bb135
MT		 852 if (uv_cpu_scir_info(cpu)->enabled) {
853 uv_cpu_scir_info(cpu)->enabled = 0;
854 del_timer(&uv_cpu_scir_info(cpu)->timer);
7f1baa06
MT		 855 }
856 uv_set_cpu_scir_bits(cpu, 0xff);
857}
858
7f1baa06
MT		 859/*
860 * cpu hotplug notifier
861 */
148f9bb8
PG		 862static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
863 void *hcpu)
7f1baa06
MT		 864{
865 long cpu = (long)hcpu;
866
f47ab81a
TG		 867 switch (action & ~CPU_TASKS_FROZEN) {
868 case CPU_DOWN_FAILED:
7f1baa06
MT		 869 case CPU_ONLINE:
870 uv_heartbeat_enable(cpu);
871 break;
872 case CPU_DOWN_PREPARE:
873 uv_heartbeat_disable(cpu);
874 break;
875 default:
876 break;
877 }
878 return NOTIFY_OK;
879}
880
881static __init void uv_scir_register_cpu_notifier(void)
882{
883 hotcpu_notifier(uv_scir_cpu_notify, 0);
884}
885
886#else /* !CONFIG_HOTPLUG_CPU */
887
888static __init void uv_scir_register_cpu_notifier(void)
889{
890}
891
892static __init int uv_init_heartbeat(void)
893{
894 int cpu;
895
896 if (is_uv_system())
897 for_each_online_cpu(cpu)
898 uv_heartbeat_enable(cpu);
899 return 0;
900}
901
902late_initcall(uv_init_heartbeat);
903
904#endif /* !CONFIG_HOTPLUG_CPU */
905
841582ea
MT		 906/* Direct Legacy VGA I/O traffic to designated IOH */
907int uv_set_vga_state(struct pci_dev *pdev, bool decode,
7ad35cf2 908 unsigned int command_bits, u32 flags)
841582ea
MT		 909{
910 int domain, bus, rc;
911
7ad35cf2
DA		 912 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
913 pdev->devfn, decode, command_bits, flags);
841582ea 914
7ad35cf2 915 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
841582ea
MT		 916 return 0;
917
918 if ((command_bits & PCI_COMMAND_IO) == 0)
919 return 0;
920
921 domain = pci_domain_nr(pdev->bus);
922 bus = pdev->bus->number;
923
924 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
925 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
926
927 return rc;
928}
929
8da077d6
JS		 930/*
931 * Called on each cpu to initialize the per_cpu UV data area.
0b1da1c8 932 * FIXME: hotplug not supported yet
8da077d6 933 */
148f9bb8 934void uv_cpu_init(void)
8da077d6 935{
6a6256f9 936 /* CPU 0 initialization will be done via uv_system_init. */
906f3b20 937 if (smp_processor_id() == 0)
8da077d6
JS		 938 return;
939
906f3b20 940 uv_hub_info->nr_online_cpus++;
8da077d6
JS		 941
942 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
943 set_x2apic_extra_bits(uv_hub_info->pnode);
944}
945
c443c03d
MT		 946struct mn {
947 unsigned char m_val;
948 unsigned char n_val;
949 unsigned char m_shift;
950 unsigned char n_lshift;
951};
952
953static void get_mn(struct mn *mnp)
ac23d4ee 954{
c443c03d
MT		 955 union uvh_rh_gam_config_mmr_u m_n_config;
956 union uv3h_gr0_gam_gr_config_u m_gr_config;
957
958 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
959 mnp->n_val = m_n_config.s.n_skt;
960 if (is_uv4_hub()) {
961 mnp->m_val = 0;
962 mnp->n_lshift = 0;
963 } else if (is_uv3_hub()) {
964 mnp->m_val = m_n_config.s3.m_skt;
965 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
966 mnp->n_lshift = m_gr_config.s3.m_skt;
967 } else if (is_uv2_hub()) {
968 mnp->m_val = m_n_config.s2.m_skt;
969 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
970 } else if (is_uv1_hub()) {
971 mnp->m_val = m_n_config.s1.m_skt;
972 mnp->n_lshift = mnp->m_val;
973 }
974 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
975}
976
977void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
978{
979 struct mn mn = {0}; /* avoid unitialized warnings */
9f5314fb 980 union uvh_node_id_u node_id;
c443c03d
MT		 981
982 get_mn(&mn);
983 hub_info->m_val = mn.m_val;
984 hub_info->n_val = mn.n_val;
985 hub_info->m_shift = mn.m_shift;
405422d8 986 hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
c443c03d
MT		 987
988 hub_info->hub_revision = uv_hub_info->hub_revision;
405422d8 989 hub_info->pnode_mask = uv_cpuid.pnode_mask;
1de329c1 990 hub_info->min_pnode = _min_pnode;
6e27b91c
MT		 991 hub_info->min_socket = _min_socket;
992 hub_info->pnode_to_socket = _pnode_to_socket;
993 hub_info->socket_to_node = _socket_to_node;
994 hub_info->socket_to_pnode = _socket_to_pnode;
405422d8
MT		 995 hub_info->gpa_mask = mn.m_val ?
996 (1UL << (mn.m_val + mn.n_val)) - 1 :
997 (1UL << uv_cpuid.gpa_shift) - 1;
c443c03d
MT		 998
999 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1000 hub_info->gnode_extra =
1001 (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
1002
1003 hub_info->gnode_upper =
1004 ((unsigned long)hub_info->gnode_extra << mn.m_val);
1005
1de329c1
MT		 1006 if (uv_gp_table) {
1007 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1008 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1009 hub_info->global_gru_base = uv_gp_table->gru_base;
1010 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1011 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1012 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1013 } else {
1014 hub_info->global_mmr_base =
1015 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1016 ~UV_MMR_ENABLE;
1017 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1018 }
c443c03d
MT		 1019
1020 get_lowmem_redirect(
1021 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
1022
405422d8 1023 hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
c443c03d
MT		 1024
1025 /* show system specific info */
1026 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
1027 hub_info->n_val, hub_info->m_val,
1028 hub_info->m_shift, hub_info->n_lshift);
1029
1de329c1
MT		 1030 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
1031 hub_info->gpa_mask, hub_info->gpa_shift,
1032 hub_info->pnode_mask, hub_info->apic_pnode_shift);
1033
1034 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
1035 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1036 hub_info->global_gru_base, hub_info->global_gru_shift);
c443c03d
MT		 1037
1038 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1039 hub_info->gnode_upper, hub_info->gnode_extra);
1de329c1
MT		 1040}
1041
1042static void __init decode_gam_params(unsigned long ptr)
1043{
1044 uv_gp_table = (struct uv_gam_parameters *)ptr;
1045
1046 pr_info("UV: GAM Params...\n");
1047 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1048 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1049 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1050 uv_gp_table->gpa_shift);
1051}
1052
1053static void __init decode_gam_rng_tbl(unsigned long ptr)
1054{
1055 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1056 unsigned long lgre = 0;
1057 int index = 0;
1058 int sock_min = 999999, pnode_min = 99999;
1059 int sock_max = -1, pnode_max = -1;
1060
1061 uv_gre_table = gre;
1062 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1063 if (!index) {
1064 pr_info("UV: GAM Range Table...\n");
1065 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s %3s\n",
1066 "Range", "", "Size", "Type", "NASID",
1067 "SID", "PN", "PXM");
1068 }
1069 pr_info(
1070 "UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x %3d\n",
1071 index++,
1072 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1073 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1074 ((unsigned long)(gre->limit - lgre)) >>
1075 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1076 gre->type, gre->nasid, gre->sockid,
1077 gre->pnode, gre->pxm);
1078
1079 lgre = gre->limit;
1080 if (sock_min > gre->sockid)
1081 sock_min = gre->sockid;
1082 if (sock_max < gre->sockid)
1083 sock_max = gre->sockid;
1084 if (pnode_min > gre->pnode)
1085 pnode_min = gre->pnode;
1086 if (pnode_max < gre->pnode)
1087 pnode_max = gre->pnode;
1088 }
1089
1090 _min_socket = sock_min;
1091 _max_socket = sock_max;
1092 _min_pnode = pnode_min;
1093 _max_pnode = pnode_max;
1094 _gr_table_len = index;
1095 pr_info(
1096 "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1097 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1098}
1099
1100static void __init decode_uv_systab(void)
1101{
1102 struct uv_systab *st;
1103 int i;
1104
1105 st = uv_systab;
1106 if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
1107 return;
1108 if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
1109 pr_crit(
1110 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1111 st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
1112 BUG();
1113 }
c443c03d 1114
1de329c1
MT		 1115 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1116 unsigned long ptr = st->entry[i].offset;
c443c03d 1117
1de329c1
MT		 1118 if (!ptr)
1119 continue;
1120
1121 ptr = ptr + (unsigned long)st;
1122
1123 switch (st->entry[i].type) {
1124 case UV_SYSTAB_TYPE_GAM_PARAMS:
1125 decode_gam_params(ptr);
1126 break;
1127
1128 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1129 decode_gam_rng_tbl(ptr);
1130 break;
1131 }
1132 }
c443c03d
MT		 1133}
1134
906f3b20
MT		 1135/*
1136 * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
1137 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
1138 * .. being replaced by GAM Range Table
1139 */
1140static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1141{
1142 size_t bytes;
1143 int blade, i, j, uv_pb = 0, num_nodes = num_possible_nodes();
1144
1145 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1146 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1147 unsigned long np;
1148
1149 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1150 if (np)
1151 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1152
1153 uv_pb += hweight64(np);
1154 }
1155 if (uv_possible_blades != uv_pb)
1156 uv_possible_blades = uv_pb;
1157
1158 bytes = num_nodes * sizeof(_node_to_pnode[0]);
1159 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1160 BUG_ON(!_node_to_pnode);
1161
1162 for (blade = 0, i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1163 unsigned short pnode;
1164 unsigned long present =
1165 uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1166
1167 for (j = 0; j < 64; j++) {
1168 if (!test_bit(j, &present))
1169 continue;
1170 pnode = (i * 64 + j) & hub_info->pnode_mask;
1171 _node_to_pnode[blade++] = pnode;
1172 }
1173 if (blade > num_nodes) {
1174 pr_err("UV: blade count(%d) exceeds node count(%d)!\n",
1175 blade, num_nodes);
1176 BUG();
1177 }
1178 }
1179}
1180
6e27b91c
MT		 1181static void __init build_socket_tables(void)
1182{
1183 struct uv_gam_range_entry *gre = uv_gre_table;
1184 int num, nump;
1185 int cpu, i, lnid;
1186 int minsock = _min_socket;
1187 int maxsock = _max_socket;
1188 int minpnode = _min_pnode;
1189 int maxpnode = _max_pnode;
1190 size_t bytes;
1191
1192 if (!gre) {
1193 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1194 pr_info("UV: No UVsystab socket table, ignoring\n");
1195 return; /* not required */
1196 }
1197 pr_crit(
1198 "UV: Error: UVsystab address translations not available!\n");
1199 BUG();
1200 }
1201
1202 /* build socket id -> node id, pnode */
1203 num = maxsock - minsock + 1;
1204 bytes = num * sizeof(_socket_to_node[0]);
1205 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1206 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1207
1208 nump = maxpnode - minpnode + 1;
1209 bytes = nump * sizeof(_pnode_to_socket[0]);
1210 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1211 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1212
1213 for (i = 0; i < num; i++)
1214 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1215
1216 for (i = 0; i < nump; i++)
1217 _pnode_to_socket[i] = SOCK_EMPTY;
1218
1219 /* fill in pnode/node/addr conversion list values */
1220 pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n");
1221 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1222 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1223 continue;
1224 i = gre->sockid - minsock;
1225 if (_socket_to_pnode[i] != SOCK_EMPTY)
1226 continue; /* duplicate */
1227 _socket_to_pnode[i] = gre->pnode;
1228 _socket_to_node[i] = gre->pxm;
1229
1230 i = gre->pnode - minpnode;
1231 _pnode_to_socket[i] = gre->sockid;
1232
1233 pr_info(
1234 "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n",
1235 gre->sockid, gre->type, gre->nasid,
1236 _socket_to_pnode[gre->sockid - minsock],
1237 _socket_to_node[gre->sockid - minsock],
1238 _pnode_to_socket[gre->pnode - minpnode]);
1239 }
1240
1241 /* check socket -> node values */
1242 lnid = -1;
1243 for_each_present_cpu(cpu) {
1244 int nid = cpu_to_node(cpu);
1245 int apicid, sockid;
1246
1247 if (lnid == nid)
1248 continue;
1249 lnid = nid;
1250 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1251 sockid = apicid >> uv_cpuid.socketid_shift;
1252 i = sockid - minsock;
1253
1254 if (nid != _socket_to_node[i]) {
1255 pr_warn(
1256 "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n",
1257 i, sockid, gre->type, _socket_to_node[i], nid);
1258 _socket_to_node[i] = nid;
1259 }
1260 }
1261
1262 /* Setup physical blade to pnode translation from GAM Range Table */
1263 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1264 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1265 BUG_ON(!_node_to_pnode);
1266
1267 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1268 unsigned short sockid;
1269
1270 for (sockid = minsock; sockid <= maxsock; sockid++) {
1271 if (lnid == _socket_to_node[sockid - minsock]) {
1272 _node_to_pnode[lnid] =
1273 _socket_to_pnode[sockid - minsock];
1274 break;
1275 }
1276 }
1277 if (sockid > maxsock) {
1278 pr_err("UV: socket for node %d not found!\n", lnid);
1279 BUG();
1280 }
1281 }
1282
1283 /*
1284 * If socket id == pnode or socket id == node for all nodes,
1285 * system runs faster by removing corresponding conversion table.
1286 */
1287 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1288 if (minsock == 0) {
1289 for (i = 0; i < num; i++)
1290 if (_socket_to_node[i] == SOCK_EMPTY ||
1291 i != _socket_to_node[i])
1292 break;
1293 if (i >= num) {
1294 kfree(_socket_to_node);
1295 _socket_to_node = NULL;
1296 pr_info("UV: 1:1 socket_to_node table removed\n");
1297 }
1298 }
1299 if (minsock == minpnode) {
1300 for (i = 0; i < num; i++)
1301 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1302 _socket_to_pnode[i] != i + minpnode)
1303 break;
1304 if (i >= num) {
1305 kfree(_socket_to_pnode);
1306 _socket_to_pnode = NULL;
1307 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1308 }
1309 }
1310}
1311
c443c03d
MT		 1312void __init uv_system_init(void)
1313{
1314 struct uv_hub_info_s hub_info = {0};
906f3b20
MT		 1315 int bytes, cpu, nodeid;
1316 unsigned short min_pnode = 9999, max_pnode = 0;
a0ec83f3
MT		 1317 char *hub = is_uv4_hub() ? "UV400" :
1318 is_uv3_hub() ? "UV300" :
1319 is_uv2_hub() ? "UV2000/3000" :
1320 is_uv1_hub() ? "UV100/1000" : NULL;
ac23d4ee 1321
1912c7af
MT		 1322 if (!hub) {
1323 pr_err("UV: Unknown/unsupported UV hub\n");
1324 return;
1325 }
b15cc4a1 1326 pr_info("UV: Found %s hub\n", hub);
d394f2d9
AT		 1327
1328 /* We now only need to map the MMRs on UV1 */
1329 if (is_uv1_hub())
1330 map_low_mmrs();
918bc960 1331
1de329c1
MT		 1332 uv_bios_init(); /* get uv_systab for decoding */
1333 decode_uv_systab();
6e27b91c 1334 build_socket_tables();
c443c03d 1335 uv_init_hub_info(&hub_info);
906f3b20
MT		 1336 uv_possible_blades = num_possible_nodes();
1337 if (!_node_to_pnode)
1338 boot_init_possible_blades(&hub_info);
da517a08
JS		 1339
1340 /* uv_num_possible_blades() is really the hub count */
0045ddd2
MT		 1341 pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1342 uv_num_possible_blades(),
1343 num_possible_nodes(),
1344 num_possible_cpus());
ac23d4ee 1345
b76365a1
RA		 1346 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
1347 &sn_region_size, &system_serial_number);
c443c03d 1348 hub_info.coherency_domain_number = sn_coherency_id;
7019cc2d
RA		 1349 uv_rtc_init();
1350
906f3b20
MT		 1351 bytes = sizeof(void *) * uv_num_possible_blades();
1352 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1353 BUG_ON(!__uv_hub_info_list);
39d30770 1354
906f3b20
MT		 1355 bytes = sizeof(struct uv_hub_info_s);
1356 for_each_node(nodeid) {
1357 struct uv_hub_info_s *new_hub;
1358 unsigned short pnode;
1359
1360 if (__uv_hub_info_list[nodeid]) {
1361 pr_err("UV: Node %d UV HUB already initialized!?\n",
1362 nodeid);
1363 BUG();
3edcf2ff 1364 }
9f5314fb 1365
906f3b20
MT		 1366 /* Allocate new per hub info list */
1367 new_hub = (nodeid == 0) ?
1368 &uv_hub_info_node0 :
1369 kzalloc_node(bytes, GFP_KERNEL, nodeid);
1370 BUG_ON(!new_hub);
1371 __uv_hub_info_list[nodeid] = new_hub;
1372 new_hub = uv_hub_info_list(nodeid);
1373 BUG_ON(!new_hub);
1374 *new_hub = hub_info;
1375
1376 pnode = _node_to_pnode[nodeid];
1377 min_pnode = min(pnode, min_pnode);
1378 max_pnode = max(pnode, max_pnode);
1379 new_hub->pnode = pnode;
1380 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1381 new_hub->memory_nid = -1;
1382 new_hub->nr_possible_cpus = 0;
1383 new_hub->nr_online_cpus = 0;
1384 }
6c7184b7 1385
906f3b20
MT		 1386 /* Initialize per cpu info */
1387 for_each_possible_cpu(cpu) {
1388 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
0045ddd2 1389
906f3b20 1390 nodeid = cpu_to_node(cpu);
3edcf2ff 1391 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
3edcf2ff 1392 uv_cpu_info_per(cpu)->blade_cpu_id =
906f3b20
MT		 1393 uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1394 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1395 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1396 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
ac23d4ee 1397 }
83f5d894 1398
906f3b20
MT		 1399 /* Display per node info */
1400 for_each_node(nodeid) {
1401 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1402 nodeid,
1403 uv_hub_info_list(nodeid)->pnode,
1404 uv_hub_info_list(nodeid)->nr_possible_cpus);
6a891a24
JS		 1405 }
1406
906f3b20 1407 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
83f5d894 1408 map_gru_high(max_pnode);
daf7b9c9 1409 map_mmr_high(max_pnode);
b15cc4a1 1410 map_mmioh_high(min_pnode, max_pnode);
ac23d4ee 1411
0d12ef0c 1412 uv_nmi_setup();
8da077d6 1413 uv_cpu_init();
7f1baa06 1414 uv_scir_register_cpu_notifier();
a3d732f9 1415 proc_mkdir("sgi_uv", NULL);
841582ea
MT		 1416
1417 /* register Legacy VGA I/O redirection handler */
1418 pci_register_set_vga_state(uv_set_vga_state);
818987e9
CW		 1419
1420 /*
1421 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
1422 * EFI is not enabled in the kdump kernel.
1423 */
1424 if (is_kdump_kernel())
1425 reboot_type = BOOT_ACPI;
ac23d4ee 1426}
107e0e0c
SS		 1427
1428apic_driver(apic_x2apic_uv_x);
Linux 6.x block layer and io_uring tree(s)