Commit | Line | Data |
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ac23d4ee JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV APIC functions (note: not an Intel compatible APIC) | |
7 | * | |
5f40f7d9 | 8 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
ac23d4ee | 9 | */ |
ac23d4ee | 10 | #include <linux/cpumask.h> |
0b1da1c8 IM |
11 | #include <linux/hardirq.h> |
12 | #include <linux/proc_fs.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
ac23d4ee | 16 | #include <linux/string.h> |
ac23d4ee | 17 | #include <linux/ctype.h> |
ac23d4ee | 18 | #include <linux/sched.h> |
7f1baa06 | 19 | #include <linux/timer.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0b1da1c8 IM |
21 | #include <linux/cpu.h> |
22 | #include <linux/init.h> | |
27229ca6 | 23 | #include <linux/io.h> |
841582ea | 24 | #include <linux/pci.h> |
78c06176 | 25 | #include <linux/kdebug.h> |
ca444564 | 26 | #include <linux/delay.h> |
818987e9 | 27 | #include <linux/crash_dump.h> |
1b3a5d02 | 28 | #include <linux/reboot.h> |
0b1da1c8 | 29 | |
ac23d4ee JS |
30 | #include <asm/uv/uv_mmrs.h> |
31 | #include <asm/uv/uv_hub.h> | |
0b1da1c8 IM |
32 | #include <asm/current.h> |
33 | #include <asm/pgtable.h> | |
7019cc2d | 34 | #include <asm/uv/bios.h> |
0b1da1c8 IM |
35 | #include <asm/uv/uv.h> |
36 | #include <asm/apic.h> | |
37 | #include <asm/ipi.h> | |
38 | #include <asm/smp.h> | |
fd12a0d6 | 39 | #include <asm/x86_init.h> |
1d44e828 JS |
40 | #include <asm/nmi.h> |
41 | ||
510b3725 YL |
42 | DEFINE_PER_CPU(int, x2apic_extra_bits); |
43 | ||
841582ea MT |
44 | #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) |
45 | ||
1b9b89e7 | 46 | static enum uv_system_type uv_system_type; |
fd12a0d6 | 47 | static u64 gru_start_paddr, gru_end_paddr; |
879d5ad0 DS |
48 | static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; |
49 | static u64 gru_dist_lmask, gru_dist_umask; | |
c8f730b1 | 50 | static union uvh_apicid uvh_apicid; |
7a1110e8 JS |
51 | int uv_min_hub_revision_id; |
52 | EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); | |
8191c9f6 DS |
53 | unsigned int uv_apicid_hibits; |
54 | EXPORT_SYMBOL_GPL(uv_apicid_hibits); | |
fd12a0d6 | 55 | |
1a8880a1 SS |
56 | static struct apic apic_x2apic_uv_x; |
57 | ||
7563421b MT |
58 | /* Set this to use hardware error handler instead of kernel panic */ |
59 | static int disable_uv_undefined_panic = 1; | |
60 | unsigned long uv_undefined(char *str) | |
61 | { | |
62 | if (likely(!disable_uv_undefined_panic)) | |
63 | panic("UV: error: undefined MMR: %s\n", str); | |
64 | else | |
65 | pr_crit("UV: error: undefined MMR: %s\n", str); | |
66 | return ~0ul; /* cause a machine fault */ | |
67 | } | |
68 | EXPORT_SYMBOL(uv_undefined); | |
69 | ||
e6810413 JS |
70 | static unsigned long __init uv_early_read_mmr(unsigned long addr) |
71 | { | |
72 | unsigned long val, *mmr; | |
73 | ||
74 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); | |
75 | val = *mmr; | |
76 | early_iounmap(mmr, sizeof(*mmr)); | |
77 | return val; | |
78 | } | |
79 | ||
eb41c8be | 80 | static inline bool is_GRU_range(u64 start, u64 end) |
fd12a0d6 | 81 | { |
879d5ad0 DS |
82 | if (gru_dist_base) { |
83 | u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */ | |
84 | u64 sl = start & gru_dist_lmask; /* base offset bits */ | |
85 | u64 eu = end & gru_dist_umask; | |
86 | u64 el = end & gru_dist_lmask; | |
87 | ||
88 | /* Must reside completely within a single GRU range */ | |
89 | return (sl == gru_dist_base && el == gru_dist_base && | |
90 | su >= gru_first_node_paddr && | |
91 | su <= gru_last_node_paddr && | |
92 | eu == su); | |
93 | } else { | |
94 | return start >= gru_start_paddr && end <= gru_end_paddr; | |
95 | } | |
fd12a0d6 JS |
96 | } |
97 | ||
eb41c8be | 98 | static bool uv_is_untracked_pat_range(u64 start, u64 end) |
fd12a0d6 JS |
99 | { |
100 | return is_ISA_range(start, end) || is_GRU_range(start, end); | |
101 | } | |
1b9b89e7 | 102 | |
d8850ba4 | 103 | static int __init early_get_pnodeid(void) |
27229ca6 JS |
104 | { |
105 | union uvh_node_id_u node_id; | |
d8850ba4 JS |
106 | union uvh_rh_gam_config_mmr_u m_n_config; |
107 | int pnode; | |
7a1110e8 JS |
108 | |
109 | /* Currently, all blades have same revision number */ | |
e6810413 | 110 | node_id.v = uv_early_read_mmr(UVH_NODE_ID); |
d8850ba4 | 111 | m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); |
7a1110e8 JS |
112 | uv_min_hub_revision_id = node_id.s.revision; |
113 | ||
b15cc4a1 MT |
114 | switch (node_id.s.part_number) { |
115 | case UV2_HUB_PART_NUMBER: | |
116 | case UV2_HUB_PART_NUMBER_X: | |
b495e039 | 117 | uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; |
b15cc4a1 MT |
118 | break; |
119 | case UV3_HUB_PART_NUMBER: | |
120 | case UV3_HUB_PART_NUMBER_X: | |
dd3c9c4b | 121 | uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; |
b15cc4a1 | 122 | break; |
a0ec83f3 MT |
123 | case UV4_HUB_PART_NUMBER: |
124 | uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; | |
125 | break; | |
b15cc4a1 | 126 | } |
2a919596 JS |
127 | |
128 | uv_hub_info->hub_revision = uv_min_hub_revision_id; | |
d8850ba4 JS |
129 | pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); |
130 | return pnode; | |
27229ca6 JS |
131 | } |
132 | ||
0520bd84 | 133 | static void __init early_get_apic_pnode_shift(void) |
c8f730b1 | 134 | { |
e6810413 | 135 | uvh_apicid.v = uv_early_read_mmr(UVH_APICID); |
c8f730b1 RA |
136 | if (!uvh_apicid.v) |
137 | /* | |
138 | * Old bios, use default value | |
139 | */ | |
140 | uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; | |
c8f730b1 RA |
141 | } |
142 | ||
8191c9f6 DS |
143 | /* |
144 | * Add an extra bit as dictated by bios to the destination apicid of | |
145 | * interrupts potentially passing through the UV HUB. This prevents | |
146 | * a deadlock between interrupts and IO port operations. | |
147 | */ | |
148 | static void __init uv_set_apicid_hibit(void) | |
149 | { | |
2a919596 | 150 | union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; |
8191c9f6 | 151 | |
2a919596 JS |
152 | if (is_uv1_hub()) { |
153 | apicid_mask.v = | |
154 | uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); | |
155 | uv_apicid_hibits = | |
156 | apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; | |
157 | } | |
8191c9f6 DS |
158 | } |
159 | ||
52459ab9 | 160 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 161 | { |
379b97e2 MT |
162 | int pnodeid; |
163 | int uv_apic; | |
1d2c867c | 164 | |
7a4e0170 MT |
165 | if (strncmp(oem_id, "SGI", 3) != 0) |
166 | return 0; | |
167 | ||
379b97e2 MT |
168 | /* |
169 | * Determine UV arch type. | |
170 | * SGI: UV100/1000 | |
171 | * SGI2: UV2000/3000 | |
172 | * SGI3: UV300 (truncated to 4 chars because of different varieties) | |
a0ec83f3 | 173 | * SGI4: UV400 (truncated to 4 chars because of different varieties) |
379b97e2 MT |
174 | */ |
175 | uv_hub_info->hub_revision = | |
a0ec83f3 | 176 | !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : |
379b97e2 MT |
177 | !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : |
178 | !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : | |
179 | !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; | |
180 | ||
181 | if (uv_hub_info->hub_revision == 0) | |
182 | goto badbios; | |
183 | ||
184 | pnodeid = early_get_pnodeid(); | |
185 | early_get_apic_pnode_shift(); | |
186 | x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; | |
187 | x86_platform.nmi_init = uv_nmi_init; | |
188 | ||
189 | if (!strcmp(oem_table_id, "UVX")) { /* most common */ | |
190 | uv_system_type = UV_X2APIC; | |
191 | uv_apic = 0; | |
192 | ||
193 | } else if (!strcmp(oem_table_id, "UVH")) { /* only UV1 systems */ | |
194 | uv_system_type = UV_NON_UNIQUE_APIC; | |
195 | __this_cpu_write(x2apic_extra_bits, | |
196 | pnodeid << uvh_apicid.s.pnode_shift); | |
197 | uv_set_apicid_hibit(); | |
198 | uv_apic = 1; | |
199 | ||
200 | } else if (!strcmp(oem_table_id, "UVL")) { /* only used for */ | |
201 | uv_system_type = UV_LEGACY_APIC; /* very small systems */ | |
202 | uv_apic = 0; | |
203 | ||
204 | } else { | |
205 | goto badbios; | |
1b9b89e7 | 206 | } |
379b97e2 MT |
207 | |
208 | pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", | |
209 | oem_id, oem_table_id, uv_system_type, | |
210 | uv_min_hub_revision_id, uv_apic); | |
211 | ||
212 | return uv_apic; | |
213 | ||
214 | badbios: | |
215 | pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); | |
216 | pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); | |
217 | BUG(); | |
1b9b89e7 YL |
218 | } |
219 | ||
220 | enum uv_system_type get_uv_system_type(void) | |
221 | { | |
222 | return uv_system_type; | |
223 | } | |
224 | ||
225 | int is_uv_system(void) | |
226 | { | |
227 | return uv_system_type != UV_NONE; | |
228 | } | |
8067794b | 229 | EXPORT_SYMBOL_GPL(is_uv_system); |
1b9b89e7 | 230 | |
ac23d4ee JS |
231 | DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
232 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); | |
233 | ||
0045ddd2 MT |
234 | DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); |
235 | EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); | |
236 | ||
ac23d4ee JS |
237 | struct uv_blade_info *uv_blade_info; |
238 | EXPORT_SYMBOL_GPL(uv_blade_info); | |
239 | ||
240 | short *uv_node_to_blade; | |
241 | EXPORT_SYMBOL_GPL(uv_node_to_blade); | |
242 | ||
243 | short *uv_cpu_to_blade; | |
244 | EXPORT_SYMBOL_GPL(uv_cpu_to_blade); | |
245 | ||
246 | short uv_possible_blades; | |
247 | EXPORT_SYMBOL_GPL(uv_possible_blades); | |
248 | ||
7019cc2d RA |
249 | unsigned long sn_rtc_cycles_per_second; |
250 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | |
251 | ||
148f9bb8 | 252 | static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
ac23d4ee JS |
253 | { |
254 | unsigned long val; | |
9f5314fb | 255 | int pnode; |
ac23d4ee | 256 | |
9f5314fb | 257 | pnode = uv_apicid_to_pnode(phys_apicid); |
8191c9f6 | 258 | phys_apicid |= uv_apicid_hibits; |
ac23d4ee JS |
259 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | |
260 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 261 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 262 | APIC_DM_INIT; |
9f5314fb | 263 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
34d05591 JS |
264 | |
265 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | |
266 | (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | | |
2b6163bf | 267 | ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | |
34d05591 | 268 | APIC_DM_STARTUP; |
9f5314fb | 269 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
2b6163bf | 270 | |
ac23d4ee JS |
271 | return 0; |
272 | } | |
273 | ||
274 | static void uv_send_IPI_one(int cpu, int vector) | |
275 | { | |
66666e50 | 276 | unsigned long apicid; |
9f5314fb | 277 | int pnode; |
ac23d4ee | 278 | |
1e0b5d00 | 279 | apicid = per_cpu(x86_cpu_to_apicid, cpu); |
9f5314fb | 280 | pnode = uv_apicid_to_pnode(apicid); |
66666e50 | 281 | uv_hub_send_ipi(pnode, apicid, vector); |
ac23d4ee JS |
282 | } |
283 | ||
bcda016e | 284 | static void uv_send_IPI_mask(const struct cpumask *mask, int vector) |
ac23d4ee JS |
285 | { |
286 | unsigned int cpu; | |
287 | ||
bcda016e | 288 | for_each_cpu(cpu, mask) |
e7986739 MT |
289 | uv_send_IPI_one(cpu, vector); |
290 | } | |
291 | ||
bcda016e | 292 | static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
e7986739 | 293 | { |
e7986739 | 294 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 295 | unsigned int cpu; |
e7986739 | 296 | |
dac5f412 | 297 | for_each_cpu(cpu, mask) { |
e7986739 | 298 | if (cpu != this_cpu) |
ac23d4ee | 299 | uv_send_IPI_one(cpu, vector); |
dac5f412 | 300 | } |
ac23d4ee JS |
301 | } |
302 | ||
303 | static void uv_send_IPI_allbutself(int vector) | |
304 | { | |
e7986739 | 305 | unsigned int this_cpu = smp_processor_id(); |
dac5f412 | 306 | unsigned int cpu; |
ac23d4ee | 307 | |
dac5f412 | 308 | for_each_online_cpu(cpu) { |
e7986739 MT |
309 | if (cpu != this_cpu) |
310 | uv_send_IPI_one(cpu, vector); | |
dac5f412 | 311 | } |
ac23d4ee JS |
312 | } |
313 | ||
314 | static void uv_send_IPI_all(int vector) | |
315 | { | |
bcda016e | 316 | uv_send_IPI_mask(cpu_online_mask, vector); |
ac23d4ee JS |
317 | } |
318 | ||
b7157acf SP |
319 | static int uv_apic_id_valid(int apicid) |
320 | { | |
321 | return 1; | |
322 | } | |
323 | ||
ac23d4ee JS |
324 | static int uv_apic_id_registered(void) |
325 | { | |
326 | return 1; | |
327 | } | |
328 | ||
277d1f58 | 329 | static void uv_init_apic_ldr(void) |
5c520a67 SS |
330 | { |
331 | } | |
332 | ||
ff164324 | 333 | static int |
debccb3e | 334 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
335 | const struct cpumask *andmask, |
336 | unsigned int *apicid) | |
95d313cf | 337 | { |
ea3807ea | 338 | int unsigned cpu; |
95d313cf MT |
339 | |
340 | /* | |
341 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
342 | * May as well be the first. | |
343 | */ | |
debccb3e | 344 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
345 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
346 | break; | |
debccb3e | 347 | } |
ff164324 | 348 | |
ea3807ea | 349 | if (likely(cpu < nr_cpu_ids)) { |
a5a39156 AG |
350 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; |
351 | return 0; | |
a5a39156 | 352 | } |
ea3807ea AG |
353 | |
354 | return -EINVAL; | |
95d313cf MT |
355 | } |
356 | ||
ca6c8ed4 | 357 | static unsigned int x2apic_get_apic_id(unsigned long x) |
0c81c746 SS |
358 | { |
359 | unsigned int id; | |
360 | ||
361 | WARN_ON(preemptible() && num_online_cpus() > 1); | |
0a3aee0d | 362 | id = x | __this_cpu_read(x2apic_extra_bits); |
0c81c746 SS |
363 | |
364 | return id; | |
365 | } | |
366 | ||
1b9b89e7 | 367 | static unsigned long set_apic_id(unsigned int id) |
f910a9dc YL |
368 | { |
369 | unsigned long x; | |
370 | ||
371 | /* maskout x2apic_extra_bits ? */ | |
372 | x = id; | |
373 | return x; | |
374 | } | |
375 | ||
376 | static unsigned int uv_read_apic_id(void) | |
377 | { | |
378 | ||
ca6c8ed4 | 379 | return x2apic_get_apic_id(apic_read(APIC_ID)); |
f910a9dc YL |
380 | } |
381 | ||
d4c9a9f3 | 382 | static int uv_phys_pkg_id(int initial_apicid, int index_msb) |
ac23d4ee | 383 | { |
0c81c746 | 384 | return uv_read_apic_id() >> index_msb; |
ac23d4ee JS |
385 | } |
386 | ||
ac23d4ee JS |
387 | static void uv_send_IPI_self(int vector) |
388 | { | |
389 | apic_write(APIC_SELF_IPI, vector); | |
390 | } | |
ac23d4ee | 391 | |
9ebd680b SS |
392 | static int uv_probe(void) |
393 | { | |
394 | return apic == &apic_x2apic_uv_x; | |
395 | } | |
396 | ||
1a8880a1 | 397 | static struct apic __refdata apic_x2apic_uv_x = { |
c7967329 IM |
398 | |
399 | .name = "UV large system", | |
9ebd680b | 400 | .probe = uv_probe, |
c7967329 | 401 | .acpi_madt_oem_check = uv_acpi_madt_oem_check, |
b7157acf | 402 | .apic_id_valid = uv_apic_id_valid, |
c7967329 IM |
403 | .apic_id_registered = uv_apic_id_registered, |
404 | ||
f8987a10 | 405 | .irq_delivery_mode = dest_Fixed, |
c5997fa8 | 406 | .irq_dest_mode = 0, /* physical */ |
c7967329 | 407 | |
bf721d3a | 408 | .target_cpus = online_target_cpus, |
08125d3e | 409 | .disable_esr = 0, |
bdb1a9b6 | 410 | .dest_logical = APIC_DEST_LOGICAL, |
c7967329 | 411 | .check_apicid_used = NULL, |
c7967329 | 412 | |
9d8e1066 | 413 | .vector_allocation_domain = default_vector_allocation_domain, |
c7967329 IM |
414 | .init_apic_ldr = uv_init_apic_ldr, |
415 | ||
416 | .ioapic_phys_id_map = NULL, | |
417 | .setup_apic_routing = NULL, | |
a21769a4 | 418 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
c7967329 | 419 | .apicid_to_cpu_present = NULL, |
a27a6210 | 420 | .check_phys_apicid_present = default_check_phys_apicid_present, |
d4c9a9f3 | 421 | .phys_pkg_id = uv_phys_pkg_id, |
c7967329 | 422 | |
ca6c8ed4 | 423 | .get_apic_id = x2apic_get_apic_id, |
c7967329 IM |
424 | .set_apic_id = set_apic_id, |
425 | .apic_id_mask = 0xFFFFFFFFu, | |
426 | ||
c7967329 IM |
427 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
428 | ||
8642ea95 | 429 | .send_IPI = uv_send_IPI_one, |
c7967329 IM |
430 | .send_IPI_mask = uv_send_IPI_mask, |
431 | .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, | |
432 | .send_IPI_allbutself = uv_send_IPI_allbutself, | |
433 | .send_IPI_all = uv_send_IPI_all, | |
434 | .send_IPI_self = uv_send_IPI_self, | |
435 | ||
1f5bcabf | 436 | .wakeup_secondary_cpu = uv_wakeup_secondary, |
c7967329 | 437 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
438 | |
439 | .read = native_apic_msr_read, | |
440 | .write = native_apic_msr_write, | |
0ab711ae | 441 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
442 | .icr_read = native_x2apic_icr_read, |
443 | .icr_write = native_x2apic_icr_write, | |
444 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
445 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
ac23d4ee JS |
446 | }; |
447 | ||
148f9bb8 | 448 | static void set_x2apic_extra_bits(int pnode) |
ac23d4ee | 449 | { |
16ee8db6 | 450 | __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); |
ac23d4ee JS |
451 | } |
452 | ||
453 | /* | |
454 | * Called on boot cpu. | |
455 | */ | |
9f5314fb JS |
456 | static __init int boot_pnode_to_blade(int pnode) |
457 | { | |
458 | int blade; | |
459 | ||
460 | for (blade = 0; blade < uv_num_possible_blades(); blade++) | |
461 | if (pnode == uv_blade_info[blade].pnode) | |
462 | return blade; | |
463 | BUG(); | |
464 | } | |
465 | ||
c443c03d | 466 | #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 |
9f5314fb JS |
467 | #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT |
468 | ||
9f5314fb JS |
469 | static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) |
470 | { | |
62b0cfc2 | 471 | union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; |
9f5314fb | 472 | union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; |
c443c03d MT |
473 | unsigned long m_redirect; |
474 | unsigned long m_overlay; | |
9f5314fb JS |
475 | int i; |
476 | ||
c443c03d MT |
477 | for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { |
478 | switch (i) { | |
479 | case 0: | |
480 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; | |
481 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; | |
482 | break; | |
483 | case 1: | |
484 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; | |
485 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; | |
486 | break; | |
487 | case 2: | |
488 | m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; | |
489 | m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; | |
490 | break; | |
491 | } | |
492 | alias.v = uv_read_local_mmr(m_overlay); | |
036ed8ba | 493 | if (alias.s.enable && alias.s.base == 0) { |
9f5314fb | 494 | *size = (1UL << alias.s.m_alias); |
c443c03d MT |
495 | redirect.v = uv_read_local_mmr(m_redirect); |
496 | *base = (unsigned long)redirect.s.dest_base | |
497 | << DEST_SHIFT; | |
9f5314fb JS |
498 | return; |
499 | } | |
500 | } | |
036ed8ba | 501 | *base = *size = 0; |
9f5314fb JS |
502 | } |
503 | ||
83f5d894 JS |
504 | enum map_type {map_wb, map_uc}; |
505 | ||
fcfbb2b5 MT |
506 | static __init void map_high(char *id, unsigned long base, int pshift, |
507 | int bshift, int max_pnode, enum map_type map_type) | |
83f5d894 JS |
508 | { |
509 | unsigned long bytes, paddr; | |
510 | ||
fcfbb2b5 MT |
511 | paddr = base << pshift; |
512 | bytes = (1UL << bshift) * (max_pnode + 1); | |
b15cc4a1 MT |
513 | if (!paddr) { |
514 | pr_info("UV: Map %s_HI base address NULL\n", id); | |
515 | return; | |
516 | } | |
879d5ad0 | 517 | pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); |
83f5d894 JS |
518 | if (map_type == map_uc) |
519 | init_extra_mapping_uc(paddr, bytes); | |
520 | else | |
521 | init_extra_mapping_wb(paddr, bytes); | |
83f5d894 | 522 | } |
b15cc4a1 | 523 | |
879d5ad0 DS |
524 | static __init void map_gru_distributed(unsigned long c) |
525 | { | |
526 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
527 | u64 paddr; | |
528 | unsigned long bytes; | |
529 | int nid; | |
530 | ||
531 | gru.v = c; | |
532 | /* only base bits 42:28 relevant in dist mode */ | |
533 | gru_dist_base = gru.v & 0x000007fff0000000UL; | |
534 | if (!gru_dist_base) { | |
535 | pr_info("UV: Map GRU_DIST base address NULL\n"); | |
536 | return; | |
537 | } | |
538 | bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
539 | gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); | |
540 | gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); | |
541 | gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ | |
542 | for_each_online_node(nid) { | |
543 | paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | | |
544 | gru_dist_base; | |
545 | init_extra_mapping_wb(paddr, bytes); | |
546 | gru_first_node_paddr = min(paddr, gru_first_node_paddr); | |
547 | gru_last_node_paddr = max(paddr, gru_last_node_paddr); | |
548 | } | |
549 | /* Save upper (63:M) bits of address only for is_GRU_range */ | |
550 | gru_first_node_paddr &= gru_dist_umask; | |
551 | gru_last_node_paddr &= gru_dist_umask; | |
552 | pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", | |
553 | gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); | |
554 | } | |
555 | ||
83f5d894 JS |
556 | static __init void map_gru_high(int max_pnode) |
557 | { | |
558 | union uvh_rh_gam_gru_overlay_config_mmr_u gru; | |
559 | int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
c443c03d MT |
560 | unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; |
561 | unsigned long base; | |
83f5d894 JS |
562 | |
563 | gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); | |
879d5ad0 | 564 | if (!gru.s.enable) { |
b15cc4a1 | 565 | pr_info("UV: GRU disabled\n"); |
879d5ad0 DS |
566 | return; |
567 | } | |
568 | ||
569 | if (is_uv3_hub() && gru.s3.mode) { | |
570 | map_gru_distributed(gru.v); | |
571 | return; | |
fd12a0d6 | 572 | } |
c443c03d MT |
573 | base = (gru.v & mask) >> shift; |
574 | map_high("GRU", base, shift, shift, max_pnode, map_wb); | |
575 | gru_start_paddr = ((u64)base << shift); | |
879d5ad0 | 576 | gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); |
83f5d894 JS |
577 | } |
578 | ||
daf7b9c9 JS |
579 | static __init void map_mmr_high(int max_pnode) |
580 | { | |
581 | union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; | |
582 | int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
583 | ||
584 | mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); | |
585 | if (mmr.s.enable) | |
fcfbb2b5 | 586 | map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); |
b15cc4a1 MT |
587 | else |
588 | pr_info("UV: MMR disabled\n"); | |
589 | } | |
590 | ||
591 | /* | |
592 | * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY | |
593 | * and REDIRECT MMR regs are exactly the same on UV3. | |
594 | */ | |
595 | struct mmioh_config { | |
596 | unsigned long overlay; | |
597 | unsigned long redirect; | |
598 | char *id; | |
599 | }; | |
600 | ||
601 | static __initdata struct mmioh_config mmiohs[] = { | |
602 | { | |
603 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, | |
604 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, | |
605 | "MMIOH0" | |
606 | }, | |
607 | { | |
608 | UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, | |
609 | UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, | |
610 | "MMIOH1" | |
611 | }, | |
612 | }; | |
613 | ||
a2f28e69 | 614 | /* UV3 & UV4 have identical MMIOH overlay configs */ |
b15cc4a1 MT |
615 | static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) |
616 | { | |
617 | union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; | |
618 | unsigned long mmr; | |
619 | unsigned long base; | |
620 | int i, n, shift, m_io, max_io; | |
621 | int nasid, lnasid, fi, li; | |
622 | char *id; | |
623 | ||
624 | id = mmiohs[index].id; | |
625 | overlay.v = uv_read_local_mmr(mmiohs[index].overlay); | |
626 | pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", | |
627 | id, overlay.v, overlay.s3.base, overlay.s3.m_io); | |
628 | if (!overlay.s3.enable) { | |
629 | pr_info("UV: %s disabled\n", id); | |
630 | return; | |
631 | } | |
632 | ||
633 | shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; | |
634 | base = (unsigned long)overlay.s3.base; | |
635 | m_io = overlay.s3.m_io; | |
636 | mmr = mmiohs[index].redirect; | |
637 | n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; | |
638 | min_pnode *= 2; /* convert to NASID */ | |
639 | max_pnode *= 2; | |
640 | max_io = lnasid = fi = li = -1; | |
641 | ||
642 | for (i = 0; i < n; i++) { | |
643 | union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; | |
644 | ||
645 | redirect.v = uv_read_local_mmr(mmr + i * 8); | |
646 | nasid = redirect.s3.nasid; | |
647 | if (nasid < min_pnode || max_pnode < nasid) | |
648 | nasid = -1; /* invalid NASID */ | |
649 | ||
650 | if (nasid == lnasid) { | |
651 | li = i; | |
652 | if (i != n-1) /* last entry check */ | |
653 | continue; | |
654 | } | |
655 | ||
656 | /* check if we have a cached (or last) redirect to print */ | |
657 | if (lnasid != -1 || (i == n-1 && nasid != -1)) { | |
658 | unsigned long addr1, addr2; | |
659 | int f, l; | |
660 | ||
661 | if (lnasid == -1) { | |
662 | f = l = i; | |
663 | lnasid = nasid; | |
664 | } else { | |
665 | f = fi; | |
666 | l = li; | |
667 | } | |
668 | addr1 = (base << shift) + | |
669 | f * (unsigned long)(1 << m_io); | |
670 | addr2 = (base << shift) + | |
671 | (l + 1) * (unsigned long)(1 << m_io); | |
672 | pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", | |
673 | id, fi, li, lnasid, addr1, addr2); | |
674 | if (max_io < l) | |
675 | max_io = l; | |
676 | } | |
677 | fi = li = i; | |
678 | lnasid = nasid; | |
679 | } | |
680 | ||
681 | pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", | |
682 | id, base, shift, m_io, max_io); | |
683 | ||
684 | if (max_io >= 0) | |
685 | map_high(id, base, shift, m_io, max_io, map_uc); | |
daf7b9c9 JS |
686 | } |
687 | ||
b15cc4a1 | 688 | static __init void map_mmioh_high(int min_pnode, int max_pnode) |
83f5d894 JS |
689 | { |
690 | union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; | |
b15cc4a1 MT |
691 | unsigned long mmr, base; |
692 | int shift, enable, m_io, n_io; | |
83f5d894 | 693 | |
a2f28e69 | 694 | if (is_uv3_hub() || is_uv4_hub()) { |
b15cc4a1 MT |
695 | /* Map both MMIOH Regions */ |
696 | map_mmioh_high_uv3(0, min_pnode, max_pnode); | |
697 | map_mmioh_high_uv3(1, min_pnode, max_pnode); | |
698 | return; | |
2a919596 | 699 | } |
b15cc4a1 MT |
700 | |
701 | if (is_uv1_hub()) { | |
702 | mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
703 | shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; | |
704 | mmioh.v = uv_read_local_mmr(mmr); | |
705 | enable = !!mmioh.s1.enable; | |
706 | base = mmioh.s1.base; | |
707 | m_io = mmioh.s1.m_io; | |
708 | n_io = mmioh.s1.n_io; | |
709 | } else if (is_uv2_hub()) { | |
710 | mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; | |
2a919596 | 711 | shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; |
b15cc4a1 MT |
712 | mmioh.v = uv_read_local_mmr(mmr); |
713 | enable = !!mmioh.s2.enable; | |
714 | base = mmioh.s2.base; | |
715 | m_io = mmioh.s2.m_io; | |
716 | n_io = mmioh.s2.n_io; | |
717 | } else | |
718 | return; | |
719 | ||
720 | if (enable) { | |
721 | max_pnode &= (1 << n_io) - 1; | |
722 | pr_info( | |
723 | "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", | |
724 | base, shift, m_io, n_io, max_pnode); | |
725 | map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); | |
726 | } else { | |
727 | pr_info("UV: MMIOH disabled\n"); | |
2a919596 | 728 | } |
83f5d894 JS |
729 | } |
730 | ||
918bc960 JS |
731 | static __init void map_low_mmrs(void) |
732 | { | |
733 | init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); | |
734 | init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); | |
735 | } | |
736 | ||
7019cc2d RA |
737 | static __init void uv_rtc_init(void) |
738 | { | |
922402f1 RA |
739 | long status; |
740 | u64 ticks_per_sec; | |
7019cc2d | 741 | |
922402f1 RA |
742 | status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, |
743 | &ticks_per_sec); | |
744 | if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { | |
7019cc2d RA |
745 | printk(KERN_WARNING |
746 | "unable to determine platform RTC clock frequency, " | |
747 | "guessing.\n"); | |
748 | /* BIOS gives wrong value for clock freq. so guess */ | |
749 | sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; | |
750 | } else | |
751 | sn_rtc_cycles_per_second = ticks_per_sec; | |
752 | } | |
753 | ||
7f1baa06 MT |
754 | /* |
755 | * percpu heartbeat timer | |
756 | */ | |
757 | static void uv_heartbeat(unsigned long ignored) | |
758 | { | |
759 | struct timer_list *timer = &uv_hub_info->scir.timer; | |
760 | unsigned char bits = uv_hub_info->scir.state; | |
761 | ||
762 | /* flip heartbeat bit */ | |
763 | bits ^= SCIR_CPU_HEARTBEAT; | |
764 | ||
69a72a0e MT |
765 | /* is this cpu idle? */ |
766 | if (idle_cpu(raw_smp_processor_id())) | |
7f1baa06 MT |
767 | bits &= ~SCIR_CPU_ACTIVITY; |
768 | else | |
769 | bits |= SCIR_CPU_ACTIVITY; | |
770 | ||
771 | /* update system controller interface reg */ | |
772 | uv_set_scir_bits(bits); | |
773 | ||
774 | /* enable next timer period */ | |
5c333864 | 775 | mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); |
7f1baa06 MT |
776 | } |
777 | ||
148f9bb8 | 778 | static void uv_heartbeat_enable(int cpu) |
7f1baa06 | 779 | { |
99659a92 | 780 | while (!uv_cpu_hub_info(cpu)->scir.enabled) { |
7f1baa06 MT |
781 | struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; |
782 | ||
783 | uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); | |
784 | setup_timer(timer, uv_heartbeat, cpu); | |
785 | timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; | |
786 | add_timer_on(timer, cpu); | |
787 | uv_cpu_hub_info(cpu)->scir.enabled = 1; | |
7f1baa06 | 788 | |
99659a92 RK |
789 | /* also ensure that boot cpu is enabled */ |
790 | cpu = 0; | |
791 | } | |
7f1baa06 MT |
792 | } |
793 | ||
77be80e4 | 794 | #ifdef CONFIG_HOTPLUG_CPU |
148f9bb8 | 795 | static void uv_heartbeat_disable(int cpu) |
7f1baa06 MT |
796 | { |
797 | if (uv_cpu_hub_info(cpu)->scir.enabled) { | |
798 | uv_cpu_hub_info(cpu)->scir.enabled = 0; | |
799 | del_timer(&uv_cpu_hub_info(cpu)->scir.timer); | |
800 | } | |
801 | uv_set_cpu_scir_bits(cpu, 0xff); | |
802 | } | |
803 | ||
7f1baa06 MT |
804 | /* |
805 | * cpu hotplug notifier | |
806 | */ | |
148f9bb8 PG |
807 | static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action, |
808 | void *hcpu) | |
7f1baa06 MT |
809 | { |
810 | long cpu = (long)hcpu; | |
811 | ||
f47ab81a TG |
812 | switch (action & ~CPU_TASKS_FROZEN) { |
813 | case CPU_DOWN_FAILED: | |
7f1baa06 MT |
814 | case CPU_ONLINE: |
815 | uv_heartbeat_enable(cpu); | |
816 | break; | |
817 | case CPU_DOWN_PREPARE: | |
818 | uv_heartbeat_disable(cpu); | |
819 | break; | |
820 | default: | |
821 | break; | |
822 | } | |
823 | return NOTIFY_OK; | |
824 | } | |
825 | ||
826 | static __init void uv_scir_register_cpu_notifier(void) | |
827 | { | |
828 | hotcpu_notifier(uv_scir_cpu_notify, 0); | |
829 | } | |
830 | ||
831 | #else /* !CONFIG_HOTPLUG_CPU */ | |
832 | ||
833 | static __init void uv_scir_register_cpu_notifier(void) | |
834 | { | |
835 | } | |
836 | ||
837 | static __init int uv_init_heartbeat(void) | |
838 | { | |
839 | int cpu; | |
840 | ||
841 | if (is_uv_system()) | |
842 | for_each_online_cpu(cpu) | |
843 | uv_heartbeat_enable(cpu); | |
844 | return 0; | |
845 | } | |
846 | ||
847 | late_initcall(uv_init_heartbeat); | |
848 | ||
849 | #endif /* !CONFIG_HOTPLUG_CPU */ | |
850 | ||
841582ea MT |
851 | /* Direct Legacy VGA I/O traffic to designated IOH */ |
852 | int uv_set_vga_state(struct pci_dev *pdev, bool decode, | |
7ad35cf2 | 853 | unsigned int command_bits, u32 flags) |
841582ea MT |
854 | { |
855 | int domain, bus, rc; | |
856 | ||
7ad35cf2 DA |
857 | PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", |
858 | pdev->devfn, decode, command_bits, flags); | |
841582ea | 859 | |
7ad35cf2 | 860 | if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) |
841582ea MT |
861 | return 0; |
862 | ||
863 | if ((command_bits & PCI_COMMAND_IO) == 0) | |
864 | return 0; | |
865 | ||
866 | domain = pci_domain_nr(pdev->bus); | |
867 | bus = pdev->bus->number; | |
868 | ||
869 | rc = uv_bios_set_legacy_vga_target(decode, domain, bus); | |
870 | PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); | |
871 | ||
872 | return rc; | |
873 | } | |
874 | ||
8da077d6 JS |
875 | /* |
876 | * Called on each cpu to initialize the per_cpu UV data area. | |
0b1da1c8 | 877 | * FIXME: hotplug not supported yet |
8da077d6 | 878 | */ |
148f9bb8 | 879 | void uv_cpu_init(void) |
8da077d6 | 880 | { |
6a6256f9 | 881 | /* CPU 0 initialization will be done via uv_system_init. */ |
8da077d6 JS |
882 | if (!uv_blade_info) |
883 | return; | |
884 | ||
885 | uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; | |
886 | ||
887 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) | |
888 | set_x2apic_extra_bits(uv_hub_info->pnode); | |
889 | } | |
890 | ||
c443c03d MT |
891 | struct mn { |
892 | unsigned char m_val; | |
893 | unsigned char n_val; | |
894 | unsigned char m_shift; | |
895 | unsigned char n_lshift; | |
896 | }; | |
897 | ||
898 | static void get_mn(struct mn *mnp) | |
ac23d4ee | 899 | { |
c443c03d MT |
900 | union uvh_rh_gam_config_mmr_u m_n_config; |
901 | union uv3h_gr0_gam_gr_config_u m_gr_config; | |
902 | ||
903 | m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); | |
904 | mnp->n_val = m_n_config.s.n_skt; | |
905 | if (is_uv4_hub()) { | |
906 | mnp->m_val = 0; | |
907 | mnp->n_lshift = 0; | |
908 | } else if (is_uv3_hub()) { | |
909 | mnp->m_val = m_n_config.s3.m_skt; | |
910 | m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); | |
911 | mnp->n_lshift = m_gr_config.s3.m_skt; | |
912 | } else if (is_uv2_hub()) { | |
913 | mnp->m_val = m_n_config.s2.m_skt; | |
914 | mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; | |
915 | } else if (is_uv1_hub()) { | |
916 | mnp->m_val = m_n_config.s1.m_skt; | |
917 | mnp->n_lshift = mnp->m_val; | |
918 | } | |
919 | mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; | |
920 | } | |
921 | ||
922 | void __init uv_init_hub_info(struct uv_hub_info_s *hub_info) | |
923 | { | |
924 | struct mn mn = {0}; /* avoid unitialized warnings */ | |
9f5314fb | 925 | union uvh_node_id_u node_id; |
c443c03d MT |
926 | |
927 | get_mn(&mn); | |
928 | hub_info->m_val = mn.m_val; | |
929 | hub_info->n_val = mn.n_val; | |
930 | hub_info->m_shift = mn.m_shift; | |
931 | hub_info->n_lshift = mn.n_lshift; | |
932 | ||
933 | hub_info->hub_revision = uv_hub_info->hub_revision; | |
934 | hub_info->pnode_mask = (1 << mn.n_val) - 1; | |
935 | hub_info->gpa_mask = (1UL << (mn.m_val + mn.n_val)) - 1; | |
936 | ||
937 | node_id.v = uv_read_local_mmr(UVH_NODE_ID); | |
938 | hub_info->gnode_extra = | |
939 | (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1; | |
940 | ||
941 | hub_info->gnode_upper = | |
942 | ((unsigned long)hub_info->gnode_extra << mn.m_val); | |
943 | ||
944 | hub_info->global_mmr_base = | |
945 | uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & | |
946 | ~UV_MMR_ENABLE; | |
947 | ||
948 | get_lowmem_redirect( | |
949 | &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top); | |
950 | ||
951 | hub_info->apic_pnode_shift = uvh_apicid.s.pnode_shift; | |
952 | ||
953 | /* show system specific info */ | |
954 | pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", | |
955 | hub_info->n_val, hub_info->m_val, | |
956 | hub_info->m_shift, hub_info->n_lshift); | |
957 | ||
958 | pr_info("UV: pnode_mask:0x%x gpa_mask:0x%lx apic_pns:%d\n", | |
959 | hub_info->pnode_mask, hub_info->gpa_mask, | |
960 | hub_info->apic_pnode_shift); | |
961 | ||
962 | pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", | |
963 | hub_info->gnode_upper, hub_info->gnode_extra); | |
964 | ||
965 | pr_info("UV: global MMR base 0x%lx\n", hub_info->global_mmr_base); | |
966 | ||
967 | } | |
968 | ||
969 | void __init uv_system_init(void) | |
970 | { | |
971 | struct uv_hub_info_s hub_info = {0}; | |
972 | int bytes, nid, cpu, pnode, blade, i, j; | |
973 | int min_pnode = 999999, max_pnode = -1; | |
a0ec83f3 MT |
974 | char *hub = is_uv4_hub() ? "UV400" : |
975 | is_uv3_hub() ? "UV300" : | |
976 | is_uv2_hub() ? "UV2000/3000" : | |
977 | is_uv1_hub() ? "UV100/1000" : NULL; | |
ac23d4ee | 978 | |
1912c7af MT |
979 | if (!hub) { |
980 | pr_err("UV: Unknown/unsupported UV hub\n"); | |
981 | return; | |
982 | } | |
b15cc4a1 | 983 | pr_info("UV: Found %s hub\n", hub); |
d394f2d9 AT |
984 | |
985 | /* We now only need to map the MMRs on UV1 */ | |
986 | if (is_uv1_hub()) | |
987 | map_low_mmrs(); | |
918bc960 | 988 | |
c443c03d | 989 | uv_init_hub_info(&hub_info); |
ac23d4ee | 990 | |
9f5314fb JS |
991 | for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) |
992 | uv_possible_blades += | |
993 | hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); | |
da517a08 JS |
994 | |
995 | /* uv_num_possible_blades() is really the hub count */ | |
0045ddd2 MT |
996 | pr_info("UV: Found %d hubs, %d nodes, %d cpus\n", |
997 | uv_num_possible_blades(), | |
998 | num_possible_nodes(), | |
999 | num_possible_cpus()); | |
ac23d4ee JS |
1000 | |
1001 | bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); | |
1d44e828 | 1002 | uv_blade_info = kzalloc(bytes, GFP_KERNEL); |
9a8709d4 | 1003 | BUG_ON(!uv_blade_info); |
1d44e828 | 1004 | |
6c7184b7 JS |
1005 | for (blade = 0; blade < uv_num_possible_blades(); blade++) |
1006 | uv_blade_info[blade].memory_nid = -1; | |
ac23d4ee | 1007 | |
9f5314fb | 1008 | |
ac23d4ee | 1009 | bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); |
ef020ab0 | 1010 | uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 1011 | BUG_ON(!uv_node_to_blade); |
ac23d4ee JS |
1012 | memset(uv_node_to_blade, 255, bytes); |
1013 | ||
1014 | bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); | |
ef020ab0 | 1015 | uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); |
9a8709d4 | 1016 | BUG_ON(!uv_cpu_to_blade); |
ac23d4ee JS |
1017 | memset(uv_cpu_to_blade, 255, bytes); |
1018 | ||
9f5314fb JS |
1019 | blade = 0; |
1020 | for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { | |
c443c03d MT |
1021 | unsigned long present = |
1022 | uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); | |
9f5314fb JS |
1023 | for (j = 0; j < 64; j++) { |
1024 | if (!test_bit(j, &present)) | |
1025 | continue; | |
c443c03d | 1026 | pnode = (i * 64 + j) & hub_info.pnode_mask; |
36ac4b98 | 1027 | uv_blade_info[blade].pnode = pnode; |
9f5314fb | 1028 | uv_blade_info[blade].nr_possible_cpus = 0; |
ac23d4ee | 1029 | uv_blade_info[blade].nr_online_cpus = 0; |
b15cc4a1 | 1030 | min_pnode = min(pnode, min_pnode); |
36ac4b98 | 1031 | max_pnode = max(pnode, max_pnode); |
9f5314fb | 1032 | blade++; |
ac23d4ee | 1033 | } |
9f5314fb | 1034 | } |
ac23d4ee | 1035 | |
7f594232 | 1036 | uv_bios_init(); |
b76365a1 RA |
1037 | uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, |
1038 | &sn_region_size, &system_serial_number); | |
c443c03d | 1039 | hub_info.coherency_domain_number = sn_coherency_id; |
7019cc2d RA |
1040 | uv_rtc_init(); |
1041 | ||
9f5314fb | 1042 | for_each_present_cpu(cpu) { |
39d30770 | 1043 | int apicid = per_cpu(x86_cpu_to_apicid, cpu); |
c443c03d MT |
1044 | int nodeid = cpu_to_node(cpu); |
1045 | int lcpu; | |
39d30770 | 1046 | |
c443c03d | 1047 | *uv_cpu_hub_info(cpu) = hub_info; /* common hub values */ |
39d30770 | 1048 | pnode = uv_apicid_to_pnode(apicid); |
9f5314fb JS |
1049 | blade = boot_pnode_to_blade(pnode); |
1050 | lcpu = uv_blade_info[blade].nr_possible_cpus; | |
1051 | uv_blade_info[blade].nr_possible_cpus++; | |
1052 | ||
6c7184b7 | 1053 | /* Any node on the blade, else will contain -1. */ |
c443c03d | 1054 | uv_blade_info[blade].memory_nid = nodeid; |
6c7184b7 | 1055 | |
ac23d4ee | 1056 | uv_cpu_hub_info(cpu)->numa_blade_id = blade; |
9f5314fb | 1057 | uv_cpu_hub_info(cpu)->pnode = pnode; |
39d30770 | 1058 | uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); |
c443c03d MT |
1059 | uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; |
1060 | uv_node_to_blade[nodeid] = blade; | |
ac23d4ee | 1061 | uv_cpu_to_blade[cpu] = blade; |
0045ddd2 MT |
1062 | |
1063 | /* Initialize per cpu info list */ | |
1064 | uv_cpu_info_per(cpu)->p_uv_hub_info = uv_cpu_hub_info(cpu); | |
ac23d4ee | 1065 | } |
83f5d894 | 1066 | |
6a891a24 JS |
1067 | /* Add blade/pnode info for nodes without cpus */ |
1068 | for_each_online_node(nid) { | |
c443c03d MT |
1069 | unsigned long paddr; |
1070 | ||
6a891a24 JS |
1071 | if (uv_node_to_blade[nid] >= 0) |
1072 | continue; | |
1073 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | |
6a469e46 | 1074 | pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); |
6a891a24 JS |
1075 | blade = boot_pnode_to_blade(pnode); |
1076 | uv_node_to_blade[nid] = blade; | |
1077 | } | |
1078 | ||
83f5d894 | 1079 | map_gru_high(max_pnode); |
daf7b9c9 | 1080 | map_mmr_high(max_pnode); |
b15cc4a1 | 1081 | map_mmioh_high(min_pnode, max_pnode); |
ac23d4ee | 1082 | |
0d12ef0c | 1083 | uv_nmi_setup(); |
8da077d6 | 1084 | uv_cpu_init(); |
7f1baa06 | 1085 | uv_scir_register_cpu_notifier(); |
a3d732f9 | 1086 | proc_mkdir("sgi_uv", NULL); |
841582ea MT |
1087 | |
1088 | /* register Legacy VGA I/O redirection handler */ | |
1089 | pci_register_set_vga_state(uv_set_vga_state); | |
818987e9 CW |
1090 | |
1091 | /* | |
1092 | * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as | |
1093 | * EFI is not enabled in the kdump kernel. | |
1094 | */ | |
1095 | if (is_kdump_kernel()) | |
1096 | reboot_type = BOOT_ACPI; | |
ac23d4ee | 1097 | } |
107e0e0c SS |
1098 | |
1099 | apic_driver(apic_x2apic_uv_x); |