Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
521b82fe TG |
2 | |
3 | #include <linux/cpuhotplug.h> | |
12a67cf6 | 4 | #include <linux/cpumask.h> |
521b82fe TG |
5 | #include <linux/slab.h> |
6 | #include <linux/mm.h> | |
7 | ||
8 | #include <asm/apic.h> | |
1b9b89e7 | 9 | |
c94f0718 | 10 | #include "local.h" |
12a67cf6 | 11 | |
023a6117 TG |
12 | struct cluster_mask { |
13 | unsigned int clusterid; | |
14 | int node; | |
15 | struct cpumask mask; | |
16 | }; | |
17 | ||
cc95a07f ED |
18 | /* |
19 | * __x2apic_send_IPI_mask() possibly needs to read | |
20 | * x86_cpu_to_logical_apicid for all online cpus in a sequential way. | |
21 | * Using per cpu variable would cost one cache line per cpu. | |
22 | */ | |
23 | static u32 *x86_cpu_to_logical_apicid __read_mostly; | |
24 | ||
9d0fa6c5 | 25 | static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); |
cc95a07f | 26 | static DEFINE_PER_CPU_READ_MOSTLY(struct cluster_mask *, cluster_masks); |
023a6117 | 27 | static struct cluster_mask *cluster_hotplug_mask; |
12a67cf6 | 28 | |
2caa3715 | 29 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 30 | { |
ef1f87aa | 31 | return x2apic_enabled(); |
1b9b89e7 YL |
32 | } |
33 | ||
7b6ce46c LT |
34 | static void x2apic_send_IPI(int cpu, int vector) |
35 | { | |
cc95a07f | 36 | u32 dest = x86_cpu_to_logical_apicid[cpu]; |
7b6ce46c | 37 | |
25a068b8 DH |
38 | /* x2apic MSRs are special and need a special fence: */ |
39 | weak_wrmsr_fence(); | |
7b6ce46c LT |
40 | __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); |
41 | } | |
42 | ||
a27d0b5e SS |
43 | static void |
44 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 45 | { |
023a6117 TG |
46 | unsigned int cpu, clustercpu; |
47 | struct cpumask *tmpmsk; | |
dac5f412 | 48 | unsigned long flags; |
9d0fa6c5 | 49 | u32 dest; |
12a67cf6 | 50 | |
25a068b8 DH |
51 | /* x2apic MSRs are special and need a special fence: */ |
52 | weak_wrmsr_fence(); | |
12a67cf6 | 53 | local_irq_save(flags); |
a27d0b5e | 54 | |
023a6117 TG |
55 | tmpmsk = this_cpu_cpumask_var_ptr(ipi_mask); |
56 | cpumask_copy(tmpmsk, mask); | |
57 | /* If IPI should not be sent to self, clear current CPU */ | |
58 | if (apic_dest != APIC_DEST_ALLINC) | |
dde3626f | 59 | __cpumask_clear_cpu(smp_processor_id(), tmpmsk); |
9d0fa6c5 | 60 | |
023a6117 TG |
61 | /* Collapse cpus in a cluster so a single IPI per cluster is sent */ |
62 | for_each_cpu(cpu, tmpmsk) { | |
63 | struct cluster_mask *cmsk = per_cpu(cluster_masks, cpu); | |
9d0fa6c5 | 64 | |
9d0fa6c5 | 65 | dest = 0; |
023a6117 | 66 | for_each_cpu_and(clustercpu, tmpmsk, &cmsk->mask) |
cc95a07f | 67 | dest |= x86_cpu_to_logical_apicid[clustercpu]; |
9d0fa6c5 CG |
68 | |
69 | if (!dest) | |
a27d0b5e | 70 | continue; |
9d0fa6c5 | 71 | |
22e0db42 | 72 | __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); |
023a6117 TG |
73 | /* Remove cluster CPUs from tmpmask */ |
74 | cpumask_andnot(tmpmsk, tmpmsk, &cmsk->mask); | |
dac5f412 | 75 | } |
a27d0b5e | 76 | |
12a67cf6 SS |
77 | local_irq_restore(flags); |
78 | } | |
79 | ||
a27d0b5e SS |
80 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
81 | { | |
82 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
83 | } | |
84 | ||
dac5f412 | 85 | static void |
49d0c7a0 | 86 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
12a67cf6 | 87 | { |
a27d0b5e | 88 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 89 | } |
12a67cf6 | 90 | |
e7986739 MT |
91 | static void x2apic_send_IPI_allbutself(int vector) |
92 | { | |
43931d35 | 93 | __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
94 | } |
95 | ||
96 | static void x2apic_send_IPI_all(int vector) | |
97 | { | |
43931d35 | 98 | __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
99 | } |
100 | ||
9f9e3bb1 TG |
101 | static u32 x2apic_calc_apicid(unsigned int cpu) |
102 | { | |
cc95a07f | 103 | return x86_cpu_to_logical_apicid[cpu]; |
9f9e3bb1 TG |
104 | } |
105 | ||
12a67cf6 | 106 | static void init_x2apic_ldr(void) |
a39d1f3f | 107 | { |
023a6117 TG |
108 | struct cluster_mask *cmsk = this_cpu_read(cluster_masks); |
109 | u32 cluster, apicid = apic_read(APIC_LDR); | |
a39d1f3f CG |
110 | unsigned int cpu; |
111 | ||
cc95a07f | 112 | x86_cpu_to_logical_apicid[smp_processor_id()] = apicid; |
a39d1f3f | 113 | |
023a6117 TG |
114 | if (cmsk) |
115 | goto update; | |
116 | ||
117 | cluster = apicid >> 16; | |
a39d1f3f | 118 | for_each_online_cpu(cpu) { |
023a6117 TG |
119 | cmsk = per_cpu(cluster_masks, cpu); |
120 | /* Matching cluster found. Link and update it. */ | |
121 | if (cmsk && cmsk->clusterid == cluster) | |
122 | goto update; | |
a39d1f3f | 123 | } |
023a6117 | 124 | cmsk = cluster_hotplug_mask; |
fed71f7d | 125 | cmsk->clusterid = cluster; |
023a6117 TG |
126 | cluster_hotplug_mask = NULL; |
127 | update: | |
128 | this_cpu_write(cluster_masks, cmsk); | |
129 | cpumask_set_cpu(smp_processor_id(), &cmsk->mask); | |
a39d1f3f CG |
130 | } |
131 | ||
023a6117 | 132 | static int alloc_clustermask(unsigned int cpu, int node) |
a39d1f3f | 133 | { |
023a6117 TG |
134 | if (per_cpu(cluster_masks, cpu)) |
135 | return 0; | |
136 | /* | |
137 | * If a hotplug spare mask exists, check whether it's on the right | |
138 | * node. If not, free it and allocate a new one. | |
139 | */ | |
140 | if (cluster_hotplug_mask) { | |
141 | if (cluster_hotplug_mask->node == node) | |
142 | return 0; | |
143 | kfree(cluster_hotplug_mask); | |
144 | } | |
6b2c2847 | 145 | |
023a6117 TG |
146 | cluster_hotplug_mask = kzalloc_node(sizeof(*cluster_hotplug_mask), |
147 | GFP_KERNEL, node); | |
148 | if (!cluster_hotplug_mask) | |
6b2c2847 | 149 | return -ENOMEM; |
023a6117 TG |
150 | cluster_hotplug_mask->node = node; |
151 | return 0; | |
152 | } | |
a39d1f3f | 153 | |
023a6117 TG |
154 | static int x2apic_prepare_cpu(unsigned int cpu) |
155 | { | |
156 | if (alloc_clustermask(cpu, cpu_to_node(cpu)) < 0) | |
157 | return -ENOMEM; | |
158 | if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) | |
159 | return -ENOMEM; | |
6b2c2847 | 160 | return 0; |
a39d1f3f CG |
161 | } |
162 | ||
023a6117 | 163 | static int x2apic_dead_cpu(unsigned int dead_cpu) |
12a67cf6 | 164 | { |
023a6117 | 165 | struct cluster_mask *cmsk = per_cpu(cluster_masks, dead_cpu); |
a39d1f3f | 166 | |
7a22e03b SC |
167 | if (cmsk) |
168 | cpumask_clear_cpu(dead_cpu, &cmsk->mask); | |
023a6117 | 169 | free_cpumask_var(per_cpu(ipi_mask, dead_cpu)); |
6b2c2847 | 170 | return 0; |
12a67cf6 SS |
171 | } |
172 | ||
9ebd680b SS |
173 | static int x2apic_cluster_probe(void) |
174 | { | |
cc95a07f ED |
175 | u32 slots; |
176 | ||
6b2c2847 | 177 | if (!x2apic_mode) |
a39d1f3f | 178 | return 0; |
6b2c2847 | 179 | |
cc95a07f ED |
180 | slots = max_t(u32, L1_CACHE_BYTES/sizeof(u32), nr_cpu_ids); |
181 | x86_cpu_to_logical_apicid = kcalloc(slots, sizeof(u32), GFP_KERNEL); | |
182 | if (!x86_cpu_to_logical_apicid) | |
183 | return 0; | |
184 | ||
023a6117 TG |
185 | if (cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare", |
186 | x2apic_prepare_cpu, x2apic_dead_cpu) < 0) { | |
d52c0569 | 187 | pr_err("Failed to register X2APIC_PREPARE\n"); |
cc95a07f ED |
188 | kfree(x86_cpu_to_logical_apicid); |
189 | x86_cpu_to_logical_apicid = NULL; | |
d52c0569 SAS |
190 | return 0; |
191 | } | |
023a6117 | 192 | init_x2apic_ldr(); |
6b2c2847 | 193 | return 1; |
9ebd680b SS |
194 | } |
195 | ||
404f6aac | 196 | static struct apic apic_x2apic_cluster __ro_after_init = { |
504a3c3a IM |
197 | |
198 | .name = "cluster x2apic", | |
9ebd680b | 199 | .probe = x2apic_cluster_probe, |
504a3c3a | 200 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
b7157acf | 201 | .apic_id_valid = x2apic_apic_id_valid, |
504a3c3a IM |
202 | .apic_id_registered = x2apic_apic_id_registered, |
203 | ||
72161299 | 204 | .delivery_mode = APIC_DELIVERY_MODE_FIXED, |
8c44963b | 205 | .dest_mode_logical = true, |
504a3c3a | 206 | |
08125d3e | 207 | .disable_esr = 0, |
504a3c3a | 208 | |
e57d04e5 | 209 | .check_apicid_used = NULL, |
504a3c3a | 210 | .init_apic_ldr = init_x2apic_ldr, |
504a3c3a IM |
211 | .ioapic_phys_id_map = NULL, |
212 | .setup_apic_routing = NULL, | |
a21769a4 | 213 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
504a3c3a | 214 | .apicid_to_cpu_present = NULL, |
a27a6210 | 215 | .check_phys_apicid_present = default_check_phys_apicid_present, |
79deb8e5 | 216 | .phys_pkg_id = x2apic_phys_pkg_id, |
504a3c3a | 217 | |
79deb8e5 CG |
218 | .get_apic_id = x2apic_get_apic_id, |
219 | .set_apic_id = x2apic_set_apic_id, | |
504a3c3a | 220 | |
9f9e3bb1 | 221 | .calc_dest_apicid = x2apic_calc_apicid, |
504a3c3a | 222 | |
7b6ce46c | 223 | .send_IPI = x2apic_send_IPI, |
504a3c3a IM |
224 | .send_IPI_mask = x2apic_send_IPI_mask, |
225 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
226 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
227 | .send_IPI_all = x2apic_send_IPI_all, | |
228 | .send_IPI_self = x2apic_send_IPI_self, | |
229 | ||
504a3c3a | 230 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
231 | |
232 | .read = native_apic_msr_read, | |
233 | .write = native_apic_msr_write, | |
0ab711ae | 234 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
235 | .icr_read = native_x2apic_icr_read, |
236 | .icr_write = native_x2apic_icr_write, | |
237 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
238 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 239 | }; |
107e0e0c SS |
240 | |
241 | apic_driver(apic_x2apic_cluster); |