Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
521b82fe TG |
2 | |
3 | #include <linux/cpuhotplug.h> | |
12a67cf6 | 4 | #include <linux/cpumask.h> |
521b82fe TG |
5 | #include <linux/slab.h> |
6 | #include <linux/mm.h> | |
7 | ||
8 | #include <asm/apic.h> | |
1b9b89e7 | 9 | |
c94f0718 | 10 | #include "local.h" |
12a67cf6 | 11 | |
cefad862 | 12 | #define apic_cluster(apicid) ((apicid) >> 4) |
023a6117 | 13 | |
cc95a07f ED |
14 | /* |
15 | * __x2apic_send_IPI_mask() possibly needs to read | |
16 | * x86_cpu_to_logical_apicid for all online cpus in a sequential way. | |
17 | * Using per cpu variable would cost one cache line per cpu. | |
18 | */ | |
19 | static u32 *x86_cpu_to_logical_apicid __read_mostly; | |
20 | ||
9d0fa6c5 | 21 | static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); |
cefad862 | 22 | static DEFINE_PER_CPU_READ_MOSTLY(struct cpumask *, cluster_masks); |
12a67cf6 | 23 | |
2caa3715 | 24 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 25 | { |
ef1f87aa | 26 | return x2apic_enabled(); |
1b9b89e7 YL |
27 | } |
28 | ||
7b6ce46c LT |
29 | static void x2apic_send_IPI(int cpu, int vector) |
30 | { | |
cc95a07f | 31 | u32 dest = x86_cpu_to_logical_apicid[cpu]; |
7b6ce46c | 32 | |
25a068b8 DH |
33 | /* x2apic MSRs are special and need a special fence: */ |
34 | weak_wrmsr_fence(); | |
7b6ce46c LT |
35 | __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); |
36 | } | |
37 | ||
a27d0b5e SS |
38 | static void |
39 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 40 | { |
023a6117 TG |
41 | unsigned int cpu, clustercpu; |
42 | struct cpumask *tmpmsk; | |
dac5f412 | 43 | unsigned long flags; |
9d0fa6c5 | 44 | u32 dest; |
12a67cf6 | 45 | |
25a068b8 DH |
46 | /* x2apic MSRs are special and need a special fence: */ |
47 | weak_wrmsr_fence(); | |
12a67cf6 | 48 | local_irq_save(flags); |
a27d0b5e | 49 | |
023a6117 TG |
50 | tmpmsk = this_cpu_cpumask_var_ptr(ipi_mask); |
51 | cpumask_copy(tmpmsk, mask); | |
52 | /* If IPI should not be sent to self, clear current CPU */ | |
53 | if (apic_dest != APIC_DEST_ALLINC) | |
dde3626f | 54 | __cpumask_clear_cpu(smp_processor_id(), tmpmsk); |
9d0fa6c5 | 55 | |
023a6117 TG |
56 | /* Collapse cpus in a cluster so a single IPI per cluster is sent */ |
57 | for_each_cpu(cpu, tmpmsk) { | |
cefad862 | 58 | struct cpumask *cmsk = per_cpu(cluster_masks, cpu); |
9d0fa6c5 | 59 | |
9d0fa6c5 | 60 | dest = 0; |
cefad862 | 61 | for_each_cpu_and(clustercpu, tmpmsk, cmsk) |
cc95a07f | 62 | dest |= x86_cpu_to_logical_apicid[clustercpu]; |
9d0fa6c5 CG |
63 | |
64 | if (!dest) | |
a27d0b5e | 65 | continue; |
9d0fa6c5 | 66 | |
22e0db42 | 67 | __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); |
023a6117 | 68 | /* Remove cluster CPUs from tmpmask */ |
cefad862 | 69 | cpumask_andnot(tmpmsk, tmpmsk, cmsk); |
dac5f412 | 70 | } |
a27d0b5e | 71 | |
12a67cf6 SS |
72 | local_irq_restore(flags); |
73 | } | |
74 | ||
a27d0b5e SS |
75 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
76 | { | |
77 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
78 | } | |
79 | ||
dac5f412 | 80 | static void |
49d0c7a0 | 81 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
12a67cf6 | 82 | { |
a27d0b5e | 83 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 84 | } |
12a67cf6 | 85 | |
e7986739 MT |
86 | static void x2apic_send_IPI_allbutself(int vector) |
87 | { | |
43931d35 | 88 | __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
89 | } |
90 | ||
91 | static void x2apic_send_IPI_all(int vector) | |
92 | { | |
43931d35 | 93 | __x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
94 | } |
95 | ||
9f9e3bb1 TG |
96 | static u32 x2apic_calc_apicid(unsigned int cpu) |
97 | { | |
cc95a07f | 98 | return x86_cpu_to_logical_apicid[cpu]; |
9f9e3bb1 TG |
99 | } |
100 | ||
12a67cf6 | 101 | static void init_x2apic_ldr(void) |
a39d1f3f | 102 | { |
cefad862 | 103 | struct cpumask *cmsk = this_cpu_read(cluster_masks); |
a39d1f3f | 104 | |
cefad862 | 105 | BUG_ON(!cmsk); |
a39d1f3f | 106 | |
cefad862 DW |
107 | cpumask_set_cpu(smp_processor_id(), cmsk); |
108 | } | |
109 | ||
110 | /* | |
111 | * As an optimisation during boot, set the cluster_mask for all present | |
112 | * CPUs at once, to prevent each of them having to iterate over the others | |
113 | * to find the existing cluster_mask. | |
114 | */ | |
115 | static void prefill_clustermask(struct cpumask *cmsk, unsigned int cpu, u32 cluster) | |
116 | { | |
117 | int cpu_i; | |
118 | ||
119 | for_each_present_cpu(cpu_i) { | |
120 | struct cpumask **cpu_cmsk = &per_cpu(cluster_masks, cpu_i); | |
121 | u32 apicid = apic->cpu_present_to_apicid(cpu_i); | |
122 | ||
123 | if (apicid == BAD_APICID || cpu_i == cpu || apic_cluster(apicid) != cluster) | |
124 | continue; | |
125 | ||
126 | if (WARN_ON_ONCE(*cpu_cmsk == cmsk)) | |
127 | continue; | |
128 | ||
129 | BUG_ON(*cpu_cmsk); | |
130 | *cpu_cmsk = cmsk; | |
a39d1f3f CG |
131 | } |
132 | } | |
133 | ||
cefad862 | 134 | static int alloc_clustermask(unsigned int cpu, u32 cluster, int node) |
a39d1f3f | 135 | { |
cefad862 DW |
136 | struct cpumask *cmsk = NULL; |
137 | unsigned int cpu_i; | |
138 | ||
139 | /* | |
140 | * At boot time, the CPU present mask is stable. The cluster mask is | |
141 | * allocated for the first CPU in the cluster and propagated to all | |
142 | * present siblings in the cluster. If the cluster mask is already set | |
143 | * on entry to this function for a given CPU, there is nothing to do. | |
144 | */ | |
023a6117 TG |
145 | if (per_cpu(cluster_masks, cpu)) |
146 | return 0; | |
cefad862 DW |
147 | |
148 | if (system_state < SYSTEM_RUNNING) | |
149 | goto alloc; | |
150 | ||
023a6117 | 151 | /* |
cefad862 DW |
152 | * On post boot hotplug for a CPU which was not present at boot time, |
153 | * iterate over all possible CPUs (even those which are not present | |
154 | * any more) to find any existing cluster mask. | |
023a6117 | 155 | */ |
cefad862 DW |
156 | for_each_possible_cpu(cpu_i) { |
157 | u32 apicid = apic->cpu_present_to_apicid(cpu_i); | |
158 | ||
159 | if (apicid != BAD_APICID && apic_cluster(apicid) == cluster) { | |
160 | cmsk = per_cpu(cluster_masks, cpu_i); | |
161 | /* | |
162 | * If the cluster is already initialized, just store | |
163 | * the mask and return. There's no need to propagate. | |
164 | */ | |
165 | if (cmsk) { | |
166 | per_cpu(cluster_masks, cpu) = cmsk; | |
167 | return 0; | |
168 | } | |
169 | } | |
023a6117 | 170 | } |
cefad862 DW |
171 | /* |
172 | * No CPU in the cluster has ever been initialized, so fall through to | |
173 | * the boot time code which will also populate the cluster mask for any | |
174 | * other CPU in the cluster which is (now) present. | |
175 | */ | |
176 | alloc: | |
177 | cmsk = kzalloc_node(sizeof(*cmsk), GFP_KERNEL, node); | |
178 | if (!cmsk) | |
6b2c2847 | 179 | return -ENOMEM; |
cefad862 DW |
180 | per_cpu(cluster_masks, cpu) = cmsk; |
181 | prefill_clustermask(cmsk, cpu, cluster); | |
182 | ||
023a6117 TG |
183 | return 0; |
184 | } | |
a39d1f3f | 185 | |
023a6117 TG |
186 | static int x2apic_prepare_cpu(unsigned int cpu) |
187 | { | |
cefad862 DW |
188 | u32 phys_apicid = apic->cpu_present_to_apicid(cpu); |
189 | u32 cluster = apic_cluster(phys_apicid); | |
190 | u32 logical_apicid = (cluster << 16) | (1 << (phys_apicid & 0xf)); | |
191 | ||
192 | x86_cpu_to_logical_apicid[cpu] = logical_apicid; | |
193 | ||
194 | if (alloc_clustermask(cpu, cluster, cpu_to_node(cpu)) < 0) | |
023a6117 TG |
195 | return -ENOMEM; |
196 | if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) | |
197 | return -ENOMEM; | |
6b2c2847 | 198 | return 0; |
a39d1f3f CG |
199 | } |
200 | ||
023a6117 | 201 | static int x2apic_dead_cpu(unsigned int dead_cpu) |
12a67cf6 | 202 | { |
cefad862 | 203 | struct cpumask *cmsk = per_cpu(cluster_masks, dead_cpu); |
a39d1f3f | 204 | |
7a22e03b | 205 | if (cmsk) |
cefad862 | 206 | cpumask_clear_cpu(dead_cpu, cmsk); |
023a6117 | 207 | free_cpumask_var(per_cpu(ipi_mask, dead_cpu)); |
6b2c2847 | 208 | return 0; |
12a67cf6 SS |
209 | } |
210 | ||
9ebd680b SS |
211 | static int x2apic_cluster_probe(void) |
212 | { | |
cc95a07f ED |
213 | u32 slots; |
214 | ||
6b2c2847 | 215 | if (!x2apic_mode) |
a39d1f3f | 216 | return 0; |
6b2c2847 | 217 | |
cc95a07f ED |
218 | slots = max_t(u32, L1_CACHE_BYTES/sizeof(u32), nr_cpu_ids); |
219 | x86_cpu_to_logical_apicid = kcalloc(slots, sizeof(u32), GFP_KERNEL); | |
220 | if (!x86_cpu_to_logical_apicid) | |
221 | return 0; | |
222 | ||
023a6117 TG |
223 | if (cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare", |
224 | x2apic_prepare_cpu, x2apic_dead_cpu) < 0) { | |
d52c0569 | 225 | pr_err("Failed to register X2APIC_PREPARE\n"); |
cc95a07f ED |
226 | kfree(x86_cpu_to_logical_apicid); |
227 | x86_cpu_to_logical_apicid = NULL; | |
d52c0569 SAS |
228 | return 0; |
229 | } | |
023a6117 | 230 | init_x2apic_ldr(); |
6b2c2847 | 231 | return 1; |
9ebd680b SS |
232 | } |
233 | ||
404f6aac | 234 | static struct apic apic_x2apic_cluster __ro_after_init = { |
504a3c3a IM |
235 | |
236 | .name = "cluster x2apic", | |
9ebd680b | 237 | .probe = x2apic_cluster_probe, |
504a3c3a | 238 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
b7157acf | 239 | .apic_id_valid = x2apic_apic_id_valid, |
504a3c3a | 240 | |
72161299 | 241 | .delivery_mode = APIC_DELIVERY_MODE_FIXED, |
8c44963b | 242 | .dest_mode_logical = true, |
504a3c3a | 243 | |
08125d3e | 244 | .disable_esr = 0, |
504a3c3a | 245 | |
e57d04e5 | 246 | .check_apicid_used = NULL, |
504a3c3a | 247 | .init_apic_ldr = init_x2apic_ldr, |
504a3c3a | 248 | .ioapic_phys_id_map = NULL, |
a21769a4 | 249 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
79deb8e5 | 250 | .phys_pkg_id = x2apic_phys_pkg_id, |
504a3c3a | 251 | |
79deb8e5 CG |
252 | .get_apic_id = x2apic_get_apic_id, |
253 | .set_apic_id = x2apic_set_apic_id, | |
504a3c3a | 254 | |
9f9e3bb1 | 255 | .calc_dest_apicid = x2apic_calc_apicid, |
504a3c3a | 256 | |
7b6ce46c | 257 | .send_IPI = x2apic_send_IPI, |
504a3c3a IM |
258 | .send_IPI_mask = x2apic_send_IPI_mask, |
259 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
260 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
261 | .send_IPI_all = x2apic_send_IPI_all, | |
262 | .send_IPI_self = x2apic_send_IPI_self, | |
263 | ||
c1eeb2de YL |
264 | .read = native_apic_msr_read, |
265 | .write = native_apic_msr_write, | |
0ab711ae | 266 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
267 | .icr_read = native_x2apic_icr_read, |
268 | .icr_write = native_x2apic_icr_write, | |
269 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
270 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 271 | }; |
107e0e0c SS |
272 | |
273 | apic_driver(apic_x2apic_cluster); |