Commit | Line | Data |
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12a67cf6 SS |
1 | #include <linux/threads.h> |
2 | #include <linux/cpumask.h> | |
3 | #include <linux/string.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/ctype.h> | |
1b9b89e7 | 6 | #include <linux/dmar.h> |
9d0fa6c5 | 7 | #include <linux/cpu.h> |
1b9b89e7 | 8 | |
12a67cf6 | 9 | #include <asm/smp.h> |
79deb8e5 | 10 | #include <asm/x2apic.h> |
12a67cf6 | 11 | |
2de1f33e | 12 | static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); |
a39d1f3f | 13 | static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster); |
9d0fa6c5 | 14 | static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); |
12a67cf6 | 15 | |
2caa3715 | 16 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 17 | { |
ef1f87aa | 18 | return x2apic_enabled(); |
1b9b89e7 YL |
19 | } |
20 | ||
a39d1f3f CG |
21 | static inline u32 x2apic_cluster(int cpu) |
22 | { | |
23 | return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16; | |
24 | } | |
25 | ||
a27d0b5e SS |
26 | static void |
27 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 28 | { |
9d0fa6c5 CG |
29 | struct cpumask *cpus_in_cluster_ptr; |
30 | struct cpumask *ipi_mask_ptr; | |
31 | unsigned int cpu, this_cpu; | |
dac5f412 | 32 | unsigned long flags; |
9d0fa6c5 | 33 | u32 dest; |
12a67cf6 | 34 | |
ce4e240c SS |
35 | x2apic_wrmsr_fence(); |
36 | ||
12a67cf6 | 37 | local_irq_save(flags); |
a27d0b5e SS |
38 | |
39 | this_cpu = smp_processor_id(); | |
9d0fa6c5 CG |
40 | |
41 | /* | |
42 | * We are to modify mask, so we need an own copy | |
43 | * and be sure it's manipulated with irq off. | |
44 | */ | |
4ba29684 | 45 | ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask); |
59f6e207 | 46 | cpumask_copy(ipi_mask_ptr, mask); |
9d0fa6c5 CG |
47 | |
48 | /* | |
49 | * The idea is to send one IPI per cluster. | |
50 | */ | |
51 | for_each_cpu(cpu, ipi_mask_ptr) { | |
52 | unsigned long i; | |
53 | ||
54 | cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu); | |
55 | dest = 0; | |
56 | ||
57 | /* Collect cpus in cluster. */ | |
58 | for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) { | |
59 | if (apic_dest == APIC_DEST_ALLINC || i != this_cpu) | |
60 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
61 | } | |
62 | ||
63 | if (!dest) | |
a27d0b5e | 64 | continue; |
9d0fa6c5 CG |
65 | |
66 | __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); | |
67 | /* | |
68 | * Cluster sibling cpus should be discared now so | |
69 | * we would not send IPI them second time. | |
70 | */ | |
71 | cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr); | |
dac5f412 | 72 | } |
a27d0b5e | 73 | |
12a67cf6 SS |
74 | local_irq_restore(flags); |
75 | } | |
76 | ||
a27d0b5e SS |
77 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
78 | { | |
79 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
80 | } | |
81 | ||
dac5f412 | 82 | static void |
49d0c7a0 | 83 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
12a67cf6 | 84 | { |
a27d0b5e | 85 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 86 | } |
12a67cf6 | 87 | |
e7986739 MT |
88 | static void x2apic_send_IPI_allbutself(int vector) |
89 | { | |
a27d0b5e | 90 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
91 | } |
92 | ||
93 | static void x2apic_send_IPI_all(int vector) | |
94 | { | |
a27d0b5e | 95 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
96 | } |
97 | ||
ff164324 | 98 | static int |
debccb3e | 99 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
100 | const struct cpumask *andmask, |
101 | unsigned int *apicid) | |
95d313cf | 102 | { |
0b8255e6 SS |
103 | u32 dest = 0; |
104 | u16 cluster; | |
105 | int i; | |
95d313cf | 106 | |
0b8255e6 SS |
107 | for_each_cpu_and(i, cpumask, andmask) { |
108 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
109 | continue; | |
110 | dest = per_cpu(x86_cpu_to_logical_apicid, i); | |
111 | cluster = x2apic_cluster(i); | |
112 | break; | |
debccb3e IM |
113 | } |
114 | ||
0b8255e6 | 115 | if (!dest) |
ff164324 | 116 | return -EINVAL; |
0b8255e6 SS |
117 | |
118 | for_each_cpu_and(i, cpumask, andmask) { | |
119 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
120 | continue; | |
121 | if (cluster != x2apic_cluster(i)) | |
122 | continue; | |
123 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
124 | } | |
125 | ||
ff164324 AG |
126 | *apicid = dest; |
127 | ||
128 | return 0; | |
95d313cf MT |
129 | } |
130 | ||
12a67cf6 | 131 | static void init_x2apic_ldr(void) |
a39d1f3f CG |
132 | { |
133 | unsigned int this_cpu = smp_processor_id(); | |
134 | unsigned int cpu; | |
135 | ||
136 | per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR); | |
137 | ||
d089f8e9 | 138 | cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu)); |
a39d1f3f CG |
139 | for_each_online_cpu(cpu) { |
140 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
141 | continue; | |
d089f8e9 RR |
142 | cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); |
143 | cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
a39d1f3f CG |
144 | } |
145 | } | |
146 | ||
147 | /* | |
148 | * At CPU state changes, update the x2apic cluster sibling info. | |
149 | */ | |
148f9bb8 | 150 | static int |
a39d1f3f CG |
151 | update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu) |
152 | { | |
153 | unsigned int this_cpu = (unsigned long)hcpu; | |
154 | unsigned int cpu; | |
155 | int err = 0; | |
156 | ||
157 | switch (action) { | |
158 | case CPU_UP_PREPARE: | |
159 | if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu), | |
160 | GFP_KERNEL)) { | |
161 | err = -ENOMEM; | |
9d0fa6c5 CG |
162 | } else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu), |
163 | GFP_KERNEL)) { | |
164 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
165 | err = -ENOMEM; | |
a39d1f3f CG |
166 | } |
167 | break; | |
168 | case CPU_UP_CANCELED: | |
169 | case CPU_UP_CANCELED_FROZEN: | |
170 | case CPU_DEAD: | |
171 | for_each_online_cpu(cpu) { | |
172 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
173 | continue; | |
fdaf3a65 RR |
174 | cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); |
175 | cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
a39d1f3f CG |
176 | } |
177 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
9d0fa6c5 | 178 | free_cpumask_var(per_cpu(ipi_mask, this_cpu)); |
a39d1f3f CG |
179 | break; |
180 | } | |
181 | ||
182 | return notifier_from_errno(err); | |
183 | } | |
184 | ||
185 | static struct notifier_block __refdata x2apic_cpu_notifier = { | |
186 | .notifier_call = update_clusterinfo, | |
187 | }; | |
188 | ||
189 | static int x2apic_init_cpu_notifier(void) | |
12a67cf6 SS |
190 | { |
191 | int cpu = smp_processor_id(); | |
192 | ||
a39d1f3f | 193 | zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL); |
9d0fa6c5 | 194 | zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL); |
a39d1f3f | 195 | |
9d0fa6c5 | 196 | BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu)); |
a39d1f3f | 197 | |
d089f8e9 | 198 | cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu)); |
a39d1f3f CG |
199 | register_hotcpu_notifier(&x2apic_cpu_notifier); |
200 | return 1; | |
12a67cf6 SS |
201 | } |
202 | ||
9ebd680b SS |
203 | static int x2apic_cluster_probe(void) |
204 | { | |
a39d1f3f CG |
205 | if (x2apic_mode) |
206 | return x2apic_init_cpu_notifier(); | |
207 | else | |
208 | return 0; | |
9ebd680b SS |
209 | } |
210 | ||
d872818d SS |
211 | static const struct cpumask *x2apic_cluster_target_cpus(void) |
212 | { | |
213 | return cpu_all_mask; | |
214 | } | |
215 | ||
0b8255e6 SS |
216 | /* |
217 | * Each x2apic cluster is an allocation domain. | |
218 | */ | |
1ac322d0 SS |
219 | static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask, |
220 | const struct cpumask *mask) | |
0b8255e6 | 221 | { |
d872818d SS |
222 | /* |
223 | * To minimize vector pressure, default case of boot, device bringup | |
224 | * etc will use a single cpu for the interrupt destination. | |
225 | * | |
226 | * On explicit migration requests coming from irqbalance etc, | |
227 | * interrupts will be routed to the x2apic cluster (cluster-id | |
228 | * derived from the first cpu in the mask) members specified | |
229 | * in the mask. | |
230 | */ | |
231 | if (mask == x2apic_cluster_target_cpus()) | |
232 | cpumask_copy(retmask, cpumask_of(cpu)); | |
233 | else | |
234 | cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu)); | |
0b8255e6 SS |
235 | } |
236 | ||
1a8880a1 | 237 | static struct apic apic_x2apic_cluster = { |
504a3c3a IM |
238 | |
239 | .name = "cluster x2apic", | |
9ebd680b | 240 | .probe = x2apic_cluster_probe, |
504a3c3a | 241 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
b7157acf | 242 | .apic_id_valid = x2apic_apic_id_valid, |
504a3c3a IM |
243 | .apic_id_registered = x2apic_apic_id_registered, |
244 | ||
f8987a10 | 245 | .irq_delivery_mode = dest_LowestPrio, |
0b06e734 | 246 | .irq_dest_mode = 1, /* logical */ |
504a3c3a | 247 | |
d872818d | 248 | .target_cpus = x2apic_cluster_target_cpus, |
08125d3e | 249 | .disable_esr = 0, |
bdb1a9b6 | 250 | .dest_logical = APIC_DEST_LOGICAL, |
504a3c3a | 251 | .check_apicid_used = NULL, |
504a3c3a | 252 | |
0b8255e6 | 253 | .vector_allocation_domain = cluster_vector_allocation_domain, |
504a3c3a IM |
254 | .init_apic_ldr = init_x2apic_ldr, |
255 | ||
256 | .ioapic_phys_id_map = NULL, | |
257 | .setup_apic_routing = NULL, | |
a21769a4 | 258 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
504a3c3a | 259 | .apicid_to_cpu_present = NULL, |
a27a6210 | 260 | .check_phys_apicid_present = default_check_phys_apicid_present, |
79deb8e5 | 261 | .phys_pkg_id = x2apic_phys_pkg_id, |
504a3c3a | 262 | |
79deb8e5 CG |
263 | .get_apic_id = x2apic_get_apic_id, |
264 | .set_apic_id = x2apic_set_apic_id, | |
504a3c3a IM |
265 | .apic_id_mask = 0xFFFFFFFFu, |
266 | ||
504a3c3a IM |
267 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, |
268 | ||
269 | .send_IPI_mask = x2apic_send_IPI_mask, | |
270 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
271 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
272 | .send_IPI_all = x2apic_send_IPI_all, | |
273 | .send_IPI_self = x2apic_send_IPI_self, | |
274 | ||
465822cf | 275 | .wait_for_init_deassert = false, |
504a3c3a | 276 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
277 | |
278 | .read = native_apic_msr_read, | |
279 | .write = native_apic_msr_write, | |
0ab711ae | 280 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
281 | .icr_read = native_x2apic_icr_read, |
282 | .icr_write = native_x2apic_icr_write, | |
283 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
284 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 285 | }; |
107e0e0c SS |
286 | |
287 | apic_driver(apic_x2apic_cluster); |