Commit | Line | Data |
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44380982 JL |
1 | /* |
2 | * Support of MSI, HPET and DMAR interrupts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
52f518a3 JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Convert to hierarchical irqdomain | |
44380982 JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/mm.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/dmar.h> | |
17 | #include <linux/hpet.h> | |
18 | #include <linux/msi.h> | |
d746d1eb | 19 | #include <asm/irqdomain.h> |
44380982 JL |
20 | #include <asm/msidef.h> |
21 | #include <asm/hpet.h> | |
22 | #include <asm/hw_irq.h> | |
23 | #include <asm/apic.h> | |
24 | #include <asm/irq_remapping.h> | |
25 | ||
52f518a3 JL |
26 | static struct irq_domain *msi_default_domain; |
27 | ||
3cb96f0c JL |
28 | static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) |
29 | { | |
30 | struct irq_cfg *cfg = irqd_cfg(data); | |
31 | ||
32 | msg->address_hi = MSI_ADDR_BASE_HI; | |
33 | ||
34 | if (x2apic_enabled()) | |
35 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); | |
36 | ||
37 | msg->address_lo = | |
38 | MSI_ADDR_BASE_LO | | |
39 | ((apic->irq_dest_mode == 0) ? | |
40 | MSI_ADDR_DEST_MODE_PHYSICAL : | |
41 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
42 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
43 | MSI_ADDR_REDIRECTION_CPU : | |
44 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
45 | MSI_ADDR_DEST_ID(cfg->dest_apicid); | |
46 | ||
47 | msg->data = | |
48 | MSI_DATA_TRIGGER_EDGE | | |
49 | MSI_DATA_LEVEL_ASSERT | | |
50 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
51 | MSI_DATA_DELIVERY_FIXED : | |
52 | MSI_DATA_DELIVERY_LOWPRI) | | |
53 | MSI_DATA_VECTOR(cfg->vector); | |
54 | } | |
55 | ||
44380982 JL |
56 | /* |
57 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
58 | * which implement the MSI or MSI-X Capability Structure. | |
59 | */ | |
52f518a3 | 60 | static struct irq_chip pci_msi_controller = { |
44380982 JL |
61 | .name = "PCI-MSI", |
62 | .irq_unmask = pci_msi_unmask_irq, | |
63 | .irq_mask = pci_msi_mask_irq, | |
52f518a3 | 64 | .irq_ack = irq_chip_ack_parent, |
52f518a3 | 65 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
52f518a3 | 66 | .irq_compose_msi_msg = irq_msi_compose_msg, |
44380982 JL |
67 | .flags = IRQCHIP_SKIP_SET_WAKE, |
68 | }; | |
69 | ||
52f518a3 | 70 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
44380982 | 71 | { |
52f518a3 JL |
72 | struct irq_domain *domain; |
73 | struct irq_alloc_info info; | |
44380982 | 74 | |
52f518a3 JL |
75 | init_irq_alloc_info(&info, NULL); |
76 | info.type = X86_IRQ_ALLOC_TYPE_MSI; | |
77 | info.msi_dev = dev; | |
44380982 | 78 | |
52f518a3 JL |
79 | domain = irq_remapping_get_irq_domain(&info); |
80 | if (domain == NULL) | |
81 | domain = msi_default_domain; | |
82 | if (domain == NULL) | |
83 | return -ENOSYS; | |
44380982 | 84 | |
699c4cec | 85 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
52f518a3 | 86 | } |
44380982 | 87 | |
52f518a3 JL |
88 | void native_teardown_msi_irq(unsigned int irq) |
89 | { | |
90 | irq_domain_free_irqs(irq, 1); | |
91 | } | |
44380982 | 92 | |
52f518a3 JL |
93 | static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info, |
94 | msi_alloc_info_t *arg) | |
95 | { | |
96 | return arg->msi_hwirq; | |
97 | } | |
44380982 | 98 | |
c8f3e518 JO |
99 | int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, |
100 | msi_alloc_info_t *arg) | |
52f518a3 JL |
101 | { |
102 | struct pci_dev *pdev = to_pci_dev(dev); | |
103 | struct msi_desc *desc = first_pci_msi_entry(pdev); | |
104 | ||
105 | init_irq_alloc_info(arg, NULL); | |
106 | arg->msi_dev = pdev; | |
107 | if (desc->msi_attrib.is_msix) { | |
108 | arg->type = X86_IRQ_ALLOC_TYPE_MSIX; | |
109 | } else { | |
110 | arg->type = X86_IRQ_ALLOC_TYPE_MSI; | |
111 | arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
112 | } | |
44380982 JL |
113 | |
114 | return 0; | |
115 | } | |
c8f3e518 | 116 | EXPORT_SYMBOL_GPL(pci_msi_prepare); |
44380982 | 117 | |
c8f3e518 | 118 | void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) |
44380982 | 119 | { |
52f518a3 JL |
120 | arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc); |
121 | } | |
c8f3e518 | 122 | EXPORT_SYMBOL_GPL(pci_msi_set_desc); |
44380982 | 123 | |
52f518a3 JL |
124 | static struct msi_domain_ops pci_msi_domain_ops = { |
125 | .get_hwirq = pci_msi_get_hwirq, | |
126 | .msi_prepare = pci_msi_prepare, | |
127 | .set_desc = pci_msi_set_desc, | |
128 | }; | |
44380982 | 129 | |
52f518a3 JL |
130 | static struct msi_domain_info pci_msi_domain_info = { |
131 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
68682a26 | 132 | MSI_FLAG_PCI_MSIX, |
52f518a3 JL |
133 | .ops = &pci_msi_domain_ops, |
134 | .chip = &pci_msi_controller, | |
135 | .handler = handle_edge_irq, | |
136 | .handler_name = "edge", | |
137 | }; | |
44380982 | 138 | |
f8f37ca7 | 139 | void __init arch_init_msi_domain(struct irq_domain *parent) |
52f518a3 | 140 | { |
f8f37ca7 TG |
141 | struct fwnode_handle *fn; |
142 | ||
52f518a3 JL |
143 | if (disable_apic) |
144 | return; | |
44380982 | 145 | |
f8f37ca7 TG |
146 | fn = irq_domain_alloc_named_fwnode("PCI-MSI"); |
147 | if (fn) { | |
148 | msi_default_domain = | |
149 | pci_msi_create_irq_domain(fn, &pci_msi_domain_info, | |
150 | parent); | |
151 | irq_domain_free_fwnode(fn); | |
152 | } | |
52f518a3 JL |
153 | if (!msi_default_domain) |
154 | pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n"); | |
44380982 JL |
155 | } |
156 | ||
52f518a3 | 157 | #ifdef CONFIG_IRQ_REMAP |
68682a26 JL |
158 | static struct irq_chip pci_msi_ir_controller = { |
159 | .name = "IR-PCI-MSI", | |
160 | .irq_unmask = pci_msi_unmask_irq, | |
161 | .irq_mask = pci_msi_mask_irq, | |
162 | .irq_ack = irq_chip_ack_parent, | |
68682a26 | 163 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
a2f1c8bd | 164 | .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, |
68682a26 JL |
165 | .flags = IRQCHIP_SKIP_SET_WAKE, |
166 | }; | |
167 | ||
168 | static struct msi_domain_info pci_msi_ir_domain_info = { | |
169 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
170 | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, | |
171 | .ops = &pci_msi_domain_ops, | |
172 | .chip = &pci_msi_ir_controller, | |
173 | .handler = handle_edge_irq, | |
174 | .handler_name = "edge", | |
175 | }; | |
176 | ||
667724c5 TG |
177 | struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent, |
178 | const char *name, int id) | |
179 | { | |
180 | struct fwnode_handle *fn; | |
181 | struct irq_domain *d; | |
182 | ||
183 | fn = irq_domain_alloc_named_id_fwnode(name, id); | |
184 | if (!fn) | |
185 | return NULL; | |
186 | d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent); | |
187 | irq_domain_free_fwnode(fn); | |
188 | return d; | |
189 | } | |
52f518a3 | 190 | #endif |
44380982 JL |
191 | |
192 | #ifdef CONFIG_DMAR_TABLE | |
62ac1780 JL |
193 | static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg) |
194 | { | |
195 | dmar_msi_write(data->irq, msg); | |
196 | } | |
197 | ||
0921f1da | 198 | static struct irq_chip dmar_msi_controller = { |
81dabe2e | 199 | .name = "DMAR-MSI", |
44380982 JL |
200 | .irq_unmask = dmar_msi_unmask, |
201 | .irq_mask = dmar_msi_mask, | |
0921f1da | 202 | .irq_ack = irq_chip_ack_parent, |
e390d895 | 203 | .irq_set_affinity = msi_domain_set_affinity, |
0921f1da JL |
204 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
205 | .irq_compose_msi_msg = irq_msi_compose_msg, | |
62ac1780 | 206 | .irq_write_msi_msg = dmar_msi_write_msg, |
44380982 JL |
207 | .flags = IRQCHIP_SKIP_SET_WAKE, |
208 | }; | |
209 | ||
e390d895 JL |
210 | static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info, |
211 | msi_alloc_info_t *arg) | |
0921f1da | 212 | { |
e390d895 | 213 | return arg->dmar_id; |
0921f1da JL |
214 | } |
215 | ||
e390d895 JL |
216 | static int dmar_msi_init(struct irq_domain *domain, |
217 | struct msi_domain_info *info, unsigned int virq, | |
218 | irq_hw_number_t hwirq, msi_alloc_info_t *arg) | |
0921f1da | 219 | { |
e390d895 JL |
220 | irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL, |
221 | handle_edge_irq, arg->dmar_data, "edge"); | |
0921f1da | 222 | |
e390d895 | 223 | return 0; |
0921f1da JL |
224 | } |
225 | ||
e390d895 JL |
226 | static struct msi_domain_ops dmar_msi_domain_ops = { |
227 | .get_hwirq = dmar_msi_get_hwirq, | |
228 | .msi_init = dmar_msi_init, | |
229 | }; | |
0921f1da | 230 | |
e390d895 JL |
231 | static struct msi_domain_info dmar_msi_domain_info = { |
232 | .ops = &dmar_msi_domain_ops, | |
233 | .chip = &dmar_msi_controller, | |
0921f1da JL |
234 | }; |
235 | ||
236 | static struct irq_domain *dmar_get_irq_domain(void) | |
237 | { | |
238 | static struct irq_domain *dmar_domain; | |
239 | static DEFINE_MUTEX(dmar_lock); | |
f8f37ca7 | 240 | struct fwnode_handle *fn; |
0921f1da JL |
241 | |
242 | mutex_lock(&dmar_lock); | |
f8f37ca7 TG |
243 | if (dmar_domain) |
244 | goto out; | |
245 | ||
246 | fn = irq_domain_alloc_named_fwnode("DMAR-MSI"); | |
247 | if (fn) { | |
248 | dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info, | |
e390d895 | 249 | x86_vector_domain); |
f8f37ca7 TG |
250 | irq_domain_free_fwnode(fn); |
251 | } | |
252 | out: | |
0921f1da | 253 | mutex_unlock(&dmar_lock); |
0921f1da JL |
254 | return dmar_domain; |
255 | } | |
256 | ||
257 | int dmar_alloc_hwirq(int id, int node, void *arg) | |
258 | { | |
259 | struct irq_domain *domain = dmar_get_irq_domain(); | |
260 | struct irq_alloc_info info; | |
261 | ||
262 | if (!domain) | |
263 | return -1; | |
264 | ||
265 | init_irq_alloc_info(&info, NULL); | |
266 | info.type = X86_IRQ_ALLOC_TYPE_DMAR; | |
267 | info.dmar_id = id; | |
268 | info.dmar_data = arg; | |
a62b32cd | 269 | |
0921f1da | 270 | return irq_domain_alloc_irqs(domain, 1, node, &info); |
a62b32cd JL |
271 | } |
272 | ||
273 | void dmar_free_hwirq(int irq) | |
274 | { | |
275 | irq_domain_free_irqs(irq, 1); | |
276 | } | |
44380982 JL |
277 | #endif |
278 | ||
279 | /* | |
280 | * MSI message composition | |
281 | */ | |
282 | #ifdef CONFIG_HPET_TIMER | |
3cb96f0c JL |
283 | static inline int hpet_dev_id(struct irq_domain *domain) |
284 | { | |
e390d895 | 285 | struct msi_domain_info *info = msi_get_domain_info(domain); |
44380982 | 286 | |
e390d895 | 287 | return (int)(long)info->data; |
44380982 JL |
288 | } |
289 | ||
62ac1780 JL |
290 | static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) |
291 | { | |
ff96b4d0 | 292 | hpet_msi_write(irq_data_get_irq_handler_data(data), msg); |
62ac1780 JL |
293 | } |
294 | ||
404f6aac | 295 | static struct irq_chip hpet_msi_controller __ro_after_init = { |
81dabe2e | 296 | .name = "HPET-MSI", |
44380982 JL |
297 | .irq_unmask = hpet_msi_unmask, |
298 | .irq_mask = hpet_msi_mask, | |
3cb96f0c | 299 | .irq_ack = irq_chip_ack_parent, |
e390d895 | 300 | .irq_set_affinity = msi_domain_set_affinity, |
3cb96f0c | 301 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
3cb96f0c | 302 | .irq_compose_msi_msg = irq_msi_compose_msg, |
62ac1780 | 303 | .irq_write_msi_msg = hpet_msi_write_msg, |
44380982 JL |
304 | .flags = IRQCHIP_SKIP_SET_WAKE, |
305 | }; | |
306 | ||
e390d895 JL |
307 | static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info, |
308 | msi_alloc_info_t *arg) | |
3cb96f0c | 309 | { |
e390d895 | 310 | return arg->hpet_index; |
3cb96f0c JL |
311 | } |
312 | ||
e390d895 JL |
313 | static int hpet_msi_init(struct irq_domain *domain, |
314 | struct msi_domain_info *info, unsigned int virq, | |
315 | irq_hw_number_t hwirq, msi_alloc_info_t *arg) | |
3cb96f0c | 316 | { |
e390d895 JL |
317 | irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); |
318 | irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL, | |
319 | handle_edge_irq, arg->hpet_data, "edge"); | |
3cb96f0c | 320 | |
e390d895 | 321 | return 0; |
3cb96f0c JL |
322 | } |
323 | ||
e390d895 JL |
324 | static void hpet_msi_free(struct irq_domain *domain, |
325 | struct msi_domain_info *info, unsigned int virq) | |
3cb96f0c | 326 | { |
e390d895 | 327 | irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); |
3cb96f0c JL |
328 | } |
329 | ||
e390d895 JL |
330 | static struct msi_domain_ops hpet_msi_domain_ops = { |
331 | .get_hwirq = hpet_msi_get_hwirq, | |
332 | .msi_init = hpet_msi_init, | |
333 | .msi_free = hpet_msi_free, | |
334 | }; | |
335 | ||
336 | static struct msi_domain_info hpet_msi_domain_info = { | |
337 | .ops = &hpet_msi_domain_ops, | |
338 | .chip = &hpet_msi_controller, | |
3cb96f0c JL |
339 | }; |
340 | ||
341 | struct irq_domain *hpet_create_irq_domain(int hpet_id) | |
342 | { | |
e390d895 | 343 | struct msi_domain_info *domain_info; |
f8f37ca7 TG |
344 | struct irq_domain *parent, *d; |
345 | struct irq_alloc_info info; | |
346 | struct fwnode_handle *fn; | |
3cb96f0c JL |
347 | |
348 | if (x86_vector_domain == NULL) | |
349 | return NULL; | |
350 | ||
e390d895 JL |
351 | domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); |
352 | if (!domain_info) | |
353 | return NULL; | |
354 | ||
355 | *domain_info = hpet_msi_domain_info; | |
356 | domain_info->data = (void *)(long)hpet_id; | |
357 | ||
3cb96f0c JL |
358 | init_irq_alloc_info(&info, NULL); |
359 | info.type = X86_IRQ_ALLOC_TYPE_HPET; | |
360 | info.hpet_id = hpet_id; | |
361 | parent = irq_remapping_get_ir_irq_domain(&info); | |
362 | if (parent == NULL) | |
363 | parent = x86_vector_domain; | |
68682a26 JL |
364 | else |
365 | hpet_msi_controller.name = "IR-HPET-MSI"; | |
3cb96f0c | 366 | |
f8f37ca7 TG |
367 | fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, |
368 | hpet_id); | |
369 | if (!fn) { | |
370 | kfree(domain_info); | |
371 | return NULL; | |
372 | } | |
373 | ||
374 | d = msi_create_irq_domain(fn, domain_info, parent); | |
375 | irq_domain_free_fwnode(fn); | |
376 | return d; | |
3cb96f0c JL |
377 | } |
378 | ||
379 | int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev, | |
380 | int dev_num) | |
381 | { | |
382 | struct irq_alloc_info info; | |
383 | ||
384 | init_irq_alloc_info(&info, NULL); | |
385 | info.type = X86_IRQ_ALLOC_TYPE_HPET; | |
386 | info.hpet_data = dev; | |
387 | info.hpet_id = hpet_dev_id(domain); | |
388 | info.hpet_index = dev_num; | |
389 | ||
4a00c95d | 390 | return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); |
3cb96f0c | 391 | } |
44380982 | 392 | #endif |