Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #include <linux/bootmem.h> |
41 | #include <linux/dmar.h> | |
58ac1e76 | 42 | #include <linux/hpet.h> |
54d5d424 | 43 | |
d4057bdb | 44 | #include <asm/idle.h> |
1da177e4 LT |
45 | #include <asm/io.h> |
46 | #include <asm/smp.h> | |
6d652ea1 | 47 | #include <asm/cpu.h> |
1da177e4 | 48 | #include <asm/desc.h> |
d4057bdb YL |
49 | #include <asm/proto.h> |
50 | #include <asm/acpi.h> | |
51 | #include <asm/dma.h> | |
1da177e4 | 52 | #include <asm/timer.h> |
306e440d | 53 | #include <asm/i8259.h> |
2d3fcc1c | 54 | #include <asm/msidef.h> |
8b955b0d | 55 | #include <asm/hypertransport.h> |
a4dbc34d | 56 | #include <asm/setup.h> |
8a8f422d | 57 | #include <asm/irq_remapping.h> |
58ac1e76 | 58 | #include <asm/hpet.h> |
2c1b284e | 59 | #include <asm/hw_irq.h> |
1da177e4 | 60 | |
7b6aa335 | 61 | #include <asm/apic.h> |
1da177e4 | 62 | |
32f71aff | 63 | #define __apicdebuginit(type) static type __init |
136d249e | 64 | |
f44d1692 JL |
65 | #define for_each_ioapic(idx) \ |
66 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
67 | #define for_each_ioapic_reverse(idx) \ | |
68 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
69 | #define for_each_pin(idx, pin) \ | |
70 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
71 | #define for_each_ioapic_pin(idx, pin) \ | |
72 | for_each_ioapic((idx)) \ | |
73 | for_each_pin((idx), (pin)) | |
74 | ||
2977fb3f CG |
75 | #define for_each_irq_pin(entry, head) \ |
76 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 77 | |
1da177e4 | 78 | /* |
54168ed7 IM |
79 | * Is the SiS APIC rmw bug present ? |
80 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
81 | */ |
82 | int sis_apic_bug = -1; | |
83 | ||
dade7716 TG |
84 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
85 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 86 | |
b69c6c3b SS |
87 | static struct ioapic { |
88 | /* | |
89 | * # of IRQ routing registers | |
90 | */ | |
91 | int nr_registers; | |
57a6f740 SS |
92 | /* |
93 | * Saved state during suspend/resume, or while enabling intr-remap. | |
94 | */ | |
95 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
96 | /* I/O APIC config */ |
97 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
98 | /* IO APIC gsi routing info */ |
99 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 100 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 101 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 102 | |
6f50d45f | 103 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 104 | |
6f50d45f | 105 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 106 | { |
6f50d45f | 107 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
108 | } |
109 | ||
6f50d45f | 110 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 111 | { |
6f50d45f | 112 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
113 | } |
114 | ||
6f50d45f | 115 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 116 | { |
6f50d45f | 117 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 118 | } |
9f640ccb | 119 | |
18e48551 JL |
120 | static inline int mp_ioapic_pin_count(int ioapic) |
121 | { | |
122 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
123 | ||
124 | return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; | |
125 | } | |
126 | ||
127 | u32 mp_pin_to_gsi(int ioapic, int pin) | |
128 | { | |
129 | return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; | |
130 | } | |
131 | ||
132 | /* Initialize all legacy IRQs and all pins on the first IOAPIC at boot */ | |
133 | static inline int mp_init_irq_at_boot(int ioapic, int irq) | |
134 | { | |
135 | return ioapic == 0 || (irq >= 0 && irq < NR_IRQS_LEGACY); | |
136 | } | |
137 | ||
c040aaeb | 138 | int nr_ioapics; |
2a4ab640 | 139 | |
a4384df3 EB |
140 | /* The one past the highest gsi number used */ |
141 | u32 gsi_top; | |
5777372a | 142 | |
584f734d | 143 | /* MP IRQ source entries */ |
c2c21745 | 144 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
145 | |
146 | /* # of MP IRQ source entries */ | |
147 | int mp_irq_entries; | |
148 | ||
bb8187d3 | 149 | #ifdef CONFIG_EISA |
8732fc4b AS |
150 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
151 | #endif | |
152 | ||
153 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
154 | ||
efa2559f YL |
155 | int skip_ioapic_setup; |
156 | ||
7167d08e HK |
157 | /** |
158 | * disable_ioapic_support() - disables ioapic support at runtime | |
159 | */ | |
160 | void disable_ioapic_support(void) | |
65a4e574 IM |
161 | { |
162 | #ifdef CONFIG_PCI | |
163 | noioapicquirk = 1; | |
164 | noioapicreroute = -1; | |
165 | #endif | |
166 | skip_ioapic_setup = 1; | |
167 | } | |
168 | ||
54168ed7 | 169 | static int __init parse_noapic(char *str) |
efa2559f YL |
170 | { |
171 | /* disable IO-APIC */ | |
7167d08e | 172 | disable_ioapic_support(); |
efa2559f YL |
173 | return 0; |
174 | } | |
175 | early_param("noapic", parse_noapic); | |
66759a01 | 176 | |
20443598 SAS |
177 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
178 | struct io_apic_irq_attr *attr); | |
710dcda6 | 179 | |
2d8009ba FT |
180 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
181 | void mp_save_irq(struct mpc_intsrc *m) | |
182 | { | |
183 | int i; | |
184 | ||
185 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
186 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
187 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
188 | m->srcbusirq, m->dstapic, m->dstirq); | |
189 | ||
190 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 191 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
192 | return; |
193 | } | |
194 | ||
0e3fa13f | 195 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
196 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
197 | panic("Max # of irq sources exceeded!!\n"); | |
198 | } | |
199 | ||
0b8f1efa YL |
200 | struct irq_pin_list { |
201 | int apic, pin; | |
202 | struct irq_pin_list *next; | |
203 | }; | |
204 | ||
7e495529 | 205 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 206 | { |
2ee39065 | 207 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
208 | } |
209 | ||
2d8009ba | 210 | |
a1420f39 | 211 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
97943390 | 212 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
a1420f39 | 213 | |
13a0c3c2 | 214 | int __init arch_early_irq_init(void) |
8f09cd20 | 215 | { |
0b8f1efa | 216 | struct irq_cfg *cfg; |
60c69948 | 217 | int count, node, i; |
d6c88a50 | 218 | |
bb84ac2d | 219 | if (!legacy_pic->nr_legacy_irqs) |
1f91233c | 220 | io_apic_irqs = ~0UL; |
1f91233c | 221 | |
f44d1692 | 222 | for_each_ioapic(i) { |
57a6f740 | 223 | ioapics[i].saved_registers = |
4c79185c | 224 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 225 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 226 | if (!ioapics[i].saved_registers) |
4c79185c SS |
227 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
228 | } | |
229 | ||
0b8f1efa YL |
230 | cfg = irq_cfgx; |
231 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 232 | node = cpu_to_node(0); |
8f09cd20 | 233 | |
0b8f1efa | 234 | for (i = 0; i < count; i++) { |
2c778651 | 235 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
236 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
237 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
238 | /* |
239 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
29c574c0 | 240 | * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. |
97943390 | 241 | */ |
54b56170 | 242 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 | 243 | cfg[i].vector = IRQ0_VECTOR + i; |
29c574c0 | 244 | cpumask_setall(cfg[i].domain); |
97943390 | 245 | } |
0b8f1efa | 246 | } |
13a0c3c2 YL |
247 | |
248 | return 0; | |
0b8f1efa | 249 | } |
8f09cd20 | 250 | |
32f5ef5d | 251 | static inline struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 252 | { |
2c778651 | 253 | return irq_get_chip_data(irq); |
8f09cd20 | 254 | } |
d6c88a50 | 255 | |
f981a3dc | 256 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 257 | { |
0b8f1efa | 258 | struct irq_cfg *cfg; |
0f978f45 | 259 | |
2ee39065 | 260 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
261 | if (!cfg) |
262 | return NULL; | |
2ee39065 | 263 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 264 | goto out_cfg; |
2ee39065 | 265 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 266 | goto out_domain; |
0b8f1efa | 267 | return cfg; |
6e2fff50 TG |
268 | out_domain: |
269 | free_cpumask_var(cfg->domain); | |
270 | out_cfg: | |
271 | kfree(cfg); | |
272 | return NULL; | |
8f09cd20 YL |
273 | } |
274 | ||
f981a3dc | 275 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 276 | { |
fbc6bff0 TG |
277 | if (!cfg) |
278 | return; | |
2c778651 | 279 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
280 | free_cpumask_var(cfg->domain); |
281 | free_cpumask_var(cfg->old_domain); | |
282 | kfree(cfg); | |
283 | } | |
284 | ||
08c33db6 TG |
285 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
286 | { | |
287 | int res = irq_alloc_desc_at(at, node); | |
288 | struct irq_cfg *cfg; | |
289 | ||
290 | if (res < 0) { | |
291 | if (res != -EEXIST) | |
292 | return NULL; | |
32f5ef5d | 293 | cfg = irq_cfg(at); |
08c33db6 TG |
294 | if (cfg) |
295 | return cfg; | |
296 | } | |
297 | ||
f981a3dc | 298 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 299 | if (cfg) |
2c778651 | 300 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
301 | else |
302 | irq_free_desc(at); | |
303 | return cfg; | |
304 | } | |
305 | ||
130fe05d LT |
306 | struct io_apic { |
307 | unsigned int index; | |
308 | unsigned int unused[3]; | |
309 | unsigned int data; | |
0280f7c4 SS |
310 | unsigned int unused2[11]; |
311 | unsigned int eoi; | |
130fe05d LT |
312 | }; |
313 | ||
314 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
315 | { | |
316 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 317 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
318 | } |
319 | ||
da165322 | 320 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
321 | { |
322 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
323 | writel(vector, &io_apic->eoi); | |
324 | } | |
325 | ||
4a8e2a31 | 326 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
327 | { |
328 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
329 | writel(reg, &io_apic->index); | |
330 | return readl(&io_apic->data); | |
331 | } | |
332 | ||
4a8e2a31 | 333 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
334 | { |
335 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 336 | |
130fe05d LT |
337 | writel(reg, &io_apic->index); |
338 | writel(value, &io_apic->data); | |
339 | } | |
340 | ||
341 | /* | |
342 | * Re-write a value: to be used for read-modify-write | |
343 | * cycles where the read already set up the index register. | |
344 | * | |
345 | * Older SiS APIC requires we rewrite the index register | |
346 | */ | |
4a8e2a31 | 347 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 348 | { |
54168ed7 | 349 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
350 | |
351 | if (sis_apic_bug) | |
352 | writel(reg, &io_apic->index); | |
130fe05d LT |
353 | writel(value, &io_apic->data); |
354 | } | |
355 | ||
cf4c6a2f AK |
356 | union entry_union { |
357 | struct { u32 w1, w2; }; | |
358 | struct IO_APIC_route_entry entry; | |
359 | }; | |
360 | ||
e57253a8 SS |
361 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
362 | { | |
363 | union entry_union eu; | |
364 | ||
365 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
366 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 367 | |
e57253a8 SS |
368 | return eu.entry; |
369 | } | |
370 | ||
cf4c6a2f AK |
371 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
372 | { | |
373 | union entry_union eu; | |
374 | unsigned long flags; | |
136d249e | 375 | |
dade7716 | 376 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 377 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 378 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 379 | |
cf4c6a2f AK |
380 | return eu.entry; |
381 | } | |
382 | ||
f9dadfa7 LT |
383 | /* |
384 | * When we write a new IO APIC routing entry, we need to write the high | |
385 | * word first! If the mask bit in the low word is clear, we will enable | |
386 | * the interrupt, and we need to make sure the entry is fully populated | |
387 | * before that happens. | |
388 | */ | |
136d249e | 389 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 390 | { |
50a8d4d2 F |
391 | union entry_union eu = {{0, 0}}; |
392 | ||
cf4c6a2f | 393 | eu.entry = e; |
f9dadfa7 LT |
394 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
395 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
396 | } |
397 | ||
1a8ce7ff | 398 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
399 | { |
400 | unsigned long flags; | |
136d249e | 401 | |
dade7716 | 402 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 403 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 404 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
405 | } |
406 | ||
407 | /* | |
408 | * When we mask an IO APIC routing entry, we need to write the low | |
409 | * word first, in order to set the mask bit before we change the | |
410 | * high bits! | |
411 | */ | |
412 | static void ioapic_mask_entry(int apic, int pin) | |
413 | { | |
414 | unsigned long flags; | |
415 | union entry_union eu = { .entry.mask = 1 }; | |
416 | ||
dade7716 | 417 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
418 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
419 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 420 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
421 | } |
422 | ||
1da177e4 LT |
423 | /* |
424 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
425 | * shared ISA-space IRQs, so we have to support them. We are super | |
426 | * fast in the common case, and fast for shared ISA-space IRQs. | |
427 | */ | |
136d249e | 428 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 429 | { |
2977fb3f | 430 | struct irq_pin_list **last, *entry; |
0f978f45 | 431 | |
2977fb3f CG |
432 | /* don't allow duplicates */ |
433 | last = &cfg->irq_2_pin; | |
434 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 435 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 436 | return 0; |
2977fb3f | 437 | last = &entry->next; |
1da177e4 | 438 | } |
0f978f45 | 439 | |
7e495529 | 440 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 441 | if (!entry) { |
c767a54b JP |
442 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
443 | node, apic, pin); | |
f3d1915a | 444 | return -ENOMEM; |
a7428cd2 | 445 | } |
1da177e4 LT |
446 | entry->apic = apic; |
447 | entry->pin = pin; | |
875e68ec | 448 | |
2977fb3f | 449 | *last = entry; |
f3d1915a CG |
450 | return 0; |
451 | } | |
452 | ||
453 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
454 | { | |
7e495529 | 455 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 456 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
457 | } |
458 | ||
459 | /* | |
460 | * Reroute an IRQ to a different pin. | |
461 | */ | |
85ac16d0 | 462 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
463 | int oldapic, int oldpin, |
464 | int newapic, int newpin) | |
1da177e4 | 465 | { |
535b6429 | 466 | struct irq_pin_list *entry; |
1da177e4 | 467 | |
2977fb3f | 468 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
469 | if (entry->apic == oldapic && entry->pin == oldpin) { |
470 | entry->apic = newapic; | |
471 | entry->pin = newpin; | |
0f978f45 | 472 | /* every one is different, right? */ |
4eea6fff | 473 | return; |
0f978f45 | 474 | } |
1da177e4 | 475 | } |
0f978f45 | 476 | |
4eea6fff JF |
477 | /* old apic/pin didn't exist, so just add new ones */ |
478 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
479 | } |
480 | ||
c29d9db3 SS |
481 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
482 | int mask_and, int mask_or, | |
483 | void (*final)(struct irq_pin_list *entry)) | |
484 | { | |
485 | unsigned int reg, pin; | |
486 | ||
487 | pin = entry->pin; | |
488 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
489 | reg &= mask_and; | |
490 | reg |= mask_or; | |
491 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
492 | if (final) | |
493 | final(entry); | |
494 | } | |
495 | ||
2f210deb JF |
496 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
497 | int mask_and, int mask_or, | |
498 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 499 | { |
87783be4 | 500 | struct irq_pin_list *entry; |
047c8fdb | 501 | |
c29d9db3 SS |
502 | for_each_irq_pin(entry, cfg->irq_2_pin) |
503 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
504 | } | |
505 | ||
7f3e632f | 506 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 507 | { |
87783be4 CG |
508 | /* |
509 | * Synchronize the IO-APIC and the CPU by doing | |
510 | * a dummy read from the IO-APIC | |
511 | */ | |
512 | struct io_apic __iomem *io_apic; | |
136d249e | 513 | |
87783be4 | 514 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 515 | readl(&io_apic->data); |
1da177e4 LT |
516 | } |
517 | ||
dd5f15e5 | 518 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 519 | { |
dd5f15e5 TG |
520 | unsigned long flags; |
521 | ||
522 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 523 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 524 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 525 | } |
1da177e4 | 526 | |
90297c5f | 527 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 528 | { |
90297c5f | 529 | mask_ioapic(data->chip_data); |
dd5f15e5 | 530 | } |
3145e941 | 531 | |
dd5f15e5 TG |
532 | static void __unmask_ioapic(struct irq_cfg *cfg) |
533 | { | |
534 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
535 | } |
536 | ||
dd5f15e5 | 537 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
538 | { |
539 | unsigned long flags; | |
540 | ||
dade7716 | 541 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 542 | __unmask_ioapic(cfg); |
dade7716 | 543 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
544 | } |
545 | ||
90297c5f | 546 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 547 | { |
90297c5f | 548 | unmask_ioapic(data->chip_data); |
3145e941 YL |
549 | } |
550 | ||
c0205701 SS |
551 | /* |
552 | * IO-APIC versions below 0x20 don't support EOI register. | |
553 | * For the record, here is the information about various versions: | |
554 | * 0Xh 82489DX | |
555 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
556 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
557 | * 30h-FFh Reserved | |
558 | * | |
559 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
560 | * version as 0x2. This is an error with documentation and these ICH chips | |
561 | * use io-apic's of version 0x20. | |
562 | * | |
563 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
564 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
565 | * mode to edge and then back to level, with RTE being masked during this. | |
566 | */ | |
da165322 | 567 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
568 | { |
569 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 570 | io_apic_eoi(apic, vector); |
c0205701 SS |
571 | } else { |
572 | struct IO_APIC_route_entry entry, entry1; | |
573 | ||
574 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
575 | ||
576 | /* | |
577 | * Mask the entry and change the trigger mode to edge. | |
578 | */ | |
579 | entry1.mask = 1; | |
580 | entry1.trigger = IOAPIC_EDGE; | |
581 | ||
582 | __ioapic_write_entry(apic, pin, entry1); | |
583 | ||
584 | /* | |
585 | * Restore the previous level triggered entry. | |
586 | */ | |
587 | __ioapic_write_entry(apic, pin, entry); | |
588 | } | |
589 | } | |
590 | ||
9b1b0e42 | 591 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
592 | { |
593 | struct irq_pin_list *entry; | |
594 | unsigned long flags; | |
595 | ||
596 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
597 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
598 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
599 | cfg->vector); | |
c0205701 SS |
600 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
601 | } | |
602 | ||
1da177e4 LT |
603 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
604 | { | |
605 | struct IO_APIC_route_entry entry; | |
36062448 | 606 | |
1da177e4 | 607 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 608 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
609 | if (entry.delivery_mode == dest_SMI) |
610 | return; | |
1e75b31d | 611 | |
1da177e4 | 612 | /* |
1e75b31d SS |
613 | * Make sure the entry is masked and re-read the contents to check |
614 | * if it is a level triggered pin and if the remote-IRR is set. | |
615 | */ | |
616 | if (!entry.mask) { | |
617 | entry.mask = 1; | |
618 | ioapic_write_entry(apic, pin, entry); | |
619 | entry = ioapic_read_entry(apic, pin); | |
620 | } | |
621 | ||
622 | if (entry.irr) { | |
c0205701 SS |
623 | unsigned long flags; |
624 | ||
1e75b31d SS |
625 | /* |
626 | * Make sure the trigger mode is set to level. Explicit EOI | |
627 | * doesn't clear the remote-IRR if the trigger mode is not | |
628 | * set to level. | |
629 | */ | |
630 | if (!entry.trigger) { | |
631 | entry.trigger = IOAPIC_LEVEL; | |
632 | ioapic_write_entry(apic, pin, entry); | |
633 | } | |
634 | ||
c0205701 | 635 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
da165322 | 636 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 637 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
638 | } |
639 | ||
640 | /* | |
641 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
642 | * bit. | |
1da177e4 | 643 | */ |
f9dadfa7 | 644 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
645 | entry = ioapic_read_entry(apic, pin); |
646 | if (entry.irr) | |
c767a54b | 647 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 648 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
649 | } |
650 | ||
54168ed7 | 651 | static void clear_IO_APIC (void) |
1da177e4 LT |
652 | { |
653 | int apic, pin; | |
654 | ||
f44d1692 JL |
655 | for_each_ioapic_pin(apic, pin) |
656 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
657 | } |
658 | ||
54168ed7 | 659 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
660 | /* |
661 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
662 | * specific CPU-side IRQs. | |
663 | */ | |
664 | ||
665 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
666 | static int pirq_entries[MAX_PIRQS] = { |
667 | [0 ... MAX_PIRQS - 1] = -1 | |
668 | }; | |
1da177e4 | 669 | |
1da177e4 LT |
670 | static int __init ioapic_pirq_setup(char *str) |
671 | { | |
672 | int i, max; | |
673 | int ints[MAX_PIRQS+1]; | |
674 | ||
675 | get_options(str, ARRAY_SIZE(ints), ints); | |
676 | ||
1da177e4 LT |
677 | apic_printk(APIC_VERBOSE, KERN_INFO |
678 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
679 | max = MAX_PIRQS; | |
680 | if (ints[0] < MAX_PIRQS) | |
681 | max = ints[0]; | |
682 | ||
683 | for (i = 0; i < max; i++) { | |
684 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
685 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
686 | /* | |
687 | * PIRQs are mapped upside down, usually. | |
688 | */ | |
689 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
690 | } | |
691 | return 1; | |
692 | } | |
693 | ||
694 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
695 | #endif /* CONFIG_X86_32 */ |
696 | ||
54168ed7 | 697 | /* |
05c3dc2c | 698 | * Saves all the IO-APIC RTE's |
54168ed7 | 699 | */ |
31dce14a | 700 | int save_ioapic_entries(void) |
54168ed7 | 701 | { |
54168ed7 | 702 | int apic, pin; |
31dce14a | 703 | int err = 0; |
54168ed7 | 704 | |
f44d1692 | 705 | for_each_ioapic(apic) { |
57a6f740 | 706 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
707 | err = -ENOMEM; |
708 | continue; | |
709 | } | |
54168ed7 | 710 | |
f44d1692 | 711 | for_each_pin(apic, pin) |
57a6f740 | 712 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 713 | ioapic_read_entry(apic, pin); |
b24696bc | 714 | } |
5ffa4eb2 | 715 | |
31dce14a | 716 | return err; |
54168ed7 IM |
717 | } |
718 | ||
b24696bc FY |
719 | /* |
720 | * Mask all IO APIC entries. | |
721 | */ | |
31dce14a | 722 | void mask_ioapic_entries(void) |
05c3dc2c SS |
723 | { |
724 | int apic, pin; | |
725 | ||
f44d1692 | 726 | for_each_ioapic(apic) { |
2f344d2e | 727 | if (!ioapics[apic].saved_registers) |
31dce14a | 728 | continue; |
b24696bc | 729 | |
f44d1692 | 730 | for_each_pin(apic, pin) { |
05c3dc2c SS |
731 | struct IO_APIC_route_entry entry; |
732 | ||
57a6f740 | 733 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
734 | if (!entry.mask) { |
735 | entry.mask = 1; | |
736 | ioapic_write_entry(apic, pin, entry); | |
737 | } | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
b24696bc | 742 | /* |
57a6f740 | 743 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 744 | */ |
31dce14a | 745 | int restore_ioapic_entries(void) |
54168ed7 IM |
746 | { |
747 | int apic, pin; | |
748 | ||
f44d1692 | 749 | for_each_ioapic(apic) { |
2f344d2e | 750 | if (!ioapics[apic].saved_registers) |
31dce14a | 751 | continue; |
b24696bc | 752 | |
f44d1692 | 753 | for_each_pin(apic, pin) |
54168ed7 | 754 | ioapic_write_entry(apic, pin, |
57a6f740 | 755 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 756 | } |
b24696bc | 757 | return 0; |
54168ed7 IM |
758 | } |
759 | ||
1da177e4 LT |
760 | /* |
761 | * Find the IRQ entry number of a certain pin. | |
762 | */ | |
6f50d45f | 763 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
764 | { |
765 | int i; | |
766 | ||
767 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 768 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 769 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
770 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
771 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
772 | return i; |
773 | ||
774 | return -1; | |
775 | } | |
776 | ||
777 | /* | |
778 | * Find the pin to which IRQ[irq] (ISA) is connected | |
779 | */ | |
fcfd636a | 780 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
781 | { |
782 | int i; | |
783 | ||
784 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 785 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 786 | |
d27e2b8e | 787 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
788 | (mp_irqs[i].irqtype == type) && |
789 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 790 | |
c2c21745 | 791 | return mp_irqs[i].dstirq; |
1da177e4 LT |
792 | } |
793 | return -1; | |
794 | } | |
795 | ||
fcfd636a EB |
796 | static int __init find_isa_irq_apic(int irq, int type) |
797 | { | |
798 | int i; | |
799 | ||
800 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 801 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 802 | |
73b2961b | 803 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
804 | (mp_irqs[i].irqtype == type) && |
805 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
806 | break; |
807 | } | |
6f50d45f | 808 | |
fcfd636a | 809 | if (i < mp_irq_entries) { |
6f50d45f YL |
810 | int ioapic_idx; |
811 | ||
f44d1692 | 812 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
813 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
814 | return ioapic_idx; | |
fcfd636a EB |
815 | } |
816 | ||
817 | return -1; | |
818 | } | |
819 | ||
bb8187d3 | 820 | #ifdef CONFIG_EISA |
1da177e4 LT |
821 | /* |
822 | * EISA Edge/Level control register, ELCR | |
823 | */ | |
824 | static int EISA_ELCR(unsigned int irq) | |
825 | { | |
b81bb373 | 826 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
827 | unsigned int port = 0x4d0 + (irq >> 3); |
828 | return (inb(port) >> (irq & 7)) & 1; | |
829 | } | |
830 | apic_printk(APIC_VERBOSE, KERN_INFO | |
831 | "Broken MPtable reports ISA irq %d\n", irq); | |
832 | return 0; | |
833 | } | |
54168ed7 | 834 | |
c0a282c2 | 835 | #endif |
1da177e4 | 836 | |
6728801d AS |
837 | /* ISA interrupts are always polarity zero edge triggered, |
838 | * when listed as conforming in the MP table. */ | |
839 | ||
840 | #define default_ISA_trigger(idx) (0) | |
841 | #define default_ISA_polarity(idx) (0) | |
842 | ||
1da177e4 LT |
843 | /* EISA interrupts are always polarity zero and can be edge or level |
844 | * trigger depending on the ELCR value. If an interrupt is listed as | |
845 | * EISA conforming in the MP table, that means its trigger type must | |
846 | * be read in from the ELCR */ | |
847 | ||
c2c21745 | 848 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 849 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
850 | |
851 | /* PCI interrupts are always polarity one level triggered, | |
852 | * when listed as conforming in the MP table. */ | |
853 | ||
854 | #define default_PCI_trigger(idx) (1) | |
855 | #define default_PCI_polarity(idx) (1) | |
856 | ||
b77cf6a8 | 857 | static int irq_polarity(int idx) |
1da177e4 | 858 | { |
c2c21745 | 859 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
860 | int polarity; |
861 | ||
862 | /* | |
863 | * Determine IRQ line polarity (high active or low active): | |
864 | */ | |
c2c21745 | 865 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 866 | { |
54168ed7 IM |
867 | case 0: /* conforms, ie. bus-type dependent polarity */ |
868 | if (test_bit(bus, mp_bus_not_pci)) | |
869 | polarity = default_ISA_polarity(idx); | |
870 | else | |
871 | polarity = default_PCI_polarity(idx); | |
872 | break; | |
873 | case 1: /* high active */ | |
874 | { | |
875 | polarity = 0; | |
876 | break; | |
877 | } | |
878 | case 2: /* reserved */ | |
879 | { | |
c767a54b | 880 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
881 | polarity = 1; |
882 | break; | |
883 | } | |
884 | case 3: /* low active */ | |
885 | { | |
886 | polarity = 1; | |
887 | break; | |
888 | } | |
889 | default: /* invalid */ | |
890 | { | |
c767a54b | 891 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
892 | polarity = 1; |
893 | break; | |
894 | } | |
1da177e4 LT |
895 | } |
896 | return polarity; | |
897 | } | |
898 | ||
b77cf6a8 | 899 | static int irq_trigger(int idx) |
1da177e4 | 900 | { |
c2c21745 | 901 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
902 | int trigger; |
903 | ||
904 | /* | |
905 | * Determine IRQ trigger mode (edge or level sensitive): | |
906 | */ | |
c2c21745 | 907 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 908 | { |
54168ed7 IM |
909 | case 0: /* conforms, ie. bus-type dependent */ |
910 | if (test_bit(bus, mp_bus_not_pci)) | |
911 | trigger = default_ISA_trigger(idx); | |
912 | else | |
913 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 914 | #ifdef CONFIG_EISA |
54168ed7 IM |
915 | switch (mp_bus_id_to_type[bus]) { |
916 | case MP_BUS_ISA: /* ISA pin */ | |
917 | { | |
918 | /* set before the switch */ | |
919 | break; | |
920 | } | |
921 | case MP_BUS_EISA: /* EISA pin */ | |
922 | { | |
923 | trigger = default_EISA_trigger(idx); | |
924 | break; | |
925 | } | |
926 | case MP_BUS_PCI: /* PCI pin */ | |
927 | { | |
928 | /* set before the switch */ | |
929 | break; | |
930 | } | |
54168ed7 IM |
931 | default: |
932 | { | |
c767a54b | 933 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
934 | trigger = 1; |
935 | break; | |
936 | } | |
937 | } | |
938 | #endif | |
1da177e4 | 939 | break; |
54168ed7 | 940 | case 1: /* edge */ |
1da177e4 | 941 | { |
54168ed7 | 942 | trigger = 0; |
1da177e4 LT |
943 | break; |
944 | } | |
54168ed7 | 945 | case 2: /* reserved */ |
1da177e4 | 946 | { |
c767a54b | 947 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 948 | trigger = 1; |
1da177e4 LT |
949 | break; |
950 | } | |
54168ed7 | 951 | case 3: /* level */ |
1da177e4 | 952 | { |
54168ed7 | 953 | trigger = 1; |
1da177e4 LT |
954 | break; |
955 | } | |
54168ed7 | 956 | default: /* invalid */ |
1da177e4 | 957 | { |
c767a54b | 958 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 959 | trigger = 0; |
1da177e4 LT |
960 | break; |
961 | } | |
962 | } | |
963 | return trigger; | |
964 | } | |
965 | ||
1da177e4 LT |
966 | static int pin_2_irq(int idx, int apic, int pin) |
967 | { | |
d464207c | 968 | int irq; |
c2c21745 | 969 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 970 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
971 | |
972 | /* | |
973 | * Debugging check, we are in big trouble if this message pops up! | |
974 | */ | |
c2c21745 | 975 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 976 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 977 | |
54168ed7 | 978 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 979 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 980 | } else { |
c040aaeb | 981 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
982 | |
983 | if (gsi >= NR_IRQS_LEGACY) | |
984 | irq = gsi; | |
985 | else | |
a4384df3 | 986 | irq = gsi_top + gsi; |
1da177e4 LT |
987 | } |
988 | ||
54168ed7 | 989 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
990 | /* |
991 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
992 | */ | |
993 | if ((pin >= 16) && (pin <= 23)) { | |
994 | if (pirq_entries[pin-16] != -1) { | |
995 | if (!pirq_entries[pin-16]) { | |
996 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
997 | "disabling PIRQ%d\n", pin-16); | |
998 | } else { | |
999 | irq = pirq_entries[pin-16]; | |
1000 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1001 | "using PIRQ%d -> IRQ %d\n", | |
1002 | pin-16, irq); | |
1003 | } | |
1004 | } | |
1005 | } | |
54168ed7 IM |
1006 | #endif |
1007 | ||
1da177e4 LT |
1008 | return irq; |
1009 | } | |
1010 | ||
e20c06fd YL |
1011 | /* |
1012 | * Find a specific PCI IRQ entry. | |
1013 | * Not an __init, possibly needed by modules | |
1014 | */ | |
1015 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 1016 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 1017 | { |
79598505 | 1018 | int irq, i, best_guess = -1; |
e20c06fd YL |
1019 | |
1020 | apic_printk(APIC_DEBUG, | |
1021 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1022 | bus, slot, pin); | |
1023 | if (test_bit(bus, mp_bus_not_pci)) { | |
1024 | apic_printk(APIC_VERBOSE, | |
1025 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1026 | return -1; | |
1027 | } | |
79598505 | 1028 | |
e20c06fd YL |
1029 | for (i = 0; i < mp_irq_entries; i++) { |
1030 | int lbus = mp_irqs[i].srcbus; | |
79598505 JL |
1031 | int ioapic_idx, found = 0; |
1032 | ||
1033 | if (bus != lbus || mp_irqs[i].irqtype != mp_INT || | |
1034 | slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f)) | |
1035 | continue; | |
e20c06fd | 1036 | |
f44d1692 | 1037 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1038 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
79598505 JL |
1039 | mp_irqs[i].dstapic == MP_APIC_ALL) { |
1040 | found = 1; | |
e20c06fd | 1041 | break; |
e20c06fd | 1042 | } |
79598505 JL |
1043 | if (!found) |
1044 | continue; | |
1045 | ||
1046 | /* Skip ISA IRQs */ | |
1047 | irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); | |
1048 | if (ioapic_idx == 0 && !IO_APIC_IRQ(irq)) | |
1049 | continue; | |
1050 | ||
1051 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
1052 | set_io_apic_irq_attr(irq_attr, ioapic_idx, | |
1053 | mp_irqs[i].dstirq, | |
1054 | irq_trigger(i), | |
1055 | irq_polarity(i)); | |
1056 | return irq; | |
1057 | } | |
1058 | /* | |
1059 | * Use the first all-but-pin matching entry as a | |
1060 | * best-guess fuzzy result for broken mptables. | |
1061 | */ | |
1062 | if (best_guess < 0) { | |
1063 | set_io_apic_irq_attr(irq_attr, ioapic_idx, | |
1064 | mp_irqs[i].dstirq, | |
1065 | irq_trigger(i), | |
1066 | irq_polarity(i)); | |
1067 | best_guess = irq; | |
e20c06fd YL |
1068 | } |
1069 | } | |
1070 | return best_guess; | |
1071 | } | |
1072 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1073 | ||
497c9a19 YL |
1074 | void lock_vector_lock(void) |
1075 | { | |
1076 | /* Used to the online set of cpus does not change | |
1077 | * during assign_irq_vector. | |
1078 | */ | |
dade7716 | 1079 | raw_spin_lock(&vector_lock); |
497c9a19 | 1080 | } |
1da177e4 | 1081 | |
497c9a19 | 1082 | void unlock_vector_lock(void) |
1da177e4 | 1083 | { |
dade7716 | 1084 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1085 | } |
1da177e4 | 1086 | |
e7986739 MT |
1087 | static int |
1088 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1089 | { |
047c8fdb YL |
1090 | /* |
1091 | * NOTE! The local APIC isn't very good at handling | |
1092 | * multiple interrupts at the same interrupt level. | |
1093 | * As the interrupt level is determined by taking the | |
1094 | * vector number and shifting that right by 4, we | |
1095 | * want to spread these out a bit so that they don't | |
1096 | * all fall in the same interrupt level. | |
1097 | * | |
1098 | * Also, we've got to be careful not to trash gate | |
1099 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1100 | */ | |
6579b474 | 1101 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1bccd58b | 1102 | static int current_offset = VECTOR_OFFSET_START % 16; |
22f65d31 MT |
1103 | int cpu, err; |
1104 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1105 | |
23359a88 | 1106 | if (cfg->move_in_progress) |
54168ed7 | 1107 | return -EBUSY; |
0a1ad60d | 1108 | |
22f65d31 MT |
1109 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1110 | return -ENOMEM; | |
ace80ab7 | 1111 | |
e7986739 | 1112 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 | 1113 | err = -ENOSPC; |
b39f25a8 SS |
1114 | cpumask_clear(cfg->old_domain); |
1115 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
1116 | while (cpu < nr_cpu_ids) { | |
1ac322d0 | 1117 | int new_cpu, vector, offset; |
497c9a19 | 1118 | |
1ac322d0 | 1119 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
497c9a19 | 1120 | |
332afa65 | 1121 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
1ac322d0 SS |
1122 | err = 0; |
1123 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
1124 | break; | |
1125 | /* | |
1126 | * New cpumask using the vector is a proper subset of | |
1127 | * the current in use mask. So cleanup the vector | |
1128 | * allocation for the members that are not used anymore. | |
1129 | */ | |
1130 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
29c574c0 SS |
1131 | cfg->move_in_progress = |
1132 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
1ac322d0 SS |
1133 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); |
1134 | break; | |
332afa65 | 1135 | } |
497c9a19 | 1136 | |
54168ed7 IM |
1137 | vector = current_vector; |
1138 | offset = current_offset; | |
497c9a19 | 1139 | next: |
1bccd58b | 1140 | vector += 16; |
54168ed7 | 1141 | if (vector >= first_system_vector) { |
1bccd58b | 1142 | offset = (offset + 1) % 16; |
6579b474 | 1143 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 | 1144 | } |
8637e38a AG |
1145 | |
1146 | if (unlikely(current_vector == vector)) { | |
b39f25a8 SS |
1147 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
1148 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
1149 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
54168ed7 | 1150 | continue; |
8637e38a | 1151 | } |
b77b881f YL |
1152 | |
1153 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1154 | goto next; |
b77b881f | 1155 | |
9345005f PB |
1156 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { |
1157 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) | |
54168ed7 | 1158 | goto next; |
9345005f | 1159 | } |
54168ed7 IM |
1160 | /* Found one! */ |
1161 | current_vector = vector; | |
1162 | current_offset = offset; | |
1ac322d0 | 1163 | if (cfg->vector) { |
22f65d31 | 1164 | cpumask_copy(cfg->old_domain, cfg->domain); |
29c574c0 SS |
1165 | cfg->move_in_progress = |
1166 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
7a959cff | 1167 | } |
22f65d31 | 1168 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1169 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1170 | cfg->vector = vector; | |
22f65d31 MT |
1171 | cpumask_copy(cfg->domain, tmp_mask); |
1172 | err = 0; | |
1173 | break; | |
54168ed7 | 1174 | } |
22f65d31 MT |
1175 | free_cpumask_var(tmp_mask); |
1176 | return err; | |
497c9a19 YL |
1177 | } |
1178 | ||
9338ad6f | 1179 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1180 | { |
1181 | int err; | |
ace80ab7 | 1182 | unsigned long flags; |
ace80ab7 | 1183 | |
dade7716 | 1184 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1185 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1186 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1187 | return err; |
1188 | } | |
1189 | ||
3145e941 | 1190 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1191 | { |
497c9a19 YL |
1192 | int cpu, vector; |
1193 | ||
497c9a19 YL |
1194 | BUG_ON(!cfg->vector); |
1195 | ||
1196 | vector = cfg->vector; | |
1d44b30f | 1197 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
9345005f | 1198 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
497c9a19 YL |
1199 | |
1200 | cfg->vector = 0; | |
22f65d31 | 1201 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1202 | |
1203 | if (likely(!cfg->move_in_progress)) | |
1204 | return; | |
1d44b30f | 1205 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
9345005f | 1206 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
0ca4b6b0 MW |
1207 | if (per_cpu(vector_irq, cpu)[vector] != irq) |
1208 | continue; | |
9345005f | 1209 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
0ca4b6b0 MW |
1210 | break; |
1211 | } | |
1212 | } | |
1213 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1214 | } |
1215 | ||
1216 | void __setup_vector_irq(int cpu) | |
1217 | { | |
1218 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1219 | int irq, vector; |
1220 | struct irq_cfg *cfg; | |
1221 | ||
9d133e5d SS |
1222 | /* |
1223 | * vector_lock will make sure that we don't run into irq vector | |
1224 | * assignments that might be happening on another cpu in parallel, | |
1225 | * while we setup our initial vector to irq mappings. | |
1226 | */ | |
dade7716 | 1227 | raw_spin_lock(&vector_lock); |
497c9a19 | 1228 | /* Mark the inuse vectors */ |
ad9f4334 | 1229 | for_each_active_irq(irq) { |
32f5ef5d | 1230 | cfg = irq_cfg(irq); |
ad9f4334 TG |
1231 | if (!cfg) |
1232 | continue; | |
36e9e1ea | 1233 | |
22f65d31 | 1234 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1235 | continue; |
1236 | vector = cfg->vector; | |
497c9a19 YL |
1237 | per_cpu(vector_irq, cpu)[vector] = irq; |
1238 | } | |
1239 | /* Mark the free vectors */ | |
1240 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1241 | irq = per_cpu(vector_irq, cpu)[vector]; | |
9345005f | 1242 | if (irq <= VECTOR_UNDEFINED) |
497c9a19 YL |
1243 | continue; |
1244 | ||
1245 | cfg = irq_cfg(irq); | |
22f65d31 | 1246 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
9345005f | 1247 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
54168ed7 | 1248 | } |
dade7716 | 1249 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1250 | } |
3fde6900 | 1251 | |
f5b9ed7a | 1252 | static struct irq_chip ioapic_chip; |
1da177e4 | 1253 | |
047c8fdb | 1254 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1255 | static inline int IO_APIC_irq_trigger(int irq) |
1256 | { | |
d6c88a50 | 1257 | int apic, idx, pin; |
1d025192 | 1258 | |
f44d1692 JL |
1259 | for_each_ioapic_pin(apic, pin) { |
1260 | idx = find_irq_entry(apic, pin, mp_INT); | |
1261 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1262 | return irq_trigger(idx); | |
d6c88a50 TG |
1263 | } |
1264 | /* | |
54168ed7 IM |
1265 | * nonexistent IRQs are edge default |
1266 | */ | |
d6c88a50 | 1267 | return 0; |
1d025192 | 1268 | } |
047c8fdb YL |
1269 | #else |
1270 | static inline int IO_APIC_irq_trigger(int irq) | |
1271 | { | |
54168ed7 | 1272 | return 1; |
047c8fdb YL |
1273 | } |
1274 | #endif | |
1d025192 | 1275 | |
1a0e62a4 TG |
1276 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1277 | unsigned long trigger) | |
1da177e4 | 1278 | { |
c60eaf25 TG |
1279 | struct irq_chip *chip = &ioapic_chip; |
1280 | irq_flow_handler_t hdl; | |
1281 | bool fasteoi; | |
199751d7 | 1282 | |
6ebcc00e | 1283 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1284 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1285 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1286 | fasteoi = true; |
1287 | } else { | |
60c69948 | 1288 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1289 | fasteoi = false; |
1290 | } | |
047c8fdb | 1291 | |
2976fd84 | 1292 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1293 | fasteoi = trigger != 0; |
29b61be6 | 1294 | |
c60eaf25 TG |
1295 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1296 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1297 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1298 | } |
1299 | ||
a6a25dd3 JR |
1300 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1301 | unsigned int destination, int vector, | |
1302 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1303 | { |
c5b4712c YL |
1304 | memset(entry, 0, sizeof(*entry)); |
1305 | ||
1306 | entry->delivery_mode = apic->irq_delivery_mode; | |
1307 | entry->dest_mode = apic->irq_dest_mode; | |
1308 | entry->dest = destination; | |
1309 | entry->vector = vector; | |
1310 | entry->mask = 0; /* enable IRQ */ | |
1311 | entry->trigger = attr->trigger; | |
1312 | entry->polarity = attr->polarity; | |
1313 | ||
1314 | /* | |
1315 | * Mask level triggered irqs. | |
497c9a19 YL |
1316 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1317 | */ | |
c5b4712c | 1318 | if (attr->trigger) |
497c9a19 | 1319 | entry->mask = 1; |
c5b4712c | 1320 | |
497c9a19 YL |
1321 | return 0; |
1322 | } | |
1323 | ||
e4aff811 YL |
1324 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1325 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1326 | { |
1da177e4 | 1327 | struct IO_APIC_route_entry entry; |
22f65d31 | 1328 | unsigned int dest; |
497c9a19 YL |
1329 | |
1330 | if (!IO_APIC_IRQ(irq)) | |
1331 | return; | |
f1c63001 | 1332 | |
fe402e1f | 1333 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1334 | return; |
1335 | ||
ff164324 AG |
1336 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1337 | &dest)) { | |
1338 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1339 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
1340 | __clear_irq_vector(irq, cfg); | |
1341 | ||
1342 | return; | |
1343 | } | |
497c9a19 YL |
1344 | |
1345 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1346 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1347 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1348 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1349 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1350 | |
a6a25dd3 JR |
1351 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1352 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1353 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
3145e941 | 1354 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1355 | |
497c9a19 YL |
1356 | return; |
1357 | } | |
1358 | ||
e4aff811 | 1359 | ioapic_register_intr(irq, cfg, attr->trigger); |
b81bb373 | 1360 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1361 | legacy_pic->mask(irq); |
497c9a19 | 1362 | |
e4aff811 | 1363 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1364 | } |
1365 | ||
6f50d45f | 1366 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
c8d6b8fe TG |
1367 | { |
1368 | if (idx != -1) | |
1369 | return false; | |
1370 | ||
1371 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
6f50d45f | 1372 | mpc_ioapic_id(ioapic_idx), pin); |
c8d6b8fe TG |
1373 | return true; |
1374 | } | |
1375 | ||
6f50d45f | 1376 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
497c9a19 | 1377 | { |
ed972ccf | 1378 | int idx, node = cpu_to_node(0); |
2d57e37d | 1379 | struct io_apic_irq_attr attr; |
ed972ccf | 1380 | unsigned int pin, irq; |
1da177e4 | 1381 | |
f44d1692 | 1382 | for_each_pin(ioapic_idx, pin) { |
6f50d45f YL |
1383 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); |
1384 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) | |
b9c61b70 | 1385 | continue; |
33a201fa | 1386 | |
6f50d45f | 1387 | irq = pin_2_irq(idx, ioapic_idx, pin); |
18e48551 | 1388 | if (!mp_init_irq_at_boot(ioapic_idx, irq)) |
fad53995 EB |
1389 | continue; |
1390 | ||
b9c61b70 YL |
1391 | /* |
1392 | * Skip the timer IRQ if there's a quirk handler | |
1393 | * installed and if it returns 1: | |
1394 | */ | |
1395 | if (apic->multi_timer_check && | |
6f50d45f | 1396 | apic->multi_timer_check(ioapic_idx, irq)) |
b9c61b70 | 1397 | continue; |
36062448 | 1398 | |
6f50d45f | 1399 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
2d57e37d | 1400 | irq_polarity(idx)); |
fbc6bff0 | 1401 | |
2d57e37d | 1402 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1403 | } |
1da177e4 LT |
1404 | } |
1405 | ||
ed972ccf TG |
1406 | static void __init setup_IO_APIC_irqs(void) |
1407 | { | |
6f50d45f | 1408 | unsigned int ioapic_idx; |
ed972ccf TG |
1409 | |
1410 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1411 | ||
f44d1692 | 1412 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1413 | __io_apic_setup_irqs(ioapic_idx); |
ed972ccf TG |
1414 | } |
1415 | ||
18dce6ba | 1416 | /* |
3eb2be5f | 1417 | * for the gsi that is not in first ioapic |
18dce6ba YL |
1418 | * but could not use acpi_register_gsi() |
1419 | * like some special sci in IBM x3330 | |
1420 | */ | |
1421 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1422 | { | |
6f50d45f | 1423 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1424 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1425 | |
1426 | /* | |
1427 | * Convert 'gsi' to 'ioapic.pin'. | |
1428 | */ | |
6f50d45f YL |
1429 | ioapic_idx = mp_find_ioapic(gsi); |
1430 | if (ioapic_idx < 0) | |
18dce6ba YL |
1431 | return; |
1432 | ||
6f50d45f YL |
1433 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
1434 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
18dce6ba YL |
1435 | if (idx == -1) |
1436 | return; | |
1437 | ||
6f50d45f | 1438 | irq = pin_2_irq(idx, ioapic_idx, pin); |
18e48551 | 1439 | if (mp_init_irq_at_boot(ioapic_idx, irq)) |
18dce6ba | 1440 | return; |
fe6dab4e | 1441 | |
6f50d45f | 1442 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
da1ad9d7 TG |
1443 | irq_polarity(idx)); |
1444 | ||
710dcda6 | 1445 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1446 | } |
1447 | ||
1da177e4 | 1448 | /* |
f7633ce5 | 1449 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1450 | */ |
6f50d45f | 1451 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1452 | unsigned int pin, int vector) |
1da177e4 LT |
1453 | { |
1454 | struct IO_APIC_route_entry entry; | |
ff164324 | 1455 | unsigned int dest; |
1da177e4 | 1456 | |
36062448 | 1457 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1458 | |
1459 | /* | |
1460 | * We use logical delivery to get the timer IRQ | |
1461 | * to the first CPU. | |
1462 | */ | |
a5a39156 AG |
1463 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1464 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1465 | dest = BAD_APICID; |
1466 | ||
9b5bc8dc | 1467 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1468 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1469 | entry.dest = dest; |
9b5bc8dc | 1470 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1471 | entry.polarity = 0; |
1472 | entry.trigger = 0; | |
1473 | entry.vector = vector; | |
1474 | ||
1475 | /* | |
1476 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1477 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1478 | */ |
2c778651 TG |
1479 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1480 | "edge"); | |
1da177e4 LT |
1481 | |
1482 | /* | |
1483 | * Add it to the IO-APIC irq-routing table: | |
1484 | */ | |
6f50d45f | 1485 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1486 | } |
1487 | ||
afcc8a40 JR |
1488 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1489 | { | |
1490 | int i; | |
1491 | ||
1492 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1493 | ||
1494 | for (i = 0; i <= nr_entries; i++) { | |
1495 | struct IO_APIC_route_entry entry; | |
1496 | ||
1497 | entry = ioapic_read_entry(apic, i); | |
1498 | ||
1499 | pr_debug(" %02x %02X ", i, entry.dest); | |
1500 | pr_cont("%1d %1d %1d %1d %1d " | |
1501 | "%1d %1d %02X\n", | |
1502 | entry.mask, | |
1503 | entry.trigger, | |
1504 | entry.irr, | |
1505 | entry.polarity, | |
1506 | entry.delivery_status, | |
1507 | entry.dest_mode, | |
1508 | entry.delivery_mode, | |
1509 | entry.vector); | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1514 | unsigned int nr_entries) | |
1da177e4 | 1515 | { |
cda417dd | 1516 | int i; |
afcc8a40 JR |
1517 | |
1518 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1519 | ||
1520 | for (i = 0; i <= nr_entries; i++) { | |
1521 | struct IR_IO_APIC_route_entry *ir_entry; | |
1522 | struct IO_APIC_route_entry entry; | |
1523 | ||
1524 | entry = ioapic_read_entry(apic, i); | |
1525 | ||
1526 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1527 | ||
1528 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1529 | pr_cont("%1d %1d %1d %1d %1d " | |
1530 | "%1d %1d %X %02X\n", | |
1531 | ir_entry->format, | |
1532 | ir_entry->mask, | |
1533 | ir_entry->trigger, | |
1534 | ir_entry->irr, | |
1535 | ir_entry->polarity, | |
1536 | ir_entry->delivery_status, | |
1537 | ir_entry->index2, | |
1538 | ir_entry->zero, | |
1539 | ir_entry->vector); | |
1540 | } | |
1541 | } | |
1542 | ||
17405453 YY |
1543 | void ioapic_zap_locks(void) |
1544 | { | |
1545 | raw_spin_lock_init(&ioapic_lock); | |
1546 | } | |
1547 | ||
afcc8a40 JR |
1548 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1549 | { | |
1da177e4 LT |
1550 | union IO_APIC_reg_00 reg_00; |
1551 | union IO_APIC_reg_01 reg_01; | |
1552 | union IO_APIC_reg_02 reg_02; | |
1553 | union IO_APIC_reg_03 reg_03; | |
1554 | unsigned long flags; | |
1da177e4 | 1555 | |
dade7716 | 1556 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1557 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1558 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1559 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1560 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1561 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1562 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1563 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1564 | |
6f50d45f | 1565 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1566 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1567 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1568 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1569 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1570 | |
54168ed7 | 1571 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1572 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1573 | reg_01.bits.entries); | |
1da177e4 LT |
1574 | |
1575 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1576 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1577 | reg_01.bits.version); | |
1da177e4 LT |
1578 | |
1579 | /* | |
1580 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1581 | * but the value of reg_02 is read as the previous read register | |
1582 | * value, so ignore it if reg_02 == reg_01. | |
1583 | */ | |
1584 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1585 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1586 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1587 | } |
1588 | ||
1589 | /* | |
1590 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1591 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1592 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1593 | */ | |
1594 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1595 | reg_03.raw != reg_01.raw) { | |
1596 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1597 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1598 | } |
1599 | ||
1600 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1601 | ||
afcc8a40 | 1602 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1603 | } |
1604 | ||
1605 | __apicdebuginit(void) print_IO_APICs(void) | |
1606 | { | |
6f50d45f | 1607 | int ioapic_idx; |
cda417dd YL |
1608 | struct irq_cfg *cfg; |
1609 | unsigned int irq; | |
6fd36ba0 | 1610 | struct irq_chip *chip; |
cda417dd YL |
1611 | |
1612 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1613 | for_each_ioapic(ioapic_idx) |
cda417dd | 1614 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1615 | mpc_ioapic_id(ioapic_idx), |
1616 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1617 | |
1618 | /* | |
1619 | * We are a bit conservative about what we expect. We have to | |
1620 | * know about every hardware change ASAP. | |
1621 | */ | |
1622 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1623 | ||
f44d1692 | 1624 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1625 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1626 | |
1da177e4 | 1627 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1628 | for_each_active_irq(irq) { |
0b8f1efa YL |
1629 | struct irq_pin_list *entry; |
1630 | ||
6fd36ba0 MN |
1631 | chip = irq_get_chip(irq); |
1632 | if (chip != &ioapic_chip) | |
1633 | continue; | |
1634 | ||
32f5ef5d | 1635 | cfg = irq_cfg(irq); |
05e40760 DK |
1636 | if (!cfg) |
1637 | continue; | |
0b8f1efa | 1638 | entry = cfg->irq_2_pin; |
0f978f45 | 1639 | if (!entry) |
1da177e4 | 1640 | continue; |
8f09cd20 | 1641 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1642 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1643 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1644 | pr_cont("\n"); | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1648 | } |
1649 | ||
251e1e44 | 1650 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1651 | { |
251e1e44 | 1652 | int i; |
1da177e4 | 1653 | |
251e1e44 IM |
1654 | printk(KERN_DEBUG); |
1655 | ||
1656 | for (i = 0; i < 8; i++) | |
c767a54b | 1657 | pr_cont("%08x", apic_read(base + i*0x10)); |
251e1e44 | 1658 | |
c767a54b | 1659 | pr_cont("\n"); |
1da177e4 LT |
1660 | } |
1661 | ||
32f71aff | 1662 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1663 | { |
97a52714 | 1664 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1665 | u64 icr; |
1da177e4 | 1666 | |
251e1e44 | 1667 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1668 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1669 | v = apic_read(APIC_ID); |
54168ed7 | 1670 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1671 | v = apic_read(APIC_LVR); |
1672 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1673 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1674 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1675 | |
1676 | v = apic_read(APIC_TASKPRI); | |
1677 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1678 | ||
54168ed7 | 1679 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1680 | if (!APIC_XAPIC(ver)) { |
1681 | v = apic_read(APIC_ARBPRI); | |
1682 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1683 | v & APIC_ARBPRI_MASK); | |
1684 | } | |
1da177e4 LT |
1685 | v = apic_read(APIC_PROCPRI); |
1686 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1687 | } | |
1688 | ||
a11b5abe YL |
1689 | /* |
1690 | * Remote read supported only in the 82489DX and local APIC for | |
1691 | * Pentium processors. | |
1692 | */ | |
1693 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1694 | v = apic_read(APIC_RRR); | |
1695 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1696 | } | |
1697 | ||
1da177e4 LT |
1698 | v = apic_read(APIC_LDR); |
1699 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1700 | if (!x2apic_enabled()) { |
1701 | v = apic_read(APIC_DFR); | |
1702 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1703 | } | |
1da177e4 LT |
1704 | v = apic_read(APIC_SPIV); |
1705 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1706 | ||
1707 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1708 | print_APIC_field(APIC_ISR); |
1da177e4 | 1709 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1710 | print_APIC_field(APIC_TMR); |
1da177e4 | 1711 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1712 | print_APIC_field(APIC_IRR); |
1da177e4 | 1713 | |
54168ed7 IM |
1714 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1715 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1716 | apic_write(APIC_ESR, 0); |
54168ed7 | 1717 | |
1da177e4 LT |
1718 | v = apic_read(APIC_ESR); |
1719 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1720 | } | |
1721 | ||
7ab6af7a | 1722 | icr = apic_icr_read(); |
0c425cec IM |
1723 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1724 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1725 | |
1726 | v = apic_read(APIC_LVTT); | |
1727 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1728 | ||
1729 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1730 | v = apic_read(APIC_LVTPC); | |
1731 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1732 | } | |
1733 | v = apic_read(APIC_LVT0); | |
1734 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1735 | v = apic_read(APIC_LVT1); | |
1736 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1737 | ||
1738 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1739 | v = apic_read(APIC_LVTERR); | |
1740 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1741 | } | |
1742 | ||
1743 | v = apic_read(APIC_TMICT); | |
1744 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1745 | v = apic_read(APIC_TMCCT); | |
1746 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1747 | v = apic_read(APIC_TDCR); | |
1748 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1749 | |
1750 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1751 | v = apic_read(APIC_EFEAT); | |
1752 | maxlvt = (v >> 16) & 0xff; | |
1753 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1754 | v = apic_read(APIC_ECTRL); | |
1755 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1756 | for (i = 0; i < maxlvt; i++) { | |
1757 | v = apic_read(APIC_EILVTn(i)); | |
1758 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1759 | } | |
1760 | } | |
c767a54b | 1761 | pr_cont("\n"); |
1da177e4 LT |
1762 | } |
1763 | ||
2626eb2b | 1764 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1765 | { |
ffd5aae7 YL |
1766 | int cpu; |
1767 | ||
2626eb2b CG |
1768 | if (!maxcpu) |
1769 | return; | |
1770 | ||
ffd5aae7 | 1771 | preempt_disable(); |
2626eb2b CG |
1772 | for_each_online_cpu(cpu) { |
1773 | if (cpu >= maxcpu) | |
1774 | break; | |
ffd5aae7 | 1775 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1776 | } |
ffd5aae7 | 1777 | preempt_enable(); |
1da177e4 LT |
1778 | } |
1779 | ||
32f71aff | 1780 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1781 | { |
1da177e4 LT |
1782 | unsigned int v; |
1783 | unsigned long flags; | |
1784 | ||
b81bb373 | 1785 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1786 | return; |
1787 | ||
1788 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1789 | ||
5619c280 | 1790 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1791 | |
1792 | v = inb(0xa1) << 8 | inb(0x21); | |
1793 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1794 | ||
1795 | v = inb(0xa0) << 8 | inb(0x20); | |
1796 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1797 | ||
54168ed7 IM |
1798 | outb(0x0b,0xa0); |
1799 | outb(0x0b,0x20); | |
1da177e4 | 1800 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1801 | outb(0x0a,0xa0); |
1802 | outb(0x0a,0x20); | |
1da177e4 | 1803 | |
5619c280 | 1804 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1805 | |
1806 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1807 | ||
1808 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1809 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1810 | } | |
1811 | ||
2626eb2b CG |
1812 | static int __initdata show_lapic = 1; |
1813 | static __init int setup_show_lapic(char *arg) | |
1814 | { | |
1815 | int num = -1; | |
1816 | ||
1817 | if (strcmp(arg, "all") == 0) { | |
1818 | show_lapic = CONFIG_NR_CPUS; | |
1819 | } else { | |
1820 | get_option(&arg, &num); | |
1821 | if (num >= 0) | |
1822 | show_lapic = num; | |
1823 | } | |
1824 | ||
1825 | return 1; | |
1826 | } | |
1827 | __setup("show_lapic=", setup_show_lapic); | |
1828 | ||
1829 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1830 | { |
2626eb2b CG |
1831 | if (apic_verbosity == APIC_QUIET) |
1832 | return 0; | |
1833 | ||
32f71aff | 1834 | print_PIC(); |
4797f6b0 YL |
1835 | |
1836 | /* don't print out if apic is not there */ | |
8312136f | 1837 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1838 | return 0; |
1839 | ||
2626eb2b | 1840 | print_local_APICs(show_lapic); |
cda417dd | 1841 | print_IO_APICs(); |
32f71aff MR |
1842 | |
1843 | return 0; | |
1844 | } | |
1845 | ||
ded1f6ab | 1846 | late_initcall(print_ICs); |
32f71aff | 1847 | |
1da177e4 | 1848 | |
efa2559f YL |
1849 | /* Where if anywhere is the i8259 connect in external int mode */ |
1850 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1851 | ||
54168ed7 | 1852 | void __init enable_IO_APIC(void) |
1da177e4 | 1853 | { |
fcfd636a | 1854 | int i8259_apic, i8259_pin; |
f44d1692 | 1855 | int apic, pin; |
bc07844a | 1856 | |
b81bb373 | 1857 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1858 | return; |
1859 | ||
f44d1692 | 1860 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1861 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1862 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1863 | |
f44d1692 JL |
1864 | /* If the interrupt line is enabled and in ExtInt mode |
1865 | * I have found the pin where the i8259 is connected. | |
1866 | */ | |
1867 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1868 | ioapic_i8259.apic = apic; | |
1869 | ioapic_i8259.pin = pin; | |
1870 | goto found_i8259; | |
fcfd636a EB |
1871 | } |
1872 | } | |
1873 | found_i8259: | |
1874 | /* Look to see what if the MP table has reported the ExtINT */ | |
1875 | /* If we could not find the appropriate pin by looking at the ioapic | |
1876 | * the i8259 probably is not connected the ioapic but give the | |
1877 | * mptable a chance anyway. | |
1878 | */ | |
1879 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1880 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1881 | /* Trust the MP table if nothing is setup in the hardware */ | |
1882 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1883 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1884 | ioapic_i8259.pin = i8259_pin; | |
1885 | ioapic_i8259.apic = i8259_apic; | |
1886 | } | |
1887 | /* Complain if the MP table and the hardware disagree */ | |
1888 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1889 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1890 | { | |
1891 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1892 | } |
1893 | ||
1894 | /* | |
1895 | * Do not trust the IO-APIC being empty at bootup | |
1896 | */ | |
1897 | clear_IO_APIC(); | |
1898 | } | |
1899 | ||
1c4248ca | 1900 | void native_disable_io_apic(void) |
1da177e4 | 1901 | { |
650927ef | 1902 | /* |
0b968d23 | 1903 | * If the i8259 is routed through an IOAPIC |
650927ef | 1904 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1905 | * so legacy interrupts can be delivered. |
650927ef | 1906 | */ |
1c4248ca | 1907 | if (ioapic_i8259.pin != -1) { |
650927ef | 1908 | struct IO_APIC_route_entry entry; |
650927ef EB |
1909 | |
1910 | memset(&entry, 0, sizeof(entry)); | |
1911 | entry.mask = 0; /* Enabled */ | |
1912 | entry.trigger = 0; /* Edge */ | |
1913 | entry.irr = 0; | |
1914 | entry.polarity = 0; /* High */ | |
1915 | entry.delivery_status = 0; | |
1916 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1917 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1918 | entry.vector = 0; |
54168ed7 | 1919 | entry.dest = read_apic_id(); |
650927ef EB |
1920 | |
1921 | /* | |
1922 | * Add it to the IO-APIC irq-routing table: | |
1923 | */ | |
cf4c6a2f | 1924 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1925 | } |
54168ed7 | 1926 | |
1c4248ca JR |
1927 | if (cpu_has_apic || apic_from_smp_config()) |
1928 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1929 | ||
1930 | } | |
1931 | ||
1932 | /* | |
1933 | * Not an __init, needed by the reboot code | |
1934 | */ | |
1935 | void disable_IO_APIC(void) | |
1936 | { | |
7c6d9f97 | 1937 | /* |
1c4248ca | 1938 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1939 | */ |
1c4248ca JR |
1940 | clear_IO_APIC(); |
1941 | ||
1942 | if (!legacy_pic->nr_legacy_irqs) | |
1943 | return; | |
1944 | ||
1945 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1946 | } |
1947 | ||
54168ed7 | 1948 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1949 | /* |
1950 | * function to set the IO-APIC physical IDs based on the | |
1951 | * values stored in the MPC table. | |
1952 | * | |
1953 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1954 | */ | |
a38c5380 | 1955 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1956 | { |
1957 | union IO_APIC_reg_00 reg_00; | |
1958 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1959 | int ioapic_idx; |
1da177e4 LT |
1960 | int i; |
1961 | unsigned char old_id; | |
1962 | unsigned long flags; | |
1963 | ||
1964 | /* | |
1965 | * This is broken; anything with a real cpu count has to | |
1966 | * circumvent this idiocy regardless. | |
1967 | */ | |
7abc0753 | 1968 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1969 | |
1970 | /* | |
1971 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1972 | */ | |
f44d1692 | 1973 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1974 | /* Read the register 0 value */ |
dade7716 | 1975 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1976 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1977 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1978 | |
6f50d45f | 1979 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1980 | |
6f50d45f | 1981 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1982 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1983 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1984 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1985 | reg_00.bits.ID); | |
6f50d45f | 1986 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1987 | } |
1988 | ||
1da177e4 LT |
1989 | /* |
1990 | * Sanity check, is the ID really free? Every APIC in a | |
1991 | * system must have a unique ID or we get lots of nice | |
1992 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1993 | */ | |
7abc0753 | 1994 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1995 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1996 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1997 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1998 | for (i = 0; i < get_physical_broadcast(); i++) |
1999 | if (!physid_isset(i, phys_id_present_map)) | |
2000 | break; | |
2001 | if (i >= get_physical_broadcast()) | |
2002 | panic("Max APIC ID exceeded!\n"); | |
2003 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2004 | i); | |
2005 | physid_set(i, phys_id_present_map); | |
6f50d45f | 2006 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
2007 | } else { |
2008 | physid_mask_t tmp; | |
6f50d45f | 2009 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 2010 | &tmp); |
1da177e4 LT |
2011 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2012 | "phys_id_present_map\n", | |
6f50d45f | 2013 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
2014 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2015 | } | |
2016 | ||
1da177e4 LT |
2017 | /* |
2018 | * We need to adjust the IRQ routing table | |
2019 | * if the ID changed. | |
2020 | */ | |
6f50d45f | 2021 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2022 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2023 | if (mp_irqs[i].dstapic == old_id) |
2024 | mp_irqs[i].dstapic | |
6f50d45f | 2025 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2026 | |
2027 | /* | |
60d79fd9 YL |
2028 | * Update the ID register according to the right value |
2029 | * from the MPC table if they are different. | |
36062448 | 2030 | */ |
6f50d45f | 2031 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2032 | continue; |
2033 | ||
1da177e4 LT |
2034 | apic_printk(APIC_VERBOSE, KERN_INFO |
2035 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2036 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2037 | |
6f50d45f | 2038 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2039 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2040 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2041 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2042 | |
2043 | /* | |
2044 | * Sanity check | |
2045 | */ | |
dade7716 | 2046 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2047 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2048 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2049 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 2050 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
2051 | else |
2052 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2053 | } | |
2054 | } | |
a38c5380 SAS |
2055 | |
2056 | void __init setup_ioapic_ids_from_mpc(void) | |
2057 | { | |
2058 | ||
2059 | if (acpi_ioapic) | |
2060 | return; | |
2061 | /* | |
2062 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2063 | * no meaning without the serial APIC bus. | |
2064 | */ | |
2065 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2066 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2067 | return; | |
2068 | setup_ioapic_ids_from_mpc_nocheck(); | |
2069 | } | |
54168ed7 | 2070 | #endif |
1da177e4 | 2071 | |
7ce0bcfd | 2072 | int no_timer_check __initdata; |
8542b200 ZA |
2073 | |
2074 | static int __init notimercheck(char *s) | |
2075 | { | |
2076 | no_timer_check = 1; | |
2077 | return 1; | |
2078 | } | |
2079 | __setup("no_timer_check", notimercheck); | |
2080 | ||
1da177e4 LT |
2081 | /* |
2082 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2083 | * about the timer IRQ. We do the following to work around the situation: | |
2084 | * | |
2085 | * - timer IRQ defaults to IO-APIC IRQ | |
2086 | * - if this function detects that timer IRQs are defunct, then we fall | |
2087 | * back to ISA timer IRQs | |
2088 | */ | |
f0a7a5c9 | 2089 | static int __init timer_irq_works(void) |
1da177e4 LT |
2090 | { |
2091 | unsigned long t1 = jiffies; | |
4aae0702 | 2092 | unsigned long flags; |
1da177e4 | 2093 | |
8542b200 ZA |
2094 | if (no_timer_check) |
2095 | return 1; | |
2096 | ||
4aae0702 | 2097 | local_save_flags(flags); |
1da177e4 LT |
2098 | local_irq_enable(); |
2099 | /* Let ten ticks pass... */ | |
2100 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2101 | local_irq_restore(flags); |
1da177e4 LT |
2102 | |
2103 | /* | |
2104 | * Expect a few ticks at least, to be sure some possible | |
2105 | * glue logic does not lock up after one or two first | |
2106 | * ticks in a non-ExtINT mode. Also the local APIC | |
2107 | * might have cached one ExtINT interrupt. Finally, at | |
2108 | * least one tick may be lost due to delays. | |
2109 | */ | |
54168ed7 IM |
2110 | |
2111 | /* jiffies wrap? */ | |
1d16b53e | 2112 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2113 | return 1; |
1da177e4 LT |
2114 | return 0; |
2115 | } | |
2116 | ||
2117 | /* | |
2118 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2119 | * number of pending IRQ events unhandled. These cases are very rare, | |
2120 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2121 | * better to do it this way as thus we do not have to be aware of | |
2122 | * 'pending' interrupts in the IRQ path, except at this point. | |
2123 | */ | |
2124 | /* | |
2125 | * Edge triggered needs to resend any interrupt | |
2126 | * that was delayed but this is now handled in the device | |
2127 | * independent code. | |
2128 | */ | |
2129 | ||
2130 | /* | |
2131 | * Starting up a edge-triggered IO-APIC interrupt is | |
2132 | * nasty - we need to make sure that we get the edge. | |
2133 | * If it is already asserted for some reason, we need | |
2134 | * return 1 to indicate that is was pending. | |
2135 | * | |
2136 | * This is not complete - we should be able to fake | |
2137 | * an edge even if it isn't on the 8259A... | |
2138 | */ | |
54168ed7 | 2139 | |
61a38ce3 | 2140 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2141 | { |
61a38ce3 | 2142 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2143 | unsigned long flags; |
2144 | ||
dade7716 | 2145 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2146 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2147 | legacy_pic->mask(irq); |
b81bb373 | 2148 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2149 | was_pending = 1; |
2150 | } | |
61a38ce3 | 2151 | __unmask_ioapic(data->chip_data); |
dade7716 | 2152 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2153 | |
2154 | return was_pending; | |
2155 | } | |
2156 | ||
90297c5f | 2157 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2158 | { |
90297c5f | 2159 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 | 2160 | unsigned long flags; |
8d966a04 | 2161 | int cpu; |
54168ed7 | 2162 | |
dade7716 | 2163 | raw_spin_lock_irqsave(&vector_lock, flags); |
8d966a04 FY |
2164 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
2165 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
dade7716 | 2166 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2167 | |
2168 | return 1; | |
2169 | } | |
497c9a19 | 2170 | |
54168ed7 IM |
2171 | /* |
2172 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2173 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2174 | * handled with the level-triggered descriptor, but that one has slightly | |
2175 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2176 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2177 | * races. | |
2178 | */ | |
497c9a19 | 2179 | |
54168ed7 | 2180 | #ifdef CONFIG_SMP |
9338ad6f | 2181 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2182 | { |
2183 | cpumask_var_t cleanup_mask; | |
2184 | ||
2185 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2186 | unsigned int i; | |
e85abf8f GH |
2187 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2188 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2189 | } else { | |
2190 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2191 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2192 | free_cpumask_var(cleanup_mask); | |
2193 | } | |
2194 | cfg->move_in_progress = 0; | |
2195 | } | |
2196 | ||
2605fc21 | 2197 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
54168ed7 IM |
2198 | { |
2199 | unsigned vector, me; | |
8f2466f4 | 2200 | |
54168ed7 | 2201 | ack_APIC_irq(); |
54168ed7 | 2202 | irq_enter(); |
98ad1cc1 | 2203 | exit_idle(); |
54168ed7 IM |
2204 | |
2205 | me = smp_processor_id(); | |
2206 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
c7a730fa | 2207 | int irq; |
68a8ca59 | 2208 | unsigned int irr; |
54168ed7 IM |
2209 | struct irq_desc *desc; |
2210 | struct irq_cfg *cfg; | |
0a3aee0d | 2211 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2212 | |
9345005f | 2213 | if (irq <= VECTOR_UNDEFINED) |
0b8f1efa YL |
2214 | continue; |
2215 | ||
54168ed7 IM |
2216 | desc = irq_to_desc(irq); |
2217 | if (!desc) | |
2218 | continue; | |
2219 | ||
2220 | cfg = irq_cfg(irq); | |
94777fc5 DS |
2221 | if (!cfg) |
2222 | continue; | |
2223 | ||
239007b8 | 2224 | raw_spin_lock(&desc->lock); |
54168ed7 | 2225 | |
7f41c2e1 SS |
2226 | /* |
2227 | * Check if the irq migration is in progress. If so, we | |
2228 | * haven't received the cleanup request yet for this irq. | |
2229 | */ | |
2230 | if (cfg->move_in_progress) | |
2231 | goto unlock; | |
2232 | ||
22f65d31 | 2233 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2234 | goto unlock; |
2235 | ||
68a8ca59 SS |
2236 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2237 | /* | |
2238 | * Check if the vector that needs to be cleanedup is | |
2239 | * registered at the cpu's IRR. If so, then this is not | |
2240 | * the best time to clean it up. Lets clean it up in the | |
2241 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2242 | * to myself. | |
2243 | */ | |
2244 | if (irr & (1 << (vector % 32))) { | |
2245 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2246 | goto unlock; | |
2247 | } | |
3eb2be5f | 2248 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); |
54168ed7 | 2249 | unlock: |
239007b8 | 2250 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2251 | } |
2252 | ||
2253 | irq_exit(); | |
2254 | } | |
2255 | ||
dd5f15e5 | 2256 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2257 | { |
a5e74b84 | 2258 | unsigned me; |
54168ed7 | 2259 | |
fcef5911 | 2260 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2261 | return; |
2262 | ||
54168ed7 | 2263 | me = smp_processor_id(); |
10b888d6 | 2264 | |
fcef5911 | 2265 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2266 | send_cleanup_vector(cfg); |
497c9a19 | 2267 | } |
a5e74b84 | 2268 | |
dd5f15e5 | 2269 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2270 | { |
dd5f15e5 | 2271 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2272 | } |
2273 | ||
2274 | void irq_force_complete_move(int irq) | |
2275 | { | |
32f5ef5d | 2276 | struct irq_cfg *cfg = irq_cfg(irq); |
a5e74b84 | 2277 | |
bbd391a1 PB |
2278 | if (!cfg) |
2279 | return; | |
2280 | ||
dd5f15e5 | 2281 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2282 | } |
497c9a19 | 2283 | #else |
dd5f15e5 | 2284 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2285 | #endif |
3145e941 | 2286 | |
7eb9ae07 SS |
2287 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
2288 | { | |
2289 | int apic, pin; | |
2290 | struct irq_pin_list *entry; | |
2291 | u8 vector = cfg->vector; | |
2292 | ||
2293 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2294 | unsigned int reg; | |
2295 | ||
2296 | apic = entry->apic; | |
2297 | pin = entry->pin; | |
9f9d39e4 JR |
2298 | |
2299 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
2300 | reg = io_apic_read(apic, 0x10 + pin*2); |
2301 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2302 | reg |= vector; | |
2303 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2304 | } | |
2305 | } | |
2306 | ||
2307 | /* | |
2308 | * Either sets data->affinity to a valid value, and returns | |
2309 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
2310 | * leaves data->affinity untouched. | |
2311 | */ | |
2312 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2313 | unsigned int *dest_id) | |
2314 | { | |
2315 | struct irq_cfg *cfg = data->chip_data; | |
2316 | unsigned int irq = data->irq; | |
2317 | int err; | |
2318 | ||
2319 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2320 | return -EPERM; |
7eb9ae07 SS |
2321 | |
2322 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2323 | return -EINVAL; | |
2324 | ||
2325 | err = assign_irq_vector(irq, cfg, mask); | |
2326 | if (err) | |
2327 | return err; | |
2328 | ||
2329 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
2330 | if (err) { | |
2331 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
2332 | pr_err("Failed to recover vector for irq %d\n", irq); | |
2333 | return err; | |
2334 | } | |
2335 | ||
2336 | cpumask_copy(data->affinity, mask); | |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
373dd7a2 JR |
2341 | |
2342 | int native_ioapic_set_affinity(struct irq_data *data, | |
2343 | const struct cpumask *mask, | |
2344 | bool force) | |
7eb9ae07 SS |
2345 | { |
2346 | unsigned int dest, irq = data->irq; | |
2347 | unsigned long flags; | |
2348 | int ret; | |
2349 | ||
2350 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2351 | return -EPERM; |
7eb9ae07 SS |
2352 | |
2353 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2354 | ret = __ioapic_set_affinity(data, mask, &dest); | |
2355 | if (!ret) { | |
2356 | /* Only the high 8 bits are valid. */ | |
2357 | dest = SET_APIC_LOGICAL_ID(dest); | |
2358 | __target_IO_APIC_irq(irq, dest, data->chip_data); | |
2359 | ret = IRQ_SET_MASK_OK_NOCOPY; | |
2360 | } | |
2361 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2362 | return ret; | |
2363 | } | |
2364 | ||
90297c5f | 2365 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2366 | { |
90297c5f | 2367 | irq_complete_move(data->chip_data); |
08221110 | 2368 | irq_move_irq(data); |
1d025192 YL |
2369 | ack_APIC_irq(); |
2370 | } | |
2371 | ||
3eb2cce8 | 2372 | atomic_t irq_mis_count; |
3eb2cce8 | 2373 | |
047c8fdb | 2374 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2375 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2376 | { | |
2377 | struct irq_pin_list *entry; | |
2378 | unsigned long flags; | |
2379 | ||
2380 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2381 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2382 | unsigned int reg; | |
2383 | int pin; | |
2384 | ||
2385 | pin = entry->pin; | |
2386 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2387 | /* Is the remote IRR bit set? */ | |
2388 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2389 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2390 | return true; | |
2391 | } | |
2392 | } | |
2393 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2394 | ||
2395 | return false; | |
2396 | } | |
2397 | ||
4da7072a AG |
2398 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2399 | { | |
54168ed7 | 2400 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2401 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2402 | mask_ioapic(cfg); |
4da7072a | 2403 | return true; |
54168ed7 | 2404 | } |
4da7072a AG |
2405 | return false; |
2406 | } | |
2407 | ||
2408 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2409 | struct irq_cfg *cfg, bool masked) | |
2410 | { | |
2411 | if (unlikely(masked)) { | |
2412 | /* Only migrate the irq if the ack has been received. | |
2413 | * | |
2414 | * On rare occasions the broadcast level triggered ack gets | |
2415 | * delayed going to ioapics, and if we reprogram the | |
2416 | * vector while Remote IRR is still set the irq will never | |
2417 | * fire again. | |
2418 | * | |
2419 | * To prevent this scenario we read the Remote IRR bit | |
2420 | * of the ioapic. This has two effects. | |
2421 | * - On any sane system the read of the ioapic will | |
2422 | * flush writes (and acks) going to the ioapic from | |
2423 | * this cpu. | |
2424 | * - We get to see if the ACK has actually been delivered. | |
2425 | * | |
2426 | * Based on failed experiments of reprogramming the | |
2427 | * ioapic entry from outside of irq context starting | |
2428 | * with masking the ioapic entry and then polling until | |
2429 | * Remote IRR was clear before reprogramming the | |
2430 | * ioapic I don't trust the Remote IRR bit to be | |
2431 | * completey accurate. | |
2432 | * | |
2433 | * However there appears to be no other way to plug | |
2434 | * this race, so if the Remote IRR bit is not | |
2435 | * accurate and is causing problems then it is a hardware bug | |
2436 | * and you can go talk to the chipset vendor about it. | |
2437 | */ | |
2438 | if (!io_apic_level_ack_pending(cfg)) | |
2439 | irq_move_masked_irq(data); | |
2440 | unmask_ioapic(cfg); | |
2441 | } | |
2442 | } | |
2443 | #else | |
2444 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2445 | { | |
2446 | return false; | |
2447 | } | |
2448 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2449 | struct irq_cfg *cfg, bool masked) | |
2450 | { | |
2451 | } | |
047c8fdb YL |
2452 | #endif |
2453 | ||
4da7072a AG |
2454 | static void ack_apic_level(struct irq_data *data) |
2455 | { | |
2456 | struct irq_cfg *cfg = data->chip_data; | |
2457 | int i, irq = data->irq; | |
2458 | unsigned long v; | |
2459 | bool masked; | |
2460 | ||
2461 | irq_complete_move(cfg); | |
2462 | masked = ioapic_irqd_mask(data, cfg); | |
2463 | ||
3eb2cce8 | 2464 | /* |
916a0fe7 JF |
2465 | * It appears there is an erratum which affects at least version 0x11 |
2466 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2467 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2468 | * erroneously delivered as edge-triggered one but the respective IRR | |
2469 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2470 | * message but it will never arrive and further interrupts are blocked | |
2471 | * from the source. The exact reason is so far unknown, but the | |
2472 | * phenomenon was observed when two consecutive interrupt requests | |
2473 | * from a given source get delivered to the same CPU and the source is | |
2474 | * temporarily disabled in between. | |
2475 | * | |
2476 | * A workaround is to simulate an EOI message manually. We achieve it | |
2477 | * by setting the trigger mode to edge and then to level when the edge | |
2478 | * trigger mode gets detected in the TMR of a local APIC for a | |
2479 | * level-triggered interrupt. We mask the source for the time of the | |
2480 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2481 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2482 | * |
2483 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2484 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2485 | * destination that is handling the corresponding interrupt. This | |
2486 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2487 | * level-triggered io-apic interrupt will be seen as an edge | |
2488 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2489 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2490 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2491 | * supporting EOI register, we do an explicit EOI to clear the | |
2492 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2493 | * we use the above logic (mask+edge followed by unmask+level) from | |
2494 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2495 | */ |
3145e941 | 2496 | i = cfg->vector; |
3eb2cce8 | 2497 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2498 | |
54168ed7 IM |
2499 | /* |
2500 | * We must acknowledge the irq before we move it or the acknowledge will | |
2501 | * not propagate properly. | |
2502 | */ | |
2503 | ack_APIC_irq(); | |
2504 | ||
1c83995b SS |
2505 | /* |
2506 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2507 | * message via io-apic EOI register write or simulating it using | |
2508 | * mask+edge followed by unnask+level logic) manually when the | |
2509 | * level triggered interrupt is seen as the edge triggered interrupt | |
2510 | * at the cpu. | |
2511 | */ | |
ca64c47c MR |
2512 | if (!(v & (1 << (i & 0x1f)))) { |
2513 | atomic_inc(&irq_mis_count); | |
2514 | ||
dd5f15e5 | 2515 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2516 | } |
2517 | ||
4da7072a | 2518 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2519 | } |
1d025192 | 2520 | |
f5b9ed7a | 2521 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2522 | .name = "IO-APIC", |
2523 | .irq_startup = startup_ioapic_irq, | |
2524 | .irq_mask = mask_ioapic_irq, | |
2525 | .irq_unmask = unmask_ioapic_irq, | |
2526 | .irq_ack = ack_apic_edge, | |
2527 | .irq_eoi = ack_apic_level, | |
373dd7a2 | 2528 | .irq_set_affinity = native_ioapic_set_affinity, |
f7e909ea | 2529 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2530 | }; |
2531 | ||
1da177e4 LT |
2532 | static inline void init_IO_APIC_traps(void) |
2533 | { | |
da51a821 | 2534 | struct irq_cfg *cfg; |
ad9f4334 | 2535 | unsigned int irq; |
1da177e4 | 2536 | |
ad9f4334 | 2537 | for_each_active_irq(irq) { |
32f5ef5d | 2538 | cfg = irq_cfg(irq); |
0b8f1efa | 2539 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2540 | /* |
2541 | * Hmm.. We don't have an entry for this, | |
2542 | * so default to an old-fashioned 8259 | |
2543 | * interrupt if we can.. | |
2544 | */ | |
b81bb373 JP |
2545 | if (irq < legacy_pic->nr_legacy_irqs) |
2546 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2547 | else |
1da177e4 | 2548 | /* Strange. Oh, well.. */ |
2c778651 | 2549 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2550 | } |
2551 | } | |
2552 | } | |
2553 | ||
f5b9ed7a IM |
2554 | /* |
2555 | * The local APIC irq-chip implementation: | |
2556 | */ | |
1da177e4 | 2557 | |
90297c5f | 2558 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2559 | { |
2560 | unsigned long v; | |
2561 | ||
2562 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2563 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2564 | } |
2565 | ||
90297c5f | 2566 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2567 | { |
f5b9ed7a | 2568 | unsigned long v; |
1da177e4 | 2569 | |
f5b9ed7a | 2570 | v = apic_read(APIC_LVT0); |
593f4a78 | 2571 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2572 | } |
1da177e4 | 2573 | |
90297c5f | 2574 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2575 | { |
2576 | ack_APIC_irq(); | |
2577 | } | |
2578 | ||
f5b9ed7a | 2579 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2580 | .name = "local-APIC", |
90297c5f TG |
2581 | .irq_mask = mask_lapic_irq, |
2582 | .irq_unmask = unmask_lapic_irq, | |
2583 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2584 | }; |
2585 | ||
60c69948 | 2586 | static void lapic_register_intr(int irq) |
c88ac1df | 2587 | { |
60c69948 | 2588 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2589 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2590 | "edge"); |
c88ac1df MR |
2591 | } |
2592 | ||
1da177e4 LT |
2593 | /* |
2594 | * This looks a bit hackish but it's about the only one way of sending | |
2595 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2596 | * not support the ExtINT mode, unfortunately. We need to send these | |
2597 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2598 | * 8259A interrupt line asserted until INTA. --macro | |
2599 | */ | |
28acf285 | 2600 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2601 | { |
fcfd636a | 2602 | int apic, pin, i; |
1da177e4 LT |
2603 | struct IO_APIC_route_entry entry0, entry1; |
2604 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2605 | |
fcfd636a | 2606 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2607 | if (pin == -1) { |
2608 | WARN_ON_ONCE(1); | |
2609 | return; | |
2610 | } | |
fcfd636a | 2611 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2612 | if (apic == -1) { |
2613 | WARN_ON_ONCE(1); | |
1da177e4 | 2614 | return; |
956fb531 | 2615 | } |
1da177e4 | 2616 | |
cf4c6a2f | 2617 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2618 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2619 | |
2620 | memset(&entry1, 0, sizeof(entry1)); | |
2621 | ||
2622 | entry1.dest_mode = 0; /* physical delivery */ | |
2623 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2624 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2625 | entry1.delivery_mode = dest_ExtINT; |
2626 | entry1.polarity = entry0.polarity; | |
2627 | entry1.trigger = 0; | |
2628 | entry1.vector = 0; | |
2629 | ||
cf4c6a2f | 2630 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2631 | |
2632 | save_control = CMOS_READ(RTC_CONTROL); | |
2633 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2634 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2635 | RTC_FREQ_SELECT); | |
2636 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2637 | ||
2638 | i = 100; | |
2639 | while (i-- > 0) { | |
2640 | mdelay(10); | |
2641 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2642 | i -= 10; | |
2643 | } | |
2644 | ||
2645 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2646 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2647 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2648 | |
cf4c6a2f | 2649 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2650 | } |
2651 | ||
efa2559f | 2652 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2653 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2654 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2655 | { |
2656 | disable_timer_pin_1 = 1; | |
2657 | return 0; | |
2658 | } | |
54168ed7 | 2659 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2660 | |
1da177e4 LT |
2661 | /* |
2662 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2663 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2664 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2665 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2666 | * |
2667 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2668 | */ |
8542b200 | 2669 | static inline void __init check_timer(void) |
1da177e4 | 2670 | { |
32f5ef5d | 2671 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2672 | int node = cpu_to_node(0); |
fcfd636a | 2673 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2674 | unsigned long flags; |
047c8fdb | 2675 | int no_pin1 = 0; |
4aae0702 IM |
2676 | |
2677 | local_irq_save(flags); | |
d4d25dec | 2678 | |
1da177e4 LT |
2679 | /* |
2680 | * get/set the timer IRQ vector: | |
2681 | */ | |
4305df94 | 2682 | legacy_pic->mask(0); |
fe402e1f | 2683 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2684 | |
2685 | /* | |
d11d5794 MR |
2686 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2687 | * wire has to be disabled in the local APIC. Also | |
2688 | * timer interrupts need to be acknowledged manually in | |
2689 | * the 8259A for the i82489DX when using the NMI | |
2690 | * watchdog as that APIC treats NMIs as level-triggered. | |
2691 | * The AEOI mode will finish them in the 8259A | |
2692 | * automatically. | |
1da177e4 | 2693 | */ |
593f4a78 | 2694 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2695 | legacy_pic->init(1); |
1da177e4 | 2696 | |
fcfd636a EB |
2697 | pin1 = find_isa_irq_pin(0, mp_INT); |
2698 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2699 | pin2 = ioapic_i8259.pin; | |
2700 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2701 | |
49a66a0b MR |
2702 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2703 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2704 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2705 | |
691874fa MR |
2706 | /* |
2707 | * Some BIOS writers are clueless and report the ExtINTA | |
2708 | * I/O APIC input from the cascaded 8259A as the timer | |
2709 | * interrupt input. So just in case, if only one pin | |
2710 | * was found above, try it both directly and through the | |
2711 | * 8259A. | |
2712 | */ | |
2713 | if (pin1 == -1) { | |
6a9f5de2 | 2714 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2715 | pin1 = pin2; |
2716 | apic1 = apic2; | |
2717 | no_pin1 = 1; | |
2718 | } else if (pin2 == -1) { | |
2719 | pin2 = pin1; | |
2720 | apic2 = apic1; | |
2721 | } | |
2722 | ||
1da177e4 LT |
2723 | if (pin1 != -1) { |
2724 | /* | |
2725 | * Ok, does IRQ0 through the IOAPIC work? | |
2726 | */ | |
691874fa | 2727 | if (no_pin1) { |
85ac16d0 | 2728 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2729 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2730 | } else { |
60c69948 | 2731 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2732 | * leave it unmasked. |
2733 | * so only need to unmask if it is level-trigger | |
2734 | * do we really have level trigger timer? | |
2735 | */ | |
2736 | int idx; | |
2737 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2738 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2739 | unmask_ioapic(cfg); |
691874fa | 2740 | } |
1da177e4 | 2741 | if (timer_irq_works()) { |
66759a01 CE |
2742 | if (disable_timer_pin_1 > 0) |
2743 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2744 | goto out; |
1da177e4 | 2745 | } |
6a9f5de2 | 2746 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2747 | local_irq_disable(); |
fcfd636a | 2748 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2749 | if (!no_pin1) |
49a66a0b MR |
2750 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2751 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2752 | |
49a66a0b MR |
2753 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2754 | "(IRQ0) through the 8259A ...\n"); | |
2755 | apic_printk(APIC_QUIET, KERN_INFO | |
2756 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2757 | /* |
2758 | * legacy devices should be connected to IO APIC #0 | |
2759 | */ | |
85ac16d0 | 2760 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2761 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2762 | legacy_pic->unmask(0); |
1da177e4 | 2763 | if (timer_irq_works()) { |
49a66a0b | 2764 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2765 | goto out; |
1da177e4 LT |
2766 | } |
2767 | /* | |
2768 | * Cleanup, just in case ... | |
2769 | */ | |
f72dccac | 2770 | local_irq_disable(); |
4305df94 | 2771 | legacy_pic->mask(0); |
fcfd636a | 2772 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2773 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2774 | } |
1da177e4 | 2775 | |
49a66a0b MR |
2776 | apic_printk(APIC_QUIET, KERN_INFO |
2777 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2778 | |
60c69948 | 2779 | lapic_register_intr(0); |
497c9a19 | 2780 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2781 | legacy_pic->unmask(0); |
1da177e4 LT |
2782 | |
2783 | if (timer_irq_works()) { | |
49a66a0b | 2784 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2785 | goto out; |
1da177e4 | 2786 | } |
f72dccac | 2787 | local_irq_disable(); |
4305df94 | 2788 | legacy_pic->mask(0); |
497c9a19 | 2789 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2790 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2791 | |
49a66a0b MR |
2792 | apic_printk(APIC_QUIET, KERN_INFO |
2793 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2794 | |
b81bb373 JP |
2795 | legacy_pic->init(0); |
2796 | legacy_pic->make_irq(0); | |
593f4a78 | 2797 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2798 | |
2799 | unlock_ExtINT_logic(); | |
2800 | ||
2801 | if (timer_irq_works()) { | |
49a66a0b | 2802 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2803 | goto out; |
1da177e4 | 2804 | } |
f72dccac | 2805 | local_irq_disable(); |
49a66a0b | 2806 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2807 | if (x2apic_preenabled) |
2808 | apic_printk(APIC_QUIET, KERN_INFO | |
2809 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2810 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2811 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2812 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2813 | out: |
2814 | local_irq_restore(flags); | |
1da177e4 LT |
2815 | } |
2816 | ||
2817 | /* | |
af174783 MR |
2818 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2819 | * to devices. However there may be an I/O APIC pin available for | |
2820 | * this interrupt regardless. The pin may be left unconnected, but | |
2821 | * typically it will be reused as an ExtINT cascade interrupt for | |
2822 | * the master 8259A. In the MPS case such a pin will normally be | |
2823 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2824 | * there is no provision for ExtINT interrupts, and in the absence | |
2825 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2826 | * interrupt, that is edge-triggered and unmasked by default. We | |
2827 | * used to do this, but it caused problems on some systems because | |
2828 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2829 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2830 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2831 | * the I/O APIC in all cases now. No actual device should request | |
2832 | * it anyway. --macro | |
1da177e4 | 2833 | */ |
bc07844a | 2834 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2835 | |
2836 | void __init setup_IO_APIC(void) | |
2837 | { | |
54168ed7 | 2838 | |
54168ed7 IM |
2839 | /* |
2840 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2841 | */ | |
b81bb373 | 2842 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2843 | |
54168ed7 | 2844 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2845 | /* |
54168ed7 IM |
2846 | * Set up IO-APIC IRQ routing. |
2847 | */ | |
de934103 TG |
2848 | x86_init.mpparse.setup_ioapic_ids(); |
2849 | ||
1da177e4 LT |
2850 | sync_Arb_IDs(); |
2851 | setup_IO_APIC_irqs(); | |
2852 | init_IO_APIC_traps(); | |
b81bb373 | 2853 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2854 | check_timer(); |
1da177e4 LT |
2855 | } |
2856 | ||
2857 | /* | |
0d2eb44f | 2858 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2859 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2860 | */ |
36062448 | 2861 | |
1da177e4 LT |
2862 | static int __init io_apic_bug_finalize(void) |
2863 | { | |
d6c88a50 TG |
2864 | if (sis_apic_bug == -1) |
2865 | sis_apic_bug = 0; | |
2866 | return 0; | |
1da177e4 LT |
2867 | } |
2868 | ||
2869 | late_initcall(io_apic_bug_finalize); | |
2870 | ||
6f50d45f | 2871 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2872 | { |
1da177e4 LT |
2873 | unsigned long flags; |
2874 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2875 | |
dade7716 | 2876 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2877 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2878 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2879 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2880 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2881 | } |
dade7716 | 2882 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2883 | } |
1da177e4 | 2884 | |
f3c6ea1b RW |
2885 | static void ioapic_resume(void) |
2886 | { | |
6f50d45f | 2887 | int ioapic_idx; |
f3c6ea1b | 2888 | |
f44d1692 | 2889 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2890 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2891 | |
2892 | restore_ioapic_entries(); | |
1da177e4 LT |
2893 | } |
2894 | ||
f3c6ea1b | 2895 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2896 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2897 | .resume = ioapic_resume, |
2898 | }; | |
2899 | ||
f3c6ea1b | 2900 | static int __init ioapic_init_ops(void) |
1da177e4 | 2901 | { |
f3c6ea1b RW |
2902 | register_syscore_ops(&ioapic_syscore_ops); |
2903 | ||
1da177e4 LT |
2904 | return 0; |
2905 | } | |
2906 | ||
f3c6ea1b | 2907 | device_initcall(ioapic_init_ops); |
1da177e4 | 2908 | |
3fc471ed | 2909 | /* |
54859f59 | 2910 | * Dynamic irq allocate and deallocation. Should be replaced by irq domains! |
3fc471ed | 2911 | */ |
b1ee5441 TG |
2912 | int arch_setup_hwirq(unsigned int irq, int node) |
2913 | { | |
2914 | struct irq_cfg *cfg; | |
2915 | unsigned long flags; | |
2916 | int ret; | |
2917 | ||
2918 | cfg = alloc_irq_cfg(irq, node); | |
2919 | if (!cfg) | |
2920 | return -ENOMEM; | |
2921 | ||
2922 | raw_spin_lock_irqsave(&vector_lock, flags); | |
2923 | ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); | |
2924 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
2925 | ||
2926 | if (!ret) | |
2927 | irq_set_chip_data(irq, cfg); | |
2928 | else | |
2929 | free_irq_cfg(irq, cfg); | |
2930 | return ret; | |
2931 | } | |
2932 | ||
2933 | void arch_teardown_hwirq(unsigned int irq) | |
2934 | { | |
32f5ef5d | 2935 | struct irq_cfg *cfg = irq_cfg(irq); |
b1ee5441 TG |
2936 | unsigned long flags; |
2937 | ||
2938 | free_remapped_irq(irq); | |
2939 | raw_spin_lock_irqsave(&vector_lock, flags); | |
2940 | __clear_irq_vector(irq, cfg); | |
2941 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
2942 | free_irq_cfg(irq, cfg); | |
2943 | } | |
2944 | ||
2d3fcc1c | 2945 | /* |
27b46d76 | 2946 | * MSI message composition |
2d3fcc1c | 2947 | */ |
7601384f JR |
2948 | void native_compose_msi_msg(struct pci_dev *pdev, |
2949 | unsigned int irq, unsigned int dest, | |
2950 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 2951 | { |
7601384f | 2952 | struct irq_cfg *cfg = irq_cfg(irq); |
2d3fcc1c | 2953 | |
7601384f | 2954 | msg->address_hi = MSI_ADDR_BASE_HI; |
54168ed7 | 2955 | |
5e2b930b | 2956 | if (x2apic_enabled()) |
7601384f | 2957 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); |
f007e99c | 2958 | |
5e2b930b JR |
2959 | msg->address_lo = |
2960 | MSI_ADDR_BASE_LO | | |
2961 | ((apic->irq_dest_mode == 0) ? | |
2962 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2963 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2964 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
2965 | MSI_ADDR_REDIRECTION_CPU: | |
2966 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2967 | MSI_ADDR_DEST_ID(dest); | |
2968 | ||
2969 | msg->data = | |
2970 | MSI_DATA_TRIGGER_EDGE | | |
2971 | MSI_DATA_LEVEL_ASSERT | | |
2972 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
2973 | MSI_DATA_DELIVERY_FIXED: | |
2974 | MSI_DATA_DELIVERY_LOWPRI) | | |
2975 | MSI_DATA_VECTOR(cfg->vector); | |
7601384f JR |
2976 | } |
2977 | ||
2978 | #ifdef CONFIG_PCI_MSI | |
2979 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |
2980 | struct msi_msg *msg, u8 hpet_id) | |
2981 | { | |
2982 | struct irq_cfg *cfg; | |
2983 | int err; | |
2984 | unsigned dest; | |
2985 | ||
2986 | if (disable_apic) | |
2987 | return -ENXIO; | |
2988 | ||
2989 | cfg = irq_cfg(irq); | |
2990 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | |
2991 | if (err) | |
2992 | return err; | |
2993 | ||
2994 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | |
2995 | apic->target_cpus(), &dest); | |
2996 | if (err) | |
2997 | return err; | |
2998 | ||
2999 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); | |
54168ed7 | 3000 | |
51906e77 | 3001 | return 0; |
2d3fcc1c EB |
3002 | } |
3003 | ||
5346b2a7 TG |
3004 | static int |
3005 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 3006 | { |
5346b2a7 | 3007 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
3008 | struct msi_msg msg; |
3009 | unsigned int dest; | |
fb24da80 | 3010 | int ret; |
3b7d1921 | 3011 | |
fb24da80 PB |
3012 | ret = __ioapic_set_affinity(data, mask, &dest); |
3013 | if (ret) | |
3014 | return ret; | |
2d3fcc1c | 3015 | |
5346b2a7 | 3016 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
3017 | |
3018 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3019 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3020 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3021 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3022 | ||
5346b2a7 | 3023 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 | 3024 | |
f841d792 | 3025 | return IRQ_SET_MASK_OK_NOCOPY; |
2d3fcc1c EB |
3026 | } |
3027 | ||
3b7d1921 EB |
3028 | /* |
3029 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3030 | * which implement the MSI or MSI-X Capability Structure. | |
3031 | */ | |
3032 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3033 | .name = "PCI-MSI", |
3034 | .irq_unmask = unmask_msi_irq, | |
3035 | .irq_mask = mask_msi_irq, | |
3036 | .irq_ack = ack_apic_edge, | |
5346b2a7 | 3037 | .irq_set_affinity = msi_set_affinity, |
5346b2a7 | 3038 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3039 | }; |
3040 | ||
5afba62c JR |
3041 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
3042 | unsigned int irq_base, unsigned int irq_offset) | |
1d025192 | 3043 | { |
c60eaf25 | 3044 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3045 | struct msi_msg msg; |
51906e77 | 3046 | unsigned int irq = irq_base + irq_offset; |
60c69948 | 3047 | int ret; |
1d025192 | 3048 | |
c8bc6f3c | 3049 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3050 | if (ret < 0) |
3051 | return ret; | |
3052 | ||
51906e77 AG |
3053 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); |
3054 | ||
3055 | /* | |
3056 | * MSI-X message is written per-IRQ, the offset is always 0. | |
3057 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. | |
3058 | */ | |
3059 | if (!irq_offset) | |
3060 | write_msi_msg(irq, &msg); | |
1d025192 | 3061 | |
32f5ef5d | 3062 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c60eaf25 TG |
3063 | |
3064 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3065 | |
c81bba49 YL |
3066 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3067 | ||
1d025192 YL |
3068 | return 0; |
3069 | } | |
3070 | ||
5afba62c | 3071 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3072 | { |
0b8f1efa | 3073 | struct msi_desc *msidesc; |
be47be6c | 3074 | unsigned int irq; |
5afba62c JR |
3075 | int node, ret; |
3076 | ||
3077 | /* Multiple MSI vectors only supported with interrupt remapping */ | |
3078 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3079 | return 1; | |
54168ed7 | 3080 | |
d047f53a | 3081 | node = dev_to_node(&dev->dev); |
be47be6c | 3082 | |
0b8f1efa | 3083 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
be47be6c TG |
3084 | irq = irq_alloc_hwirq(node); |
3085 | if (!irq) | |
51906e77 | 3086 | return -ENOSPC; |
5afba62c | 3087 | |
51906e77 | 3088 | ret = setup_msi_irq(dev, msidesc, irq, 0); |
be47be6c TG |
3089 | if (ret < 0) { |
3090 | irq_free_hwirq(irq); | |
3091 | return ret; | |
3092 | } | |
3093 | ||
54168ed7 IM |
3094 | } |
3095 | return 0; | |
047c8fdb YL |
3096 | } |
3097 | ||
294ee6f8 | 3098 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3099 | { |
be47be6c | 3100 | irq_free_hwirq(irq); |
3b7d1921 EB |
3101 | } |
3102 | ||
d3f13810 | 3103 | #ifdef CONFIG_DMAR_TABLE |
fe52b2d2 TG |
3104 | static int |
3105 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3106 | bool force) | |
54168ed7 | 3107 | { |
fe52b2d2 TG |
3108 | struct irq_cfg *cfg = data->chip_data; |
3109 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3110 | struct msi_msg msg; |
fb24da80 | 3111 | int ret; |
54168ed7 | 3112 | |
fb24da80 PB |
3113 | ret = __ioapic_set_affinity(data, mask, &dest); |
3114 | if (ret) | |
3115 | return ret; | |
54168ed7 | 3116 | |
54168ed7 IM |
3117 | dmar_msi_read(irq, &msg); |
3118 | ||
3119 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3120 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3121 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3122 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3123 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3124 | |
3125 | dmar_msi_write(irq, &msg); | |
d5dedd45 | 3126 | |
f841d792 | 3127 | return IRQ_SET_MASK_OK_NOCOPY; |
54168ed7 | 3128 | } |
3145e941 | 3129 | |
8f7007aa | 3130 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3131 | .name = "DMAR_MSI", |
3132 | .irq_unmask = dmar_msi_unmask, | |
3133 | .irq_mask = dmar_msi_mask, | |
3134 | .irq_ack = ack_apic_edge, | |
fe52b2d2 | 3135 | .irq_set_affinity = dmar_msi_set_affinity, |
fe52b2d2 | 3136 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3137 | }; |
3138 | ||
3139 | int arch_setup_dmar_msi(unsigned int irq) | |
3140 | { | |
3141 | int ret; | |
3142 | struct msi_msg msg; | |
2d3fcc1c | 3143 | |
c8bc6f3c | 3144 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3145 | if (ret < 0) |
3146 | return ret; | |
3147 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3148 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3149 | "edge"); | |
54168ed7 IM |
3150 | return 0; |
3151 | } | |
3152 | #endif | |
3153 | ||
58ac1e76 | 3154 | #ifdef CONFIG_HPET_TIMER |
3155 | ||
d0fbca8f TG |
3156 | static int hpet_msi_set_affinity(struct irq_data *data, |
3157 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3158 | { |
d0fbca8f | 3159 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3160 | struct msi_msg msg; |
3161 | unsigned int dest; | |
fb24da80 | 3162 | int ret; |
58ac1e76 | 3163 | |
fb24da80 PB |
3164 | ret = __ioapic_set_affinity(data, mask, &dest); |
3165 | if (ret) | |
3166 | return ret; | |
58ac1e76 | 3167 | |
d0fbca8f | 3168 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3169 | |
3170 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3171 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3172 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3173 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3174 | ||
d0fbca8f | 3175 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 | 3176 | |
f841d792 | 3177 | return IRQ_SET_MASK_OK_NOCOPY; |
58ac1e76 | 3178 | } |
3145e941 | 3179 | |
1cc18521 | 3180 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3181 | .name = "HPET_MSI", |
d0fbca8f TG |
3182 | .irq_unmask = hpet_msi_unmask, |
3183 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3184 | .irq_ack = ack_apic_edge, |
d0fbca8f | 3185 | .irq_set_affinity = hpet_msi_set_affinity, |
90297c5f | 3186 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3187 | }; |
3188 | ||
71054d88 | 3189 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3190 | { |
c60eaf25 | 3191 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3192 | struct msi_msg msg; |
d0fbca8f | 3193 | int ret; |
58ac1e76 | 3194 | |
c8bc6f3c | 3195 | ret = msi_compose_msg(NULL, irq, &msg, id); |
58ac1e76 | 3196 | if (ret < 0) |
3197 | return ret; | |
3198 | ||
2c778651 | 3199 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3200 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
32f5ef5d | 3201 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c81bba49 | 3202 | |
c60eaf25 | 3203 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3204 | return 0; |
3205 | } | |
3206 | #endif | |
3207 | ||
54168ed7 | 3208 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3209 | /* |
3210 | * Hypertransport interrupt support | |
3211 | */ | |
3212 | #ifdef CONFIG_HT_IRQ | |
3213 | ||
497c9a19 | 3214 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3215 | { |
ec68307c EB |
3216 | struct ht_irq_msg msg; |
3217 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3218 | |
497c9a19 | 3219 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3220 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3221 | |
497c9a19 | 3222 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3223 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3224 | |
ec68307c | 3225 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3226 | } |
3227 | ||
be5b7bf7 TG |
3228 | static int |
3229 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3230 | { |
be5b7bf7 | 3231 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3232 | unsigned int dest; |
fb24da80 | 3233 | int ret; |
8b955b0d | 3234 | |
fb24da80 PB |
3235 | ret = __ioapic_set_affinity(data, mask, &dest); |
3236 | if (ret) | |
3237 | return ret; | |
8b955b0d | 3238 | |
be5b7bf7 | 3239 | target_ht_irq(data->irq, dest, cfg->vector); |
f841d792 | 3240 | return IRQ_SET_MASK_OK_NOCOPY; |
8b955b0d | 3241 | } |
3145e941 | 3242 | |
c37e108d | 3243 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3244 | .name = "PCI-HT", |
3245 | .irq_mask = mask_ht_irq, | |
3246 | .irq_unmask = unmask_ht_irq, | |
3247 | .irq_ack = ack_apic_edge, | |
be5b7bf7 | 3248 | .irq_set_affinity = ht_set_affinity, |
be5b7bf7 | 3249 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3250 | }; |
3251 | ||
3252 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3253 | { | |
497c9a19 | 3254 | struct irq_cfg *cfg; |
ff164324 AG |
3255 | struct ht_irq_msg msg; |
3256 | unsigned dest; | |
497c9a19 | 3257 | int err; |
8b955b0d | 3258 | |
f1182638 JB |
3259 | if (disable_apic) |
3260 | return -ENXIO; | |
3261 | ||
3145e941 | 3262 | cfg = irq_cfg(irq); |
fe402e1f | 3263 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
ff164324 AG |
3264 | if (err) |
3265 | return err; | |
8b955b0d | 3266 | |
ff164324 AG |
3267 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3268 | apic->target_cpus(), &dest); | |
3269 | if (err) | |
3270 | return err; | |
8b955b0d | 3271 | |
ff164324 | 3272 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3273 | |
ff164324 AG |
3274 | msg.address_lo = |
3275 | HT_IRQ_LOW_BASE | | |
3276 | HT_IRQ_LOW_DEST_ID(dest) | | |
3277 | HT_IRQ_LOW_VECTOR(cfg->vector) | | |
3278 | ((apic->irq_dest_mode == 0) ? | |
3279 | HT_IRQ_LOW_DM_PHYSICAL : | |
3280 | HT_IRQ_LOW_DM_LOGICAL) | | |
3281 | HT_IRQ_LOW_RQEOI_EDGE | | |
3282 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3283 | HT_IRQ_LOW_MT_FIXED : | |
3284 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3285 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3286 | |
ff164324 | 3287 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3288 | |
ff164324 AG |
3289 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3290 | handle_edge_irq, "edge"); | |
8b955b0d | 3291 | |
ff164324 | 3292 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
c81bba49 | 3293 | |
ff164324 | 3294 | return 0; |
8b955b0d EB |
3295 | } |
3296 | #endif /* CONFIG_HT_IRQ */ | |
3297 | ||
20443598 | 3298 | static int |
ff973d04 TG |
3299 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3300 | { | |
3301 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3302 | int ret; | |
3303 | ||
3304 | if (!cfg) | |
3305 | return -EINVAL; | |
3306 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3307 | if (!ret) | |
e4aff811 | 3308 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3309 | return ret; |
3310 | } | |
3311 | ||
20443598 SAS |
3312 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3313 | struct io_apic_irq_attr *attr) | |
710dcda6 | 3314 | { |
6f50d45f | 3315 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
710dcda6 | 3316 | int ret; |
25aa2957 | 3317 | struct IO_APIC_route_entry orig_entry; |
710dcda6 TG |
3318 | |
3319 | /* Avoid redundant programming */ | |
6f50d45f | 3320 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
25aa2957 LPF |
3321 | pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin); |
3322 | orig_entry = ioapic_read_entry(attr->ioapic, pin); | |
3323 | if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity) | |
3324 | return 0; | |
3325 | return -EBUSY; | |
710dcda6 TG |
3326 | } |
3327 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3328 | if (!ret) | |
6f50d45f | 3329 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
710dcda6 TG |
3330 | return ret; |
3331 | } | |
3332 | ||
41098ffe | 3333 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3334 | { |
3335 | union IO_APIC_reg_01 reg_01; | |
3336 | unsigned long flags; | |
3337 | ||
dade7716 | 3338 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3339 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3340 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3341 | |
4b6b19a1 EB |
3342 | /* The register returns the maximum index redir index |
3343 | * supported, which is one less than the total number of redir | |
3344 | * entries. | |
3345 | */ | |
3346 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3347 | } |
3348 | ||
62a08ae2 TG |
3349 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
3350 | { | |
518b2c63 JL |
3351 | unsigned int min = gsi_top + NR_IRQS_LEGACY; |
3352 | ||
3353 | return from < min ? min : from; | |
62a08ae2 TG |
3354 | } |
3355 | ||
4a046d17 YL |
3356 | int __init arch_probe_nr_irqs(void) |
3357 | { | |
3358 | int nr; | |
3359 | ||
f1ee5548 YL |
3360 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3361 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3362 | |
518b2c63 | 3363 | nr = (gsi_top + NR_IRQS_LEGACY) + 8 * nr_cpu_ids; |
f1ee5548 YL |
3364 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) |
3365 | /* | |
3366 | * for MSI and HT dyn irq | |
3367 | */ | |
518b2c63 | 3368 | nr += (gsi_top + NR_IRQS_LEGACY) * 16; |
f1ee5548 YL |
3369 | #endif |
3370 | if (nr < nr_irqs) | |
4a046d17 YL |
3371 | nr_irqs = nr; |
3372 | ||
b683de2b | 3373 | return NR_IRQS_LEGACY; |
4a046d17 | 3374 | } |
4a046d17 | 3375 | |
710dcda6 TG |
3376 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3377 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3378 | { |
5ef21837 YL |
3379 | int node; |
3380 | ||
3381 | if (!IO_APIC_IRQ(irq)) { | |
3382 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3383 | irq_attr->ioapic); |
5ef21837 YL |
3384 | return -EINVAL; |
3385 | } | |
3386 | ||
e0799c04 | 3387 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3388 | |
710dcda6 | 3389 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3390 | } |
3391 | ||
54168ed7 | 3392 | #ifdef CONFIG_X86_32 |
41098ffe | 3393 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3394 | { |
3395 | union IO_APIC_reg_00 reg_00; | |
3396 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3397 | physid_mask_t tmp; | |
3398 | unsigned long flags; | |
3399 | int i = 0; | |
3400 | ||
3401 | /* | |
36062448 PC |
3402 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3403 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3404 | * supports up to 16 on one shared APIC bus. |
36062448 | 3405 | * |
1da177e4 LT |
3406 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3407 | * advantage of new APIC bus architecture. | |
3408 | */ | |
3409 | ||
3410 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3411 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3412 | |
dade7716 | 3413 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3414 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3415 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3416 | |
3417 | if (apic_id >= get_physical_broadcast()) { | |
3418 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3419 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3420 | apic_id = reg_00.bits.ID; | |
3421 | } | |
3422 | ||
3423 | /* | |
36062448 | 3424 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3425 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3426 | */ | |
7abc0753 | 3427 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3428 | |
3429 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3430 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3431 | break; |
3432 | } | |
3433 | ||
3434 | if (i == get_physical_broadcast()) | |
3435 | panic("Max apic_id exceeded!\n"); | |
3436 | ||
3437 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3438 | "trying %d\n", ioapic, apic_id, i); | |
3439 | ||
3440 | apic_id = i; | |
36062448 | 3441 | } |
1da177e4 | 3442 | |
7abc0753 | 3443 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3444 | physids_or(apic_id_map, apic_id_map, tmp); |
3445 | ||
3446 | if (reg_00.bits.ID != apic_id) { | |
3447 | reg_00.bits.ID = apic_id; | |
3448 | ||
dade7716 | 3449 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3450 | io_apic_write(ioapic, 0, reg_00.raw); |
3451 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3452 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3453 | |
3454 | /* Sanity check */ | |
6070f9ec | 3455 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
3456 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3457 | ioapic); | |
6070f9ec AD |
3458 | return -1; |
3459 | } | |
1da177e4 LT |
3460 | } |
3461 | ||
3462 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3463 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3464 | ||
3465 | return apic_id; | |
3466 | } | |
41098ffe TG |
3467 | |
3468 | static u8 __init io_apic_unique_id(u8 id) | |
3469 | { | |
3470 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3471 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3472 | return io_apic_get_unique_id(nr_ioapics, id); | |
3473 | else | |
3474 | return id; | |
3475 | } | |
3476 | #else | |
3477 | static u8 __init io_apic_unique_id(u8 id) | |
3478 | { | |
3479 | int i; | |
3480 | DECLARE_BITMAP(used, 256); | |
3481 | ||
3482 | bitmap_zero(used, 256); | |
f44d1692 | 3483 | for_each_ioapic(i) |
d5371430 | 3484 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3485 | if (!test_bit(id, used)) |
3486 | return id; | |
3487 | return find_first_zero_bit(used, 256); | |
3488 | } | |
58f892e0 | 3489 | #endif |
1da177e4 | 3490 | |
41098ffe | 3491 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3492 | { |
3493 | union IO_APIC_reg_01 reg_01; | |
3494 | unsigned long flags; | |
3495 | ||
dade7716 | 3496 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3497 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3498 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3499 | |
3500 | return reg_01.bits.version; | |
3501 | } | |
3502 | ||
9a0a91bb | 3503 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3504 | { |
9a0a91bb | 3505 | int ioapic, pin, idx; |
61fd47e0 SL |
3506 | |
3507 | if (skip_ioapic_setup) | |
3508 | return -1; | |
3509 | ||
9a0a91bb EB |
3510 | ioapic = mp_find_ioapic(gsi); |
3511 | if (ioapic < 0) | |
61fd47e0 SL |
3512 | return -1; |
3513 | ||
9a0a91bb EB |
3514 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3515 | if (pin < 0) | |
3516 | return -1; | |
3517 | ||
3518 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3519 | if (idx < 0) | |
61fd47e0 SL |
3520 | return -1; |
3521 | ||
9a0a91bb EB |
3522 | *trigger = irq_trigger(idx); |
3523 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3524 | return 0; |
3525 | } | |
3526 | ||
497c9a19 YL |
3527 | /* |
3528 | * This function currently is only a helper for the i386 smp boot process where | |
3529 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3530 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3531 | */ |
3532 | #ifdef CONFIG_SMP | |
3533 | void __init setup_ioapic_dest(void) | |
3534 | { | |
fad53995 | 3535 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3536 | const struct cpumask *mask; |
5451ddc5 | 3537 | struct irq_data *idata; |
497c9a19 YL |
3538 | |
3539 | if (skip_ioapic_setup == 1) | |
3540 | return; | |
3541 | ||
f44d1692 | 3542 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
3543 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3544 | if (irq_entry == -1) | |
3545 | continue; | |
6c2e9403 | 3546 | |
18e48551 JL |
3547 | irq = pin_2_irq(irq_entry, ioapic, pin); |
3548 | if (!mp_init_irq_at_boot(ioapic, irq)) | |
fad53995 EB |
3549 | continue; |
3550 | ||
5451ddc5 | 3551 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3552 | |
b9c61b70 YL |
3553 | /* |
3554 | * Honour affinities which have been set in early boot | |
3555 | */ | |
5451ddc5 TG |
3556 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3557 | mask = idata->affinity; | |
b9c61b70 YL |
3558 | else |
3559 | mask = apic->target_cpus(); | |
497c9a19 | 3560 | |
373dd7a2 | 3561 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 3562 | } |
b9c61b70 | 3563 | |
497c9a19 YL |
3564 | } |
3565 | #endif | |
3566 | ||
54168ed7 IM |
3567 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3568 | ||
3569 | static struct resource *ioapic_resources; | |
3570 | ||
f44d1692 | 3571 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
3572 | { |
3573 | unsigned long n; | |
3574 | struct resource *res; | |
3575 | char *mem; | |
f44d1692 | 3576 | int i, num = 0; |
54168ed7 | 3577 | |
f44d1692 JL |
3578 | for_each_ioapic(i) |
3579 | num++; | |
3580 | if (num == 0) | |
54168ed7 IM |
3581 | return NULL; |
3582 | ||
3583 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 3584 | n *= num; |
54168ed7 IM |
3585 | |
3586 | mem = alloc_bootmem(n); | |
3587 | res = (void *)mem; | |
3588 | ||
f44d1692 | 3589 | mem += sizeof(struct resource) * num; |
54168ed7 | 3590 | |
f44d1692 JL |
3591 | num = 0; |
3592 | for_each_ioapic(i) { | |
3593 | res[num].name = mem; | |
3594 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3595 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3596 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 3597 | num++; |
54168ed7 IM |
3598 | } |
3599 | ||
3600 | ioapic_resources = res; | |
3601 | ||
3602 | return res; | |
3603 | } | |
54168ed7 | 3604 | |
4a8e2a31 | 3605 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
3606 | { |
3607 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3608 | struct resource *ioapic_res; |
d6c88a50 | 3609 | int i; |
f3294a33 | 3610 | |
f44d1692 JL |
3611 | ioapic_res = ioapic_setup_resources(); |
3612 | for_each_ioapic(i) { | |
f3294a33 | 3613 | if (smp_found_config) { |
d5371430 | 3614 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3615 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3616 | if (!ioapic_phys) { |
3617 | printk(KERN_ERR | |
3618 | "WARNING: bogus zero IO-APIC " | |
3619 | "address found in MPTABLE, " | |
3620 | "disabling IO/APIC support!\n"); | |
3621 | smp_found_config = 0; | |
3622 | skip_ioapic_setup = 1; | |
3623 | goto fake_ioapic_page; | |
3624 | } | |
54168ed7 | 3625 | #endif |
f3294a33 | 3626 | } else { |
54168ed7 | 3627 | #ifdef CONFIG_X86_32 |
f3294a33 | 3628 | fake_ioapic_page: |
54168ed7 | 3629 | #endif |
e79c65a9 | 3630 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3631 | ioapic_phys = __pa(ioapic_phys); |
3632 | } | |
3633 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3634 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3635 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3636 | ioapic_phys); | |
f3294a33 | 3637 | idx++; |
54168ed7 | 3638 | |
ffc43836 | 3639 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3640 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3641 | ioapic_res++; |
f3294a33 YL |
3642 | } |
3643 | } | |
3644 | ||
857fdc53 | 3645 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3646 | { |
3647 | int i; | |
3648 | struct resource *r = ioapic_resources; | |
3649 | ||
3650 | if (!r) { | |
857fdc53 | 3651 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3652 | printk(KERN_ERR |
3653 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3654 | return; |
54168ed7 IM |
3655 | } |
3656 | ||
f44d1692 | 3657 | for_each_ioapic(i) { |
54168ed7 IM |
3658 | insert_resource(&iomem_resource, r); |
3659 | r++; | |
3660 | } | |
54168ed7 | 3661 | } |
2a4ab640 | 3662 | |
eddb0c55 | 3663 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 3664 | { |
f44d1692 | 3665 | int i; |
2a4ab640 | 3666 | |
678301ec PB |
3667 | if (nr_ioapics == 0) |
3668 | return -1; | |
3669 | ||
2a4ab640 | 3670 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 3671 | for_each_ioapic(i) { |
c040aaeb | 3672 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 3673 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
3674 | return i; |
3675 | } | |
54168ed7 | 3676 | |
2a4ab640 FT |
3677 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3678 | return -1; | |
3679 | } | |
3680 | ||
eddb0c55 | 3681 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3682 | { |
c040aaeb SS |
3683 | struct mp_ioapic_gsi *gsi_cfg; |
3684 | ||
f44d1692 | 3685 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 3686 | return -1; |
c040aaeb SS |
3687 | |
3688 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3689 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3690 | return -1; |
3691 | ||
c040aaeb | 3692 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3693 | } |
3694 | ||
41098ffe | 3695 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3696 | { |
3697 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3698 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3699 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3700 | return 1; |
3701 | } | |
3702 | if (!address) { | |
73d63d03 | 3703 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3704 | return 1; |
3705 | } | |
54168ed7 IM |
3706 | return 0; |
3707 | } | |
3708 | ||
73d63d03 SS |
3709 | static __init int bad_ioapic_register(int idx) |
3710 | { | |
3711 | union IO_APIC_reg_00 reg_00; | |
3712 | union IO_APIC_reg_01 reg_01; | |
3713 | union IO_APIC_reg_02 reg_02; | |
3714 | ||
3715 | reg_00.raw = io_apic_read(idx, 0); | |
3716 | reg_01.raw = io_apic_read(idx, 1); | |
3717 | reg_02.raw = io_apic_read(idx, 2); | |
3718 | ||
3719 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3720 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3721 | mpc_ioapic_addr(idx)); | |
3722 | return 1; | |
3723 | } | |
3724 | ||
3725 | return 0; | |
3726 | } | |
3727 | ||
2a4ab640 FT |
3728 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3729 | { | |
3730 | int idx = 0; | |
7716a5c4 | 3731 | int entries; |
c040aaeb | 3732 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3733 | |
3734 | if (bad_ioapic(address)) | |
3735 | return; | |
3736 | ||
3737 | idx = nr_ioapics; | |
3738 | ||
d5371430 SS |
3739 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3740 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3741 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3742 | |
3743 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3744 | |
3745 | if (bad_ioapic_register(idx)) { | |
3746 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3747 | return; | |
3748 | } | |
3749 | ||
d5371430 SS |
3750 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3751 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3752 | |
3753 | /* | |
3754 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3755 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3756 | */ | |
7716a5c4 | 3757 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3758 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3759 | gsi_cfg->gsi_base = gsi_base; | |
3760 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3761 | |
3762 | /* | |
3763 | * The number of IO-APIC IRQ registers (== #pins): | |
3764 | */ | |
b69c6c3b | 3765 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3766 | |
c040aaeb SS |
3767 | if (gsi_cfg->gsi_end >= gsi_top) |
3768 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 3769 | |
73d63d03 SS |
3770 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3771 | idx, mpc_ioapic_id(idx), | |
3772 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3773 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
3774 | |
3775 | nr_ioapics++; | |
3776 | } | |
05ddafb1 JP |
3777 | |
3778 | /* Enable IOAPIC early just for system timer */ | |
3779 | void __init pre_init_apic_IRQ0(void) | |
3780 | { | |
f880ec78 | 3781 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3782 | |
3783 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3784 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3785 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3786 | &phys_cpu_present_map); | |
05ddafb1 | 3787 | #endif |
05ddafb1 JP |
3788 | setup_local_APIC(); |
3789 | ||
f880ec78 | 3790 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3791 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3792 | "edge"); | |
05ddafb1 | 3793 | } |