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iommu/vt-d: Convert MSI remapping setup to remap_ops
[linux-2.6-block.git] / arch / x86 / kernel / apic / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
8f47e163 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
1da177e4
LT		 5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
d4057bdb 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
129f6946 32#include <linux/module.h>
f3c6ea1b 33#include <linux/syscore_ops.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54168ed7 38#include <linux/jiffies.h> /* time_after() */
5a0e3ad6 39#include <linux/slab.h>
d4057bdb
YL		 40#ifdef CONFIG_ACPI
41#include <acpi/acpi_bus.h>
42#endif
43#include <linux/bootmem.h>
44#include <linux/dmar.h>
58ac1e76 45#include <linux/hpet.h>
54d5d424 46
d4057bdb 47#include <asm/idle.h>
1da177e4
LT		 48#include <asm/io.h>
49#include <asm/smp.h>
6d652ea1 50#include <asm/cpu.h>
1da177e4 51#include <asm/desc.h>
d4057bdb
YL		 52#include <asm/proto.h>
53#include <asm/acpi.h>
54#include <asm/dma.h>
1da177e4 55#include <asm/timer.h>
306e440d 56#include <asm/i8259.h>
2d3fcc1c 57#include <asm/msidef.h>
8b955b0d 58#include <asm/hypertransport.h>
a4dbc34d 59#include <asm/setup.h>
736baef4 60#include <asm/intr_remapping.h>
d4057bdb 61#include <asm/irq_remapping.h>
58ac1e76 62#include <asm/hpet.h>
2c1b284e 63#include <asm/hw_irq.h>
1da177e4 64
7b6aa335 65#include <asm/apic.h>
1da177e4 66
32f71aff 67#define __apicdebuginit(type) static type __init
136d249e 68
2977fb3f
CG		 69#define for_each_irq_pin(entry, head) \
70 for (entry = head; entry; entry = entry->next)
32f71aff 71
136d249e
JF		 72static void __init __ioapic_init_mappings(void);
73
74static unsigned int __io_apic_read (unsigned int apic, unsigned int reg);
75static void __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
76static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
77
78static struct io_apic_ops io_apic_ops = {
79 .init = __ioapic_init_mappings,
80 .read = __io_apic_read,
81 .write = __io_apic_write,
82 .modify = __io_apic_modify,
83};
84
85void __init set_io_apic_ops(const struct io_apic_ops *ops)
86{
87 io_apic_ops = *ops;
88}
89
1da177e4 90/*
54168ed7
IM		 91 * Is the SiS APIC rmw bug present ?
92 * -1 = don't know, 0 = no, 1 = yes
1da177e4
LT		 93 */
94int sis_apic_bug = -1;
95
dade7716
TG		 96static DEFINE_RAW_SPINLOCK(ioapic_lock);
97static DEFINE_RAW_SPINLOCK(vector_lock);
efa2559f 98
b69c6c3b
SS		 99static struct ioapic {
100 /*
101 * # of IRQ routing registers
102 */
103 int nr_registers;
57a6f740
SS		 104 /*
105 * Saved state during suspend/resume, or while enabling intr-remap.
106 */
107 struct IO_APIC_route_entry *saved_registers;
d5371430
SS		 108 /* I/O APIC config */
109 struct mpc_ioapic mp_config;
c040aaeb
SS		 110 /* IO APIC gsi routing info */
111 struct mp_ioapic_gsi gsi_config;
8f18c971 112 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
b69c6c3b 113} ioapics[MAX_IO_APICS];
1da177e4 114
6f50d45f 115#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
d5371430 116
6f50d45f 117int mpc_ioapic_id(int ioapic_idx)
d5371430 118{
6f50d45f 119 return ioapics[ioapic_idx].mp_config.apicid;
d5371430
SS		 120}
121
6f50d45f 122unsigned int mpc_ioapic_addr(int ioapic_idx)
d5371430 123{
6f50d45f 124 return ioapics[ioapic_idx].mp_config.apicaddr;
d5371430
SS		 125}
126
6f50d45f 127struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
c040aaeb 128{
6f50d45f 129 return &ioapics[ioapic_idx].gsi_config;
c040aaeb 130}
9f640ccb 131
c040aaeb 132int nr_ioapics;
2a4ab640 133
a4384df3
EB		 134/* The one past the highest gsi number used */
135u32 gsi_top;
5777372a 136
584f734d 137/* MP IRQ source entries */
c2c21745 138struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
584f734d
AS		 139
140/* # of MP IRQ source entries */
141int mp_irq_entries;
142
bc07844a
TG		 143/* GSI interrupts */
144static int nr_irqs_gsi = NR_IRQS_LEGACY;
145
8732fc4b
AS		 146#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
147int mp_bus_id_to_type[MAX_MP_BUSSES];
148#endif
149
150DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
151
efa2559f
YL		 152int skip_ioapic_setup;
153
7167d08e
HK		 154/**
155 * disable_ioapic_support() - disables ioapic support at runtime
156 */
157void disable_ioapic_support(void)
65a4e574
IM		 158{
159#ifdef CONFIG_PCI
160 noioapicquirk = 1;
161 noioapicreroute = -1;
162#endif
163 skip_ioapic_setup = 1;
164}
165
54168ed7 166static int __init parse_noapic(char *str)
efa2559f
YL		 167{
168 /* disable IO-APIC */
7167d08e 169 disable_ioapic_support();
efa2559f
YL		 170 return 0;
171}
172early_param("noapic", parse_noapic);
66759a01 173
20443598
SAS		 174static int io_apic_setup_irq_pin(unsigned int irq, int node,
175 struct io_apic_irq_attr *attr);
710dcda6 176
2d8009ba
FT		 177/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
178void mp_save_irq(struct mpc_intsrc *m)
179{
180 int i;
181
182 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
183 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
184 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
185 m->srcbusirq, m->dstapic, m->dstirq);
186
187 for (i = 0; i < mp_irq_entries; i++) {
0e3fa13f 188 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
2d8009ba
FT		 189 return;
190 }
191
0e3fa13f 192 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
2d8009ba
FT		 193 if (++mp_irq_entries == MAX_IRQ_SOURCES)
194 panic("Max # of irq sources exceeded!!\n");
195}
196
0b8f1efa
YL		 197struct irq_pin_list {
198 int apic, pin;
199 struct irq_pin_list *next;
200};
201
7e495529 202static struct irq_pin_list *alloc_irq_pin_list(int node)
0b8f1efa 203{
2ee39065 204 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
0b8f1efa
YL		 205}
206
2d8009ba 207
a1420f39 208/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
97943390 209static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
a1420f39 210
13a0c3c2 211int __init arch_early_irq_init(void)
8f09cd20 212{
0b8f1efa 213 struct irq_cfg *cfg;
60c69948 214 int count, node, i;
d6c88a50 215
bb84ac2d 216 if (!legacy_pic->nr_legacy_irqs)
1f91233c 217 io_apic_irqs = ~0UL;
1f91233c 218
4c79185c 219 for (i = 0; i < nr_ioapics; i++) {
57a6f740 220 ioapics[i].saved_registers =
4c79185c 221 kzalloc(sizeof(struct IO_APIC_route_entry) *
b69c6c3b 222 ioapics[i].nr_registers, GFP_KERNEL);
57a6f740 223 if (!ioapics[i].saved_registers)
4c79185c
SS		 224 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
225 }
226
0b8f1efa
YL		 227 cfg = irq_cfgx;
228 count = ARRAY_SIZE(irq_cfgx);
f6e9456c 229 node = cpu_to_node(0);
8f09cd20 230
fbc6bff0
TG		 231 /* Make sure the legacy interrupts are marked in the bitmap */
232 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
233
0b8f1efa 234 for (i = 0; i < count; i++) {
2c778651 235 irq_set_chip_data(i, &cfg[i]);
2ee39065
TG		 236 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
237 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
97943390
SS		 238 /*
239 * For legacy IRQ's, start with assigning irq0 to irq15 to
240 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
241 */
54b56170 242 if (i < legacy_pic->nr_legacy_irqs) {
97943390
SS		 243 cfg[i].vector = IRQ0_VECTOR + i;
244 cpumask_set_cpu(0, cfg[i].domain);
245 }
0b8f1efa 246 }
13a0c3c2
YL		 247
248 return 0;
0b8f1efa 249}
8f09cd20 250
48b26501 251static struct irq_cfg *irq_cfg(unsigned int irq)
8f09cd20 252{
2c778651 253 return irq_get_chip_data(irq);
8f09cd20 254}
d6c88a50 255
f981a3dc 256static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
8f09cd20 257{
0b8f1efa 258 struct irq_cfg *cfg;
0f978f45 259
2ee39065 260 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
6e2fff50
TG		 261 if (!cfg)
262 return NULL;
2ee39065 263 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
6e2fff50 264 goto out_cfg;
2ee39065 265 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
6e2fff50 266 goto out_domain;
0b8f1efa 267 return cfg;
6e2fff50
TG		 268out_domain:
269 free_cpumask_var(cfg->domain);
270out_cfg:
271 kfree(cfg);
272 return NULL;
8f09cd20
YL		 273}
274
f981a3dc 275static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
08c33db6 276{
fbc6bff0
TG		 277 if (!cfg)
278 return;
2c778651 279 irq_set_chip_data(at, NULL);
08c33db6
TG		 280 free_cpumask_var(cfg->domain);
281 free_cpumask_var(cfg->old_domain);
282 kfree(cfg);
283}
284
08c33db6
TG		 285static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
286{
287 int res = irq_alloc_desc_at(at, node);
288 struct irq_cfg *cfg;
289
290 if (res < 0) {
291 if (res != -EEXIST)
292 return NULL;
2c778651 293 cfg = irq_get_chip_data(at);
08c33db6
TG		 294 if (cfg)
295 return cfg;
296 }
297
f981a3dc 298 cfg = alloc_irq_cfg(at, node);
08c33db6 299 if (cfg)
2c778651 300 irq_set_chip_data(at, cfg);
08c33db6
TG		 301 else
302 irq_free_desc(at);
303 return cfg;
304}
305
306static int alloc_irq_from(unsigned int from, int node)
307{
308 return irq_alloc_desc_from(from, node);
309}
310
311static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
312{
f981a3dc 313 free_irq_cfg(at, cfg);
08c33db6
TG		 314 irq_free_desc(at);
315}
316
136d249e
JF		 317static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
318{
319 return io_apic_ops.read(apic, reg);
320}
321
322static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
323{
324 io_apic_ops.write(apic, reg, value);
325}
326
327static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
328{
329 io_apic_ops.modify(apic, reg, value);
330}
331
332
130fe05d
LT		 333struct io_apic {
334 unsigned int index;
335 unsigned int unused[3];
336 unsigned int data;
0280f7c4
SS		 337 unsigned int unused2[11];
338 unsigned int eoi;
130fe05d
LT		 339};
340
341static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
342{
343 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
d5371430 344 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
130fe05d
LT		 345}
346
0280f7c4
SS		 347static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
348{
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(vector, &io_apic->eoi);
351}
352
136d249e 353static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
130fe05d
LT		 354{
355 struct io_apic __iomem *io_apic = io_apic_base(apic);
356 writel(reg, &io_apic->index);
357 return readl(&io_apic->data);
358}
359
136d249e 360static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
130fe05d
LT		 361{
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
136d249e 363
130fe05d
LT		 364 writel(reg, &io_apic->index);
365 writel(value, &io_apic->data);
366}
367
368/*
369 * Re-write a value: to be used for read-modify-write
370 * cycles where the read already set up the index register.
371 *
372 * Older SiS APIC requires we rewrite the index register
373 */
136d249e 374static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
130fe05d 375{
54168ed7 376 struct io_apic __iomem *io_apic = io_apic_base(apic);
d6c88a50
TG		 377
378 if (sis_apic_bug)
379 writel(reg, &io_apic->index);
130fe05d
LT		 380 writel(value, &io_apic->data);
381}
382
3145e941 383static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
047c8fdb
YL		 384{
385 struct irq_pin_list *entry;
386 unsigned long flags;
047c8fdb 387
dade7716 388 raw_spin_lock_irqsave(&ioapic_lock, flags);
2977fb3f 389 for_each_irq_pin(entry, cfg->irq_2_pin) {
047c8fdb
YL		 390 unsigned int reg;
391 int pin;
392
047c8fdb
YL		 393 pin = entry->pin;
394 reg = io_apic_read(entry->apic, 0x10 + pin*2);
395 /* Is the remote IRR bit set? */
396 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
dade7716 397 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
047c8fdb
YL		 398 return true;
399 }
047c8fdb 400 }
dade7716 401 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
047c8fdb
YL		 402
403 return false;
404}
047c8fdb 405
cf4c6a2f
AK		 406union entry_union {
407 struct { u32 w1, w2; };
408 struct IO_APIC_route_entry entry;
409};
410
e57253a8
SS		 411static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
412{
413 union entry_union eu;
414
415 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
416 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
136d249e 417
e57253a8
SS		 418 return eu.entry;
419}
420
cf4c6a2f
AK		 421static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
422{
423 union entry_union eu;
424 unsigned long flags;
136d249e 425
dade7716 426 raw_spin_lock_irqsave(&ioapic_lock, flags);
e57253a8 427 eu.entry = __ioapic_read_entry(apic, pin);
dade7716 428 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
136d249e 429
cf4c6a2f
AK		 430 return eu.entry;
431}
432
f9dadfa7
LT		 433/*
434 * When we write a new IO APIC routing entry, we need to write the high
435 * word first! If the mask bit in the low word is clear, we will enable
436 * the interrupt, and we need to make sure the entry is fully populated
437 * before that happens.
438 */
136d249e 439static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 440{
50a8d4d2
F		 441 union entry_union eu = {{0, 0}};
442
cf4c6a2f 443 eu.entry = e;
f9dadfa7
LT		 444 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
445 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 446}
447
1a8ce7ff 448static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
d15512f4
AK		 449{
450 unsigned long flags;
136d249e 451
dade7716 452 raw_spin_lock_irqsave(&ioapic_lock, flags);
d15512f4 453 __ioapic_write_entry(apic, pin, e);
dade7716 454 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
f9dadfa7
LT		 455}
456
457/*
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
460 * high bits!
461 */
462static void ioapic_mask_entry(int apic, int pin)
463{
464 unsigned long flags;
465 union entry_union eu = { .entry.mask = 1 };
466
dade7716 467 raw_spin_lock_irqsave(&ioapic_lock, flags);
cf4c6a2f
AK		 468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
dade7716 470 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
cf4c6a2f
AK		 471}
472
1da177e4
LT		 473/*
474 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
475 * shared ISA-space IRQs, so we have to support them. We are super
476 * fast in the common case, and fast for shared ISA-space IRQs.
477 */
136d249e 478static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
1da177e4 479{
2977fb3f 480 struct irq_pin_list **last, *entry;
0f978f45 481
2977fb3f
CG		 482 /* don't allow duplicates */
483 last = &cfg->irq_2_pin;
484 for_each_irq_pin(entry, cfg->irq_2_pin) {
0f978f45 485 if (entry->apic == apic && entry->pin == pin)
f3d1915a 486 return 0;
2977fb3f 487 last = &entry->next;
1da177e4 488 }
0f978f45 489
7e495529 490 entry = alloc_irq_pin_list(node);
a7428cd2 491 if (!entry) {
f3d1915a
CG		 492 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
493 node, apic, pin);
494 return -ENOMEM;
a7428cd2 495 }
1da177e4
LT		 496 entry->apic = apic;
497 entry->pin = pin;
875e68ec 498
2977fb3f 499 *last = entry;
f3d1915a
CG		 500 return 0;
501}
502
503static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
504{
7e495529 505 if (__add_pin_to_irq_node(cfg, node, apic, pin))
f3d1915a 506 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
1da177e4
LT		 507}
508
509/*
510 * Reroute an IRQ to a different pin.
511 */
85ac16d0 512static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
4eea6fff
JF		 513 int oldapic, int oldpin,
514 int newapic, int newpin)
1da177e4 515{
535b6429 516 struct irq_pin_list *entry;
1da177e4 517
2977fb3f 518 for_each_irq_pin(entry, cfg->irq_2_pin) {
1da177e4
LT		 519 if (entry->apic == oldapic && entry->pin == oldpin) {
520 entry->apic = newapic;
521 entry->pin = newpin;
0f978f45 522 /* every one is different, right? */
4eea6fff 523 return;
0f978f45 524 }
1da177e4 525 }
0f978f45 526
4eea6fff
JF		 527 /* old apic/pin didn't exist, so just add new ones */
528 add_pin_to_irq_node(cfg, node, newapic, newpin);
1da177e4
LT		 529}
530
c29d9db3
SS		 531static void __io_apic_modify_irq(struct irq_pin_list *entry,
532 int mask_and, int mask_or,
533 void (*final)(struct irq_pin_list *entry))
534{
535 unsigned int reg, pin;
536
537 pin = entry->pin;
538 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
539 reg &= mask_and;
540 reg |= mask_or;
541 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
542 if (final)
543 final(entry);
544}
545
2f210deb
JF		 546static void io_apic_modify_irq(struct irq_cfg *cfg,
547 int mask_and, int mask_or,
548 void (*final)(struct irq_pin_list *entry))
87783be4 549{
87783be4 550 struct irq_pin_list *entry;
047c8fdb 551
c29d9db3
SS		 552 for_each_irq_pin(entry, cfg->irq_2_pin)
553 __io_apic_modify_irq(entry, mask_and, mask_or, final);
554}
555
7f3e632f 556static void io_apic_sync(struct irq_pin_list *entry)
1da177e4 557{
87783be4
CG		 558 /*
559 * Synchronize the IO-APIC and the CPU by doing
560 * a dummy read from the IO-APIC
561 */
562 struct io_apic __iomem *io_apic;
136d249e 563
87783be4 564 io_apic = io_apic_base(entry->apic);
4e738e2f 565 readl(&io_apic->data);
1da177e4
LT		 566}
567
dd5f15e5 568static void mask_ioapic(struct irq_cfg *cfg)
87783be4 569{
dd5f15e5
TG		 570 unsigned long flags;
571
572 raw_spin_lock_irqsave(&ioapic_lock, flags);
3145e941 573 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
dd5f15e5 574 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
87783be4 575}
1da177e4 576
90297c5f 577static void mask_ioapic_irq(struct irq_data *data)
1da177e4 578{
90297c5f 579 mask_ioapic(data->chip_data);
dd5f15e5 580}
3145e941 581
dd5f15e5
TG		 582static void __unmask_ioapic(struct irq_cfg *cfg)
583{
584 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
1da177e4
LT		 585}
586
dd5f15e5 587static void unmask_ioapic(struct irq_cfg *cfg)
1da177e4
LT		 588{
589 unsigned long flags;
590
dade7716 591 raw_spin_lock_irqsave(&ioapic_lock, flags);
dd5f15e5 592 __unmask_ioapic(cfg);
dade7716 593 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 594}
595
90297c5f 596static void unmask_ioapic_irq(struct irq_data *data)
3145e941 597{
90297c5f 598 unmask_ioapic(data->chip_data);
3145e941
YL		 599}
600
c0205701
SS		 601/*
602 * IO-APIC versions below 0x20 don't support EOI register.
603 * For the record, here is the information about various versions:
604 * 0Xh 82489DX
605 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
606 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
607 * 30h-FFh Reserved
608 *
609 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
610 * version as 0x2. This is an error with documentation and these ICH chips
611 * use io-apic's of version 0x20.
612 *
613 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
614 * Otherwise, we simulate the EOI message manually by changing the trigger
615 * mode to edge and then back to level, with RTE being masked during this.
616 */
617static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
618{
619 if (mpc_ioapic_ver(apic) >= 0x20) {
620 /*
621 * Intr-remapping uses pin number as the virtual vector
622 * in the RTE. Actual vector is programmed in
623 * intr-remapping table entry. Hence for the io-apic
624 * EOI we use the pin number.
625 */
626 if (cfg && irq_remapped(cfg))
627 io_apic_eoi(apic, pin);
628 else
629 io_apic_eoi(apic, vector);
630 } else {
631 struct IO_APIC_route_entry entry, entry1;
632
633 entry = entry1 = __ioapic_read_entry(apic, pin);
634
635 /*
636 * Mask the entry and change the trigger mode to edge.
637 */
638 entry1.mask = 1;
639 entry1.trigger = IOAPIC_EDGE;
640
641 __ioapic_write_entry(apic, pin, entry1);
642
643 /*
644 * Restore the previous level triggered entry.
645 */
646 __ioapic_write_entry(apic, pin, entry);
647 }
648}
649
650static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
651{
652 struct irq_pin_list *entry;
653 unsigned long flags;
654
655 raw_spin_lock_irqsave(&ioapic_lock, flags);
656 for_each_irq_pin(entry, cfg->irq_2_pin)
657 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
658 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
659}
660
1da177e4
LT		 661static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
662{
663 struct IO_APIC_route_entry entry;
36062448 664
1da177e4 665 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 666 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 667 if (entry.delivery_mode == dest_SMI)
668 return;
1e75b31d 669
1da177e4 670 /*
1e75b31d
SS		 671 * Make sure the entry is masked and re-read the contents to check
672 * if it is a level triggered pin and if the remote-IRR is set.
673 */
674 if (!entry.mask) {
675 entry.mask = 1;
676 ioapic_write_entry(apic, pin, entry);
677 entry = ioapic_read_entry(apic, pin);
678 }
679
680 if (entry.irr) {
c0205701
SS		 681 unsigned long flags;
682
1e75b31d
SS		 683 /*
684 * Make sure the trigger mode is set to level. Explicit EOI
685 * doesn't clear the remote-IRR if the trigger mode is not
686 * set to level.
687 */
688 if (!entry.trigger) {
689 entry.trigger = IOAPIC_LEVEL;
690 ioapic_write_entry(apic, pin, entry);
691 }
692
c0205701
SS		 693 raw_spin_lock_irqsave(&ioapic_lock, flags);
694 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
695 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1e75b31d
SS		 696 }
697
698 /*
699 * Clear the rest of the bits in the IO-APIC RTE except for the mask
700 * bit.
1da177e4 701 */
f9dadfa7 702 ioapic_mask_entry(apic, pin);
1e75b31d
SS		 703 entry = ioapic_read_entry(apic, pin);
704 if (entry.irr)
705 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
706 mpc_ioapic_id(apic), pin);
1da177e4
LT		 707}
708
54168ed7 709static void clear_IO_APIC (void)
1da177e4
LT		 710{
711 int apic, pin;
712
713 for (apic = 0; apic < nr_ioapics; apic++)
b69c6c3b 714 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
1da177e4
LT		 715 clear_IO_APIC_pin(apic, pin);
716}
717
54168ed7 718#ifdef CONFIG_X86_32
1da177e4
LT		 719/*
720 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
721 * specific CPU-side IRQs.
722 */
723
724#define MAX_PIRQS 8
3bd25d0f
YL		 725static int pirq_entries[MAX_PIRQS] = {
726 [0 ... MAX_PIRQS - 1] = -1
727};
1da177e4 728
1da177e4
LT		 729static int __init ioapic_pirq_setup(char *str)
730{
731 int i, max;
732 int ints[MAX_PIRQS+1];
733
734 get_options(str, ARRAY_SIZE(ints), ints);
735
1da177e4
LT		 736 apic_printk(APIC_VERBOSE, KERN_INFO
737 "PIRQ redirection, working around broken MP-BIOS.\n");
738 max = MAX_PIRQS;
739 if (ints[0] < MAX_PIRQS)
740 max = ints[0];
741
742 for (i = 0; i < max; i++) {
743 apic_printk(APIC_VERBOSE, KERN_DEBUG
744 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
745 /*
746 * PIRQs are mapped upside down, usually.
747 */
748 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
749 }
750 return 1;
751}
752
753__setup("pirq=", ioapic_pirq_setup);
54168ed7
IM		 754#endif /* CONFIG_X86_32 */
755
54168ed7 756/*
05c3dc2c 757 * Saves all the IO-APIC RTE's
54168ed7 758 */
31dce14a 759int save_ioapic_entries(void)
54168ed7 760{
54168ed7 761 int apic, pin;
31dce14a 762 int err = 0;
54168ed7
IM		 763
764 for (apic = 0; apic < nr_ioapics; apic++) {
57a6f740 765 if (!ioapics[apic].saved_registers) {
31dce14a
SS		 766 err = -ENOMEM;
767 continue;
768 }
54168ed7 769
b69c6c3b 770 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
57a6f740 771 ioapics[apic].saved_registers[pin] =
54168ed7 772 ioapic_read_entry(apic, pin);
b24696bc 773 }
5ffa4eb2 774
31dce14a 775 return err;
54168ed7
IM		 776}
777
b24696bc
FY		 778/*
779 * Mask all IO APIC entries.
780 */
31dce14a 781void mask_ioapic_entries(void)
05c3dc2c
SS		 782{
783 int apic, pin;
784
785 for (apic = 0; apic < nr_ioapics; apic++) {
2f344d2e 786 if (!ioapics[apic].saved_registers)
31dce14a 787 continue;
b24696bc 788
b69c6c3b 789 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
05c3dc2c
SS		 790 struct IO_APIC_route_entry entry;
791
57a6f740 792 entry = ioapics[apic].saved_registers[pin];
05c3dc2c
SS		 793 if (!entry.mask) {
794 entry.mask = 1;
795 ioapic_write_entry(apic, pin, entry);
796 }
797 }
798 }
799}
800
b24696bc 801/*
57a6f740 802 * Restore IO APIC entries which was saved in the ioapic structure.
b24696bc 803 */
31dce14a 804int restore_ioapic_entries(void)
54168ed7
IM		 805{
806 int apic, pin;
807
5ffa4eb2 808 for (apic = 0; apic < nr_ioapics; apic++) {
2f344d2e 809 if (!ioapics[apic].saved_registers)
31dce14a 810 continue;
b24696bc 811
b69c6c3b 812 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
54168ed7 813 ioapic_write_entry(apic, pin,
57a6f740 814 ioapics[apic].saved_registers[pin]);
5ffa4eb2 815 }
b24696bc 816 return 0;
54168ed7
IM		 817}
818
1da177e4
LT		 819/*
820 * Find the IRQ entry number of a certain pin.
821 */
6f50d45f 822static int find_irq_entry(int ioapic_idx, int pin, int type)
1da177e4
LT		 823{
824 int i;
825
826 for (i = 0; i < mp_irq_entries; i++)
c2c21745 827 if (mp_irqs[i].irqtype == type &&
6f50d45f 828 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
c2c21745
JSR		 829 mp_irqs[i].dstapic == MP_APIC_ALL) &&
830 mp_irqs[i].dstirq == pin)
1da177e4
LT		 831 return i;
832
833 return -1;
834}
835
836/*
837 * Find the pin to which IRQ[irq] (ISA) is connected
838 */
fcfd636a 839static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 840{
841 int i;
842
843 for (i = 0; i < mp_irq_entries; i++) {
c2c21745 844 int lbus = mp_irqs[i].srcbus;
1da177e4 845
d27e2b8e 846 if (test_bit(lbus, mp_bus_not_pci) &&
c2c21745
JSR		 847 (mp_irqs[i].irqtype == type) &&
848 (mp_irqs[i].srcbusirq == irq))
1da177e4 849
c2c21745 850 return mp_irqs[i].dstirq;
1da177e4
LT		 851 }
852 return -1;
853}
854
fcfd636a
EB		 855static int __init find_isa_irq_apic(int irq, int type)
856{
857 int i;
858
859 for (i = 0; i < mp_irq_entries; i++) {
c2c21745 860 int lbus = mp_irqs[i].srcbus;
fcfd636a 861
73b2961b 862 if (test_bit(lbus, mp_bus_not_pci) &&
c2c21745
JSR		 863 (mp_irqs[i].irqtype == type) &&
864 (mp_irqs[i].srcbusirq == irq))
fcfd636a
EB		 865 break;
866 }
6f50d45f 867
fcfd636a 868 if (i < mp_irq_entries) {
6f50d45f
YL		 869 int ioapic_idx;
870
871 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
872 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
873 return ioapic_idx;
fcfd636a
EB		 874 }
875
876 return -1;
877}
878
c0a282c2 879#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1da177e4
LT		 880/*
881 * EISA Edge/Level control register, ELCR
882 */
883static int EISA_ELCR(unsigned int irq)
884{
b81bb373 885 if (irq < legacy_pic->nr_legacy_irqs) {
1da177e4
LT		 886 unsigned int port = 0x4d0 + (irq >> 3);
887 return (inb(port) >> (irq & 7)) & 1;
888 }
889 apic_printk(APIC_VERBOSE, KERN_INFO
890 "Broken MPtable reports ISA irq %d\n", irq);
891 return 0;
892}
54168ed7 893
c0a282c2 894#endif
1da177e4 895
6728801d
AS		 896/* ISA interrupts are always polarity zero edge triggered,
897 * when listed as conforming in the MP table. */
898
899#define default_ISA_trigger(idx) (0)
900#define default_ISA_polarity(idx) (0)
901
1da177e4
LT		 902/* EISA interrupts are always polarity zero and can be edge or level
903 * trigger depending on the ELCR value. If an interrupt is listed as
904 * EISA conforming in the MP table, that means its trigger type must
905 * be read in from the ELCR */
906
c2c21745 907#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
6728801d 908#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1da177e4
LT		 909
910/* PCI interrupts are always polarity one level triggered,
911 * when listed as conforming in the MP table. */
912
913#define default_PCI_trigger(idx) (1)
914#define default_PCI_polarity(idx) (1)
915
916/* MCA interrupts are always polarity zero level triggered,
917 * when listed as conforming in the MP table. */
918
919#define default_MCA_trigger(idx) (1)
6728801d 920#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1da177e4 921
b77cf6a8 922static int irq_polarity(int idx)
1da177e4 923{
c2c21745 924 int bus = mp_irqs[idx].srcbus;
1da177e4
LT		 925 int polarity;
926
927 /*
928 * Determine IRQ line polarity (high active or low active):
929 */
c2c21745 930 switch (mp_irqs[idx].irqflag & 3)
36062448 931 {
54168ed7
IM		 932 case 0: /* conforms, ie. bus-type dependent polarity */
933 if (test_bit(bus, mp_bus_not_pci))
934 polarity = default_ISA_polarity(idx);
935 else
936 polarity = default_PCI_polarity(idx);
937 break;
938 case 1: /* high active */
939 {
940 polarity = 0;
941 break;
942 }
943 case 2: /* reserved */
944 {
945 printk(KERN_WARNING "broken BIOS!!\n");
946 polarity = 1;
947 break;
948 }
949 case 3: /* low active */
950 {
951 polarity = 1;
952 break;
953 }
954 default: /* invalid */
955 {
956 printk(KERN_WARNING "broken BIOS!!\n");
957 polarity = 1;
958 break;
959 }
1da177e4
LT		 960 }
961 return polarity;
962}
963
b77cf6a8 964static int irq_trigger(int idx)
1da177e4 965{
c2c21745 966 int bus = mp_irqs[idx].srcbus;
1da177e4
LT		 967 int trigger;
968
969 /*
970 * Determine IRQ trigger mode (edge or level sensitive):
971 */
c2c21745 972 switch ((mp_irqs[idx].irqflag>>2) & 3)
1da177e4 973 {
54168ed7
IM		 974 case 0: /* conforms, ie. bus-type dependent */
975 if (test_bit(bus, mp_bus_not_pci))
976 trigger = default_ISA_trigger(idx);
977 else
978 trigger = default_PCI_trigger(idx);
c0a282c2 979#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
54168ed7
IM		 980 switch (mp_bus_id_to_type[bus]) {
981 case MP_BUS_ISA: /* ISA pin */
982 {
983 /* set before the switch */
984 break;
985 }
986 case MP_BUS_EISA: /* EISA pin */
987 {
988 trigger = default_EISA_trigger(idx);
989 break;
990 }
991 case MP_BUS_PCI: /* PCI pin */
992 {
993 /* set before the switch */
994 break;
995 }
996 case MP_BUS_MCA: /* MCA pin */
997 {
998 trigger = default_MCA_trigger(idx);
999 break;
1000 }
1001 default:
1002 {
1003 printk(KERN_WARNING "broken BIOS!!\n");
1004 trigger = 1;
1005 break;
1006 }
1007 }
1008#endif
1da177e4 1009 break;
54168ed7 1010 case 1: /* edge */
1da177e4 1011 {
54168ed7 1012 trigger = 0;
1da177e4
LT		 1013 break;
1014 }
54168ed7 1015 case 2: /* reserved */
1da177e4 1016 {
54168ed7
IM		 1017 printk(KERN_WARNING "broken BIOS!!\n");
1018 trigger = 1;
1da177e4
LT		 1019 break;
1020 }
54168ed7 1021 case 3: /* level */
1da177e4 1022 {
54168ed7 1023 trigger = 1;
1da177e4
LT		 1024 break;
1025 }
54168ed7 1026 default: /* invalid */
1da177e4
LT		 1027 {
1028 printk(KERN_WARNING "broken BIOS!!\n");
54168ed7 1029 trigger = 0;
1da177e4
LT		 1030 break;
1031 }
1032 }
1033 return trigger;
1034}
1035
1da177e4
LT		 1036static int pin_2_irq(int idx, int apic, int pin)
1037{
d464207c 1038 int irq;
c2c21745 1039 int bus = mp_irqs[idx].srcbus;
c040aaeb 1040 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1da177e4
LT		 1041
1042 /*
1043 * Debugging check, we are in big trouble if this message pops up!
1044 */
c2c21745 1045 if (mp_irqs[idx].dstirq != pin)
1da177e4
LT		 1046 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1047
54168ed7 1048 if (test_bit(bus, mp_bus_not_pci)) {
c2c21745 1049 irq = mp_irqs[idx].srcbusirq;
54168ed7 1050 } else {
c040aaeb 1051 u32 gsi = gsi_cfg->gsi_base + pin;
988856ee
EB		 1052
1053 if (gsi >= NR_IRQS_LEGACY)
1054 irq = gsi;
1055 else
a4384df3 1056 irq = gsi_top + gsi;
1da177e4
LT		 1057 }
1058
54168ed7 1059#ifdef CONFIG_X86_32
1da177e4
LT		 1060 /*
1061 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1062 */
1063 if ((pin >= 16) && (pin <= 23)) {
1064 if (pirq_entries[pin-16] != -1) {
1065 if (!pirq_entries[pin-16]) {
1066 apic_printk(APIC_VERBOSE, KERN_DEBUG
1067 "disabling PIRQ%d\n", pin-16);
1068 } else {
1069 irq = pirq_entries[pin-16];
1070 apic_printk(APIC_VERBOSE, KERN_DEBUG
1071 "using PIRQ%d -> IRQ %d\n",
1072 pin-16, irq);
1073 }
1074 }
1075 }
54168ed7
IM		 1076#endif
1077
1da177e4
LT		 1078 return irq;
1079}
1080
e20c06fd
YL		 1081/*
1082 * Find a specific PCI IRQ entry.
1083 * Not an __init, possibly needed by modules
1084 */
1085int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
e5198075 1086 struct io_apic_irq_attr *irq_attr)
e20c06fd 1087{
6f50d45f 1088 int ioapic_idx, i, best_guess = -1;
e20c06fd
YL		 1089
1090 apic_printk(APIC_DEBUG,
1091 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1092 bus, slot, pin);
1093 if (test_bit(bus, mp_bus_not_pci)) {
1094 apic_printk(APIC_VERBOSE,
1095 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1096 return -1;
1097 }
1098 for (i = 0; i < mp_irq_entries; i++) {
1099 int lbus = mp_irqs[i].srcbus;
1100
6f50d45f
YL		 1101 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1102 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
e20c06fd
YL		 1103 mp_irqs[i].dstapic == MP_APIC_ALL)
1104 break;
1105
1106 if (!test_bit(lbus, mp_bus_not_pci) &&
1107 !mp_irqs[i].irqtype &&
1108 (bus == lbus) &&
1109 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
6f50d45f 1110 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
e20c06fd 1111
6f50d45f 1112 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
e20c06fd
YL		 1113 continue;
1114
1115 if (pin == (mp_irqs[i].srcbusirq & 3)) {
6f50d45f 1116 set_io_apic_irq_attr(irq_attr, ioapic_idx,
e5198075
YL		 1117 mp_irqs[i].dstirq,
1118 irq_trigger(i),
1119 irq_polarity(i));
e20c06fd
YL		 1120 return irq;
1121 }
1122 /*
1123 * Use the first all-but-pin matching entry as a
1124 * best-guess fuzzy result for broken mptables.
1125 */
1126 if (best_guess < 0) {
6f50d45f 1127 set_io_apic_irq_attr(irq_attr, ioapic_idx,
e5198075
YL		 1128 mp_irqs[i].dstirq,
1129 irq_trigger(i),
1130 irq_polarity(i));
e20c06fd
YL		 1131 best_guess = irq;
1132 }
1133 }
1134 }
1135 return best_guess;
1136}
1137EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1138
497c9a19
YL		 1139void lock_vector_lock(void)
1140{
1141 /* Used to the online set of cpus does not change
1142 * during assign_irq_vector.
1143 */
dade7716 1144 raw_spin_lock(&vector_lock);
497c9a19 1145}
1da177e4 1146
497c9a19 1147void unlock_vector_lock(void)
1da177e4 1148{
dade7716 1149 raw_spin_unlock(&vector_lock);
497c9a19 1150}
1da177e4 1151
e7986739
MT		 1152static int
1153__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
497c9a19 1154{
047c8fdb
YL		 1155 /*
1156 * NOTE! The local APIC isn't very good at handling
1157 * multiple interrupts at the same interrupt level.
1158 * As the interrupt level is determined by taking the
1159 * vector number and shifting that right by 4, we
1160 * want to spread these out a bit so that they don't
1161 * all fall in the same interrupt level.
1162 *
1163 * Also, we've got to be careful not to trash gate
1164 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1165 */
6579b474 1166 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
ea943966 1167 static int current_offset = VECTOR_OFFSET_START % 8;
54168ed7 1168 unsigned int old_vector;
22f65d31
MT		 1169 int cpu, err;
1170 cpumask_var_t tmp_mask;
ace80ab7 1171
23359a88 1172 if (cfg->move_in_progress)
54168ed7 1173 return -EBUSY;
0a1ad60d 1174
22f65d31
MT		 1175 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1176 return -ENOMEM;
ace80ab7 1177
54168ed7
IM		 1178 old_vector = cfg->vector;
1179 if (old_vector) {
22f65d31
MT		 1180 cpumask_and(tmp_mask, mask, cpu_online_mask);
1181 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1182 if (!cpumask_empty(tmp_mask)) {
1183 free_cpumask_var(tmp_mask);
54168ed7 1184 return 0;
22f65d31 1185 }
54168ed7 1186 }
497c9a19 1187
e7986739 1188 /* Only try and allocate irqs on cpus that are present */
22f65d31
MT		 1189 err = -ENOSPC;
1190 for_each_cpu_and(cpu, mask, cpu_online_mask) {
54168ed7
IM		 1191 int new_cpu;
1192 int vector, offset;
497c9a19 1193
e2d40b18 1194 apic->vector_allocation_domain(cpu, tmp_mask);
497c9a19 1195
54168ed7
IM		 1196 vector = current_vector;
1197 offset = current_offset;
497c9a19 1198next:
54168ed7
IM		 1199 vector += 8;
1200 if (vector >= first_system_vector) {
e7986739 1201 /* If out of vectors on large boxen, must share them. */
54168ed7 1202 offset = (offset + 1) % 8;
6579b474 1203 vector = FIRST_EXTERNAL_VECTOR + offset;
54168ed7
IM		 1204 }
1205 if (unlikely(current_vector == vector))
1206 continue;
b77b881f
YL		 1207
1208 if (test_bit(vector, used_vectors))
54168ed7 1209 goto next;
b77b881f 1210
22f65d31 1211 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
54168ed7
IM		 1212 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1213 goto next;
1214 /* Found one! */
1215 current_vector = vector;
1216 current_offset = offset;
1217 if (old_vector) {
1218 cfg->move_in_progress = 1;
22f65d31 1219 cpumask_copy(cfg->old_domain, cfg->domain);
7a959cff 1220 }
22f65d31 1221 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
54168ed7
IM		 1222 per_cpu(vector_irq, new_cpu)[vector] = irq;
1223 cfg->vector = vector;
22f65d31
MT		 1224 cpumask_copy(cfg->domain, tmp_mask);
1225 err = 0;
1226 break;
54168ed7 1227 }
22f65d31
MT		 1228 free_cpumask_var(tmp_mask);
1229 return err;
497c9a19
YL		 1230}
1231
9338ad6f 1232int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
497c9a19
YL		 1233{
1234 int err;
ace80ab7 1235 unsigned long flags;
ace80ab7 1236
dade7716 1237 raw_spin_lock_irqsave(&vector_lock, flags);
3145e941 1238 err = __assign_irq_vector(irq, cfg, mask);
dade7716 1239 raw_spin_unlock_irqrestore(&vector_lock, flags);
497c9a19
YL		 1240 return err;
1241}
1242
3145e941 1243static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
497c9a19 1244{
497c9a19
YL		 1245 int cpu, vector;
1246
497c9a19
YL		 1247 BUG_ON(!cfg->vector);
1248
1249 vector = cfg->vector;
22f65d31 1250 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
497c9a19
YL		 1251 per_cpu(vector_irq, cpu)[vector] = -1;
1252
1253 cfg->vector = 0;
22f65d31 1254 cpumask_clear(cfg->domain);
0ca4b6b0
MW		 1255
1256 if (likely(!cfg->move_in_progress))
1257 return;
22f65d31 1258 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
0ca4b6b0
MW		 1259 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1260 vector++) {
1261 if (per_cpu(vector_irq, cpu)[vector] != irq)
1262 continue;
1263 per_cpu(vector_irq, cpu)[vector] = -1;
1264 break;
1265 }
1266 }
1267 cfg->move_in_progress = 0;
497c9a19
YL		 1268}
1269
1270void __setup_vector_irq(int cpu)
1271{
1272 /* Initialize vector_irq on a new cpu */
497c9a19
YL		 1273 int irq, vector;
1274 struct irq_cfg *cfg;
1275
9d133e5d
SS		 1276 /*
1277 * vector_lock will make sure that we don't run into irq vector
1278 * assignments that might be happening on another cpu in parallel,
1279 * while we setup our initial vector to irq mappings.
1280 */
dade7716 1281 raw_spin_lock(&vector_lock);
497c9a19 1282 /* Mark the inuse vectors */
ad9f4334 1283 for_each_active_irq(irq) {
2c778651 1284 cfg = irq_get_chip_data(irq);
ad9f4334
TG		 1285 if (!cfg)
1286 continue;
36e9e1ea
SS		 1287 /*
1288 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1289 * will be part of the irq_cfg's domain.
1290 */
1291 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1292 cpumask_set_cpu(cpu, cfg->domain);
1293
22f65d31 1294 if (!cpumask_test_cpu(cpu, cfg->domain))
497c9a19
YL		 1295 continue;
1296 vector = cfg->vector;
497c9a19
YL		 1297 per_cpu(vector_irq, cpu)[vector] = irq;
1298 }
1299 /* Mark the free vectors */
1300 for (vector = 0; vector < NR_VECTORS; ++vector) {
1301 irq = per_cpu(vector_irq, cpu)[vector];
1302 if (irq < 0)
1303 continue;
1304
1305 cfg = irq_cfg(irq);
22f65d31 1306 if (!cpumask_test_cpu(cpu, cfg->domain))
497c9a19 1307 per_cpu(vector_irq, cpu)[vector] = -1;
54168ed7 1308 }
dade7716 1309 raw_spin_unlock(&vector_lock);
1da177e4 1310}
3fde6900 1311
f5b9ed7a 1312static struct irq_chip ioapic_chip;
1da177e4 1313
047c8fdb 1314#ifdef CONFIG_X86_32
1d025192
YL		 1315static inline int IO_APIC_irq_trigger(int irq)
1316{
d6c88a50 1317 int apic, idx, pin;
1d025192 1318
d6c88a50 1319 for (apic = 0; apic < nr_ioapics; apic++) {
b69c6c3b 1320 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
d6c88a50
TG		 1321 idx = find_irq_entry(apic, pin, mp_INT);
1322 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1323 return irq_trigger(idx);
1324 }
1325 }
1326 /*
54168ed7
IM		 1327 * nonexistent IRQs are edge default
1328 */
d6c88a50 1329 return 0;
1d025192 1330}
047c8fdb
YL		 1331#else
1332static inline int IO_APIC_irq_trigger(int irq)
1333{
54168ed7 1334 return 1;
047c8fdb
YL		 1335}
1336#endif
1d025192 1337
1a0e62a4
TG		 1338static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1339 unsigned long trigger)
1da177e4 1340{
c60eaf25
TG		 1341 struct irq_chip *chip = &ioapic_chip;
1342 irq_flow_handler_t hdl;
1343 bool fasteoi;
199751d7 1344
6ebcc00e 1345 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
c60eaf25 1346 trigger == IOAPIC_LEVEL) {
60c69948 1347 irq_set_status_flags(irq, IRQ_LEVEL);
c60eaf25
TG		 1348 fasteoi = true;
1349 } else {
60c69948 1350 irq_clear_status_flags(irq, IRQ_LEVEL);
c60eaf25
TG		 1351 fasteoi = false;
1352 }
047c8fdb 1353
1a0e62a4 1354 if (irq_remapped(cfg)) {
60c69948 1355 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
c39d77ff 1356 irq_remap_modify_chip_defaults(chip);
c60eaf25 1357 fasteoi = trigger != 0;
54168ed7 1358 }
29b61be6 1359
c60eaf25
TG		 1360 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1361 irq_set_chip_and_handler_name(irq, chip, hdl,
1362 fasteoi ? "fasteoi" : "edge");
1da177e4
LT		 1363}
1364
c5b4712c
YL		 1365static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1366 unsigned int destination, int vector,
1367 struct io_apic_irq_attr *attr)
1368{
1369 if (intr_remapping_enabled)
0c3f173a
JR		 1370 return intr_setup_ioapic_entry(irq, entry, destination,
1371 vector, attr);
497c9a19 1372
c5b4712c
YL		 1373 memset(entry, 0, sizeof(*entry));
1374
1375 entry->delivery_mode = apic->irq_delivery_mode;
1376 entry->dest_mode = apic->irq_dest_mode;
1377 entry->dest = destination;
1378 entry->vector = vector;
1379 entry->mask = 0; /* enable IRQ */
1380 entry->trigger = attr->trigger;
1381 entry->polarity = attr->polarity;
1382
1383 /*
1384 * Mask level triggered irqs.
497c9a19
YL		 1385 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1386 */
c5b4712c 1387 if (attr->trigger)
497c9a19 1388 entry->mask = 1;
c5b4712c 1389
497c9a19
YL		 1390 return 0;
1391}
1392
e4aff811
YL		 1393static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1394 struct io_apic_irq_attr *attr)
497c9a19 1395{
1da177e4 1396 struct IO_APIC_route_entry entry;
22f65d31 1397 unsigned int dest;
497c9a19
YL		 1398
1399 if (!IO_APIC_IRQ(irq))
1400 return;
69c89efb
SS		 1401 /*
1402 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1403 * controllers like 8259. Now that IO-APIC can handle this irq, update
1404 * the cfg->domain.
1405 */
28c6a0ba 1406 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
69c89efb
SS		 1407 apic->vector_allocation_domain(0, cfg->domain);
1408
fe402e1f 1409 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
497c9a19
YL		 1410 return;
1411
debccb3e 1412 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
497c9a19
YL		 1413
1414 apic_printk(APIC_VERBOSE,KERN_DEBUG
1415 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
7fece832 1416 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
e4aff811
YL		 1417 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1418 cfg->vector, irq, attr->trigger, attr->polarity, dest);
497c9a19 1419
c5b4712c
YL		 1420 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1421 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1422 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
3145e941 1423 __clear_irq_vector(irq, cfg);
c5b4712c 1424
497c9a19
YL		 1425 return;
1426 }
1427
e4aff811 1428 ioapic_register_intr(irq, cfg, attr->trigger);
b81bb373 1429 if (irq < legacy_pic->nr_legacy_irqs)
4305df94 1430 legacy_pic->mask(irq);
497c9a19 1431
e4aff811 1432 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
497c9a19
YL		 1433}
1434
6f50d45f 1435static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
c8d6b8fe
TG		 1436{
1437 if (idx != -1)
1438 return false;
1439
1440 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
6f50d45f 1441 mpc_ioapic_id(ioapic_idx), pin);
c8d6b8fe
TG		 1442 return true;
1443}
1444
6f50d45f 1445static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
497c9a19 1446{
ed972ccf 1447 int idx, node = cpu_to_node(0);
2d57e37d 1448 struct io_apic_irq_attr attr;
ed972ccf 1449 unsigned int pin, irq;
1da177e4 1450
6f50d45f
YL		 1451 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1452 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1453 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
b9c61b70 1454 continue;
33a201fa 1455
6f50d45f 1456 irq = pin_2_irq(idx, ioapic_idx, pin);
33a201fa 1457
6f50d45f 1458 if ((ioapic_idx > 0) && (irq > 16))
fad53995
EB		 1459 continue;
1460
b9c61b70
YL		 1461 /*
1462 * Skip the timer IRQ if there's a quirk handler
1463 * installed and if it returns 1:
1464 */
1465 if (apic->multi_timer_check &&
6f50d45f 1466 apic->multi_timer_check(ioapic_idx, irq))
b9c61b70 1467 continue;
36062448 1468
6f50d45f 1469 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
2d57e37d 1470 irq_polarity(idx));
fbc6bff0 1471
2d57e37d 1472 io_apic_setup_irq_pin(irq, node, &attr);
1da177e4 1473 }
1da177e4
LT		 1474}
1475
ed972ccf
TG		 1476static void __init setup_IO_APIC_irqs(void)
1477{
6f50d45f 1478 unsigned int ioapic_idx;
ed972ccf
TG		 1479
1480 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1481
6f50d45f
YL		 1482 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1483 __io_apic_setup_irqs(ioapic_idx);
ed972ccf
TG		 1484}
1485
18dce6ba
YL		 1486/*
1487 * for the gsit that is not in first ioapic
1488 * but could not use acpi_register_gsi()
1489 * like some special sci in IBM x3330
1490 */
1491void setup_IO_APIC_irq_extra(u32 gsi)
1492{
6f50d45f 1493 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
da1ad9d7 1494 struct io_apic_irq_attr attr;
18dce6ba
YL		 1495
1496 /*
1497 * Convert 'gsi' to 'ioapic.pin'.
1498 */
6f50d45f
YL		 1499 ioapic_idx = mp_find_ioapic(gsi);
1500 if (ioapic_idx < 0)
18dce6ba
YL		 1501 return;
1502
6f50d45f
YL		 1503 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1504 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
18dce6ba
YL		 1505 if (idx == -1)
1506 return;
1507
6f50d45f 1508 irq = pin_2_irq(idx, ioapic_idx, pin);
fe6dab4e
YL		 1509
1510 /* Only handle the non legacy irqs on secondary ioapics */
6f50d45f 1511 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
18dce6ba 1512 return;
fe6dab4e 1513
6f50d45f 1514 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
da1ad9d7
TG		 1515 irq_polarity(idx));
1516
710dcda6 1517 io_apic_setup_irq_pin_once(irq, node, &attr);
18dce6ba
YL		 1518}
1519
1da177e4 1520/*
f7633ce5 1521 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1522 */
6f50d45f
YL		 1523static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1524 unsigned int pin, int vector)
1da177e4
LT		 1525{
1526 struct IO_APIC_route_entry entry;
1da177e4 1527
54168ed7
IM		 1528 if (intr_remapping_enabled)
1529 return;
54168ed7 1530
36062448 1531 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 1532
1533 /*
1534 * We use logical delivery to get the timer IRQ
1535 * to the first CPU.
1536 */
9b5bc8dc 1537 entry.dest_mode = apic->irq_dest_mode;
f72dccac 1538 entry.mask = 0; /* don't mask IRQ for edge */
debccb3e 1539 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
9b5bc8dc 1540 entry.delivery_mode = apic->irq_delivery_mode;
1da177e4
LT		 1541 entry.polarity = 0;
1542 entry.trigger = 0;
1543 entry.vector = vector;
1544
1545 /*
1546 * The timer IRQ doesn't have to know that behind the
f7633ce5 1547 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1548 */
2c778651
TG		 1549 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1550 "edge");
1da177e4
LT		 1551
1552 /*
1553 * Add it to the IO-APIC irq-routing table:
1554 */
6f50d45f 1555 ioapic_write_entry(ioapic_idx, pin, entry);
1da177e4
LT		 1556}
1557
6f50d45f 1558__apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1da177e4 1559{
cda417dd 1560 int i;
1da177e4
LT		 1561 union IO_APIC_reg_00 reg_00;
1562 union IO_APIC_reg_01 reg_01;
1563 union IO_APIC_reg_02 reg_02;
1564 union IO_APIC_reg_03 reg_03;
1565 unsigned long flags;
1da177e4 1566
dade7716 1567 raw_spin_lock_irqsave(&ioapic_lock, flags);
6f50d45f
YL		 1568 reg_00.raw = io_apic_read(ioapic_idx, 0);
1569 reg_01.raw = io_apic_read(ioapic_idx, 1);
1da177e4 1570 if (reg_01.bits.version >= 0x10)
6f50d45f 1571 reg_02.raw = io_apic_read(ioapic_idx, 2);
d6c88a50 1572 if (reg_01.bits.version >= 0x20)
6f50d45f 1573 reg_03.raw = io_apic_read(ioapic_idx, 3);
dade7716 1574 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4 1575
54168ed7 1576 printk("\n");
6f50d45f 1577 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1da177e4
LT		 1578 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1579 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1580 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1581 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4 1582
54168ed7 1583 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
bd6a46e0
NC		 1584 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1585 reg_01.bits.entries);
1da177e4
LT		 1586
1587 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
bd6a46e0
NC		 1588 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1589 reg_01.bits.version);
1da177e4
LT		 1590
1591 /*
1592 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1593 * but the value of reg_02 is read as the previous read register
1594 * value, so ignore it if reg_02 == reg_01.
1595 */
1596 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1597 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1598 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1599 }
1600
1601 /*
1602 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1603 * or reg_03, but the value of reg_0[23] is read as the previous read
1604 * register value, so ignore it if reg_03 == reg_0[12].
1605 */
1606 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1607 reg_03.raw != reg_01.raw) {
1608 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1609 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1610 }
1611
1612 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1613
42f0efc5
NC		 1614 if (intr_remapping_enabled) {
1615 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1616 " Pol Stat Indx2 Zero Vect:\n");
1617 } else {
1618 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1619 " Stat Dmod Deli Vect:\n");
1620 }
1da177e4
LT		 1621
1622 for (i = 0; i <= reg_01.bits.entries; i++) {
42f0efc5
NC		 1623 if (intr_remapping_enabled) {
1624 struct IO_APIC_route_entry entry;
1625 struct IR_IO_APIC_route_entry *ir_entry;
1626
6f50d45f 1627 entry = ioapic_read_entry(ioapic_idx, i);
42f0efc5
NC		 1628 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1629 printk(KERN_DEBUG " %02x %04X ",
1630 i,
1631 ir_entry->index
1632 );
1633 printk("%1d %1d %1d %1d %1d "
1634 "%1d %1d %X %02X\n",
1635 ir_entry->format,
1636 ir_entry->mask,
1637 ir_entry->trigger,
1638 ir_entry->irr,
1639 ir_entry->polarity,
1640 ir_entry->delivery_status,
1641 ir_entry->index2,
1642 ir_entry->zero,
1643 ir_entry->vector
1644 );
1645 } else {
1646 struct IO_APIC_route_entry entry;
1647
6f50d45f 1648 entry = ioapic_read_entry(ioapic_idx, i);
42f0efc5
NC		 1649 printk(KERN_DEBUG " %02x %02X ",
1650 i,
1651 entry.dest
1652 );
1653 printk("%1d %1d %1d %1d %1d "
1654 "%1d %1d %02X\n",
1655 entry.mask,
1656 entry.trigger,
1657 entry.irr,
1658 entry.polarity,
1659 entry.delivery_status,
1660 entry.dest_mode,
1661 entry.delivery_mode,
1662 entry.vector
1663 );
1664 }
1da177e4 1665 }
cda417dd
YL		 1666}
1667
1668__apicdebuginit(void) print_IO_APICs(void)
1669{
6f50d45f 1670 int ioapic_idx;
cda417dd
YL		 1671 struct irq_cfg *cfg;
1672 unsigned int irq;
6fd36ba0 1673 struct irq_chip *chip;
cda417dd
YL		 1674
1675 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
6f50d45f 1676 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
cda417dd 1677 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
6f50d45f
YL		 1678 mpc_ioapic_id(ioapic_idx),
1679 ioapics[ioapic_idx].nr_registers);
cda417dd
YL		 1680
1681 /*
1682 * We are a bit conservative about what we expect. We have to
1683 * know about every hardware change ASAP.
1684 */
1685 printk(KERN_INFO "testing the IO APIC.......................\n");
1686
6f50d45f
YL		 1687 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1688 print_IO_APIC(ioapic_idx);
42f0efc5 1689
1da177e4 1690 printk(KERN_DEBUG "IRQ to pin mappings:\n");
ad9f4334 1691 for_each_active_irq(irq) {
0b8f1efa
YL		 1692 struct irq_pin_list *entry;
1693
6fd36ba0
MN		 1694 chip = irq_get_chip(irq);
1695 if (chip != &ioapic_chip)
1696 continue;
1697
2c778651 1698 cfg = irq_get_chip_data(irq);
05e40760
DK		 1699 if (!cfg)
1700 continue;
0b8f1efa 1701 entry = cfg->irq_2_pin;
0f978f45 1702 if (!entry)
1da177e4 1703 continue;
8f09cd20 1704 printk(KERN_DEBUG "IRQ%d ", irq);
2977fb3f 1705 for_each_irq_pin(entry, cfg->irq_2_pin)
1da177e4 1706 printk("-> %d:%d", entry->apic, entry->pin);
1da177e4
LT		 1707 printk("\n");
1708 }
1709
1710 printk(KERN_INFO ".................................... done.\n");
1da177e4
LT		 1711}
1712
251e1e44 1713__apicdebuginit(void) print_APIC_field(int base)
1da177e4 1714{
251e1e44 1715 int i;
1da177e4 1716
251e1e44
IM		 1717 printk(KERN_DEBUG);
1718
1719 for (i = 0; i < 8; i++)
1720 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1721
1722 printk(KERN_CONT "\n");
1da177e4
LT		 1723}
1724
32f71aff 1725__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4 1726{
97a52714 1727 unsigned int i, v, ver, maxlvt;
7ab6af7a 1728 u64 icr;
1da177e4 1729
251e1e44 1730 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1da177e4 1731 smp_processor_id(), hard_smp_processor_id());
66823114 1732 v = apic_read(APIC_ID);
54168ed7 1733 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1734 v = apic_read(APIC_LVR);
1735 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1736 ver = GET_APIC_VERSION(v);
e05d723f 1737 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1738
1739 v = apic_read(APIC_TASKPRI);
1740 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1741
54168ed7 1742 if (APIC_INTEGRATED(ver)) { /* !82489DX */
a11b5abe
YL		 1743 if (!APIC_XAPIC(ver)) {
1744 v = apic_read(APIC_ARBPRI);
1745 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1746 v & APIC_ARBPRI_MASK);
1747 }
1da177e4
LT		 1748 v = apic_read(APIC_PROCPRI);
1749 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1750 }
1751
a11b5abe
YL		 1752 /*
1753 * Remote read supported only in the 82489DX and local APIC for
1754 * Pentium processors.
1755 */
1756 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1757 v = apic_read(APIC_RRR);
1758 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1759 }
1760
1da177e4
LT		 1761 v = apic_read(APIC_LDR);
1762 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
a11b5abe
YL		 1763 if (!x2apic_enabled()) {
1764 v = apic_read(APIC_DFR);
1765 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1766 }
1da177e4
LT		 1767 v = apic_read(APIC_SPIV);
1768 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1769
1770 printk(KERN_DEBUG "... APIC ISR field:\n");
251e1e44 1771 print_APIC_field(APIC_ISR);
1da177e4 1772 printk(KERN_DEBUG "... APIC TMR field:\n");
251e1e44 1773 print_APIC_field(APIC_TMR);
1da177e4 1774 printk(KERN_DEBUG "... APIC IRR field:\n");
251e1e44 1775 print_APIC_field(APIC_IRR);
1da177e4 1776
54168ed7
IM		 1777 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1778 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1da177e4 1779 apic_write(APIC_ESR, 0);
54168ed7 1780
1da177e4
LT		 1781 v = apic_read(APIC_ESR);
1782 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1783 }
1784
7ab6af7a 1785 icr = apic_icr_read();
0c425cec
IM		 1786 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1787 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1788
1789 v = apic_read(APIC_LVTT);
1790 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1791
1792 if (maxlvt > 3) { /* PC is LVT#4. */
1793 v = apic_read(APIC_LVTPC);
1794 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1795 }
1796 v = apic_read(APIC_LVT0);
1797 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1798 v = apic_read(APIC_LVT1);
1799 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1800
1801 if (maxlvt > 2) { /* ERR is LVT#3. */
1802 v = apic_read(APIC_LVTERR);
1803 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1804 }
1805
1806 v = apic_read(APIC_TMICT);
1807 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1808 v = apic_read(APIC_TMCCT);
1809 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1810 v = apic_read(APIC_TDCR);
1811 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
97a52714
AH		 1812
1813 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1814 v = apic_read(APIC_EFEAT);
1815 maxlvt = (v >> 16) & 0xff;
1816 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1817 v = apic_read(APIC_ECTRL);
1818 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1819 for (i = 0; i < maxlvt; i++) {
1820 v = apic_read(APIC_EILVTn(i));
1821 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1822 }
1823 }
1da177e4
LT		 1824 printk("\n");
1825}
1826
2626eb2b 1827__apicdebuginit(void) print_local_APICs(int maxcpu)
1da177e4 1828{
ffd5aae7
YL		 1829 int cpu;
1830
2626eb2b
CG		 1831 if (!maxcpu)
1832 return;
1833
ffd5aae7 1834 preempt_disable();
2626eb2b
CG		 1835 for_each_online_cpu(cpu) {
1836 if (cpu >= maxcpu)
1837 break;
ffd5aae7 1838 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
2626eb2b 1839 }
ffd5aae7 1840 preempt_enable();
1da177e4
LT		 1841}
1842
32f71aff 1843__apicdebuginit(void) print_PIC(void)
1da177e4 1844{
1da177e4
LT		 1845 unsigned int v;
1846 unsigned long flags;
1847
b81bb373 1848 if (!legacy_pic->nr_legacy_irqs)
1da177e4
LT		 1849 return;
1850
1851 printk(KERN_DEBUG "\nprinting PIC contents\n");
1852
5619c280 1853 raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4
LT		 1854
1855 v = inb(0xa1) << 8 | inb(0x21);
1856 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1857
1858 v = inb(0xa0) << 8 | inb(0x20);
1859 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1860
54168ed7
IM		 1861 outb(0x0b,0xa0);
1862 outb(0x0b,0x20);
1da177e4 1863 v = inb(0xa0) << 8 | inb(0x20);
54168ed7
IM		 1864 outb(0x0a,0xa0);
1865 outb(0x0a,0x20);
1da177e4 1866
5619c280 1867 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4
LT		 1868
1869 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1870
1871 v = inb(0x4d1) << 8 | inb(0x4d0);
1872 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1873}
1874
2626eb2b
CG		 1875static int __initdata show_lapic = 1;
1876static __init int setup_show_lapic(char *arg)
1877{
1878 int num = -1;
1879
1880 if (strcmp(arg, "all") == 0) {
1881 show_lapic = CONFIG_NR_CPUS;
1882 } else {
1883 get_option(&arg, &num);
1884 if (num >= 0)
1885 show_lapic = num;
1886 }
1887
1888 return 1;
1889}
1890__setup("show_lapic=", setup_show_lapic);
1891
1892__apicdebuginit(int) print_ICs(void)
32f71aff 1893{
2626eb2b
CG		 1894 if (apic_verbosity == APIC_QUIET)
1895 return 0;
1896
32f71aff 1897 print_PIC();
4797f6b0
YL		 1898
1899 /* don't print out if apic is not there */
8312136f 1900 if (!cpu_has_apic && !apic_from_smp_config())
4797f6b0
YL		 1901 return 0;
1902
2626eb2b 1903 print_local_APICs(show_lapic);
cda417dd 1904 print_IO_APICs();
32f71aff
MR		 1905
1906 return 0;
1907}
1908
ded1f6ab 1909late_initcall(print_ICs);
32f71aff 1910
1da177e4 1911
efa2559f
YL		 1912/* Where if anywhere is the i8259 connect in external int mode */
1913static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1914
54168ed7 1915void __init enable_IO_APIC(void)
1da177e4 1916{
fcfd636a 1917 int i8259_apic, i8259_pin;
54168ed7 1918 int apic;
bc07844a 1919
b81bb373 1920 if (!legacy_pic->nr_legacy_irqs)
bc07844a
TG		 1921 return;
1922
54168ed7 1923 for(apic = 0; apic < nr_ioapics; apic++) {
fcfd636a
EB		 1924 int pin;
1925 /* See if any of the pins is in ExtINT mode */
b69c6c3b 1926 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
fcfd636a 1927 struct IO_APIC_route_entry entry;
cf4c6a2f 1928 entry = ioapic_read_entry(apic, pin);
fcfd636a 1929
fcfd636a
EB		 1930 /* If the interrupt line is enabled and in ExtInt mode
1931 * I have found the pin where the i8259 is connected.
1932 */
1933 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1934 ioapic_i8259.apic = apic;
1935 ioapic_i8259.pin = pin;
1936 goto found_i8259;
1937 }
1938 }
1939 }
1940 found_i8259:
1941 /* Look to see what if the MP table has reported the ExtINT */
1942 /* If we could not find the appropriate pin by looking at the ioapic
1943 * the i8259 probably is not connected the ioapic but give the
1944 * mptable a chance anyway.
1945 */
1946 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1947 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1948 /* Trust the MP table if nothing is setup in the hardware */
1949 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1950 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1951 ioapic_i8259.pin = i8259_pin;
1952 ioapic_i8259.apic = i8259_apic;
1953 }
1954 /* Complain if the MP table and the hardware disagree */
1955 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1956 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1957 {
1958 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1959 }
1960
1961 /*
1962 * Do not trust the IO-APIC being empty at bootup
1963 */
1964 clear_IO_APIC();
1965}
1966
1967/*
1968 * Not an __init, needed by the reboot code
1969 */
1970void disable_IO_APIC(void)
1971{
1972 /*
1973 * Clear the IO-APIC before rebooting:
1974 */
1975 clear_IO_APIC();
1976
b81bb373 1977 if (!legacy_pic->nr_legacy_irqs)
bc07844a
TG		 1978 return;
1979
650927ef 1980 /*
0b968d23 1981 * If the i8259 is routed through an IOAPIC
650927ef 1982 * Put that IOAPIC in virtual wire mode
0b968d23 1983 * so legacy interrupts can be delivered.
7c6d9f97
SS		 1984 *
1985 * With interrupt-remapping, for now we will use virtual wire A mode,
1986 * as virtual wire B is little complex (need to configure both
0d2eb44f 1987 * IOAPIC RTE as well as interrupt-remapping table entry).
7c6d9f97 1988 * As this gets called during crash dump, keep this simple for now.
650927ef 1989 */
7c6d9f97 1990 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
650927ef 1991 struct IO_APIC_route_entry entry;
650927ef
EB		 1992
1993 memset(&entry, 0, sizeof(entry));
1994 entry.mask = 0; /* Enabled */
1995 entry.trigger = 0; /* Edge */
1996 entry.irr = 0;
1997 entry.polarity = 0; /* High */
1998 entry.delivery_status = 0;
1999 entry.dest_mode = 0; /* Physical */
fcfd636a 2000 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 2001 entry.vector = 0;
54168ed7 2002 entry.dest = read_apic_id();
650927ef
EB		 2003
2004 /*
2005 * Add it to the IO-APIC irq-routing table:
2006 */
cf4c6a2f 2007 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 2008 }
54168ed7 2009
7c6d9f97
SS		 2010 /*
2011 * Use virtual wire A mode when interrupt remapping is enabled.
2012 */
8312136f 2013 if (cpu_has_apic || apic_from_smp_config())
3f4c3955
CG		 2014 disconnect_bsp_APIC(!intr_remapping_enabled &&
2015 ioapic_i8259.pin != -1);
1da177e4
LT		 2016}
2017
54168ed7 2018#ifdef CONFIG_X86_32
1da177e4
LT		 2019/*
2020 * function to set the IO-APIC physical IDs based on the
2021 * values stored in the MPC table.
2022 *
2023 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2024 */
a38c5380 2025void __init setup_ioapic_ids_from_mpc_nocheck(void)
1da177e4
LT		 2026{
2027 union IO_APIC_reg_00 reg_00;
2028 physid_mask_t phys_id_present_map;
6f50d45f 2029 int ioapic_idx;
1da177e4
LT		 2030 int i;
2031 unsigned char old_id;
2032 unsigned long flags;
2033
2034 /*
2035 * This is broken; anything with a real cpu count has to
2036 * circumvent this idiocy regardless.
2037 */
7abc0753 2038 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1da177e4
LT		 2039
2040 /*
2041 * Set the IOAPIC ID to the value stored in the MPC table.
2042 */
6f50d45f 2043 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1da177e4 2044 /* Read the register 0 value */
dade7716 2045 raw_spin_lock_irqsave(&ioapic_lock, flags);
6f50d45f 2046 reg_00.raw = io_apic_read(ioapic_idx, 0);
dade7716 2047 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2048
6f50d45f 2049 old_id = mpc_ioapic_id(ioapic_idx);
1da177e4 2050
6f50d45f 2051 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1da177e4 2052 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
6f50d45f 2053 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1da177e4
LT		 2054 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2055 reg_00.bits.ID);
6f50d45f 2056 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1da177e4
LT		 2057 }
2058
1da177e4
LT		 2059 /*
2060 * Sanity check, is the ID really free? Every APIC in a
2061 * system must have a unique ID or we get lots of nice
2062 * 'stuck on smp_invalidate_needed IPI wait' messages.
2063 */
7abc0753 2064 if (apic->check_apicid_used(&phys_id_present_map,
6f50d45f 2065 mpc_ioapic_id(ioapic_idx))) {
1da177e4 2066 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
6f50d45f 2067 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1da177e4
LT		 2068 for (i = 0; i < get_physical_broadcast(); i++)
2069 if (!physid_isset(i, phys_id_present_map))
2070 break;
2071 if (i >= get_physical_broadcast())
2072 panic("Max APIC ID exceeded!\n");
2073 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2074 i);
2075 physid_set(i, phys_id_present_map);
6f50d45f 2076 ioapics[ioapic_idx].mp_config.apicid = i;
1da177e4
LT		 2077 } else {
2078 physid_mask_t tmp;
6f50d45f 2079 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
d5371430 2080 &tmp);
1da177e4
LT		 2081 apic_printk(APIC_VERBOSE, "Setting %d in the "
2082 "phys_id_present_map\n",
6f50d45f 2083 mpc_ioapic_id(ioapic_idx));
1da177e4
LT		 2084 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2085 }
2086
1da177e4
LT		 2087 /*
2088 * We need to adjust the IRQ routing table
2089 * if the ID changed.
2090 */
6f50d45f 2091 if (old_id != mpc_ioapic_id(ioapic_idx))
1da177e4 2092 for (i = 0; i < mp_irq_entries; i++)
c2c21745
JSR		 2093 if (mp_irqs[i].dstapic == old_id)
2094 mp_irqs[i].dstapic
6f50d45f 2095 = mpc_ioapic_id(ioapic_idx);
1da177e4
LT		 2096
2097 /*
60d79fd9
YL		 2098 * Update the ID register according to the right value
2099 * from the MPC table if they are different.
36062448 2100 */
6f50d45f 2101 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
60d79fd9
YL		 2102 continue;
2103
1da177e4
LT		 2104 apic_printk(APIC_VERBOSE, KERN_INFO
2105 "...changing IO-APIC physical APIC ID to %d ...",
6f50d45f 2106 mpc_ioapic_id(ioapic_idx));
1da177e4 2107
6f50d45f 2108 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
dade7716 2109 raw_spin_lock_irqsave(&ioapic_lock, flags);
6f50d45f 2110 io_apic_write(ioapic_idx, 0, reg_00.raw);
dade7716 2111 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 2112
2113 /*
2114 * Sanity check
2115 */
dade7716 2116 raw_spin_lock_irqsave(&ioapic_lock, flags);
6f50d45f 2117 reg_00.raw = io_apic_read(ioapic_idx, 0);
dade7716 2118 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
6f50d45f 2119 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1da177e4
LT		 2120 printk("could not set ID!\n");
2121 else
2122 apic_printk(APIC_VERBOSE, " ok.\n");
2123 }
2124}
a38c5380
SAS		 2125
2126void __init setup_ioapic_ids_from_mpc(void)
2127{
2128
2129 if (acpi_ioapic)
2130 return;
2131 /*
2132 * Don't check I/O APIC IDs for xAPIC systems. They have
2133 * no meaning without the serial APIC bus.
2134 */
2135 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2136 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2137 return;
2138 setup_ioapic_ids_from_mpc_nocheck();
2139}
54168ed7 2140#endif
1da177e4 2141
7ce0bcfd 2142int no_timer_check __initdata;
8542b200
ZA		 2143
2144static int __init notimercheck(char *s)
2145{
2146 no_timer_check = 1;
2147 return 1;
2148}
2149__setup("no_timer_check", notimercheck);
2150
1da177e4
LT		 2151/*
2152 * There is a nasty bug in some older SMP boards, their mptable lies
2153 * about the timer IRQ. We do the following to work around the situation:
2154 *
2155 * - timer IRQ defaults to IO-APIC IRQ
2156 * - if this function detects that timer IRQs are defunct, then we fall
2157 * back to ISA timer IRQs
2158 */
f0a7a5c9 2159static int __init timer_irq_works(void)
1da177e4
LT		 2160{
2161 unsigned long t1 = jiffies;
4aae0702 2162 unsigned long flags;
1da177e4 2163
8542b200
ZA		 2164 if (no_timer_check)
2165 return 1;
2166
4aae0702 2167 local_save_flags(flags);
1da177e4
LT		 2168 local_irq_enable();
2169 /* Let ten ticks pass... */
2170 mdelay((10 * 1000) / HZ);
4aae0702 2171 local_irq_restore(flags);
1da177e4
LT		 2172
2173 /*
2174 * Expect a few ticks at least, to be sure some possible
2175 * glue logic does not lock up after one or two first
2176 * ticks in a non-ExtINT mode. Also the local APIC
2177 * might have cached one ExtINT interrupt. Finally, at
2178 * least one tick may be lost due to delays.
2179 */
54168ed7
IM		 2180
2181 /* jiffies wrap? */
1d16b53e 2182 if (time_after(jiffies, t1 + 4))
1da177e4 2183 return 1;
1da177e4
LT		 2184 return 0;
2185}
2186
2187/*
2188 * In the SMP+IOAPIC case it might happen that there are an unspecified
2189 * number of pending IRQ events unhandled. These cases are very rare,
2190 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2191 * better to do it this way as thus we do not have to be aware of
2192 * 'pending' interrupts in the IRQ path, except at this point.
2193 */
2194/*
2195 * Edge triggered needs to resend any interrupt
2196 * that was delayed but this is now handled in the device
2197 * independent code.
2198 */
2199
2200/*
2201 * Starting up a edge-triggered IO-APIC interrupt is
2202 * nasty - we need to make sure that we get the edge.
2203 * If it is already asserted for some reason, we need
2204 * return 1 to indicate that is was pending.
2205 *
2206 * This is not complete - we should be able to fake
2207 * an edge even if it isn't on the 8259A...
2208 */
54168ed7 2209
61a38ce3 2210static unsigned int startup_ioapic_irq(struct irq_data *data)
1da177e4 2211{
61a38ce3 2212 int was_pending = 0, irq = data->irq;
1da177e4
LT		 2213 unsigned long flags;
2214
dade7716 2215 raw_spin_lock_irqsave(&ioapic_lock, flags);
b81bb373 2216 if (irq < legacy_pic->nr_legacy_irqs) {
4305df94 2217 legacy_pic->mask(irq);
b81bb373 2218 if (legacy_pic->irq_pending(irq))
1da177e4
LT		 2219 was_pending = 1;
2220 }
61a38ce3 2221 __unmask_ioapic(data->chip_data);
dade7716 2222 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 2223
2224 return was_pending;
2225}
2226
90297c5f 2227static int ioapic_retrigger_irq(struct irq_data *data)
1da177e4 2228{
90297c5f 2229 struct irq_cfg *cfg = data->chip_data;
54168ed7
IM		 2230 unsigned long flags;
2231
dade7716 2232 raw_spin_lock_irqsave(&vector_lock, flags);
dac5f412 2233 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
dade7716 2234 raw_spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 2235
2236 return 1;
2237}
497c9a19 2238
54168ed7
IM		 2239/*
2240 * Level and edge triggered IO-APIC interrupts need different handling,
2241 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2242 * handled with the level-triggered descriptor, but that one has slightly
2243 * more overhead. Level-triggered interrupts cannot be handled with the
2244 * edge-triggered handler, without risking IRQ storms and other ugly
2245 * races.
2246 */
497c9a19 2247
54168ed7 2248#ifdef CONFIG_SMP
9338ad6f 2249void send_cleanup_vector(struct irq_cfg *cfg)
e85abf8f
GH		 2250{
2251 cpumask_var_t cleanup_mask;
2252
2253 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2254 unsigned int i;
e85abf8f
GH		 2255 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2256 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2257 } else {
2258 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
e85abf8f
GH		 2259 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2260 free_cpumask_var(cleanup_mask);
2261 }
2262 cfg->move_in_progress = 0;
2263}
2264
4420471f 2265static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
e85abf8f
GH		 2266{
2267 int apic, pin;
2268 struct irq_pin_list *entry;
2269 u8 vector = cfg->vector;
2270
2977fb3f 2271 for_each_irq_pin(entry, cfg->irq_2_pin) {
e85abf8f
GH		 2272 unsigned int reg;
2273
e85abf8f
GH		 2274 apic = entry->apic;
2275 pin = entry->pin;
2276 /*
2277 * With interrupt-remapping, destination information comes
2278 * from interrupt-remapping table entry.
2279 */
1a0730d6 2280 if (!irq_remapped(cfg))
e85abf8f
GH		 2281 io_apic_write(apic, 0x11 + pin*2, dest);
2282 reg = io_apic_read(apic, 0x10 + pin*2);
2283 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2284 reg |= vector;
2285 io_apic_modify(apic, 0x10 + pin*2, reg);
e85abf8f
GH		 2286 }
2287}
2288
2289/*
f7e909ea 2290 * Either sets data->affinity to a valid value, and returns
18374d89 2291 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
f7e909ea 2292 * leaves data->affinity untouched.
e85abf8f 2293 */
f7e909ea
TG		 2294int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2295 unsigned int *dest_id)
e85abf8f 2296{
f7e909ea 2297 struct irq_cfg *cfg = data->chip_data;
e85abf8f
GH		 2298
2299 if (!cpumask_intersects(mask, cpu_online_mask))
18374d89 2300 return -1;
e85abf8f 2301
f7e909ea 2302 if (assign_irq_vector(data->irq, data->chip_data, mask))
18374d89 2303 return -1;
e85abf8f 2304
f7e909ea 2305 cpumask_copy(data->affinity, mask);
e85abf8f 2306
f7e909ea 2307 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
18374d89 2308 return 0;
e85abf8f
GH		 2309}
2310
4420471f 2311static int
f7e909ea
TG		 2312ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2313 bool force)
e85abf8f 2314{
f7e909ea 2315 unsigned int dest, irq = data->irq;
e85abf8f 2316 unsigned long flags;
f7e909ea 2317 int ret;
e85abf8f 2318
dade7716 2319 raw_spin_lock_irqsave(&ioapic_lock, flags);
f7e909ea 2320 ret = __ioapic_set_affinity(data, mask, &dest);
18374d89 2321 if (!ret) {
e85abf8f
GH		 2322 /* Only the high 8 bits are valid. */
2323 dest = SET_APIC_LOGICAL_ID(dest);
f7e909ea 2324 __target_IO_APIC_irq(irq, dest, data->chip_data);
e85abf8f 2325 }
dade7716 2326 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
4420471f 2327 return ret;
e85abf8f
GH		 2328}
2329
54168ed7
IM		 2330asmlinkage void smp_irq_move_cleanup_interrupt(void)
2331{
2332 unsigned vector, me;
8f2466f4 2333
54168ed7 2334 ack_APIC_irq();
54168ed7 2335 irq_enter();
98ad1cc1 2336 exit_idle();
54168ed7
IM		 2337
2338 me = smp_processor_id();
2339 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2340 unsigned int irq;
68a8ca59 2341 unsigned int irr;
54168ed7
IM		 2342 struct irq_desc *desc;
2343 struct irq_cfg *cfg;
0a3aee0d 2344 irq = __this_cpu_read(vector_irq[vector]);
54168ed7 2345
0b8f1efa
YL		 2346 if (irq == -1)
2347 continue;
2348
54168ed7
IM		 2349 desc = irq_to_desc(irq);
2350 if (!desc)
2351 continue;
2352
2353 cfg = irq_cfg(irq);
239007b8 2354 raw_spin_lock(&desc->lock);
54168ed7 2355
7f41c2e1
SS		 2356 /*
2357 * Check if the irq migration is in progress. If so, we
2358 * haven't received the cleanup request yet for this irq.
2359 */
2360 if (cfg->move_in_progress)
2361 goto unlock;
2362
22f65d31 2363 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
54168ed7
IM		 2364 goto unlock;
2365
68a8ca59
SS		 2366 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2367 /*
2368 * Check if the vector that needs to be cleanedup is
2369 * registered at the cpu's IRR. If so, then this is not
2370 * the best time to clean it up. Lets clean it up in the
2371 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2372 * to myself.
2373 */
2374 if (irr & (1 << (vector % 32))) {
2375 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2376 goto unlock;
2377 }
0a3aee0d 2378 __this_cpu_write(vector_irq[vector], -1);
54168ed7 2379unlock:
239007b8 2380 raw_spin_unlock(&desc->lock);
54168ed7
IM		 2381 }
2382
2383 irq_exit();
2384}
2385
dd5f15e5 2386static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
54168ed7 2387{
a5e74b84 2388 unsigned me;
54168ed7 2389
fcef5911 2390 if (likely(!cfg->move_in_progress))
54168ed7
IM		 2391 return;
2392
54168ed7 2393 me = smp_processor_id();
10b888d6 2394
fcef5911 2395 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
22f65d31 2396 send_cleanup_vector(cfg);
497c9a19 2397}
a5e74b84 2398
dd5f15e5 2399static void irq_complete_move(struct irq_cfg *cfg)
a5e74b84 2400{
dd5f15e5 2401 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
a5e74b84
SS		 2402}
2403
2404void irq_force_complete_move(int irq)
2405{
2c778651 2406 struct irq_cfg *cfg = irq_get_chip_data(irq);
a5e74b84 2407
bbd391a1
PB		 2408 if (!cfg)
2409 return;
2410
dd5f15e5 2411 __irq_complete_move(cfg, cfg->vector);
a5e74b84 2412}
497c9a19 2413#else
dd5f15e5 2414static inline void irq_complete_move(struct irq_cfg *cfg) { }
497c9a19 2415#endif
3145e941 2416
90297c5f 2417static void ack_apic_edge(struct irq_data *data)
1d025192 2418{
90297c5f 2419 irq_complete_move(data->chip_data);
08221110 2420 irq_move_irq(data);
1d025192
YL		 2421 ack_APIC_irq();
2422}
2423
3eb2cce8 2424atomic_t irq_mis_count;
3eb2cce8 2425
047c8fdb 2426#ifdef CONFIG_GENERIC_PENDING_IRQ
4da7072a
AG		 2427static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2428{
54168ed7 2429 /* If we are moving the irq we need to mask it */
5451ddc5 2430 if (unlikely(irqd_is_setaffinity_pending(data))) {
dd5f15e5 2431 mask_ioapic(cfg);
4da7072a 2432 return true;
54168ed7 2433 }
4da7072a
AG		 2434 return false;
2435}
2436
2437static inline void ioapic_irqd_unmask(struct irq_data *data,
2438 struct irq_cfg *cfg, bool masked)
2439{
2440 if (unlikely(masked)) {
2441 /* Only migrate the irq if the ack has been received.
2442 *
2443 * On rare occasions the broadcast level triggered ack gets
2444 * delayed going to ioapics, and if we reprogram the
2445 * vector while Remote IRR is still set the irq will never
2446 * fire again.
2447 *
2448 * To prevent this scenario we read the Remote IRR bit
2449 * of the ioapic. This has two effects.
2450 * - On any sane system the read of the ioapic will
2451 * flush writes (and acks) going to the ioapic from
2452 * this cpu.
2453 * - We get to see if the ACK has actually been delivered.
2454 *
2455 * Based on failed experiments of reprogramming the
2456 * ioapic entry from outside of irq context starting
2457 * with masking the ioapic entry and then polling until
2458 * Remote IRR was clear before reprogramming the
2459 * ioapic I don't trust the Remote IRR bit to be
2460 * completey accurate.
2461 *
2462 * However there appears to be no other way to plug
2463 * this race, so if the Remote IRR bit is not
2464 * accurate and is causing problems then it is a hardware bug
2465 * and you can go talk to the chipset vendor about it.
2466 */
2467 if (!io_apic_level_ack_pending(cfg))
2468 irq_move_masked_irq(data);
2469 unmask_ioapic(cfg);
2470 }
2471}
2472#else
2473static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2474{
2475 return false;
2476}
2477static inline void ioapic_irqd_unmask(struct irq_data *data,
2478 struct irq_cfg *cfg, bool masked)
2479{
2480}
047c8fdb
YL		 2481#endif
2482
4da7072a
AG		 2483static void ack_apic_level(struct irq_data *data)
2484{
2485 struct irq_cfg *cfg = data->chip_data;
2486 int i, irq = data->irq;
2487 unsigned long v;
2488 bool masked;
2489
2490 irq_complete_move(cfg);
2491 masked = ioapic_irqd_mask(data, cfg);
2492
3eb2cce8 2493 /*
916a0fe7
JF		 2494 * It appears there is an erratum which affects at least version 0x11
2495 * of I/O APIC (that's the 82093AA and cores integrated into various
2496 * chipsets). Under certain conditions a level-triggered interrupt is
2497 * erroneously delivered as edge-triggered one but the respective IRR
2498 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2499 * message but it will never arrive and further interrupts are blocked
2500 * from the source. The exact reason is so far unknown, but the
2501 * phenomenon was observed when two consecutive interrupt requests
2502 * from a given source get delivered to the same CPU and the source is
2503 * temporarily disabled in between.
2504 *
2505 * A workaround is to simulate an EOI message manually. We achieve it
2506 * by setting the trigger mode to edge and then to level when the edge
2507 * trigger mode gets detected in the TMR of a local APIC for a
2508 * level-triggered interrupt. We mask the source for the time of the
2509 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2510 * The idea is from Manfred Spraul. --macro
1c83995b
SS		 2511 *
2512 * Also in the case when cpu goes offline, fixup_irqs() will forward
2513 * any unhandled interrupt on the offlined cpu to the new cpu
2514 * destination that is handling the corresponding interrupt. This
2515 * interrupt forwarding is done via IPI's. Hence, in this case also
2516 * level-triggered io-apic interrupt will be seen as an edge
2517 * interrupt in the IRR. And we can't rely on the cpu's EOI
2518 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2519 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2520 * supporting EOI register, we do an explicit EOI to clear the
2521 * remote IRR and on IO-APIC's which don't have an EOI register,
2522 * we use the above logic (mask+edge followed by unmask+level) from
2523 * Manfred Spraul to clear the remote IRR.
916a0fe7 2524 */
3145e941 2525 i = cfg->vector;
3eb2cce8 2526 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
3eb2cce8 2527
54168ed7
IM		 2528 /*
2529 * We must acknowledge the irq before we move it or the acknowledge will
2530 * not propagate properly.
2531 */
2532 ack_APIC_irq();
2533
1c83995b
SS		 2534 /*
2535 * Tail end of clearing remote IRR bit (either by delivering the EOI
2536 * message via io-apic EOI register write or simulating it using
2537 * mask+edge followed by unnask+level logic) manually when the
2538 * level triggered interrupt is seen as the edge triggered interrupt
2539 * at the cpu.
2540 */
ca64c47c
MR		 2541 if (!(v & (1 << (i & 0x1f)))) {
2542 atomic_inc(&irq_mis_count);
2543
dd5f15e5 2544 eoi_ioapic_irq(irq, cfg);
ca64c47c
MR		 2545 }
2546
4da7072a 2547 ioapic_irqd_unmask(data, cfg, masked);
3eb2cce8 2548}
1d025192 2549
d3f13810 2550#ifdef CONFIG_IRQ_REMAP
90297c5f 2551static void ir_ack_apic_edge(struct irq_data *data)
d0b03bd1 2552{
5d0ae2db 2553 ack_APIC_irq();
d0b03bd1
HW		 2554}
2555
90297c5f 2556static void ir_ack_apic_level(struct irq_data *data)
d0b03bd1 2557{
5d0ae2db 2558 ack_APIC_irq();
90297c5f 2559 eoi_ioapic_irq(data->irq, data->chip_data);
d0b03bd1 2560}
c39d77ff
SS		 2561
2562static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2563{
2564 seq_printf(p, " IR-%s", data->chip->name);
2565}
2566
2567static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2568{
2569 chip->irq_print_chip = ir_print_prefix;
2570 chip->irq_ack = ir_ack_apic_edge;
2571 chip->irq_eoi = ir_ack_apic_level;
2572
2573#ifdef CONFIG_SMP
4c1bad6a 2574 chip->irq_set_affinity = intr_set_affinity;
c39d77ff
SS		 2575#endif
2576}
d3f13810 2577#endif /* CONFIG_IRQ_REMAP */
d0b03bd1 2578
f5b9ed7a 2579static struct irq_chip ioapic_chip __read_mostly = {
f7e909ea
TG		 2580 .name = "IO-APIC",
2581 .irq_startup = startup_ioapic_irq,
2582 .irq_mask = mask_ioapic_irq,
2583 .irq_unmask = unmask_ioapic_irq,
2584 .irq_ack = ack_apic_edge,
2585 .irq_eoi = ack_apic_level,
54d5d424 2586#ifdef CONFIG_SMP
f7e909ea 2587 .irq_set_affinity = ioapic_set_affinity,
54d5d424 2588#endif
f7e909ea 2589 .irq_retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2590};
2591
1da177e4
LT		 2592static inline void init_IO_APIC_traps(void)
2593{
da51a821 2594 struct irq_cfg *cfg;
ad9f4334 2595 unsigned int irq;
1da177e4
LT		 2596
2597 /*
2598 * NOTE! The local APIC isn't very good at handling
2599 * multiple interrupts at the same interrupt level.
2600 * As the interrupt level is determined by taking the
2601 * vector number and shifting that right by 4, we
2602 * want to spread these out a bit so that they don't
2603 * all fall in the same interrupt level.
2604 *
2605 * Also, we've got to be careful not to trash gate
2606 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2607 */
ad9f4334 2608 for_each_active_irq(irq) {
2c778651 2609 cfg = irq_get_chip_data(irq);
0b8f1efa 2610 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1da177e4
LT		 2611 /*
2612 * Hmm.. We don't have an entry for this,
2613 * so default to an old-fashioned 8259
2614 * interrupt if we can..
2615 */
b81bb373
JP		 2616 if (irq < legacy_pic->nr_legacy_irqs)
2617 legacy_pic->make_irq(irq);
0b8f1efa 2618 else
1da177e4 2619 /* Strange. Oh, well.. */
2c778651 2620 irq_set_chip(irq, &no_irq_chip);
1da177e4
LT		 2621 }
2622 }
2623}
2624
f5b9ed7a
IM		 2625/*
2626 * The local APIC irq-chip implementation:
2627 */
1da177e4 2628
90297c5f 2629static void mask_lapic_irq(struct irq_data *data)
1da177e4
LT		 2630{
2631 unsigned long v;
2632
2633 v = apic_read(APIC_LVT0);
593f4a78 2634 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2635}
2636
90297c5f 2637static void unmask_lapic_irq(struct irq_data *data)
1da177e4 2638{
f5b9ed7a 2639 unsigned long v;
1da177e4 2640
f5b9ed7a 2641 v = apic_read(APIC_LVT0);
593f4a78 2642 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
f5b9ed7a 2643}
1da177e4 2644
90297c5f 2645static void ack_lapic_irq(struct irq_data *data)
1d025192
YL		 2646{
2647 ack_APIC_irq();
2648}
2649
f5b9ed7a 2650static struct irq_chip lapic_chip __read_mostly = {
9a1c6192 2651 .name = "local-APIC",
90297c5f
TG		 2652 .irq_mask = mask_lapic_irq,
2653 .irq_unmask = unmask_lapic_irq,
2654 .irq_ack = ack_lapic_irq,
1da177e4
LT		 2655};
2656
60c69948 2657static void lapic_register_intr(int irq)
c88ac1df 2658{
60c69948 2659 irq_clear_status_flags(irq, IRQ_LEVEL);
2c778651 2660 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
c88ac1df 2661 "edge");
c88ac1df
MR		 2662}
2663
1da177e4
LT		 2664/*
2665 * This looks a bit hackish but it's about the only one way of sending
2666 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2667 * not support the ExtINT mode, unfortunately. We need to send these
2668 * cycles as some i82489DX-based boards have glue logic that keeps the
2669 * 8259A interrupt line asserted until INTA. --macro
2670 */
28acf285 2671static inline void __init unlock_ExtINT_logic(void)
1da177e4 2672{
fcfd636a 2673 int apic, pin, i;
1da177e4
LT		 2674 struct IO_APIC_route_entry entry0, entry1;
2675 unsigned char save_control, save_freq_select;
1da177e4 2676
fcfd636a 2677 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2678 if (pin == -1) {
2679 WARN_ON_ONCE(1);
2680 return;
2681 }
fcfd636a 2682 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2683 if (apic == -1) {
2684 WARN_ON_ONCE(1);
1da177e4 2685 return;
956fb531 2686 }
1da177e4 2687
cf4c6a2f 2688 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2689 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2690
2691 memset(&entry1, 0, sizeof(entry1));
2692
2693 entry1.dest_mode = 0; /* physical delivery */
2694 entry1.mask = 0; /* unmask IRQ now */
d83e94ac 2695 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2696 entry1.delivery_mode = dest_ExtINT;
2697 entry1.polarity = entry0.polarity;
2698 entry1.trigger = 0;
2699 entry1.vector = 0;
2700
cf4c6a2f 2701 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2702
2703 save_control = CMOS_READ(RTC_CONTROL);
2704 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2705 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2706 RTC_FREQ_SELECT);
2707 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2708
2709 i = 100;
2710 while (i-- > 0) {
2711 mdelay(10);
2712 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2713 i -= 10;
2714 }
2715
2716 CMOS_WRITE(save_control, RTC_CONTROL);
2717 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2718 clear_IO_APIC_pin(apic, pin);
1da177e4 2719
cf4c6a2f 2720 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2721}
2722
efa2559f 2723static int disable_timer_pin_1 __initdata;
047c8fdb 2724/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
54168ed7 2725static int __init disable_timer_pin_setup(char *arg)
efa2559f
YL		 2726{
2727 disable_timer_pin_1 = 1;
2728 return 0;
2729}
54168ed7 2730early_param("disable_timer_pin_1", disable_timer_pin_setup);
efa2559f
YL		 2731
2732int timer_through_8259 __initdata;
2733
1da177e4
LT		 2734/*
2735 * This code may look a bit paranoid, but it's supposed to cooperate with
2736 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2737 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2738 * fanatically on his truly buggy board.
54168ed7
IM		 2739 *
2740 * FIXME: really need to revamp this for all platforms.
1da177e4 2741 */
8542b200 2742static inline void __init check_timer(void)
1da177e4 2743{
2c778651 2744 struct irq_cfg *cfg = irq_get_chip_data(0);
f6e9456c 2745 int node = cpu_to_node(0);
fcfd636a 2746 int apic1, pin1, apic2, pin2;
4aae0702 2747 unsigned long flags;
047c8fdb 2748 int no_pin1 = 0;
4aae0702
IM		 2749
2750 local_irq_save(flags);
d4d25dec 2751
1da177e4
LT		 2752 /*
2753 * get/set the timer IRQ vector:
2754 */
4305df94 2755 legacy_pic->mask(0);
fe402e1f 2756 assign_irq_vector(0, cfg, apic->target_cpus());
1da177e4
LT		 2757
2758 /*
d11d5794
MR		 2759 * As IRQ0 is to be enabled in the 8259A, the virtual
2760 * wire has to be disabled in the local APIC. Also
2761 * timer interrupts need to be acknowledged manually in
2762 * the 8259A for the i82489DX when using the NMI
2763 * watchdog as that APIC treats NMIs as level-triggered.
2764 * The AEOI mode will finish them in the 8259A
2765 * automatically.
1da177e4 2766 */
593f4a78 2767 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
b81bb373 2768 legacy_pic->init(1);
1da177e4 2769
fcfd636a
EB		 2770 pin1 = find_isa_irq_pin(0, mp_INT);
2771 apic1 = find_isa_irq_apic(0, mp_INT);
2772 pin2 = ioapic_i8259.pin;
2773 apic2 = ioapic_i8259.apic;
1da177e4 2774
49a66a0b
MR		 2775 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2776 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
497c9a19 2777 cfg->vector, apic1, pin1, apic2, pin2);
1da177e4 2778
691874fa
MR		 2779 /*
2780 * Some BIOS writers are clueless and report the ExtINTA
2781 * I/O APIC input from the cascaded 8259A as the timer
2782 * interrupt input. So just in case, if only one pin
2783 * was found above, try it both directly and through the
2784 * 8259A.
2785 */
2786 if (pin1 == -1) {
54168ed7
IM		 2787 if (intr_remapping_enabled)
2788 panic("BIOS bug: timer not connected to IO-APIC");
691874fa
MR		 2789 pin1 = pin2;
2790 apic1 = apic2;
2791 no_pin1 = 1;
2792 } else if (pin2 == -1) {
2793 pin2 = pin1;
2794 apic2 = apic1;
2795 }
2796
1da177e4
LT		 2797 if (pin1 != -1) {
2798 /*
2799 * Ok, does IRQ0 through the IOAPIC work?
2800 */
691874fa 2801 if (no_pin1) {
85ac16d0 2802 add_pin_to_irq_node(cfg, node, apic1, pin1);
497c9a19 2803 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
f72dccac 2804 } else {
60c69948 2805 /* for edge trigger, setup_ioapic_irq already
f72dccac
YL		 2806 * leave it unmasked.
2807 * so only need to unmask if it is level-trigger
2808 * do we really have level trigger timer?
2809 */
2810 int idx;
2811 idx = find_irq_entry(apic1, pin1, mp_INT);
2812 if (idx != -1 && irq_trigger(idx))
dd5f15e5 2813 unmask_ioapic(cfg);
691874fa 2814 }
1da177e4 2815 if (timer_irq_works()) {
66759a01
CE		 2816 if (disable_timer_pin_1 > 0)
2817 clear_IO_APIC_pin(0, pin1);
4aae0702 2818 goto out;
1da177e4 2819 }
54168ed7
IM		 2820 if (intr_remapping_enabled)
2821 panic("timer doesn't work through Interrupt-remapped IO-APIC");
f72dccac 2822 local_irq_disable();
fcfd636a 2823 clear_IO_APIC_pin(apic1, pin1);
691874fa 2824 if (!no_pin1)
49a66a0b
MR		 2825 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2826 "8254 timer not connected to IO-APIC\n");
1da177e4 2827
49a66a0b
MR		 2828 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2829 "(IRQ0) through the 8259A ...\n");
2830 apic_printk(APIC_QUIET, KERN_INFO
2831 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1da177e4
LT		 2832 /*
2833 * legacy devices should be connected to IO APIC #0
2834 */
85ac16d0 2835 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
497c9a19 2836 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
4305df94 2837 legacy_pic->unmask(0);
1da177e4 2838 if (timer_irq_works()) {
49a66a0b 2839 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2840 timer_through_8259 = 1;
4aae0702 2841 goto out;
1da177e4
LT		 2842 }
2843 /*
2844 * Cleanup, just in case ...
2845 */
f72dccac 2846 local_irq_disable();
4305df94 2847 legacy_pic->mask(0);
fcfd636a 2848 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2849 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2850 }
1da177e4 2851
49a66a0b
MR		 2852 apic_printk(APIC_QUIET, KERN_INFO
2853 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2854
60c69948 2855 lapic_register_intr(0);
497c9a19 2856 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
4305df94 2857 legacy_pic->unmask(0);
1da177e4
LT		 2858
2859 if (timer_irq_works()) {
49a66a0b 2860 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2861 goto out;
1da177e4 2862 }
f72dccac 2863 local_irq_disable();
4305df94 2864 legacy_pic->mask(0);
497c9a19 2865 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2866 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2867
49a66a0b
MR		 2868 apic_printk(APIC_QUIET, KERN_INFO
2869 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4 2870
b81bb373
JP		 2871 legacy_pic->init(0);
2872 legacy_pic->make_irq(0);
593f4a78 2873 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2874
2875 unlock_ExtINT_logic();
2876
2877 if (timer_irq_works()) {
49a66a0b 2878 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2879 goto out;
1da177e4 2880 }
f72dccac 2881 local_irq_disable();
49a66a0b 2882 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
fb209bd8
YL		 2883 if (x2apic_preenabled)
2884 apic_printk(APIC_QUIET, KERN_INFO
2885 "Perhaps problem with the pre-enabled x2apic mode\n"
2886 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
1da177e4 2887 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
49a66a0b 2888 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2889out:
2890 local_irq_restore(flags);
1da177e4
LT		 2891}
2892
2893/*
af174783
MR		 2894 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2895 * to devices. However there may be an I/O APIC pin available for
2896 * this interrupt regardless. The pin may be left unconnected, but
2897 * typically it will be reused as an ExtINT cascade interrupt for
2898 * the master 8259A. In the MPS case such a pin will normally be
2899 * reported as an ExtINT interrupt in the MP table. With ACPI
2900 * there is no provision for ExtINT interrupts, and in the absence
2901 * of an override it would be treated as an ordinary ISA I/O APIC
2902 * interrupt, that is edge-triggered and unmasked by default. We
2903 * used to do this, but it caused problems on some systems because
2904 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2905 * the same ExtINT cascade interrupt to drive the local APIC of the
2906 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2907 * the I/O APIC in all cases now. No actual device should request
2908 * it anyway. --macro
1da177e4 2909 */
bc07844a 2910#define PIC_IRQS (1UL << PIC_CASCADE_IR)
1da177e4
LT		 2911
2912void __init setup_IO_APIC(void)
2913{
54168ed7 2914
54168ed7
IM		 2915 /*
2916 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2917 */
b81bb373 2918 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
1da177e4 2919
54168ed7 2920 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
d6c88a50 2921 /*
54168ed7
IM		 2922 * Set up IO-APIC IRQ routing.
2923 */
de934103
TG		 2924 x86_init.mpparse.setup_ioapic_ids();
2925
1da177e4
LT		 2926 sync_Arb_IDs();
2927 setup_IO_APIC_irqs();
2928 init_IO_APIC_traps();
b81bb373 2929 if (legacy_pic->nr_legacy_irqs)
bc07844a 2930 check_timer();
1da177e4
LT		 2931}
2932
2933/*
0d2eb44f 2934 * Called after all the initialization is done. If we didn't find any
54168ed7 2935 * APIC bugs then we can allow the modify fast path
1da177e4 2936 */
36062448 2937
1da177e4
LT		 2938static int __init io_apic_bug_finalize(void)
2939{
d6c88a50
TG		 2940 if (sis_apic_bug == -1)
2941 sis_apic_bug = 0;
2942 return 0;
1da177e4
LT		 2943}
2944
2945late_initcall(io_apic_bug_finalize);
2946
6f50d45f 2947static void resume_ioapic_id(int ioapic_idx)
1da177e4 2948{
1da177e4
LT		 2949 unsigned long flags;
2950 union IO_APIC_reg_00 reg_00;
36062448 2951
dade7716 2952 raw_spin_lock_irqsave(&ioapic_lock, flags);
6f50d45f
YL		 2953 reg_00.raw = io_apic_read(ioapic_idx, 0);
2954 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2955 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2956 io_apic_write(ioapic_idx, 0, reg_00.raw);
1da177e4 2957 }
dade7716 2958 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
f3c6ea1b 2959}
1da177e4 2960
f3c6ea1b
RW		 2961static void ioapic_resume(void)
2962{
6f50d45f 2963 int ioapic_idx;
f3c6ea1b 2964
6f50d45f
YL		 2965 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2966 resume_ioapic_id(ioapic_idx);
15bac20b
SS		 2967
2968 restore_ioapic_entries();
1da177e4
LT		 2969}
2970
f3c6ea1b 2971static struct syscore_ops ioapic_syscore_ops = {
15bac20b 2972 .suspend = save_ioapic_entries,
1da177e4
LT		 2973 .resume = ioapic_resume,
2974};
2975
f3c6ea1b 2976static int __init ioapic_init_ops(void)
1da177e4 2977{
f3c6ea1b
RW		 2978 register_syscore_ops(&ioapic_syscore_ops);
2979
1da177e4
LT		 2980 return 0;
2981}
2982
f3c6ea1b 2983device_initcall(ioapic_init_ops);
1da177e4 2984
3fc471ed 2985/*
95d77884 2986 * Dynamic irq allocate and deallocation
3fc471ed 2987 */
fbc6bff0 2988unsigned int create_irq_nr(unsigned int from, int node)
3fc471ed 2989{
fbc6bff0 2990 struct irq_cfg *cfg;
3fc471ed 2991 unsigned long flags;
fbc6bff0
TG		 2992 unsigned int ret = 0;
2993 int irq;
d047f53a 2994
fbc6bff0
TG		 2995 if (from < nr_irqs_gsi)
2996 from = nr_irqs_gsi;
d047f53a 2997
fbc6bff0
TG		 2998 irq = alloc_irq_from(from, node);
2999 if (irq < 0)
3000 return 0;
3001 cfg = alloc_irq_cfg(irq, node);
3002 if (!cfg) {
3003 free_irq_at(irq, NULL);
3004 return 0;
ace80ab7 3005 }
3fc471ed 3006
fbc6bff0
TG		 3007 raw_spin_lock_irqsave(&vector_lock, flags);
3008 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3009 ret = irq;
3010 raw_spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 3011
fbc6bff0 3012 if (ret) {
2c778651 3013 irq_set_chip_data(irq, cfg);
fbc6bff0
TG		 3014 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3015 } else {
3016 free_irq_at(irq, cfg);
3017 }
3018 return ret;
3fc471ed
EB		 3019}
3020
199751d7
YL		 3021int create_irq(void)
3022{
f6e9456c 3023 int node = cpu_to_node(0);
be5d5350 3024 unsigned int irq_want;
54168ed7
IM		 3025 int irq;
3026
be5d5350 3027 irq_want = nr_irqs_gsi;
d047f53a 3028 irq = create_irq_nr(irq_want, node);
54168ed7
IM		 3029
3030 if (irq == 0)
3031 irq = -1;
3032
3033 return irq;
199751d7
YL		 3034}
3035
3fc471ed
EB		 3036void destroy_irq(unsigned int irq)
3037{
2c778651 3038 struct irq_cfg *cfg = irq_get_chip_data(irq);
3fc471ed 3039 unsigned long flags;
3fc471ed 3040
fbc6bff0 3041 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3fc471ed 3042
7b79462a 3043 if (irq_remapped(cfg))
9d619f65 3044 intr_free_irq(irq);
dade7716 3045 raw_spin_lock_irqsave(&vector_lock, flags);
fbc6bff0 3046 __clear_irq_vector(irq, cfg);
dade7716 3047 raw_spin_unlock_irqrestore(&vector_lock, flags);
fbc6bff0 3048 free_irq_at(irq, cfg);
3fc471ed 3049}
3fc471ed 3050
2d3fcc1c 3051/*
27b46d76 3052 * MSI message composition
2d3fcc1c
EB		 3053 */
3054#ifdef CONFIG_PCI_MSI
c8bc6f3c
SS		 3055static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3056 struct msi_msg *msg, u8 hpet_id)
2d3fcc1c 3057{
497c9a19
YL		 3058 struct irq_cfg *cfg;
3059 int err;
2d3fcc1c
EB		 3060 unsigned dest;
3061
f1182638
JB		 3062 if (disable_apic)
3063 return -ENXIO;
3064
3145e941 3065 cfg = irq_cfg(irq);
fe402e1f 3066 err = assign_irq_vector(irq, cfg, apic->target_cpus());
497c9a19
YL		 3067 if (err)
3068 return err;
2d3fcc1c 3069
debccb3e 3070 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
497c9a19 3071
1a0e62a4 3072 if (irq_remapped(cfg)) {
5e2b930b
JR		 3073 intr_compose_msi_msg(pdev, irq, dest, msg, hpet_id);
3074 return err;
3075 }
54168ed7 3076
5e2b930b
JR		 3077 if (x2apic_enabled())
3078 msg->address_hi = MSI_ADDR_BASE_HI |
3079 MSI_ADDR_EXT_DEST_ID(dest);
3080 else
3081 msg->address_hi = MSI_ADDR_BASE_HI;
f007e99c 3082
5e2b930b
JR		 3083 msg->address_lo =
3084 MSI_ADDR_BASE_LO |
3085 ((apic->irq_dest_mode == 0) ?
3086 MSI_ADDR_DEST_MODE_PHYSICAL:
3087 MSI_ADDR_DEST_MODE_LOGICAL) |
3088 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3089 MSI_ADDR_REDIRECTION_CPU:
3090 MSI_ADDR_REDIRECTION_LOWPRI) |
3091 MSI_ADDR_DEST_ID(dest);
3092
3093 msg->data =
3094 MSI_DATA_TRIGGER_EDGE |
3095 MSI_DATA_LEVEL_ASSERT |
3096 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3097 MSI_DATA_DELIVERY_FIXED:
3098 MSI_DATA_DELIVERY_LOWPRI) |
3099 MSI_DATA_VECTOR(cfg->vector);
54168ed7 3100
497c9a19 3101 return err;
2d3fcc1c
EB		 3102}
3103
3b7d1921 3104#ifdef CONFIG_SMP
5346b2a7
TG		 3105static int
3106msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
2d3fcc1c 3107{
5346b2a7 3108 struct irq_cfg *cfg = data->chip_data;
3b7d1921
EB		 3109 struct msi_msg msg;
3110 unsigned int dest;
3b7d1921 3111
5346b2a7 3112 if (__ioapic_set_affinity(data, mask, &dest))
d5dedd45 3113 return -1;
2d3fcc1c 3114
5346b2a7 3115 __get_cached_msi_msg(data->msi_desc, &msg);
3b7d1921
EB		 3116
3117 msg.data &= ~MSI_DATA_VECTOR_MASK;
497c9a19 3118 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 3119 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3120 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3121
5346b2a7 3122 __write_msi_msg(data->msi_desc, &msg);
d5dedd45
YL		 3123
3124 return 0;
2d3fcc1c 3125}
3b7d1921 3126#endif /* CONFIG_SMP */
2d3fcc1c 3127
3b7d1921
EB		 3128/*
3129 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3130 * which implement the MSI or MSI-X Capability Structure.
3131 */
3132static struct irq_chip msi_chip = {
5346b2a7
TG		 3133 .name = "PCI-MSI",
3134 .irq_unmask = unmask_msi_irq,
3135 .irq_mask = mask_msi_irq,
3136 .irq_ack = ack_apic_edge,
3b7d1921 3137#ifdef CONFIG_SMP
5346b2a7 3138 .irq_set_affinity = msi_set_affinity,
3b7d1921 3139#endif
5346b2a7 3140 .irq_retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 3141};
3142
3145e941 3143static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
1d025192 3144{
c60eaf25 3145 struct irq_chip *chip = &msi_chip;
1d025192 3146 struct msi_msg msg;
60c69948 3147 int ret;
1d025192 3148
c8bc6f3c 3149 ret = msi_compose_msg(dev, irq, &msg, -1);
1d025192
YL		 3150 if (ret < 0)
3151 return ret;
3152
2c778651 3153 irq_set_msi_desc(irq, msidesc);
1d025192
YL		 3154 write_msi_msg(irq, &msg);
3155
2c778651 3156 if (irq_remapped(irq_get_chip_data(irq))) {
60c69948 3157 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
c39d77ff 3158 irq_remap_modify_chip_defaults(chip);
c60eaf25
TG		 3159 }
3160
3161 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
1d025192 3162
c81bba49
YL		 3163 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3164
1d025192
YL		 3165 return 0;
3166}
3167
294ee6f8 3168int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
047c8fdb 3169{
60c69948
TG		 3170 int node, ret, sub_handle, index = 0;
3171 unsigned int irq, irq_want;
0b8f1efa 3172 struct msi_desc *msidesc;
54168ed7 3173
1c8d7b0a
MW		 3174 /* x86 doesn't support multiple MSI yet */
3175 if (type == PCI_CAP_ID_MSI && nvec > 1)
3176 return 1;
3177
d047f53a 3178 node = dev_to_node(&dev->dev);
be5d5350 3179 irq_want = nr_irqs_gsi;
54168ed7 3180 sub_handle = 0;
0b8f1efa 3181 list_for_each_entry(msidesc, &dev->msi_list, list) {
d047f53a 3182 irq = create_irq_nr(irq_want, node);
54168ed7
IM		 3183 if (irq == 0)
3184 return -1;
f1ee5548 3185 irq_want = irq + 1;
54168ed7
IM		 3186 if (!intr_remapping_enabled)
3187 goto no_ir;
3188
3189 if (!sub_handle) {
3190 /*
3191 * allocate the consecutive block of IRTE's
3192 * for 'nvec'
3193 */
5e2b930b 3194 index = intr_msi_alloc_irq(dev, irq, nvec);
54168ed7
IM		 3195 if (index < 0) {
3196 ret = index;
3197 goto error;
3198 }
3199 } else {
5e2b930b
JR		 3200 ret = intr_msi_setup_irq(dev, irq, index, sub_handle);
3201 if (ret < 0)
54168ed7 3202 goto error;
54168ed7
IM		 3203 }
3204no_ir:
0b8f1efa 3205 ret = setup_msi_irq(dev, msidesc, irq);
54168ed7
IM		 3206 if (ret < 0)
3207 goto error;
3208 sub_handle++;
3209 }
3210 return 0;
047c8fdb
YL		 3211
3212error:
54168ed7
IM		 3213 destroy_irq(irq);
3214 return ret;
047c8fdb
YL		 3215}
3216
294ee6f8 3217void native_teardown_msi_irq(unsigned int irq)
3b7d1921 3218{
f7feaca7 3219 destroy_irq(irq);
3b7d1921
EB		 3220}
3221
d3f13810 3222#ifdef CONFIG_DMAR_TABLE
54168ed7 3223#ifdef CONFIG_SMP
fe52b2d2
TG		 3224static int
3225dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3226 bool force)
54168ed7 3227{
fe52b2d2
TG		 3228 struct irq_cfg *cfg = data->chip_data;
3229 unsigned int dest, irq = data->irq;
54168ed7 3230 struct msi_msg msg;
54168ed7 3231
fe52b2d2 3232 if (__ioapic_set_affinity(data, mask, &dest))
d5dedd45 3233 return -1;
54168ed7 3234
54168ed7
IM		 3235 dmar_msi_read(irq, &msg);
3236
3237 msg.data &= ~MSI_DATA_VECTOR_MASK;
3238 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3239 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3240 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
086e8ced 3241 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
54168ed7
IM		 3242
3243 dmar_msi_write(irq, &msg);
d5dedd45
YL		 3244
3245 return 0;
54168ed7 3246}
3145e941 3247
54168ed7
IM		 3248#endif /* CONFIG_SMP */
3249
8f7007aa 3250static struct irq_chip dmar_msi_type = {
fe52b2d2
TG		 3251 .name = "DMAR_MSI",
3252 .irq_unmask = dmar_msi_unmask,
3253 .irq_mask = dmar_msi_mask,
3254 .irq_ack = ack_apic_edge,
54168ed7 3255#ifdef CONFIG_SMP
fe52b2d2 3256 .irq_set_affinity = dmar_msi_set_affinity,
54168ed7 3257#endif
fe52b2d2 3258 .irq_retrigger = ioapic_retrigger_irq,
54168ed7
IM		 3259};
3260
3261int arch_setup_dmar_msi(unsigned int irq)
3262{
3263 int ret;
3264 struct msi_msg msg;
2d3fcc1c 3265
c8bc6f3c 3266 ret = msi_compose_msg(NULL, irq, &msg, -1);
54168ed7
IM		 3267 if (ret < 0)
3268 return ret;
3269 dmar_msi_write(irq, &msg);
2c778651
TG		 3270 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3271 "edge");
54168ed7
IM		 3272 return 0;
3273}
3274#endif
3275
58ac1e76 3276#ifdef CONFIG_HPET_TIMER
3277
3278#ifdef CONFIG_SMP
d0fbca8f
TG		 3279static int hpet_msi_set_affinity(struct irq_data *data,
3280 const struct cpumask *mask, bool force)
58ac1e76 3281{
d0fbca8f 3282 struct irq_cfg *cfg = data->chip_data;
58ac1e76 3283 struct msi_msg msg;
3284 unsigned int dest;
58ac1e76 3285
0e09ddf2 3286 if (__ioapic_set_affinity(data, mask, &dest))
d5dedd45 3287 return -1;
58ac1e76 3288
d0fbca8f 3289 hpet_msi_read(data->handler_data, &msg);
58ac1e76 3290
3291 msg.data &= ~MSI_DATA_VECTOR_MASK;
3292 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3293 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3294 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3295
d0fbca8f 3296 hpet_msi_write(data->handler_data, &msg);
d5dedd45
YL		 3297
3298 return 0;
58ac1e76 3299}
3145e941 3300
58ac1e76 3301#endif /* CONFIG_SMP */
3302
1cc18521 3303static struct irq_chip hpet_msi_type = {
58ac1e76 3304 .name = "HPET_MSI",
d0fbca8f
TG		 3305 .irq_unmask = hpet_msi_unmask,
3306 .irq_mask = hpet_msi_mask,
90297c5f 3307 .irq_ack = ack_apic_edge,
58ac1e76 3308#ifdef CONFIG_SMP
d0fbca8f 3309 .irq_set_affinity = hpet_msi_set_affinity,
58ac1e76 3310#endif
90297c5f 3311 .irq_retrigger = ioapic_retrigger_irq,
58ac1e76 3312};
3313
c8bc6f3c 3314int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
58ac1e76 3315{
c60eaf25 3316 struct irq_chip *chip = &hpet_msi_type;
58ac1e76 3317 struct msi_msg msg;
d0fbca8f 3318 int ret;
58ac1e76 3319
c8bc6f3c 3320 if (intr_remapping_enabled) {
5e2b930b 3321 if (!intr_setup_hpet_msi(irq, id))
c8bc6f3c
SS		 3322 return -1;
3323 }
3324
3325 ret = msi_compose_msg(NULL, irq, &msg, id);
58ac1e76 3326 if (ret < 0)
3327 return ret;
3328
2c778651 3329 hpet_msi_write(irq_get_handler_data(irq), &msg);
60c69948 3330 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
2c778651 3331 if (irq_remapped(irq_get_chip_data(irq)))
c39d77ff 3332 irq_remap_modify_chip_defaults(chip);
c81bba49 3333
c60eaf25 3334 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
58ac1e76 3335 return 0;
3336}
3337#endif
3338
54168ed7 3339#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3340/*
3341 * Hypertransport interrupt support
3342 */
3343#ifdef CONFIG_HT_IRQ
3344
3345#ifdef CONFIG_SMP
3346
497c9a19 3347static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
8b955b0d 3348{
ec68307c
EB		 3349 struct ht_irq_msg msg;
3350 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3351
497c9a19 3352 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
ec68307c 3353 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3354
497c9a19 3355 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
ec68307c 3356 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3357
ec68307c 3358 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3359}
3360
be5b7bf7
TG		 3361static int
3362ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
8b955b0d 3363{
be5b7bf7 3364 struct irq_cfg *cfg = data->chip_data;
8b955b0d 3365 unsigned int dest;
8b955b0d 3366
be5b7bf7 3367 if (__ioapic_set_affinity(data, mask, &dest))
d5dedd45 3368 return -1;
8b955b0d 3369
be5b7bf7 3370 target_ht_irq(data->irq, dest, cfg->vector);
d5dedd45 3371 return 0;
8b955b0d 3372}
3145e941 3373
8b955b0d
EB		 3374#endif
3375
c37e108d 3376static struct irq_chip ht_irq_chip = {
be5b7bf7
TG		 3377 .name = "PCI-HT",
3378 .irq_mask = mask_ht_irq,
3379 .irq_unmask = unmask_ht_irq,
3380 .irq_ack = ack_apic_edge,
8b955b0d 3381#ifdef CONFIG_SMP
be5b7bf7 3382 .irq_set_affinity = ht_set_affinity,
8b955b0d 3383#endif
be5b7bf7 3384 .irq_retrigger = ioapic_retrigger_irq,
8b955b0d
EB		 3385};
3386
3387int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3388{
497c9a19
YL		 3389 struct irq_cfg *cfg;
3390 int err;
8b955b0d 3391
f1182638
JB		 3392 if (disable_apic)
3393 return -ENXIO;
3394
3145e941 3395 cfg = irq_cfg(irq);
fe402e1f 3396 err = assign_irq_vector(irq, cfg, apic->target_cpus());
54168ed7 3397 if (!err) {
ec68307c 3398 struct ht_irq_msg msg;
8b955b0d 3399 unsigned dest;
8b955b0d 3400
debccb3e
IM		 3401 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3402 apic->target_cpus());
8b955b0d 3403
ec68307c 3404 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3405
ec68307c
EB		 3406 msg.address_lo =
3407 HT_IRQ_LOW_BASE |
8b955b0d 3408 HT_IRQ_LOW_DEST_ID(dest) |
497c9a19 3409 HT_IRQ_LOW_VECTOR(cfg->vector) |
9b5bc8dc 3410 ((apic->irq_dest_mode == 0) ?
8b955b0d
EB		 3411 HT_IRQ_LOW_DM_PHYSICAL :
3412 HT_IRQ_LOW_DM_LOGICAL) |
3413 HT_IRQ_LOW_RQEOI_EDGE |
9b5bc8dc 3414 ((apic->irq_delivery_mode != dest_LowestPrio) ?
8b955b0d
EB		 3415 HT_IRQ_LOW_MT_FIXED :
3416 HT_IRQ_LOW_MT_ARBITRATED) |
3417 HT_IRQ_LOW_IRQ_MASKED;
3418
ec68307c 3419 write_ht_irq_msg(irq, &msg);
8b955b0d 3420
2c778651 3421 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
a460e745 3422 handle_edge_irq, "edge");
c81bba49
YL		 3423
3424 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
8b955b0d 3425 }
497c9a19 3426 return err;
8b955b0d
EB		 3427}
3428#endif /* CONFIG_HT_IRQ */
3429
20443598 3430static int
ff973d04
TG		 3431io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3432{
3433 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3434 int ret;
3435
3436 if (!cfg)
3437 return -EINVAL;
3438 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3439 if (!ret)
e4aff811 3440 setup_ioapic_irq(irq, cfg, attr);
ff973d04
TG		 3441 return ret;
3442}
3443
20443598
SAS		 3444int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3445 struct io_apic_irq_attr *attr)
710dcda6 3446{
6f50d45f 3447 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
710dcda6
TG		 3448 int ret;
3449
3450 /* Avoid redundant programming */
6f50d45f 3451 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
710dcda6 3452 pr_debug("Pin %d-%d already programmed\n",
6f50d45f 3453 mpc_ioapic_id(ioapic_idx), pin);
710dcda6
TG		 3454 return 0;
3455 }
3456 ret = io_apic_setup_irq_pin(irq, node, attr);
3457 if (!ret)
6f50d45f 3458 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
710dcda6
TG		 3459 return ret;
3460}
3461
41098ffe 3462static int __init io_apic_get_redir_entries(int ioapic)
9d6a4d08
YL		 3463{
3464 union IO_APIC_reg_01 reg_01;
3465 unsigned long flags;
3466
dade7716 3467 raw_spin_lock_irqsave(&ioapic_lock, flags);
9d6a4d08 3468 reg_01.raw = io_apic_read(ioapic, 1);
dade7716 3469 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
9d6a4d08 3470
4b6b19a1
EB		 3471 /* The register returns the maximum index redir index
3472 * supported, which is one less than the total number of redir
3473 * entries.
3474 */
3475 return reg_01.bits.entries + 1;
9d6a4d08
YL		 3476}
3477
23f9b267 3478static void __init probe_nr_irqs_gsi(void)
9d6a4d08 3479{
4afc51a8 3480 int nr;
be5d5350 3481
a4384df3 3482 nr = gsi_top + NR_IRQS_LEGACY;
4afc51a8 3483 if (nr > nr_irqs_gsi)
be5d5350 3484 nr_irqs_gsi = nr;
cc6c5006
YL		 3485
3486 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
9d6a4d08
YL		 3487}
3488
7b586d71
JF		 3489int get_nr_irqs_gsi(void)
3490{
3491 return nr_irqs_gsi;
3492}
3493
4a046d17
YL		 3494int __init arch_probe_nr_irqs(void)
3495{
3496 int nr;
3497
f1ee5548
YL		 3498 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3499 nr_irqs = NR_VECTORS * nr_cpu_ids;
4a046d17 3500
f1ee5548
YL		 3501 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3502#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3503 /*
3504 * for MSI and HT dyn irq
3505 */
3506 nr += nr_irqs_gsi * 16;
3507#endif
3508 if (nr < nr_irqs)
4a046d17
YL		 3509 nr_irqs = nr;
3510
b683de2b 3511 return NR_IRQS_LEGACY;
4a046d17 3512}
4a046d17 3513
710dcda6
TG		 3514int io_apic_set_pci_routing(struct device *dev, int irq,
3515 struct io_apic_irq_attr *irq_attr)
5ef21837 3516{
5ef21837
YL		 3517 int node;
3518
3519 if (!IO_APIC_IRQ(irq)) {
3520 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
e0799c04 3521 irq_attr->ioapic);
5ef21837
YL		 3522 return -EINVAL;
3523 }
3524
e0799c04 3525 node = dev ? dev_to_node(dev) : cpu_to_node(0);
e5198075 3526
710dcda6 3527 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
5ef21837
YL		 3528}
3529
54168ed7 3530#ifdef CONFIG_X86_32
41098ffe 3531static int __init io_apic_get_unique_id(int ioapic, int apic_id)
1da177e4
LT		 3532{
3533 union IO_APIC_reg_00 reg_00;
3534 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3535 physid_mask_t tmp;
3536 unsigned long flags;
3537 int i = 0;
3538
3539 /*
36062448
PC		 3540 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3541 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1da177e4 3542 * supports up to 16 on one shared APIC bus.
36062448 3543 *
1da177e4
LT		 3544 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3545 * advantage of new APIC bus architecture.
3546 */
3547
3548 if (physids_empty(apic_id_map))
7abc0753 3549 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
1da177e4 3550
dade7716 3551 raw_spin_lock_irqsave(&ioapic_lock, flags);
1da177e4 3552 reg_00.raw = io_apic_read(ioapic, 0);
dade7716 3553 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 3554
3555 if (apic_id >= get_physical_broadcast()) {
3556 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3557 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3558 apic_id = reg_00.bits.ID;
3559 }
3560
3561 /*
36062448 3562 * Every APIC in a system must have a unique ID or we get lots of nice
1da177e4
LT		 3563 * 'stuck on smp_invalidate_needed IPI wait' messages.
3564 */
7abc0753 3565 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
1da177e4
LT		 3566
3567 for (i = 0; i < get_physical_broadcast(); i++) {
7abc0753 3568 if (!apic->check_apicid_used(&apic_id_map, i))
1da177e4
LT		 3569 break;
3570 }
3571
3572 if (i == get_physical_broadcast())
3573 panic("Max apic_id exceeded!\n");
3574
3575 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3576 "trying %d\n", ioapic, apic_id, i);
3577
3578 apic_id = i;
36062448 3579 }
1da177e4 3580
7abc0753 3581 apic->apicid_to_cpu_present(apic_id, &tmp);
1da177e4
LT		 3582 physids_or(apic_id_map, apic_id_map, tmp);
3583
3584 if (reg_00.bits.ID != apic_id) {
3585 reg_00.bits.ID = apic_id;
3586
dade7716 3587 raw_spin_lock_irqsave(&ioapic_lock, flags);
1da177e4
LT		 3588 io_apic_write(ioapic, 0, reg_00.raw);
3589 reg_00.raw = io_apic_read(ioapic, 0);
dade7716 3590 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 3591
3592 /* Sanity check */
6070f9ec
AD		 3593 if (reg_00.bits.ID != apic_id) {
3594 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3595 return -1;
3596 }
1da177e4
LT		 3597 }
3598
3599 apic_printk(APIC_VERBOSE, KERN_INFO
3600 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3601
3602 return apic_id;
3603}
41098ffe
TG		 3604
3605static u8 __init io_apic_unique_id(u8 id)
3606{
3607 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3608 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3609 return io_apic_get_unique_id(nr_ioapics, id);
3610 else
3611 return id;
3612}
3613#else
3614static u8 __init io_apic_unique_id(u8 id)
3615{
3616 int i;
3617 DECLARE_BITMAP(used, 256);
3618
3619 bitmap_zero(used, 256);
3620 for (i = 0; i < nr_ioapics; i++) {
d5371430 3621 __set_bit(mpc_ioapic_id(i), used);
41098ffe
TG		 3622 }
3623 if (!test_bit(id, used))
3624 return id;
3625 return find_first_zero_bit(used, 256);
3626}
58f892e0 3627#endif
1da177e4 3628
41098ffe 3629static int __init io_apic_get_version(int ioapic)
1da177e4
LT		 3630{
3631 union IO_APIC_reg_01 reg_01;
3632 unsigned long flags;
3633
dade7716 3634 raw_spin_lock_irqsave(&ioapic_lock, flags);
1da177e4 3635 reg_01.raw = io_apic_read(ioapic, 1);
dade7716 3636 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 3637
3638 return reg_01.bits.version;
3639}
3640
9a0a91bb 3641int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
61fd47e0 3642{
9a0a91bb 3643 int ioapic, pin, idx;
61fd47e0
SL		 3644
3645 if (skip_ioapic_setup)
3646 return -1;
3647
9a0a91bb
EB		 3648 ioapic = mp_find_ioapic(gsi);
3649 if (ioapic < 0)
61fd47e0
SL		 3650 return -1;
3651
9a0a91bb
EB		 3652 pin = mp_find_ioapic_pin(ioapic, gsi);
3653 if (pin < 0)
3654 return -1;
3655
3656 idx = find_irq_entry(ioapic, pin, mp_INT);
3657 if (idx < 0)
61fd47e0
SL		 3658 return -1;
3659
9a0a91bb
EB		 3660 *trigger = irq_trigger(idx);
3661 *polarity = irq_polarity(idx);
61fd47e0
SL		 3662 return 0;
3663}
3664
497c9a19
YL		 3665/*
3666 * This function currently is only a helper for the i386 smp boot process where
3667 * we need to reprogram the ioredtbls to cater for the cpus which have come online
fe402e1f 3668 * so mask in all cases should simply be apic->target_cpus()
497c9a19
YL		 3669 */
3670#ifdef CONFIG_SMP
3671void __init setup_ioapic_dest(void)
3672{
fad53995 3673 int pin, ioapic, irq, irq_entry;
22f65d31 3674 const struct cpumask *mask;
5451ddc5 3675 struct irq_data *idata;
497c9a19
YL		 3676
3677 if (skip_ioapic_setup == 1)
3678 return;
3679
fad53995 3680 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
b69c6c3b 3681 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
b9c61b70
YL		 3682 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3683 if (irq_entry == -1)
3684 continue;
3685 irq = pin_2_irq(irq_entry, ioapic, pin);
6c2e9403 3686
fad53995
EB		 3687 if ((ioapic > 0) && (irq > 16))
3688 continue;
3689
5451ddc5 3690 idata = irq_get_irq_data(irq);
6c2e9403 3691
b9c61b70
YL		 3692 /*
3693 * Honour affinities which have been set in early boot
3694 */
5451ddc5
TG		 3695 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3696 mask = idata->affinity;
b9c61b70
YL		 3697 else
3698 mask = apic->target_cpus();
497c9a19 3699
b9c61b70 3700 if (intr_remapping_enabled)
4c1bad6a 3701 intr_set_affinity(idata, mask, false);
b9c61b70 3702 else
5451ddc5 3703 ioapic_set_affinity(idata, mask, false);
497c9a19 3704 }
b9c61b70 3705
497c9a19
YL		 3706}
3707#endif
3708
54168ed7
IM		 3709#define IOAPIC_RESOURCE_NAME_SIZE 11
3710
3711static struct resource *ioapic_resources;
3712
ffc43836 3713static struct resource * __init ioapic_setup_resources(int nr_ioapics)
54168ed7
IM		 3714{
3715 unsigned long n;
3716 struct resource *res;
3717 char *mem;
3718 int i;
3719
3720 if (nr_ioapics <= 0)
3721 return NULL;
3722
3723 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3724 n *= nr_ioapics;
3725
3726 mem = alloc_bootmem(n);
3727 res = (void *)mem;
3728
ffc43836 3729 mem += sizeof(struct resource) * nr_ioapics;
54168ed7 3730
ffc43836
CG		 3731 for (i = 0; i < nr_ioapics; i++) {
3732 res[i].name = mem;
3733 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4343fe10 3734 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
ffc43836 3735 mem += IOAPIC_RESOURCE_NAME_SIZE;
54168ed7
IM		 3736 }
3737
3738 ioapic_resources = res;
3739
3740 return res;
3741}
54168ed7 3742
23f9b267 3743void __init ioapic_and_gsi_init(void)
136d249e
JF		 3744{
3745 io_apic_ops.init();
3746}
3747
3748static void __init __ioapic_init_mappings(void)
f3294a33
YL		 3749{
3750 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
54168ed7 3751 struct resource *ioapic_res;
d6c88a50 3752 int i;
f3294a33 3753
ffc43836 3754 ioapic_res = ioapic_setup_resources(nr_ioapics);
f3294a33
YL		 3755 for (i = 0; i < nr_ioapics; i++) {
3756 if (smp_found_config) {
d5371430 3757 ioapic_phys = mpc_ioapic_addr(i);
54168ed7 3758#ifdef CONFIG_X86_32
d6c88a50
TG		 3759 if (!ioapic_phys) {
3760 printk(KERN_ERR
3761 "WARNING: bogus zero IO-APIC "
3762 "address found in MPTABLE, "
3763 "disabling IO/APIC support!\n");
3764 smp_found_config = 0;
3765 skip_ioapic_setup = 1;
3766 goto fake_ioapic_page;
3767 }
54168ed7 3768#endif
f3294a33 3769 } else {
54168ed7 3770#ifdef CONFIG_X86_32
f3294a33 3771fake_ioapic_page:
54168ed7 3772#endif
e79c65a9 3773 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
f3294a33
YL		 3774 ioapic_phys = __pa(ioapic_phys);
3775 }
3776 set_fixmap_nocache(idx, ioapic_phys);
e79c65a9
CG		 3777 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3778 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3779 ioapic_phys);
f3294a33 3780 idx++;
54168ed7 3781
ffc43836 3782 ioapic_res->start = ioapic_phys;
e79c65a9 3783 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
ffc43836 3784 ioapic_res++;
f3294a33 3785 }
23f9b267
TG		 3786
3787 probe_nr_irqs_gsi();
f3294a33
YL		 3788}
3789
857fdc53 3790void __init ioapic_insert_resources(void)
54168ed7
IM		 3791{
3792 int i;
3793 struct resource *r = ioapic_resources;
3794
3795 if (!r) {
857fdc53 3796 if (nr_ioapics > 0)
04c93ce4
BZ		 3797 printk(KERN_ERR
3798 "IO APIC resources couldn't be allocated.\n");
857fdc53 3799 return;
54168ed7
IM		 3800 }
3801
3802 for (i = 0; i < nr_ioapics; i++) {
3803 insert_resource(&iomem_resource, r);
3804 r++;
3805 }
54168ed7 3806}
2a4ab640 3807
eddb0c55 3808int mp_find_ioapic(u32 gsi)
2a4ab640
FT		 3809{
3810 int i = 0;
3811
678301ec
PB		 3812 if (nr_ioapics == 0)
3813 return -1;
3814
2a4ab640
FT		 3815 /* Find the IOAPIC that manages this GSI. */
3816 for (i = 0; i < nr_ioapics; i++) {
c040aaeb
SS		 3817 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3818 if ((gsi >= gsi_cfg->gsi_base)
3819 && (gsi <= gsi_cfg->gsi_end))
2a4ab640
FT		 3820 return i;
3821 }
54168ed7 3822
2a4ab640
FT		 3823 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3824 return -1;
3825}
3826
eddb0c55 3827int mp_find_ioapic_pin(int ioapic, u32 gsi)
2a4ab640 3828{
c040aaeb
SS		 3829 struct mp_ioapic_gsi *gsi_cfg;
3830
2a4ab640
FT		 3831 if (WARN_ON(ioapic == -1))
3832 return -1;
c040aaeb
SS		 3833
3834 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3835 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2a4ab640
FT		 3836 return -1;
3837
c040aaeb 3838 return gsi - gsi_cfg->gsi_base;
2a4ab640
FT		 3839}
3840
41098ffe 3841static __init int bad_ioapic(unsigned long address)
2a4ab640
FT		 3842{
3843 if (nr_ioapics >= MAX_IO_APICS) {
73d63d03
SS		 3844 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3845 MAX_IO_APICS, nr_ioapics);
2a4ab640
FT		 3846 return 1;
3847 }
3848 if (!address) {
73d63d03 3849 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
2a4ab640
FT		 3850 return 1;
3851 }
54168ed7
IM		 3852 return 0;
3853}
3854
73d63d03
SS		 3855static __init int bad_ioapic_register(int idx)
3856{
3857 union IO_APIC_reg_00 reg_00;
3858 union IO_APIC_reg_01 reg_01;
3859 union IO_APIC_reg_02 reg_02;
3860
3861 reg_00.raw = io_apic_read(idx, 0);
3862 reg_01.raw = io_apic_read(idx, 1);
3863 reg_02.raw = io_apic_read(idx, 2);
3864
3865 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3866 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3867 mpc_ioapic_addr(idx));
3868 return 1;
3869 }
3870
3871 return 0;
3872}
3873
2a4ab640
FT		 3874void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3875{
3876 int idx = 0;
7716a5c4 3877 int entries;
c040aaeb 3878 struct mp_ioapic_gsi *gsi_cfg;
2a4ab640
FT		 3879
3880 if (bad_ioapic(address))
3881 return;
3882
3883 idx = nr_ioapics;
3884
d5371430
SS		 3885 ioapics[idx].mp_config.type = MP_IOAPIC;
3886 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3887 ioapics[idx].mp_config.apicaddr = address;
2a4ab640
FT		 3888
3889 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
73d63d03
SS		 3890
3891 if (bad_ioapic_register(idx)) {
3892 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3893 return;
3894 }
3895
d5371430
SS		 3896 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3897 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2a4ab640
FT		 3898
3899 /*
3900 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3901 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3902 */
7716a5c4 3903 entries = io_apic_get_redir_entries(idx);
c040aaeb
SS		 3904 gsi_cfg = mp_ioapic_gsi_routing(idx);
3905 gsi_cfg->gsi_base = gsi_base;
3906 gsi_cfg->gsi_end = gsi_base + entries - 1;
7716a5c4
EB		 3907
3908 /*
3909 * The number of IO-APIC IRQ registers (== #pins):
3910 */
b69c6c3b 3911 ioapics[idx].nr_registers = entries;
2a4ab640 3912
c040aaeb
SS		 3913 if (gsi_cfg->gsi_end >= gsi_top)
3914 gsi_top = gsi_cfg->gsi_end + 1;
2a4ab640 3915
73d63d03
SS		 3916 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3917 idx, mpc_ioapic_id(idx),
3918 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3919 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2a4ab640
FT		 3920
3921 nr_ioapics++;
3922}
05ddafb1
JP		 3923
3924/* Enable IOAPIC early just for system timer */
3925void __init pre_init_apic_IRQ0(void)
3926{
f880ec78 3927 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
05ddafb1
JP		 3928
3929 printk(KERN_INFO "Early APIC setup for system timer0\n");
3930#ifndef CONFIG_SMP
cb2ded37
YL		 3931 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3932 &phys_cpu_present_map);
05ddafb1 3933#endif
05ddafb1
JP		 3934 setup_local_APIC();
3935
f880ec78 3936 io_apic_setup_irq_pin(0, 0, &attr);
2c778651
TG		 3937 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
3938 "edge");
05ddafb1 3939}
Linux 6.x block layer and io_uring tree(s)