Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
8f47e163 | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
1da177e4 LT |
5 | * |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
f3c6ea1b | 33 | #include <linux/syscore_ops.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
5a0e3ad6 | 39 | #include <linux/slab.h> |
d4057bdb YL |
40 | #include <linux/bootmem.h> |
41 | #include <linux/dmar.h> | |
58ac1e76 | 42 | #include <linux/hpet.h> |
54d5d424 | 43 | |
d4057bdb | 44 | #include <asm/idle.h> |
1da177e4 LT |
45 | #include <asm/io.h> |
46 | #include <asm/smp.h> | |
6d652ea1 | 47 | #include <asm/cpu.h> |
1da177e4 | 48 | #include <asm/desc.h> |
d4057bdb YL |
49 | #include <asm/proto.h> |
50 | #include <asm/acpi.h> | |
51 | #include <asm/dma.h> | |
1da177e4 | 52 | #include <asm/timer.h> |
306e440d | 53 | #include <asm/i8259.h> |
2d3fcc1c | 54 | #include <asm/msidef.h> |
8b955b0d | 55 | #include <asm/hypertransport.h> |
a4dbc34d | 56 | #include <asm/setup.h> |
8a8f422d | 57 | #include <asm/irq_remapping.h> |
58ac1e76 | 58 | #include <asm/hpet.h> |
2c1b284e | 59 | #include <asm/hw_irq.h> |
1da177e4 | 60 | |
7b6aa335 | 61 | #include <asm/apic.h> |
1da177e4 | 62 | |
32f71aff | 63 | #define __apicdebuginit(type) static type __init |
136d249e | 64 | |
f44d1692 JL |
65 | #define for_each_ioapic(idx) \ |
66 | for ((idx) = 0; (idx) < nr_ioapics; (idx)++) | |
67 | #define for_each_ioapic_reverse(idx) \ | |
68 | for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--) | |
69 | #define for_each_pin(idx, pin) \ | |
70 | for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++) | |
71 | #define for_each_ioapic_pin(idx, pin) \ | |
72 | for_each_ioapic((idx)) \ | |
73 | for_each_pin((idx), (pin)) | |
74 | ||
2977fb3f CG |
75 | #define for_each_irq_pin(entry, head) \ |
76 | for (entry = head; entry; entry = entry->next) | |
32f71aff | 77 | |
1da177e4 | 78 | /* |
54168ed7 IM |
79 | * Is the SiS APIC rmw bug present ? |
80 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
81 | */ |
82 | int sis_apic_bug = -1; | |
83 | ||
dade7716 TG |
84 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
85 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
efa2559f | 86 | |
b69c6c3b SS |
87 | static struct ioapic { |
88 | /* | |
89 | * # of IRQ routing registers | |
90 | */ | |
91 | int nr_registers; | |
57a6f740 SS |
92 | /* |
93 | * Saved state during suspend/resume, or while enabling intr-remap. | |
94 | */ | |
95 | struct IO_APIC_route_entry *saved_registers; | |
d5371430 SS |
96 | /* I/O APIC config */ |
97 | struct mpc_ioapic mp_config; | |
c040aaeb SS |
98 | /* IO APIC gsi routing info */ |
99 | struct mp_ioapic_gsi gsi_config; | |
8f18c971 | 100 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
b69c6c3b | 101 | } ioapics[MAX_IO_APICS]; |
1da177e4 | 102 | |
6f50d45f | 103 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
d5371430 | 104 | |
6f50d45f | 105 | int mpc_ioapic_id(int ioapic_idx) |
d5371430 | 106 | { |
6f50d45f | 107 | return ioapics[ioapic_idx].mp_config.apicid; |
d5371430 SS |
108 | } |
109 | ||
6f50d45f | 110 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
d5371430 | 111 | { |
6f50d45f | 112 | return ioapics[ioapic_idx].mp_config.apicaddr; |
d5371430 SS |
113 | } |
114 | ||
6f50d45f | 115 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
c040aaeb | 116 | { |
6f50d45f | 117 | return &ioapics[ioapic_idx].gsi_config; |
c040aaeb | 118 | } |
9f640ccb | 119 | |
c040aaeb | 120 | int nr_ioapics; |
2a4ab640 | 121 | |
a4384df3 EB |
122 | /* The one past the highest gsi number used */ |
123 | u32 gsi_top; | |
5777372a | 124 | |
584f734d | 125 | /* MP IRQ source entries */ |
c2c21745 | 126 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
127 | |
128 | /* # of MP IRQ source entries */ | |
129 | int mp_irq_entries; | |
130 | ||
bb8187d3 | 131 | #ifdef CONFIG_EISA |
8732fc4b AS |
132 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
133 | #endif | |
134 | ||
135 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
136 | ||
efa2559f YL |
137 | int skip_ioapic_setup; |
138 | ||
7167d08e HK |
139 | /** |
140 | * disable_ioapic_support() - disables ioapic support at runtime | |
141 | */ | |
142 | void disable_ioapic_support(void) | |
65a4e574 IM |
143 | { |
144 | #ifdef CONFIG_PCI | |
145 | noioapicquirk = 1; | |
146 | noioapicreroute = -1; | |
147 | #endif | |
148 | skip_ioapic_setup = 1; | |
149 | } | |
150 | ||
54168ed7 | 151 | static int __init parse_noapic(char *str) |
efa2559f YL |
152 | { |
153 | /* disable IO-APIC */ | |
7167d08e | 154 | disable_ioapic_support(); |
efa2559f YL |
155 | return 0; |
156 | } | |
157 | early_param("noapic", parse_noapic); | |
66759a01 | 158 | |
20443598 SAS |
159 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
160 | struct io_apic_irq_attr *attr); | |
710dcda6 | 161 | |
2d8009ba FT |
162 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
163 | void mp_save_irq(struct mpc_intsrc *m) | |
164 | { | |
165 | int i; | |
166 | ||
167 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," | |
168 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
169 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, | |
170 | m->srcbusirq, m->dstapic, m->dstirq); | |
171 | ||
172 | for (i = 0; i < mp_irq_entries; i++) { | |
0e3fa13f | 173 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
2d8009ba FT |
174 | return; |
175 | } | |
176 | ||
0e3fa13f | 177 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
2d8009ba FT |
178 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
179 | panic("Max # of irq sources exceeded!!\n"); | |
180 | } | |
181 | ||
0b8f1efa YL |
182 | struct irq_pin_list { |
183 | int apic, pin; | |
184 | struct irq_pin_list *next; | |
185 | }; | |
186 | ||
7e495529 | 187 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
0b8f1efa | 188 | { |
2ee39065 | 189 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
0b8f1efa YL |
190 | } |
191 | ||
2d8009ba | 192 | |
a1420f39 | 193 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
97943390 | 194 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
a1420f39 | 195 | |
13a0c3c2 | 196 | int __init arch_early_irq_init(void) |
8f09cd20 | 197 | { |
0b8f1efa | 198 | struct irq_cfg *cfg; |
60c69948 | 199 | int count, node, i; |
d6c88a50 | 200 | |
bb84ac2d | 201 | if (!legacy_pic->nr_legacy_irqs) |
1f91233c | 202 | io_apic_irqs = ~0UL; |
1f91233c | 203 | |
f44d1692 | 204 | for_each_ioapic(i) { |
57a6f740 | 205 | ioapics[i].saved_registers = |
4c79185c | 206 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
b69c6c3b | 207 | ioapics[i].nr_registers, GFP_KERNEL); |
57a6f740 | 208 | if (!ioapics[i].saved_registers) |
4c79185c SS |
209 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
210 | } | |
211 | ||
0b8f1efa YL |
212 | cfg = irq_cfgx; |
213 | count = ARRAY_SIZE(irq_cfgx); | |
f6e9456c | 214 | node = cpu_to_node(0); |
8f09cd20 | 215 | |
0b8f1efa | 216 | for (i = 0; i < count; i++) { |
2c778651 | 217 | irq_set_chip_data(i, &cfg[i]); |
2ee39065 TG |
218 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
219 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); | |
97943390 SS |
220 | /* |
221 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
29c574c0 | 222 | * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. |
97943390 | 223 | */ |
54b56170 | 224 | if (i < legacy_pic->nr_legacy_irqs) { |
97943390 | 225 | cfg[i].vector = IRQ0_VECTOR + i; |
29c574c0 | 226 | cpumask_setall(cfg[i].domain); |
97943390 | 227 | } |
0b8f1efa | 228 | } |
13a0c3c2 YL |
229 | |
230 | return 0; | |
0b8f1efa | 231 | } |
8f09cd20 | 232 | |
32f5ef5d | 233 | static inline struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 234 | { |
2c778651 | 235 | return irq_get_chip_data(irq); |
8f09cd20 | 236 | } |
d6c88a50 | 237 | |
f981a3dc | 238 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
8f09cd20 | 239 | { |
0b8f1efa | 240 | struct irq_cfg *cfg; |
0f978f45 | 241 | |
2ee39065 | 242 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
6e2fff50 TG |
243 | if (!cfg) |
244 | return NULL; | |
2ee39065 | 245 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
6e2fff50 | 246 | goto out_cfg; |
2ee39065 | 247 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
6e2fff50 | 248 | goto out_domain; |
0b8f1efa | 249 | return cfg; |
6e2fff50 TG |
250 | out_domain: |
251 | free_cpumask_var(cfg->domain); | |
252 | out_cfg: | |
253 | kfree(cfg); | |
254 | return NULL; | |
8f09cd20 YL |
255 | } |
256 | ||
f981a3dc | 257 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
08c33db6 | 258 | { |
fbc6bff0 TG |
259 | if (!cfg) |
260 | return; | |
2c778651 | 261 | irq_set_chip_data(at, NULL); |
08c33db6 TG |
262 | free_cpumask_var(cfg->domain); |
263 | free_cpumask_var(cfg->old_domain); | |
264 | kfree(cfg); | |
265 | } | |
266 | ||
08c33db6 TG |
267 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
268 | { | |
269 | int res = irq_alloc_desc_at(at, node); | |
270 | struct irq_cfg *cfg; | |
271 | ||
272 | if (res < 0) { | |
273 | if (res != -EEXIST) | |
274 | return NULL; | |
32f5ef5d | 275 | cfg = irq_cfg(at); |
08c33db6 TG |
276 | if (cfg) |
277 | return cfg; | |
278 | } | |
279 | ||
f981a3dc | 280 | cfg = alloc_irq_cfg(at, node); |
08c33db6 | 281 | if (cfg) |
2c778651 | 282 | irq_set_chip_data(at, cfg); |
08c33db6 TG |
283 | else |
284 | irq_free_desc(at); | |
285 | return cfg; | |
286 | } | |
287 | ||
130fe05d LT |
288 | struct io_apic { |
289 | unsigned int index; | |
290 | unsigned int unused[3]; | |
291 | unsigned int data; | |
0280f7c4 SS |
292 | unsigned int unused2[11]; |
293 | unsigned int eoi; | |
130fe05d LT |
294 | }; |
295 | ||
296 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
297 | { | |
298 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
d5371430 | 299 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
130fe05d LT |
300 | } |
301 | ||
da165322 | 302 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
0280f7c4 SS |
303 | { |
304 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
305 | writel(vector, &io_apic->eoi); | |
306 | } | |
307 | ||
4a8e2a31 | 308 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
130fe05d LT |
309 | { |
310 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
311 | writel(reg, &io_apic->index); | |
312 | return readl(&io_apic->data); | |
313 | } | |
314 | ||
4a8e2a31 | 315 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d LT |
316 | { |
317 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
136d249e | 318 | |
130fe05d LT |
319 | writel(reg, &io_apic->index); |
320 | writel(value, &io_apic->data); | |
321 | } | |
322 | ||
323 | /* | |
324 | * Re-write a value: to be used for read-modify-write | |
325 | * cycles where the read already set up the index register. | |
326 | * | |
327 | * Older SiS APIC requires we rewrite the index register | |
328 | */ | |
4a8e2a31 | 329 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
130fe05d | 330 | { |
54168ed7 | 331 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
332 | |
333 | if (sis_apic_bug) | |
334 | writel(reg, &io_apic->index); | |
130fe05d LT |
335 | writel(value, &io_apic->data); |
336 | } | |
337 | ||
cf4c6a2f AK |
338 | union entry_union { |
339 | struct { u32 w1, w2; }; | |
340 | struct IO_APIC_route_entry entry; | |
341 | }; | |
342 | ||
e57253a8 SS |
343 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
344 | { | |
345 | union entry_union eu; | |
346 | ||
347 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
348 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
136d249e | 349 | |
e57253a8 SS |
350 | return eu.entry; |
351 | } | |
352 | ||
cf4c6a2f AK |
353 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
354 | { | |
355 | union entry_union eu; | |
356 | unsigned long flags; | |
136d249e | 357 | |
dade7716 | 358 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
e57253a8 | 359 | eu.entry = __ioapic_read_entry(apic, pin); |
dade7716 | 360 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
136d249e | 361 | |
cf4c6a2f AK |
362 | return eu.entry; |
363 | } | |
364 | ||
f9dadfa7 LT |
365 | /* |
366 | * When we write a new IO APIC routing entry, we need to write the high | |
367 | * word first! If the mask bit in the low word is clear, we will enable | |
368 | * the interrupt, and we need to make sure the entry is fully populated | |
369 | * before that happens. | |
370 | */ | |
136d249e | 371 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
cf4c6a2f | 372 | { |
50a8d4d2 F |
373 | union entry_union eu = {{0, 0}}; |
374 | ||
cf4c6a2f | 375 | eu.entry = e; |
f9dadfa7 LT |
376 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
377 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
378 | } |
379 | ||
1a8ce7ff | 380 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
d15512f4 AK |
381 | { |
382 | unsigned long flags; | |
136d249e | 383 | |
dade7716 | 384 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
d15512f4 | 385 | __ioapic_write_entry(apic, pin, e); |
dade7716 | 386 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f9dadfa7 LT |
387 | } |
388 | ||
389 | /* | |
390 | * When we mask an IO APIC routing entry, we need to write the low | |
391 | * word first, in order to set the mask bit before we change the | |
392 | * high bits! | |
393 | */ | |
394 | static void ioapic_mask_entry(int apic, int pin) | |
395 | { | |
396 | unsigned long flags; | |
397 | union entry_union eu = { .entry.mask = 1 }; | |
398 | ||
dade7716 | 399 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
cf4c6a2f AK |
400 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
401 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
dade7716 | 402 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
403 | } |
404 | ||
1da177e4 LT |
405 | /* |
406 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
407 | * shared ISA-space IRQs, so we have to support them. We are super | |
408 | * fast in the common case, and fast for shared ISA-space IRQs. | |
409 | */ | |
136d249e | 410 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
1da177e4 | 411 | { |
2977fb3f | 412 | struct irq_pin_list **last, *entry; |
0f978f45 | 413 | |
2977fb3f CG |
414 | /* don't allow duplicates */ |
415 | last = &cfg->irq_2_pin; | |
416 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
0f978f45 | 417 | if (entry->apic == apic && entry->pin == pin) |
f3d1915a | 418 | return 0; |
2977fb3f | 419 | last = &entry->next; |
1da177e4 | 420 | } |
0f978f45 | 421 | |
7e495529 | 422 | entry = alloc_irq_pin_list(node); |
a7428cd2 | 423 | if (!entry) { |
c767a54b JP |
424 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
425 | node, apic, pin); | |
f3d1915a | 426 | return -ENOMEM; |
a7428cd2 | 427 | } |
1da177e4 LT |
428 | entry->apic = apic; |
429 | entry->pin = pin; | |
875e68ec | 430 | |
2977fb3f | 431 | *last = entry; |
f3d1915a CG |
432 | return 0; |
433 | } | |
434 | ||
435 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) | |
436 | { | |
7e495529 | 437 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
f3d1915a | 438 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
1da177e4 LT |
439 | } |
440 | ||
441 | /* | |
442 | * Reroute an IRQ to a different pin. | |
443 | */ | |
85ac16d0 | 444 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
4eea6fff JF |
445 | int oldapic, int oldpin, |
446 | int newapic, int newpin) | |
1da177e4 | 447 | { |
535b6429 | 448 | struct irq_pin_list *entry; |
1da177e4 | 449 | |
2977fb3f | 450 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
1da177e4 LT |
451 | if (entry->apic == oldapic && entry->pin == oldpin) { |
452 | entry->apic = newapic; | |
453 | entry->pin = newpin; | |
0f978f45 | 454 | /* every one is different, right? */ |
4eea6fff | 455 | return; |
0f978f45 | 456 | } |
1da177e4 | 457 | } |
0f978f45 | 458 | |
4eea6fff JF |
459 | /* old apic/pin didn't exist, so just add new ones */ |
460 | add_pin_to_irq_node(cfg, node, newapic, newpin); | |
1da177e4 LT |
461 | } |
462 | ||
c29d9db3 SS |
463 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
464 | int mask_and, int mask_or, | |
465 | void (*final)(struct irq_pin_list *entry)) | |
466 | { | |
467 | unsigned int reg, pin; | |
468 | ||
469 | pin = entry->pin; | |
470 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
471 | reg &= mask_and; | |
472 | reg |= mask_or; | |
473 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
474 | if (final) | |
475 | final(entry); | |
476 | } | |
477 | ||
2f210deb JF |
478 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
479 | int mask_and, int mask_or, | |
480 | void (*final)(struct irq_pin_list *entry)) | |
87783be4 | 481 | { |
87783be4 | 482 | struct irq_pin_list *entry; |
047c8fdb | 483 | |
c29d9db3 SS |
484 | for_each_irq_pin(entry, cfg->irq_2_pin) |
485 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | |
486 | } | |
487 | ||
7f3e632f | 488 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 489 | { |
87783be4 CG |
490 | /* |
491 | * Synchronize the IO-APIC and the CPU by doing | |
492 | * a dummy read from the IO-APIC | |
493 | */ | |
494 | struct io_apic __iomem *io_apic; | |
136d249e | 495 | |
87783be4 | 496 | io_apic = io_apic_base(entry->apic); |
4e738e2f | 497 | readl(&io_apic->data); |
1da177e4 LT |
498 | } |
499 | ||
dd5f15e5 | 500 | static void mask_ioapic(struct irq_cfg *cfg) |
87783be4 | 501 | { |
dd5f15e5 TG |
502 | unsigned long flags; |
503 | ||
504 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 505 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
dd5f15e5 | 506 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
87783be4 | 507 | } |
1da177e4 | 508 | |
90297c5f | 509 | static void mask_ioapic_irq(struct irq_data *data) |
1da177e4 | 510 | { |
90297c5f | 511 | mask_ioapic(data->chip_data); |
dd5f15e5 | 512 | } |
3145e941 | 513 | |
dd5f15e5 TG |
514 | static void __unmask_ioapic(struct irq_cfg *cfg) |
515 | { | |
516 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
1da177e4 LT |
517 | } |
518 | ||
dd5f15e5 | 519 | static void unmask_ioapic(struct irq_cfg *cfg) |
1da177e4 LT |
520 | { |
521 | unsigned long flags; | |
522 | ||
dade7716 | 523 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
dd5f15e5 | 524 | __unmask_ioapic(cfg); |
dade7716 | 525 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
526 | } |
527 | ||
90297c5f | 528 | static void unmask_ioapic_irq(struct irq_data *data) |
3145e941 | 529 | { |
90297c5f | 530 | unmask_ioapic(data->chip_data); |
3145e941 YL |
531 | } |
532 | ||
c0205701 SS |
533 | /* |
534 | * IO-APIC versions below 0x20 don't support EOI register. | |
535 | * For the record, here is the information about various versions: | |
536 | * 0Xh 82489DX | |
537 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant | |
538 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant | |
539 | * 30h-FFh Reserved | |
540 | * | |
541 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic | |
542 | * version as 0x2. This is an error with documentation and these ICH chips | |
543 | * use io-apic's of version 0x20. | |
544 | * | |
545 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. | |
546 | * Otherwise, we simulate the EOI message manually by changing the trigger | |
547 | * mode to edge and then back to level, with RTE being masked during this. | |
548 | */ | |
da165322 | 549 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
c0205701 SS |
550 | { |
551 | if (mpc_ioapic_ver(apic) >= 0x20) { | |
da165322 | 552 | io_apic_eoi(apic, vector); |
c0205701 SS |
553 | } else { |
554 | struct IO_APIC_route_entry entry, entry1; | |
555 | ||
556 | entry = entry1 = __ioapic_read_entry(apic, pin); | |
557 | ||
558 | /* | |
559 | * Mask the entry and change the trigger mode to edge. | |
560 | */ | |
561 | entry1.mask = 1; | |
562 | entry1.trigger = IOAPIC_EDGE; | |
563 | ||
564 | __ioapic_write_entry(apic, pin, entry1); | |
565 | ||
566 | /* | |
567 | * Restore the previous level triggered entry. | |
568 | */ | |
569 | __ioapic_write_entry(apic, pin, entry); | |
570 | } | |
571 | } | |
572 | ||
9b1b0e42 | 573 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
c0205701 SS |
574 | { |
575 | struct irq_pin_list *entry; | |
576 | unsigned long flags; | |
577 | ||
578 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
579 | for_each_irq_pin(entry, cfg->irq_2_pin) | |
da165322 JR |
580 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
581 | cfg->vector); | |
c0205701 SS |
582 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
583 | } | |
584 | ||
1da177e4 LT |
585 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
586 | { | |
587 | struct IO_APIC_route_entry entry; | |
36062448 | 588 | |
1da177e4 | 589 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 590 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
591 | if (entry.delivery_mode == dest_SMI) |
592 | return; | |
1e75b31d | 593 | |
1da177e4 | 594 | /* |
1e75b31d SS |
595 | * Make sure the entry is masked and re-read the contents to check |
596 | * if it is a level triggered pin and if the remote-IRR is set. | |
597 | */ | |
598 | if (!entry.mask) { | |
599 | entry.mask = 1; | |
600 | ioapic_write_entry(apic, pin, entry); | |
601 | entry = ioapic_read_entry(apic, pin); | |
602 | } | |
603 | ||
604 | if (entry.irr) { | |
c0205701 SS |
605 | unsigned long flags; |
606 | ||
1e75b31d SS |
607 | /* |
608 | * Make sure the trigger mode is set to level. Explicit EOI | |
609 | * doesn't clear the remote-IRR if the trigger mode is not | |
610 | * set to level. | |
611 | */ | |
612 | if (!entry.trigger) { | |
613 | entry.trigger = IOAPIC_LEVEL; | |
614 | ioapic_write_entry(apic, pin, entry); | |
615 | } | |
616 | ||
c0205701 | 617 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
da165322 | 618 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
c0205701 | 619 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1e75b31d SS |
620 | } |
621 | ||
622 | /* | |
623 | * Clear the rest of the bits in the IO-APIC RTE except for the mask | |
624 | * bit. | |
1da177e4 | 625 | */ |
f9dadfa7 | 626 | ioapic_mask_entry(apic, pin); |
1e75b31d SS |
627 | entry = ioapic_read_entry(apic, pin); |
628 | if (entry.irr) | |
c767a54b | 629 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
1e75b31d | 630 | mpc_ioapic_id(apic), pin); |
1da177e4 LT |
631 | } |
632 | ||
54168ed7 | 633 | static void clear_IO_APIC (void) |
1da177e4 LT |
634 | { |
635 | int apic, pin; | |
636 | ||
f44d1692 JL |
637 | for_each_ioapic_pin(apic, pin) |
638 | clear_IO_APIC_pin(apic, pin); | |
1da177e4 LT |
639 | } |
640 | ||
54168ed7 | 641 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
642 | /* |
643 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
644 | * specific CPU-side IRQs. | |
645 | */ | |
646 | ||
647 | #define MAX_PIRQS 8 | |
3bd25d0f YL |
648 | static int pirq_entries[MAX_PIRQS] = { |
649 | [0 ... MAX_PIRQS - 1] = -1 | |
650 | }; | |
1da177e4 | 651 | |
1da177e4 LT |
652 | static int __init ioapic_pirq_setup(char *str) |
653 | { | |
654 | int i, max; | |
655 | int ints[MAX_PIRQS+1]; | |
656 | ||
657 | get_options(str, ARRAY_SIZE(ints), ints); | |
658 | ||
1da177e4 LT |
659 | apic_printk(APIC_VERBOSE, KERN_INFO |
660 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
661 | max = MAX_PIRQS; | |
662 | if (ints[0] < MAX_PIRQS) | |
663 | max = ints[0]; | |
664 | ||
665 | for (i = 0; i < max; i++) { | |
666 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
667 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
668 | /* | |
669 | * PIRQs are mapped upside down, usually. | |
670 | */ | |
671 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
672 | } | |
673 | return 1; | |
674 | } | |
675 | ||
676 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
677 | #endif /* CONFIG_X86_32 */ |
678 | ||
54168ed7 | 679 | /* |
05c3dc2c | 680 | * Saves all the IO-APIC RTE's |
54168ed7 | 681 | */ |
31dce14a | 682 | int save_ioapic_entries(void) |
54168ed7 | 683 | { |
54168ed7 | 684 | int apic, pin; |
31dce14a | 685 | int err = 0; |
54168ed7 | 686 | |
f44d1692 | 687 | for_each_ioapic(apic) { |
57a6f740 | 688 | if (!ioapics[apic].saved_registers) { |
31dce14a SS |
689 | err = -ENOMEM; |
690 | continue; | |
691 | } | |
54168ed7 | 692 | |
f44d1692 | 693 | for_each_pin(apic, pin) |
57a6f740 | 694 | ioapics[apic].saved_registers[pin] = |
54168ed7 | 695 | ioapic_read_entry(apic, pin); |
b24696bc | 696 | } |
5ffa4eb2 | 697 | |
31dce14a | 698 | return err; |
54168ed7 IM |
699 | } |
700 | ||
b24696bc FY |
701 | /* |
702 | * Mask all IO APIC entries. | |
703 | */ | |
31dce14a | 704 | void mask_ioapic_entries(void) |
05c3dc2c SS |
705 | { |
706 | int apic, pin; | |
707 | ||
f44d1692 | 708 | for_each_ioapic(apic) { |
2f344d2e | 709 | if (!ioapics[apic].saved_registers) |
31dce14a | 710 | continue; |
b24696bc | 711 | |
f44d1692 | 712 | for_each_pin(apic, pin) { |
05c3dc2c SS |
713 | struct IO_APIC_route_entry entry; |
714 | ||
57a6f740 | 715 | entry = ioapics[apic].saved_registers[pin]; |
05c3dc2c SS |
716 | if (!entry.mask) { |
717 | entry.mask = 1; | |
718 | ioapic_write_entry(apic, pin, entry); | |
719 | } | |
720 | } | |
721 | } | |
722 | } | |
723 | ||
b24696bc | 724 | /* |
57a6f740 | 725 | * Restore IO APIC entries which was saved in the ioapic structure. |
b24696bc | 726 | */ |
31dce14a | 727 | int restore_ioapic_entries(void) |
54168ed7 IM |
728 | { |
729 | int apic, pin; | |
730 | ||
f44d1692 | 731 | for_each_ioapic(apic) { |
2f344d2e | 732 | if (!ioapics[apic].saved_registers) |
31dce14a | 733 | continue; |
b24696bc | 734 | |
f44d1692 | 735 | for_each_pin(apic, pin) |
54168ed7 | 736 | ioapic_write_entry(apic, pin, |
57a6f740 | 737 | ioapics[apic].saved_registers[pin]); |
5ffa4eb2 | 738 | } |
b24696bc | 739 | return 0; |
54168ed7 IM |
740 | } |
741 | ||
1da177e4 LT |
742 | /* |
743 | * Find the IRQ entry number of a certain pin. | |
744 | */ | |
6f50d45f | 745 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
1da177e4 LT |
746 | { |
747 | int i; | |
748 | ||
749 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 | 750 | if (mp_irqs[i].irqtype == type && |
6f50d45f | 751 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
c2c21745 JSR |
752 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
753 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
754 | return i; |
755 | ||
756 | return -1; | |
757 | } | |
758 | ||
759 | /* | |
760 | * Find the pin to which IRQ[irq] (ISA) is connected | |
761 | */ | |
fcfd636a | 762 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
763 | { |
764 | int i; | |
765 | ||
766 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 767 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 768 | |
d27e2b8e | 769 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
770 | (mp_irqs[i].irqtype == type) && |
771 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 772 | |
c2c21745 | 773 | return mp_irqs[i].dstirq; |
1da177e4 LT |
774 | } |
775 | return -1; | |
776 | } | |
777 | ||
fcfd636a EB |
778 | static int __init find_isa_irq_apic(int irq, int type) |
779 | { | |
780 | int i; | |
781 | ||
782 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 783 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 784 | |
73b2961b | 785 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
786 | (mp_irqs[i].irqtype == type) && |
787 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
788 | break; |
789 | } | |
6f50d45f | 790 | |
fcfd636a | 791 | if (i < mp_irq_entries) { |
6f50d45f YL |
792 | int ioapic_idx; |
793 | ||
f44d1692 | 794 | for_each_ioapic(ioapic_idx) |
6f50d45f YL |
795 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
796 | return ioapic_idx; | |
fcfd636a EB |
797 | } |
798 | ||
799 | return -1; | |
800 | } | |
801 | ||
bb8187d3 | 802 | #ifdef CONFIG_EISA |
1da177e4 LT |
803 | /* |
804 | * EISA Edge/Level control register, ELCR | |
805 | */ | |
806 | static int EISA_ELCR(unsigned int irq) | |
807 | { | |
b81bb373 | 808 | if (irq < legacy_pic->nr_legacy_irqs) { |
1da177e4 LT |
809 | unsigned int port = 0x4d0 + (irq >> 3); |
810 | return (inb(port) >> (irq & 7)) & 1; | |
811 | } | |
812 | apic_printk(APIC_VERBOSE, KERN_INFO | |
813 | "Broken MPtable reports ISA irq %d\n", irq); | |
814 | return 0; | |
815 | } | |
54168ed7 | 816 | |
c0a282c2 | 817 | #endif |
1da177e4 | 818 | |
6728801d AS |
819 | /* ISA interrupts are always polarity zero edge triggered, |
820 | * when listed as conforming in the MP table. */ | |
821 | ||
822 | #define default_ISA_trigger(idx) (0) | |
823 | #define default_ISA_polarity(idx) (0) | |
824 | ||
1da177e4 LT |
825 | /* EISA interrupts are always polarity zero and can be edge or level |
826 | * trigger depending on the ELCR value. If an interrupt is listed as | |
827 | * EISA conforming in the MP table, that means its trigger type must | |
828 | * be read in from the ELCR */ | |
829 | ||
c2c21745 | 830 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 831 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
832 | |
833 | /* PCI interrupts are always polarity one level triggered, | |
834 | * when listed as conforming in the MP table. */ | |
835 | ||
836 | #define default_PCI_trigger(idx) (1) | |
837 | #define default_PCI_polarity(idx) (1) | |
838 | ||
b77cf6a8 | 839 | static int irq_polarity(int idx) |
1da177e4 | 840 | { |
c2c21745 | 841 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
842 | int polarity; |
843 | ||
844 | /* | |
845 | * Determine IRQ line polarity (high active or low active): | |
846 | */ | |
c2c21745 | 847 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 848 | { |
54168ed7 IM |
849 | case 0: /* conforms, ie. bus-type dependent polarity */ |
850 | if (test_bit(bus, mp_bus_not_pci)) | |
851 | polarity = default_ISA_polarity(idx); | |
852 | else | |
853 | polarity = default_PCI_polarity(idx); | |
854 | break; | |
855 | case 1: /* high active */ | |
856 | { | |
857 | polarity = 0; | |
858 | break; | |
859 | } | |
860 | case 2: /* reserved */ | |
861 | { | |
c767a54b | 862 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
863 | polarity = 1; |
864 | break; | |
865 | } | |
866 | case 3: /* low active */ | |
867 | { | |
868 | polarity = 1; | |
869 | break; | |
870 | } | |
871 | default: /* invalid */ | |
872 | { | |
c767a54b | 873 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
874 | polarity = 1; |
875 | break; | |
876 | } | |
1da177e4 LT |
877 | } |
878 | return polarity; | |
879 | } | |
880 | ||
b77cf6a8 | 881 | static int irq_trigger(int idx) |
1da177e4 | 882 | { |
c2c21745 | 883 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
884 | int trigger; |
885 | ||
886 | /* | |
887 | * Determine IRQ trigger mode (edge or level sensitive): | |
888 | */ | |
c2c21745 | 889 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 890 | { |
54168ed7 IM |
891 | case 0: /* conforms, ie. bus-type dependent */ |
892 | if (test_bit(bus, mp_bus_not_pci)) | |
893 | trigger = default_ISA_trigger(idx); | |
894 | else | |
895 | trigger = default_PCI_trigger(idx); | |
bb8187d3 | 896 | #ifdef CONFIG_EISA |
54168ed7 IM |
897 | switch (mp_bus_id_to_type[bus]) { |
898 | case MP_BUS_ISA: /* ISA pin */ | |
899 | { | |
900 | /* set before the switch */ | |
901 | break; | |
902 | } | |
903 | case MP_BUS_EISA: /* EISA pin */ | |
904 | { | |
905 | trigger = default_EISA_trigger(idx); | |
906 | break; | |
907 | } | |
908 | case MP_BUS_PCI: /* PCI pin */ | |
909 | { | |
910 | /* set before the switch */ | |
911 | break; | |
912 | } | |
54168ed7 IM |
913 | default: |
914 | { | |
c767a54b | 915 | pr_warn("broken BIOS!!\n"); |
54168ed7 IM |
916 | trigger = 1; |
917 | break; | |
918 | } | |
919 | } | |
920 | #endif | |
1da177e4 | 921 | break; |
54168ed7 | 922 | case 1: /* edge */ |
1da177e4 | 923 | { |
54168ed7 | 924 | trigger = 0; |
1da177e4 LT |
925 | break; |
926 | } | |
54168ed7 | 927 | case 2: /* reserved */ |
1da177e4 | 928 | { |
c767a54b | 929 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 930 | trigger = 1; |
1da177e4 LT |
931 | break; |
932 | } | |
54168ed7 | 933 | case 3: /* level */ |
1da177e4 | 934 | { |
54168ed7 | 935 | trigger = 1; |
1da177e4 LT |
936 | break; |
937 | } | |
54168ed7 | 938 | default: /* invalid */ |
1da177e4 | 939 | { |
c767a54b | 940 | pr_warn("broken BIOS!!\n"); |
54168ed7 | 941 | trigger = 0; |
1da177e4 LT |
942 | break; |
943 | } | |
944 | } | |
945 | return trigger; | |
946 | } | |
947 | ||
1da177e4 LT |
948 | static int pin_2_irq(int idx, int apic, int pin) |
949 | { | |
d464207c | 950 | int irq; |
c2c21745 | 951 | int bus = mp_irqs[idx].srcbus; |
c040aaeb | 952 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
1da177e4 LT |
953 | |
954 | /* | |
955 | * Debugging check, we are in big trouble if this message pops up! | |
956 | */ | |
c2c21745 | 957 | if (mp_irqs[idx].dstirq != pin) |
c767a54b | 958 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
1da177e4 | 959 | |
54168ed7 | 960 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 961 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 962 | } else { |
c040aaeb | 963 | u32 gsi = gsi_cfg->gsi_base + pin; |
988856ee EB |
964 | |
965 | if (gsi >= NR_IRQS_LEGACY) | |
966 | irq = gsi; | |
967 | else | |
a4384df3 | 968 | irq = gsi_top + gsi; |
1da177e4 LT |
969 | } |
970 | ||
54168ed7 | 971 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
972 | /* |
973 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
974 | */ | |
975 | if ((pin >= 16) && (pin <= 23)) { | |
976 | if (pirq_entries[pin-16] != -1) { | |
977 | if (!pirq_entries[pin-16]) { | |
978 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
979 | "disabling PIRQ%d\n", pin-16); | |
980 | } else { | |
981 | irq = pirq_entries[pin-16]; | |
982 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
983 | "using PIRQ%d -> IRQ %d\n", | |
984 | pin-16, irq); | |
985 | } | |
986 | } | |
987 | } | |
54168ed7 IM |
988 | #endif |
989 | ||
1da177e4 LT |
990 | return irq; |
991 | } | |
992 | ||
e20c06fd YL |
993 | /* |
994 | * Find a specific PCI IRQ entry. | |
995 | * Not an __init, possibly needed by modules | |
996 | */ | |
997 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, | |
e5198075 | 998 | struct io_apic_irq_attr *irq_attr) |
e20c06fd | 999 | { |
6f50d45f | 1000 | int ioapic_idx, i, best_guess = -1; |
e20c06fd YL |
1001 | |
1002 | apic_printk(APIC_DEBUG, | |
1003 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
1004 | bus, slot, pin); | |
1005 | if (test_bit(bus, mp_bus_not_pci)) { | |
1006 | apic_printk(APIC_VERBOSE, | |
1007 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
1008 | return -1; | |
1009 | } | |
1010 | for (i = 0; i < mp_irq_entries; i++) { | |
1011 | int lbus = mp_irqs[i].srcbus; | |
1012 | ||
f44d1692 | 1013 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1014 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
e20c06fd YL |
1015 | mp_irqs[i].dstapic == MP_APIC_ALL) |
1016 | break; | |
1017 | ||
1018 | if (!test_bit(lbus, mp_bus_not_pci) && | |
3eb2be5f | 1019 | mp_irqs[i].irqtype == mp_INT && |
e20c06fd YL |
1020 | (bus == lbus) && |
1021 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { | |
6f50d45f | 1022 | int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); |
e20c06fd | 1023 | |
6f50d45f | 1024 | if (!(ioapic_idx || IO_APIC_IRQ(irq))) |
e20c06fd YL |
1025 | continue; |
1026 | ||
1027 | if (pin == (mp_irqs[i].srcbusirq & 3)) { | |
6f50d45f | 1028 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1029 | mp_irqs[i].dstirq, |
1030 | irq_trigger(i), | |
1031 | irq_polarity(i)); | |
e20c06fd YL |
1032 | return irq; |
1033 | } | |
1034 | /* | |
1035 | * Use the first all-but-pin matching entry as a | |
1036 | * best-guess fuzzy result for broken mptables. | |
1037 | */ | |
1038 | if (best_guess < 0) { | |
6f50d45f | 1039 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
e5198075 YL |
1040 | mp_irqs[i].dstirq, |
1041 | irq_trigger(i), | |
1042 | irq_polarity(i)); | |
e20c06fd YL |
1043 | best_guess = irq; |
1044 | } | |
1045 | } | |
1046 | } | |
1047 | return best_guess; | |
1048 | } | |
1049 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); | |
1050 | ||
497c9a19 YL |
1051 | void lock_vector_lock(void) |
1052 | { | |
1053 | /* Used to the online set of cpus does not change | |
1054 | * during assign_irq_vector. | |
1055 | */ | |
dade7716 | 1056 | raw_spin_lock(&vector_lock); |
497c9a19 | 1057 | } |
1da177e4 | 1058 | |
497c9a19 | 1059 | void unlock_vector_lock(void) |
1da177e4 | 1060 | { |
dade7716 | 1061 | raw_spin_unlock(&vector_lock); |
497c9a19 | 1062 | } |
1da177e4 | 1063 | |
e7986739 MT |
1064 | static int |
1065 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1066 | { |
047c8fdb YL |
1067 | /* |
1068 | * NOTE! The local APIC isn't very good at handling | |
1069 | * multiple interrupts at the same interrupt level. | |
1070 | * As the interrupt level is determined by taking the | |
1071 | * vector number and shifting that right by 4, we | |
1072 | * want to spread these out a bit so that they don't | |
1073 | * all fall in the same interrupt level. | |
1074 | * | |
1075 | * Also, we've got to be careful not to trash gate | |
1076 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1077 | */ | |
6579b474 | 1078 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1bccd58b | 1079 | static int current_offset = VECTOR_OFFSET_START % 16; |
22f65d31 MT |
1080 | int cpu, err; |
1081 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1082 | |
23359a88 | 1083 | if (cfg->move_in_progress) |
54168ed7 | 1084 | return -EBUSY; |
0a1ad60d | 1085 | |
22f65d31 MT |
1086 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1087 | return -ENOMEM; | |
ace80ab7 | 1088 | |
e7986739 | 1089 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 | 1090 | err = -ENOSPC; |
b39f25a8 SS |
1091 | cpumask_clear(cfg->old_domain); |
1092 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
1093 | while (cpu < nr_cpu_ids) { | |
1ac322d0 | 1094 | int new_cpu, vector, offset; |
497c9a19 | 1095 | |
1ac322d0 | 1096 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
497c9a19 | 1097 | |
332afa65 | 1098 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
1ac322d0 SS |
1099 | err = 0; |
1100 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
1101 | break; | |
1102 | /* | |
1103 | * New cpumask using the vector is a proper subset of | |
1104 | * the current in use mask. So cleanup the vector | |
1105 | * allocation for the members that are not used anymore. | |
1106 | */ | |
1107 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
29c574c0 SS |
1108 | cfg->move_in_progress = |
1109 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
1ac322d0 SS |
1110 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); |
1111 | break; | |
332afa65 | 1112 | } |
497c9a19 | 1113 | |
54168ed7 IM |
1114 | vector = current_vector; |
1115 | offset = current_offset; | |
497c9a19 | 1116 | next: |
1bccd58b | 1117 | vector += 16; |
54168ed7 | 1118 | if (vector >= first_system_vector) { |
1bccd58b | 1119 | offset = (offset + 1) % 16; |
6579b474 | 1120 | vector = FIRST_EXTERNAL_VECTOR + offset; |
54168ed7 | 1121 | } |
8637e38a AG |
1122 | |
1123 | if (unlikely(current_vector == vector)) { | |
b39f25a8 SS |
1124 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
1125 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
1126 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
54168ed7 | 1127 | continue; |
8637e38a | 1128 | } |
b77b881f YL |
1129 | |
1130 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1131 | goto next; |
b77b881f | 1132 | |
9345005f PB |
1133 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { |
1134 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) | |
54168ed7 | 1135 | goto next; |
9345005f | 1136 | } |
54168ed7 IM |
1137 | /* Found one! */ |
1138 | current_vector = vector; | |
1139 | current_offset = offset; | |
1ac322d0 | 1140 | if (cfg->vector) { |
22f65d31 | 1141 | cpumask_copy(cfg->old_domain, cfg->domain); |
29c574c0 SS |
1142 | cfg->move_in_progress = |
1143 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
7a959cff | 1144 | } |
22f65d31 | 1145 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1146 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1147 | cfg->vector = vector; | |
22f65d31 MT |
1148 | cpumask_copy(cfg->domain, tmp_mask); |
1149 | err = 0; | |
1150 | break; | |
54168ed7 | 1151 | } |
22f65d31 MT |
1152 | free_cpumask_var(tmp_mask); |
1153 | return err; | |
497c9a19 YL |
1154 | } |
1155 | ||
9338ad6f | 1156 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
497c9a19 YL |
1157 | { |
1158 | int err; | |
ace80ab7 | 1159 | unsigned long flags; |
ace80ab7 | 1160 | |
dade7716 | 1161 | raw_spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 1162 | err = __assign_irq_vector(irq, cfg, mask); |
dade7716 | 1163 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1164 | return err; |
1165 | } | |
1166 | ||
3145e941 | 1167 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1168 | { |
497c9a19 YL |
1169 | int cpu, vector; |
1170 | ||
497c9a19 YL |
1171 | BUG_ON(!cfg->vector); |
1172 | ||
1173 | vector = cfg->vector; | |
1d44b30f | 1174 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
9345005f | 1175 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
497c9a19 YL |
1176 | |
1177 | cfg->vector = 0; | |
22f65d31 | 1178 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1179 | |
1180 | if (likely(!cfg->move_in_progress)) | |
1181 | return; | |
1d44b30f | 1182 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
9345005f | 1183 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
0ca4b6b0 MW |
1184 | if (per_cpu(vector_irq, cpu)[vector] != irq) |
1185 | continue; | |
9345005f | 1186 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
0ca4b6b0 MW |
1187 | break; |
1188 | } | |
1189 | } | |
1190 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1191 | } |
1192 | ||
1193 | void __setup_vector_irq(int cpu) | |
1194 | { | |
1195 | /* Initialize vector_irq on a new cpu */ | |
497c9a19 YL |
1196 | int irq, vector; |
1197 | struct irq_cfg *cfg; | |
1198 | ||
9d133e5d SS |
1199 | /* |
1200 | * vector_lock will make sure that we don't run into irq vector | |
1201 | * assignments that might be happening on another cpu in parallel, | |
1202 | * while we setup our initial vector to irq mappings. | |
1203 | */ | |
dade7716 | 1204 | raw_spin_lock(&vector_lock); |
497c9a19 | 1205 | /* Mark the inuse vectors */ |
ad9f4334 | 1206 | for_each_active_irq(irq) { |
32f5ef5d | 1207 | cfg = irq_cfg(irq); |
ad9f4334 TG |
1208 | if (!cfg) |
1209 | continue; | |
36e9e1ea | 1210 | |
22f65d31 | 1211 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1212 | continue; |
1213 | vector = cfg->vector; | |
497c9a19 YL |
1214 | per_cpu(vector_irq, cpu)[vector] = irq; |
1215 | } | |
1216 | /* Mark the free vectors */ | |
1217 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1218 | irq = per_cpu(vector_irq, cpu)[vector]; | |
9345005f | 1219 | if (irq <= VECTOR_UNDEFINED) |
497c9a19 YL |
1220 | continue; |
1221 | ||
1222 | cfg = irq_cfg(irq); | |
22f65d31 | 1223 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
9345005f | 1224 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
54168ed7 | 1225 | } |
dade7716 | 1226 | raw_spin_unlock(&vector_lock); |
1da177e4 | 1227 | } |
3fde6900 | 1228 | |
f5b9ed7a | 1229 | static struct irq_chip ioapic_chip; |
1da177e4 | 1230 | |
047c8fdb | 1231 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1232 | static inline int IO_APIC_irq_trigger(int irq) |
1233 | { | |
d6c88a50 | 1234 | int apic, idx, pin; |
1d025192 | 1235 | |
f44d1692 JL |
1236 | for_each_ioapic_pin(apic, pin) { |
1237 | idx = find_irq_entry(apic, pin, mp_INT); | |
1238 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1239 | return irq_trigger(idx); | |
d6c88a50 TG |
1240 | } |
1241 | /* | |
54168ed7 IM |
1242 | * nonexistent IRQs are edge default |
1243 | */ | |
d6c88a50 | 1244 | return 0; |
1d025192 | 1245 | } |
047c8fdb YL |
1246 | #else |
1247 | static inline int IO_APIC_irq_trigger(int irq) | |
1248 | { | |
54168ed7 | 1249 | return 1; |
047c8fdb YL |
1250 | } |
1251 | #endif | |
1d025192 | 1252 | |
1a0e62a4 TG |
1253 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
1254 | unsigned long trigger) | |
1da177e4 | 1255 | { |
c60eaf25 TG |
1256 | struct irq_chip *chip = &ioapic_chip; |
1257 | irq_flow_handler_t hdl; | |
1258 | bool fasteoi; | |
199751d7 | 1259 | |
6ebcc00e | 1260 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
c60eaf25 | 1261 | trigger == IOAPIC_LEVEL) { |
60c69948 | 1262 | irq_set_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1263 | fasteoi = true; |
1264 | } else { | |
60c69948 | 1265 | irq_clear_status_flags(irq, IRQ_LEVEL); |
c60eaf25 TG |
1266 | fasteoi = false; |
1267 | } | |
047c8fdb | 1268 | |
2976fd84 | 1269 | if (setup_remapped_irq(irq, cfg, chip)) |
c60eaf25 | 1270 | fasteoi = trigger != 0; |
29b61be6 | 1271 | |
c60eaf25 TG |
1272 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
1273 | irq_set_chip_and_handler_name(irq, chip, hdl, | |
1274 | fasteoi ? "fasteoi" : "edge"); | |
1da177e4 LT |
1275 | } |
1276 | ||
a6a25dd3 JR |
1277 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
1278 | unsigned int destination, int vector, | |
1279 | struct io_apic_irq_attr *attr) | |
c5b4712c | 1280 | { |
c5b4712c YL |
1281 | memset(entry, 0, sizeof(*entry)); |
1282 | ||
1283 | entry->delivery_mode = apic->irq_delivery_mode; | |
1284 | entry->dest_mode = apic->irq_dest_mode; | |
1285 | entry->dest = destination; | |
1286 | entry->vector = vector; | |
1287 | entry->mask = 0; /* enable IRQ */ | |
1288 | entry->trigger = attr->trigger; | |
1289 | entry->polarity = attr->polarity; | |
1290 | ||
1291 | /* | |
1292 | * Mask level triggered irqs. | |
497c9a19 YL |
1293 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
1294 | */ | |
c5b4712c | 1295 | if (attr->trigger) |
497c9a19 | 1296 | entry->mask = 1; |
c5b4712c | 1297 | |
497c9a19 YL |
1298 | return 0; |
1299 | } | |
1300 | ||
e4aff811 YL |
1301 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
1302 | struct io_apic_irq_attr *attr) | |
497c9a19 | 1303 | { |
1da177e4 | 1304 | struct IO_APIC_route_entry entry; |
22f65d31 | 1305 | unsigned int dest; |
497c9a19 YL |
1306 | |
1307 | if (!IO_APIC_IRQ(irq)) | |
1308 | return; | |
f1c63001 | 1309 | |
fe402e1f | 1310 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
497c9a19 YL |
1311 | return; |
1312 | ||
ff164324 AG |
1313 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1314 | &dest)) { | |
1315 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | |
1316 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | |
1317 | __clear_irq_vector(irq, cfg); | |
1318 | ||
1319 | return; | |
1320 | } | |
497c9a19 YL |
1321 | |
1322 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1323 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
7fece832 | 1324 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
e4aff811 YL |
1325 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
1326 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | |
497c9a19 | 1327 | |
a6a25dd3 JR |
1328 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
1329 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
c5b4712c | 1330 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
3145e941 | 1331 | __clear_irq_vector(irq, cfg); |
c5b4712c | 1332 | |
497c9a19 YL |
1333 | return; |
1334 | } | |
1335 | ||
e4aff811 | 1336 | ioapic_register_intr(irq, cfg, attr->trigger); |
b81bb373 | 1337 | if (irq < legacy_pic->nr_legacy_irqs) |
4305df94 | 1338 | legacy_pic->mask(irq); |
497c9a19 | 1339 | |
e4aff811 | 1340 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
497c9a19 YL |
1341 | } |
1342 | ||
6f50d45f | 1343 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
c8d6b8fe TG |
1344 | { |
1345 | if (idx != -1) | |
1346 | return false; | |
1347 | ||
1348 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", | |
6f50d45f | 1349 | mpc_ioapic_id(ioapic_idx), pin); |
c8d6b8fe TG |
1350 | return true; |
1351 | } | |
1352 | ||
6f50d45f | 1353 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
497c9a19 | 1354 | { |
ed972ccf | 1355 | int idx, node = cpu_to_node(0); |
2d57e37d | 1356 | struct io_apic_irq_attr attr; |
ed972ccf | 1357 | unsigned int pin, irq; |
1da177e4 | 1358 | |
f44d1692 | 1359 | for_each_pin(ioapic_idx, pin) { |
6f50d45f YL |
1360 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); |
1361 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) | |
b9c61b70 | 1362 | continue; |
33a201fa | 1363 | |
6f50d45f | 1364 | irq = pin_2_irq(idx, ioapic_idx, pin); |
33a201fa | 1365 | |
3eb2be5f | 1366 | if ((ioapic_idx > 0) && (irq > NR_IRQS_LEGACY)) |
fad53995 EB |
1367 | continue; |
1368 | ||
b9c61b70 YL |
1369 | /* |
1370 | * Skip the timer IRQ if there's a quirk handler | |
1371 | * installed and if it returns 1: | |
1372 | */ | |
1373 | if (apic->multi_timer_check && | |
6f50d45f | 1374 | apic->multi_timer_check(ioapic_idx, irq)) |
b9c61b70 | 1375 | continue; |
36062448 | 1376 | |
6f50d45f | 1377 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
2d57e37d | 1378 | irq_polarity(idx)); |
fbc6bff0 | 1379 | |
2d57e37d | 1380 | io_apic_setup_irq_pin(irq, node, &attr); |
1da177e4 | 1381 | } |
1da177e4 LT |
1382 | } |
1383 | ||
ed972ccf TG |
1384 | static void __init setup_IO_APIC_irqs(void) |
1385 | { | |
6f50d45f | 1386 | unsigned int ioapic_idx; |
ed972ccf TG |
1387 | |
1388 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1389 | ||
f44d1692 | 1390 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1391 | __io_apic_setup_irqs(ioapic_idx); |
ed972ccf TG |
1392 | } |
1393 | ||
18dce6ba | 1394 | /* |
3eb2be5f | 1395 | * for the gsi that is not in first ioapic |
18dce6ba YL |
1396 | * but could not use acpi_register_gsi() |
1397 | * like some special sci in IBM x3330 | |
1398 | */ | |
1399 | void setup_IO_APIC_irq_extra(u32 gsi) | |
1400 | { | |
6f50d45f | 1401 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
da1ad9d7 | 1402 | struct io_apic_irq_attr attr; |
18dce6ba YL |
1403 | |
1404 | /* | |
1405 | * Convert 'gsi' to 'ioapic.pin'. | |
1406 | */ | |
6f50d45f YL |
1407 | ioapic_idx = mp_find_ioapic(gsi); |
1408 | if (ioapic_idx < 0) | |
18dce6ba YL |
1409 | return; |
1410 | ||
6f50d45f YL |
1411 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
1412 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); | |
18dce6ba YL |
1413 | if (idx == -1) |
1414 | return; | |
1415 | ||
6f50d45f | 1416 | irq = pin_2_irq(idx, ioapic_idx, pin); |
fe6dab4e YL |
1417 | |
1418 | /* Only handle the non legacy irqs on secondary ioapics */ | |
6f50d45f | 1419 | if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) |
18dce6ba | 1420 | return; |
fe6dab4e | 1421 | |
6f50d45f | 1422 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
da1ad9d7 TG |
1423 | irq_polarity(idx)); |
1424 | ||
710dcda6 | 1425 | io_apic_setup_irq_pin_once(irq, node, &attr); |
18dce6ba YL |
1426 | } |
1427 | ||
1da177e4 | 1428 | /* |
f7633ce5 | 1429 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1430 | */ |
6f50d45f | 1431 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
49d0c7a0 | 1432 | unsigned int pin, int vector) |
1da177e4 LT |
1433 | { |
1434 | struct IO_APIC_route_entry entry; | |
ff164324 | 1435 | unsigned int dest; |
1da177e4 | 1436 | |
36062448 | 1437 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1438 | |
1439 | /* | |
1440 | * We use logical delivery to get the timer IRQ | |
1441 | * to the first CPU. | |
1442 | */ | |
a5a39156 AG |
1443 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
1444 | apic->target_cpus(), &dest))) | |
ff164324 AG |
1445 | dest = BAD_APICID; |
1446 | ||
9b5bc8dc | 1447 | entry.dest_mode = apic->irq_dest_mode; |
f72dccac | 1448 | entry.mask = 0; /* don't mask IRQ for edge */ |
ff164324 | 1449 | entry.dest = dest; |
9b5bc8dc | 1450 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1451 | entry.polarity = 0; |
1452 | entry.trigger = 0; | |
1453 | entry.vector = vector; | |
1454 | ||
1455 | /* | |
1456 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1457 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1458 | */ |
2c778651 TG |
1459 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
1460 | "edge"); | |
1da177e4 LT |
1461 | |
1462 | /* | |
1463 | * Add it to the IO-APIC irq-routing table: | |
1464 | */ | |
6f50d45f | 1465 | ioapic_write_entry(ioapic_idx, pin, entry); |
1da177e4 LT |
1466 | } |
1467 | ||
afcc8a40 JR |
1468 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
1469 | { | |
1470 | int i; | |
1471 | ||
1472 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); | |
1473 | ||
1474 | for (i = 0; i <= nr_entries; i++) { | |
1475 | struct IO_APIC_route_entry entry; | |
1476 | ||
1477 | entry = ioapic_read_entry(apic, i); | |
1478 | ||
1479 | pr_debug(" %02x %02X ", i, entry.dest); | |
1480 | pr_cont("%1d %1d %1d %1d %1d " | |
1481 | "%1d %1d %02X\n", | |
1482 | entry.mask, | |
1483 | entry.trigger, | |
1484 | entry.irr, | |
1485 | entry.polarity, | |
1486 | entry.delivery_status, | |
1487 | entry.dest_mode, | |
1488 | entry.delivery_mode, | |
1489 | entry.vector); | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | void intel_ir_io_apic_print_entries(unsigned int apic, | |
1494 | unsigned int nr_entries) | |
1da177e4 | 1495 | { |
cda417dd | 1496 | int i; |
afcc8a40 JR |
1497 | |
1498 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); | |
1499 | ||
1500 | for (i = 0; i <= nr_entries; i++) { | |
1501 | struct IR_IO_APIC_route_entry *ir_entry; | |
1502 | struct IO_APIC_route_entry entry; | |
1503 | ||
1504 | entry = ioapic_read_entry(apic, i); | |
1505 | ||
1506 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; | |
1507 | ||
1508 | pr_debug(" %02x %04X ", i, ir_entry->index); | |
1509 | pr_cont("%1d %1d %1d %1d %1d " | |
1510 | "%1d %1d %X %02X\n", | |
1511 | ir_entry->format, | |
1512 | ir_entry->mask, | |
1513 | ir_entry->trigger, | |
1514 | ir_entry->irr, | |
1515 | ir_entry->polarity, | |
1516 | ir_entry->delivery_status, | |
1517 | ir_entry->index2, | |
1518 | ir_entry->zero, | |
1519 | ir_entry->vector); | |
1520 | } | |
1521 | } | |
1522 | ||
17405453 YY |
1523 | void ioapic_zap_locks(void) |
1524 | { | |
1525 | raw_spin_lock_init(&ioapic_lock); | |
1526 | } | |
1527 | ||
afcc8a40 JR |
1528 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
1529 | { | |
1da177e4 LT |
1530 | union IO_APIC_reg_00 reg_00; |
1531 | union IO_APIC_reg_01 reg_01; | |
1532 | union IO_APIC_reg_02 reg_02; | |
1533 | union IO_APIC_reg_03 reg_03; | |
1534 | unsigned long flags; | |
1da177e4 | 1535 | |
dade7716 | 1536 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
1537 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
1538 | reg_01.raw = io_apic_read(ioapic_idx, 1); | |
1da177e4 | 1539 | if (reg_01.bits.version >= 0x10) |
6f50d45f | 1540 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
d6c88a50 | 1541 | if (reg_01.bits.version >= 0x20) |
6f50d45f | 1542 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
dade7716 | 1543 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 | 1544 | |
6f50d45f | 1545 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1546 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1547 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1548 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1549 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1550 | |
54168ed7 | 1551 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
bd6a46e0 NC |
1552 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
1553 | reg_01.bits.entries); | |
1da177e4 LT |
1554 | |
1555 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
bd6a46e0 NC |
1556 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
1557 | reg_01.bits.version); | |
1da177e4 LT |
1558 | |
1559 | /* | |
1560 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1561 | * but the value of reg_02 is read as the previous read register | |
1562 | * value, so ignore it if reg_02 == reg_01. | |
1563 | */ | |
1564 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1565 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1566 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1567 | } |
1568 | ||
1569 | /* | |
1570 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1571 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1572 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1573 | */ | |
1574 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1575 | reg_03.raw != reg_01.raw) { | |
1576 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1577 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1578 | } |
1579 | ||
1580 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1581 | ||
afcc8a40 | 1582 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
cda417dd YL |
1583 | } |
1584 | ||
1585 | __apicdebuginit(void) print_IO_APICs(void) | |
1586 | { | |
6f50d45f | 1587 | int ioapic_idx; |
cda417dd YL |
1588 | struct irq_cfg *cfg; |
1589 | unsigned int irq; | |
6fd36ba0 | 1590 | struct irq_chip *chip; |
cda417dd YL |
1591 | |
1592 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
f44d1692 | 1593 | for_each_ioapic(ioapic_idx) |
cda417dd | 1594 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
6f50d45f YL |
1595 | mpc_ioapic_id(ioapic_idx), |
1596 | ioapics[ioapic_idx].nr_registers); | |
cda417dd YL |
1597 | |
1598 | /* | |
1599 | * We are a bit conservative about what we expect. We have to | |
1600 | * know about every hardware change ASAP. | |
1601 | */ | |
1602 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1603 | ||
f44d1692 | 1604 | for_each_ioapic(ioapic_idx) |
6f50d45f | 1605 | print_IO_APIC(ioapic_idx); |
42f0efc5 | 1606 | |
1da177e4 | 1607 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
ad9f4334 | 1608 | for_each_active_irq(irq) { |
0b8f1efa YL |
1609 | struct irq_pin_list *entry; |
1610 | ||
6fd36ba0 MN |
1611 | chip = irq_get_chip(irq); |
1612 | if (chip != &ioapic_chip) | |
1613 | continue; | |
1614 | ||
32f5ef5d | 1615 | cfg = irq_cfg(irq); |
05e40760 DK |
1616 | if (!cfg) |
1617 | continue; | |
0b8f1efa | 1618 | entry = cfg->irq_2_pin; |
0f978f45 | 1619 | if (!entry) |
1da177e4 | 1620 | continue; |
8f09cd20 | 1621 | printk(KERN_DEBUG "IRQ%d ", irq); |
2977fb3f | 1622 | for_each_irq_pin(entry, cfg->irq_2_pin) |
c767a54b JP |
1623 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1624 | pr_cont("\n"); | |
1da177e4 LT |
1625 | } |
1626 | ||
1627 | printk(KERN_INFO ".................................... done.\n"); | |
1da177e4 LT |
1628 | } |
1629 | ||
251e1e44 | 1630 | __apicdebuginit(void) print_APIC_field(int base) |
1da177e4 | 1631 | { |
251e1e44 | 1632 | int i; |
1da177e4 | 1633 | |
251e1e44 IM |
1634 | printk(KERN_DEBUG); |
1635 | ||
1636 | for (i = 0; i < 8; i++) | |
c767a54b | 1637 | pr_cont("%08x", apic_read(base + i*0x10)); |
251e1e44 | 1638 | |
c767a54b | 1639 | pr_cont("\n"); |
1da177e4 LT |
1640 | } |
1641 | ||
32f71aff | 1642 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 | 1643 | { |
97a52714 | 1644 | unsigned int i, v, ver, maxlvt; |
7ab6af7a | 1645 | u64 icr; |
1da177e4 | 1646 | |
251e1e44 | 1647 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
1da177e4 | 1648 | smp_processor_id(), hard_smp_processor_id()); |
66823114 | 1649 | v = apic_read(APIC_ID); |
54168ed7 | 1650 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1651 | v = apic_read(APIC_LVR); |
1652 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1653 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1654 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1655 | |
1656 | v = apic_read(APIC_TASKPRI); | |
1657 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1658 | ||
54168ed7 | 1659 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1660 | if (!APIC_XAPIC(ver)) { |
1661 | v = apic_read(APIC_ARBPRI); | |
1662 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1663 | v & APIC_ARBPRI_MASK); | |
1664 | } | |
1da177e4 LT |
1665 | v = apic_read(APIC_PROCPRI); |
1666 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1667 | } | |
1668 | ||
a11b5abe YL |
1669 | /* |
1670 | * Remote read supported only in the 82489DX and local APIC for | |
1671 | * Pentium processors. | |
1672 | */ | |
1673 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1674 | v = apic_read(APIC_RRR); | |
1675 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1676 | } | |
1677 | ||
1da177e4 LT |
1678 | v = apic_read(APIC_LDR); |
1679 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1680 | if (!x2apic_enabled()) { |
1681 | v = apic_read(APIC_DFR); | |
1682 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1683 | } | |
1da177e4 LT |
1684 | v = apic_read(APIC_SPIV); |
1685 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1686 | ||
1687 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
251e1e44 | 1688 | print_APIC_field(APIC_ISR); |
1da177e4 | 1689 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
251e1e44 | 1690 | print_APIC_field(APIC_TMR); |
1da177e4 | 1691 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
251e1e44 | 1692 | print_APIC_field(APIC_IRR); |
1da177e4 | 1693 | |
54168ed7 IM |
1694 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1695 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1696 | apic_write(APIC_ESR, 0); |
54168ed7 | 1697 | |
1da177e4 LT |
1698 | v = apic_read(APIC_ESR); |
1699 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1700 | } | |
1701 | ||
7ab6af7a | 1702 | icr = apic_icr_read(); |
0c425cec IM |
1703 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1704 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1705 | |
1706 | v = apic_read(APIC_LVTT); | |
1707 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1708 | ||
1709 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1710 | v = apic_read(APIC_LVTPC); | |
1711 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1712 | } | |
1713 | v = apic_read(APIC_LVT0); | |
1714 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1715 | v = apic_read(APIC_LVT1); | |
1716 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1717 | ||
1718 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1719 | v = apic_read(APIC_LVTERR); | |
1720 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1721 | } | |
1722 | ||
1723 | v = apic_read(APIC_TMICT); | |
1724 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1725 | v = apic_read(APIC_TMCCT); | |
1726 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1727 | v = apic_read(APIC_TDCR); | |
1728 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
97a52714 AH |
1729 | |
1730 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
1731 | v = apic_read(APIC_EFEAT); | |
1732 | maxlvt = (v >> 16) & 0xff; | |
1733 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); | |
1734 | v = apic_read(APIC_ECTRL); | |
1735 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); | |
1736 | for (i = 0; i < maxlvt; i++) { | |
1737 | v = apic_read(APIC_EILVTn(i)); | |
1738 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | |
1739 | } | |
1740 | } | |
c767a54b | 1741 | pr_cont("\n"); |
1da177e4 LT |
1742 | } |
1743 | ||
2626eb2b | 1744 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
1da177e4 | 1745 | { |
ffd5aae7 YL |
1746 | int cpu; |
1747 | ||
2626eb2b CG |
1748 | if (!maxcpu) |
1749 | return; | |
1750 | ||
ffd5aae7 | 1751 | preempt_disable(); |
2626eb2b CG |
1752 | for_each_online_cpu(cpu) { |
1753 | if (cpu >= maxcpu) | |
1754 | break; | |
ffd5aae7 | 1755 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
2626eb2b | 1756 | } |
ffd5aae7 | 1757 | preempt_enable(); |
1da177e4 LT |
1758 | } |
1759 | ||
32f71aff | 1760 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1761 | { |
1da177e4 LT |
1762 | unsigned int v; |
1763 | unsigned long flags; | |
1764 | ||
b81bb373 | 1765 | if (!legacy_pic->nr_legacy_irqs) |
1da177e4 LT |
1766 | return; |
1767 | ||
1768 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1769 | ||
5619c280 | 1770 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
1da177e4 LT |
1771 | |
1772 | v = inb(0xa1) << 8 | inb(0x21); | |
1773 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1774 | ||
1775 | v = inb(0xa0) << 8 | inb(0x20); | |
1776 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1777 | ||
54168ed7 IM |
1778 | outb(0x0b,0xa0); |
1779 | outb(0x0b,0x20); | |
1da177e4 | 1780 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1781 | outb(0x0a,0xa0); |
1782 | outb(0x0a,0x20); | |
1da177e4 | 1783 | |
5619c280 | 1784 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
1da177e4 LT |
1785 | |
1786 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1787 | ||
1788 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1789 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1790 | } | |
1791 | ||
2626eb2b CG |
1792 | static int __initdata show_lapic = 1; |
1793 | static __init int setup_show_lapic(char *arg) | |
1794 | { | |
1795 | int num = -1; | |
1796 | ||
1797 | if (strcmp(arg, "all") == 0) { | |
1798 | show_lapic = CONFIG_NR_CPUS; | |
1799 | } else { | |
1800 | get_option(&arg, &num); | |
1801 | if (num >= 0) | |
1802 | show_lapic = num; | |
1803 | } | |
1804 | ||
1805 | return 1; | |
1806 | } | |
1807 | __setup("show_lapic=", setup_show_lapic); | |
1808 | ||
1809 | __apicdebuginit(int) print_ICs(void) | |
32f71aff | 1810 | { |
2626eb2b CG |
1811 | if (apic_verbosity == APIC_QUIET) |
1812 | return 0; | |
1813 | ||
32f71aff | 1814 | print_PIC(); |
4797f6b0 YL |
1815 | |
1816 | /* don't print out if apic is not there */ | |
8312136f | 1817 | if (!cpu_has_apic && !apic_from_smp_config()) |
4797f6b0 YL |
1818 | return 0; |
1819 | ||
2626eb2b | 1820 | print_local_APICs(show_lapic); |
cda417dd | 1821 | print_IO_APICs(); |
32f71aff MR |
1822 | |
1823 | return 0; | |
1824 | } | |
1825 | ||
ded1f6ab | 1826 | late_initcall(print_ICs); |
32f71aff | 1827 | |
1da177e4 | 1828 | |
efa2559f YL |
1829 | /* Where if anywhere is the i8259 connect in external int mode */ |
1830 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1831 | ||
54168ed7 | 1832 | void __init enable_IO_APIC(void) |
1da177e4 | 1833 | { |
fcfd636a | 1834 | int i8259_apic, i8259_pin; |
f44d1692 | 1835 | int apic, pin; |
bc07844a | 1836 | |
b81bb373 | 1837 | if (!legacy_pic->nr_legacy_irqs) |
bc07844a TG |
1838 | return; |
1839 | ||
f44d1692 | 1840 | for_each_ioapic_pin(apic, pin) { |
fcfd636a | 1841 | /* See if any of the pins is in ExtINT mode */ |
f44d1692 | 1842 | struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1843 | |
f44d1692 JL |
1844 | /* If the interrupt line is enabled and in ExtInt mode |
1845 | * I have found the pin where the i8259 is connected. | |
1846 | */ | |
1847 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1848 | ioapic_i8259.apic = apic; | |
1849 | ioapic_i8259.pin = pin; | |
1850 | goto found_i8259; | |
fcfd636a EB |
1851 | } |
1852 | } | |
1853 | found_i8259: | |
1854 | /* Look to see what if the MP table has reported the ExtINT */ | |
1855 | /* If we could not find the appropriate pin by looking at the ioapic | |
1856 | * the i8259 probably is not connected the ioapic but give the | |
1857 | * mptable a chance anyway. | |
1858 | */ | |
1859 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1860 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1861 | /* Trust the MP table if nothing is setup in the hardware */ | |
1862 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1863 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1864 | ioapic_i8259.pin = i8259_pin; | |
1865 | ioapic_i8259.apic = i8259_apic; | |
1866 | } | |
1867 | /* Complain if the MP table and the hardware disagree */ | |
1868 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1869 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1870 | { | |
1871 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1872 | } |
1873 | ||
1874 | /* | |
1875 | * Do not trust the IO-APIC being empty at bootup | |
1876 | */ | |
1877 | clear_IO_APIC(); | |
1878 | } | |
1879 | ||
1c4248ca | 1880 | void native_disable_io_apic(void) |
1da177e4 | 1881 | { |
650927ef | 1882 | /* |
0b968d23 | 1883 | * If the i8259 is routed through an IOAPIC |
650927ef | 1884 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1885 | * so legacy interrupts can be delivered. |
650927ef | 1886 | */ |
1c4248ca | 1887 | if (ioapic_i8259.pin != -1) { |
650927ef | 1888 | struct IO_APIC_route_entry entry; |
650927ef EB |
1889 | |
1890 | memset(&entry, 0, sizeof(entry)); | |
1891 | entry.mask = 0; /* Enabled */ | |
1892 | entry.trigger = 0; /* Edge */ | |
1893 | entry.irr = 0; | |
1894 | entry.polarity = 0; /* High */ | |
1895 | entry.delivery_status = 0; | |
1896 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1897 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1898 | entry.vector = 0; |
54168ed7 | 1899 | entry.dest = read_apic_id(); |
650927ef EB |
1900 | |
1901 | /* | |
1902 | * Add it to the IO-APIC irq-routing table: | |
1903 | */ | |
cf4c6a2f | 1904 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1905 | } |
54168ed7 | 1906 | |
1c4248ca JR |
1907 | if (cpu_has_apic || apic_from_smp_config()) |
1908 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); | |
1909 | ||
1910 | } | |
1911 | ||
1912 | /* | |
1913 | * Not an __init, needed by the reboot code | |
1914 | */ | |
1915 | void disable_IO_APIC(void) | |
1916 | { | |
7c6d9f97 | 1917 | /* |
1c4248ca | 1918 | * Clear the IO-APIC before rebooting: |
7c6d9f97 | 1919 | */ |
1c4248ca JR |
1920 | clear_IO_APIC(); |
1921 | ||
1922 | if (!legacy_pic->nr_legacy_irqs) | |
1923 | return; | |
1924 | ||
1925 | x86_io_apic_ops.disable(); | |
1da177e4 LT |
1926 | } |
1927 | ||
54168ed7 | 1928 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1929 | /* |
1930 | * function to set the IO-APIC physical IDs based on the | |
1931 | * values stored in the MPC table. | |
1932 | * | |
1933 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1934 | */ | |
a38c5380 | 1935 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
1da177e4 LT |
1936 | { |
1937 | union IO_APIC_reg_00 reg_00; | |
1938 | physid_mask_t phys_id_present_map; | |
6f50d45f | 1939 | int ioapic_idx; |
1da177e4 LT |
1940 | int i; |
1941 | unsigned char old_id; | |
1942 | unsigned long flags; | |
1943 | ||
1944 | /* | |
1945 | * This is broken; anything with a real cpu count has to | |
1946 | * circumvent this idiocy regardless. | |
1947 | */ | |
7abc0753 | 1948 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
1da177e4 LT |
1949 | |
1950 | /* | |
1951 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1952 | */ | |
f44d1692 | 1953 | for_each_ioapic(ioapic_idx) { |
1da177e4 | 1954 | /* Read the register 0 value */ |
dade7716 | 1955 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 1956 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 1957 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 1958 | |
6f50d45f | 1959 | old_id = mpc_ioapic_id(ioapic_idx); |
1da177e4 | 1960 | |
6f50d45f | 1961 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
1da177e4 | 1962 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
6f50d45f | 1963 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1964 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1965 | reg_00.bits.ID); | |
6f50d45f | 1966 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
1da177e4 LT |
1967 | } |
1968 | ||
1da177e4 LT |
1969 | /* |
1970 | * Sanity check, is the ID really free? Every APIC in a | |
1971 | * system must have a unique ID or we get lots of nice | |
1972 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1973 | */ | |
7abc0753 | 1974 | if (apic->check_apicid_used(&phys_id_present_map, |
6f50d45f | 1975 | mpc_ioapic_id(ioapic_idx))) { |
1da177e4 | 1976 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
6f50d45f | 1977 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1978 | for (i = 0; i < get_physical_broadcast(); i++) |
1979 | if (!physid_isset(i, phys_id_present_map)) | |
1980 | break; | |
1981 | if (i >= get_physical_broadcast()) | |
1982 | panic("Max APIC ID exceeded!\n"); | |
1983 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1984 | i); | |
1985 | physid_set(i, phys_id_present_map); | |
6f50d45f | 1986 | ioapics[ioapic_idx].mp_config.apicid = i; |
1da177e4 LT |
1987 | } else { |
1988 | physid_mask_t tmp; | |
6f50d45f | 1989 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
d5371430 | 1990 | &tmp); |
1da177e4 LT |
1991 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1992 | "phys_id_present_map\n", | |
6f50d45f | 1993 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 LT |
1994 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1995 | } | |
1996 | ||
1da177e4 LT |
1997 | /* |
1998 | * We need to adjust the IRQ routing table | |
1999 | * if the ID changed. | |
2000 | */ | |
6f50d45f | 2001 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
1da177e4 | 2002 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2003 | if (mp_irqs[i].dstapic == old_id) |
2004 | mp_irqs[i].dstapic | |
6f50d45f | 2005 | = mpc_ioapic_id(ioapic_idx); |
1da177e4 LT |
2006 | |
2007 | /* | |
60d79fd9 YL |
2008 | * Update the ID register according to the right value |
2009 | * from the MPC table if they are different. | |
36062448 | 2010 | */ |
6f50d45f | 2011 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
60d79fd9 YL |
2012 | continue; |
2013 | ||
1da177e4 LT |
2014 | apic_printk(APIC_VERBOSE, KERN_INFO |
2015 | "...changing IO-APIC physical APIC ID to %d ...", | |
6f50d45f | 2016 | mpc_ioapic_id(ioapic_idx)); |
1da177e4 | 2017 | |
6f50d45f | 2018 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
dade7716 | 2019 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2020 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
dade7716 | 2021 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2022 | |
2023 | /* | |
2024 | * Sanity check | |
2025 | */ | |
dade7716 | 2026 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f | 2027 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
dade7716 | 2028 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
6f50d45f | 2029 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
c767a54b | 2030 | pr_cont("could not set ID!\n"); |
1da177e4 LT |
2031 | else |
2032 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2033 | } | |
2034 | } | |
a38c5380 SAS |
2035 | |
2036 | void __init setup_ioapic_ids_from_mpc(void) | |
2037 | { | |
2038 | ||
2039 | if (acpi_ioapic) | |
2040 | return; | |
2041 | /* | |
2042 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2043 | * no meaning without the serial APIC bus. | |
2044 | */ | |
2045 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2046 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
2047 | return; | |
2048 | setup_ioapic_ids_from_mpc_nocheck(); | |
2049 | } | |
54168ed7 | 2050 | #endif |
1da177e4 | 2051 | |
7ce0bcfd | 2052 | int no_timer_check __initdata; |
8542b200 ZA |
2053 | |
2054 | static int __init notimercheck(char *s) | |
2055 | { | |
2056 | no_timer_check = 1; | |
2057 | return 1; | |
2058 | } | |
2059 | __setup("no_timer_check", notimercheck); | |
2060 | ||
1da177e4 LT |
2061 | /* |
2062 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2063 | * about the timer IRQ. We do the following to work around the situation: | |
2064 | * | |
2065 | * - timer IRQ defaults to IO-APIC IRQ | |
2066 | * - if this function detects that timer IRQs are defunct, then we fall | |
2067 | * back to ISA timer IRQs | |
2068 | */ | |
f0a7a5c9 | 2069 | static int __init timer_irq_works(void) |
1da177e4 LT |
2070 | { |
2071 | unsigned long t1 = jiffies; | |
4aae0702 | 2072 | unsigned long flags; |
1da177e4 | 2073 | |
8542b200 ZA |
2074 | if (no_timer_check) |
2075 | return 1; | |
2076 | ||
4aae0702 | 2077 | local_save_flags(flags); |
1da177e4 LT |
2078 | local_irq_enable(); |
2079 | /* Let ten ticks pass... */ | |
2080 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2081 | local_irq_restore(flags); |
1da177e4 LT |
2082 | |
2083 | /* | |
2084 | * Expect a few ticks at least, to be sure some possible | |
2085 | * glue logic does not lock up after one or two first | |
2086 | * ticks in a non-ExtINT mode. Also the local APIC | |
2087 | * might have cached one ExtINT interrupt. Finally, at | |
2088 | * least one tick may be lost due to delays. | |
2089 | */ | |
54168ed7 IM |
2090 | |
2091 | /* jiffies wrap? */ | |
1d16b53e | 2092 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2093 | return 1; |
1da177e4 LT |
2094 | return 0; |
2095 | } | |
2096 | ||
2097 | /* | |
2098 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2099 | * number of pending IRQ events unhandled. These cases are very rare, | |
2100 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2101 | * better to do it this way as thus we do not have to be aware of | |
2102 | * 'pending' interrupts in the IRQ path, except at this point. | |
2103 | */ | |
2104 | /* | |
2105 | * Edge triggered needs to resend any interrupt | |
2106 | * that was delayed but this is now handled in the device | |
2107 | * independent code. | |
2108 | */ | |
2109 | ||
2110 | /* | |
2111 | * Starting up a edge-triggered IO-APIC interrupt is | |
2112 | * nasty - we need to make sure that we get the edge. | |
2113 | * If it is already asserted for some reason, we need | |
2114 | * return 1 to indicate that is was pending. | |
2115 | * | |
2116 | * This is not complete - we should be able to fake | |
2117 | * an edge even if it isn't on the 8259A... | |
2118 | */ | |
54168ed7 | 2119 | |
61a38ce3 | 2120 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
1da177e4 | 2121 | { |
61a38ce3 | 2122 | int was_pending = 0, irq = data->irq; |
1da177e4 LT |
2123 | unsigned long flags; |
2124 | ||
dade7716 | 2125 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
b81bb373 | 2126 | if (irq < legacy_pic->nr_legacy_irqs) { |
4305df94 | 2127 | legacy_pic->mask(irq); |
b81bb373 | 2128 | if (legacy_pic->irq_pending(irq)) |
1da177e4 LT |
2129 | was_pending = 1; |
2130 | } | |
61a38ce3 | 2131 | __unmask_ioapic(data->chip_data); |
dade7716 | 2132 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2133 | |
2134 | return was_pending; | |
2135 | } | |
2136 | ||
90297c5f | 2137 | static int ioapic_retrigger_irq(struct irq_data *data) |
1da177e4 | 2138 | { |
90297c5f | 2139 | struct irq_cfg *cfg = data->chip_data; |
54168ed7 | 2140 | unsigned long flags; |
8d966a04 | 2141 | int cpu; |
54168ed7 | 2142 | |
dade7716 | 2143 | raw_spin_lock_irqsave(&vector_lock, flags); |
8d966a04 FY |
2144 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
2145 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
dade7716 | 2146 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2147 | |
2148 | return 1; | |
2149 | } | |
497c9a19 | 2150 | |
54168ed7 IM |
2151 | /* |
2152 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2153 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2154 | * handled with the level-triggered descriptor, but that one has slightly | |
2155 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2156 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2157 | * races. | |
2158 | */ | |
497c9a19 | 2159 | |
54168ed7 | 2160 | #ifdef CONFIG_SMP |
9338ad6f | 2161 | void send_cleanup_vector(struct irq_cfg *cfg) |
e85abf8f GH |
2162 | { |
2163 | cpumask_var_t cleanup_mask; | |
2164 | ||
2165 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
2166 | unsigned int i; | |
e85abf8f GH |
2167 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
2168 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
2169 | } else { | |
2170 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
e85abf8f GH |
2171 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
2172 | free_cpumask_var(cleanup_mask); | |
2173 | } | |
2174 | cfg->move_in_progress = 0; | |
2175 | } | |
2176 | ||
2605fc21 | 2177 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
54168ed7 IM |
2178 | { |
2179 | unsigned vector, me; | |
8f2466f4 | 2180 | |
54168ed7 | 2181 | ack_APIC_irq(); |
54168ed7 | 2182 | irq_enter(); |
98ad1cc1 | 2183 | exit_idle(); |
54168ed7 IM |
2184 | |
2185 | me = smp_processor_id(); | |
2186 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
c7a730fa | 2187 | int irq; |
68a8ca59 | 2188 | unsigned int irr; |
54168ed7 IM |
2189 | struct irq_desc *desc; |
2190 | struct irq_cfg *cfg; | |
0a3aee0d | 2191 | irq = __this_cpu_read(vector_irq[vector]); |
54168ed7 | 2192 | |
9345005f | 2193 | if (irq <= VECTOR_UNDEFINED) |
0b8f1efa YL |
2194 | continue; |
2195 | ||
54168ed7 IM |
2196 | desc = irq_to_desc(irq); |
2197 | if (!desc) | |
2198 | continue; | |
2199 | ||
2200 | cfg = irq_cfg(irq); | |
94777fc5 DS |
2201 | if (!cfg) |
2202 | continue; | |
2203 | ||
239007b8 | 2204 | raw_spin_lock(&desc->lock); |
54168ed7 | 2205 | |
7f41c2e1 SS |
2206 | /* |
2207 | * Check if the irq migration is in progress. If so, we | |
2208 | * haven't received the cleanup request yet for this irq. | |
2209 | */ | |
2210 | if (cfg->move_in_progress) | |
2211 | goto unlock; | |
2212 | ||
22f65d31 | 2213 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2214 | goto unlock; |
2215 | ||
68a8ca59 SS |
2216 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
2217 | /* | |
2218 | * Check if the vector that needs to be cleanedup is | |
2219 | * registered at the cpu's IRR. If so, then this is not | |
2220 | * the best time to clean it up. Lets clean it up in the | |
2221 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
2222 | * to myself. | |
2223 | */ | |
2224 | if (irr & (1 << (vector % 32))) { | |
2225 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
2226 | goto unlock; | |
2227 | } | |
3eb2be5f | 2228 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); |
54168ed7 | 2229 | unlock: |
239007b8 | 2230 | raw_spin_unlock(&desc->lock); |
54168ed7 IM |
2231 | } |
2232 | ||
2233 | irq_exit(); | |
2234 | } | |
2235 | ||
dd5f15e5 | 2236 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
54168ed7 | 2237 | { |
a5e74b84 | 2238 | unsigned me; |
54168ed7 | 2239 | |
fcef5911 | 2240 | if (likely(!cfg->move_in_progress)) |
54168ed7 IM |
2241 | return; |
2242 | ||
54168ed7 | 2243 | me = smp_processor_id(); |
10b888d6 | 2244 | |
fcef5911 | 2245 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
22f65d31 | 2246 | send_cleanup_vector(cfg); |
497c9a19 | 2247 | } |
a5e74b84 | 2248 | |
dd5f15e5 | 2249 | static void irq_complete_move(struct irq_cfg *cfg) |
a5e74b84 | 2250 | { |
dd5f15e5 | 2251 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
a5e74b84 SS |
2252 | } |
2253 | ||
2254 | void irq_force_complete_move(int irq) | |
2255 | { | |
32f5ef5d | 2256 | struct irq_cfg *cfg = irq_cfg(irq); |
a5e74b84 | 2257 | |
bbd391a1 PB |
2258 | if (!cfg) |
2259 | return; | |
2260 | ||
dd5f15e5 | 2261 | __irq_complete_move(cfg, cfg->vector); |
a5e74b84 | 2262 | } |
497c9a19 | 2263 | #else |
dd5f15e5 | 2264 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
497c9a19 | 2265 | #endif |
3145e941 | 2266 | |
7eb9ae07 SS |
2267 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
2268 | { | |
2269 | int apic, pin; | |
2270 | struct irq_pin_list *entry; | |
2271 | u8 vector = cfg->vector; | |
2272 | ||
2273 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2274 | unsigned int reg; | |
2275 | ||
2276 | apic = entry->apic; | |
2277 | pin = entry->pin; | |
9f9d39e4 JR |
2278 | |
2279 | io_apic_write(apic, 0x11 + pin*2, dest); | |
7eb9ae07 SS |
2280 | reg = io_apic_read(apic, 0x10 + pin*2); |
2281 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
2282 | reg |= vector; | |
2283 | io_apic_modify(apic, 0x10 + pin*2, reg); | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | /* | |
2288 | * Either sets data->affinity to a valid value, and returns | |
2289 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
2290 | * leaves data->affinity untouched. | |
2291 | */ | |
2292 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
2293 | unsigned int *dest_id) | |
2294 | { | |
2295 | struct irq_cfg *cfg = data->chip_data; | |
2296 | unsigned int irq = data->irq; | |
2297 | int err; | |
2298 | ||
2299 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2300 | return -EPERM; |
7eb9ae07 SS |
2301 | |
2302 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
2303 | return -EINVAL; | |
2304 | ||
2305 | err = assign_irq_vector(irq, cfg, mask); | |
2306 | if (err) | |
2307 | return err; | |
2308 | ||
2309 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
2310 | if (err) { | |
2311 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
2312 | pr_err("Failed to recover vector for irq %d\n", irq); | |
2313 | return err; | |
2314 | } | |
2315 | ||
2316 | cpumask_copy(data->affinity, mask); | |
2317 | ||
2318 | return 0; | |
2319 | } | |
2320 | ||
373dd7a2 JR |
2321 | |
2322 | int native_ioapic_set_affinity(struct irq_data *data, | |
2323 | const struct cpumask *mask, | |
2324 | bool force) | |
7eb9ae07 SS |
2325 | { |
2326 | unsigned int dest, irq = data->irq; | |
2327 | unsigned long flags; | |
2328 | int ret; | |
2329 | ||
2330 | if (!config_enabled(CONFIG_SMP)) | |
fb24da80 | 2331 | return -EPERM; |
7eb9ae07 SS |
2332 | |
2333 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2334 | ret = __ioapic_set_affinity(data, mask, &dest); | |
2335 | if (!ret) { | |
2336 | /* Only the high 8 bits are valid. */ | |
2337 | dest = SET_APIC_LOGICAL_ID(dest); | |
2338 | __target_IO_APIC_irq(irq, dest, data->chip_data); | |
2339 | ret = IRQ_SET_MASK_OK_NOCOPY; | |
2340 | } | |
2341 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2342 | return ret; | |
2343 | } | |
2344 | ||
90297c5f | 2345 | static void ack_apic_edge(struct irq_data *data) |
1d025192 | 2346 | { |
90297c5f | 2347 | irq_complete_move(data->chip_data); |
08221110 | 2348 | irq_move_irq(data); |
1d025192 YL |
2349 | ack_APIC_irq(); |
2350 | } | |
2351 | ||
3eb2cce8 | 2352 | atomic_t irq_mis_count; |
3eb2cce8 | 2353 | |
047c8fdb | 2354 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
d1ecad6e MN |
2355 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
2356 | { | |
2357 | struct irq_pin_list *entry; | |
2358 | unsigned long flags; | |
2359 | ||
2360 | raw_spin_lock_irqsave(&ioapic_lock, flags); | |
2361 | for_each_irq_pin(entry, cfg->irq_2_pin) { | |
2362 | unsigned int reg; | |
2363 | int pin; | |
2364 | ||
2365 | pin = entry->pin; | |
2366 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
2367 | /* Is the remote IRR bit set? */ | |
2368 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
2369 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2370 | return true; | |
2371 | } | |
2372 | } | |
2373 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | |
2374 | ||
2375 | return false; | |
2376 | } | |
2377 | ||
4da7072a AG |
2378 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
2379 | { | |
54168ed7 | 2380 | /* If we are moving the irq we need to mask it */ |
5451ddc5 | 2381 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
dd5f15e5 | 2382 | mask_ioapic(cfg); |
4da7072a | 2383 | return true; |
54168ed7 | 2384 | } |
4da7072a AG |
2385 | return false; |
2386 | } | |
2387 | ||
2388 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2389 | struct irq_cfg *cfg, bool masked) | |
2390 | { | |
2391 | if (unlikely(masked)) { | |
2392 | /* Only migrate the irq if the ack has been received. | |
2393 | * | |
2394 | * On rare occasions the broadcast level triggered ack gets | |
2395 | * delayed going to ioapics, and if we reprogram the | |
2396 | * vector while Remote IRR is still set the irq will never | |
2397 | * fire again. | |
2398 | * | |
2399 | * To prevent this scenario we read the Remote IRR bit | |
2400 | * of the ioapic. This has two effects. | |
2401 | * - On any sane system the read of the ioapic will | |
2402 | * flush writes (and acks) going to the ioapic from | |
2403 | * this cpu. | |
2404 | * - We get to see if the ACK has actually been delivered. | |
2405 | * | |
2406 | * Based on failed experiments of reprogramming the | |
2407 | * ioapic entry from outside of irq context starting | |
2408 | * with masking the ioapic entry and then polling until | |
2409 | * Remote IRR was clear before reprogramming the | |
2410 | * ioapic I don't trust the Remote IRR bit to be | |
2411 | * completey accurate. | |
2412 | * | |
2413 | * However there appears to be no other way to plug | |
2414 | * this race, so if the Remote IRR bit is not | |
2415 | * accurate and is causing problems then it is a hardware bug | |
2416 | * and you can go talk to the chipset vendor about it. | |
2417 | */ | |
2418 | if (!io_apic_level_ack_pending(cfg)) | |
2419 | irq_move_masked_irq(data); | |
2420 | unmask_ioapic(cfg); | |
2421 | } | |
2422 | } | |
2423 | #else | |
2424 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) | |
2425 | { | |
2426 | return false; | |
2427 | } | |
2428 | static inline void ioapic_irqd_unmask(struct irq_data *data, | |
2429 | struct irq_cfg *cfg, bool masked) | |
2430 | { | |
2431 | } | |
047c8fdb YL |
2432 | #endif |
2433 | ||
4da7072a AG |
2434 | static void ack_apic_level(struct irq_data *data) |
2435 | { | |
2436 | struct irq_cfg *cfg = data->chip_data; | |
2437 | int i, irq = data->irq; | |
2438 | unsigned long v; | |
2439 | bool masked; | |
2440 | ||
2441 | irq_complete_move(cfg); | |
2442 | masked = ioapic_irqd_mask(data, cfg); | |
2443 | ||
3eb2cce8 | 2444 | /* |
916a0fe7 JF |
2445 | * It appears there is an erratum which affects at least version 0x11 |
2446 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2447 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2448 | * erroneously delivered as edge-triggered one but the respective IRR | |
2449 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2450 | * message but it will never arrive and further interrupts are blocked | |
2451 | * from the source. The exact reason is so far unknown, but the | |
2452 | * phenomenon was observed when two consecutive interrupt requests | |
2453 | * from a given source get delivered to the same CPU and the source is | |
2454 | * temporarily disabled in between. | |
2455 | * | |
2456 | * A workaround is to simulate an EOI message manually. We achieve it | |
2457 | * by setting the trigger mode to edge and then to level when the edge | |
2458 | * trigger mode gets detected in the TMR of a local APIC for a | |
2459 | * level-triggered interrupt. We mask the source for the time of the | |
2460 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2461 | * The idea is from Manfred Spraul. --macro | |
1c83995b SS |
2462 | * |
2463 | * Also in the case when cpu goes offline, fixup_irqs() will forward | |
2464 | * any unhandled interrupt on the offlined cpu to the new cpu | |
2465 | * destination that is handling the corresponding interrupt. This | |
2466 | * interrupt forwarding is done via IPI's. Hence, in this case also | |
2467 | * level-triggered io-apic interrupt will be seen as an edge | |
2468 | * interrupt in the IRR. And we can't rely on the cpu's EOI | |
2469 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR | |
2470 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's | |
2471 | * supporting EOI register, we do an explicit EOI to clear the | |
2472 | * remote IRR and on IO-APIC's which don't have an EOI register, | |
2473 | * we use the above logic (mask+edge followed by unmask+level) from | |
2474 | * Manfred Spraul to clear the remote IRR. | |
916a0fe7 | 2475 | */ |
3145e941 | 2476 | i = cfg->vector; |
3eb2cce8 | 2477 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
3eb2cce8 | 2478 | |
54168ed7 IM |
2479 | /* |
2480 | * We must acknowledge the irq before we move it or the acknowledge will | |
2481 | * not propagate properly. | |
2482 | */ | |
2483 | ack_APIC_irq(); | |
2484 | ||
1c83995b SS |
2485 | /* |
2486 | * Tail end of clearing remote IRR bit (either by delivering the EOI | |
2487 | * message via io-apic EOI register write or simulating it using | |
2488 | * mask+edge followed by unnask+level logic) manually when the | |
2489 | * level triggered interrupt is seen as the edge triggered interrupt | |
2490 | * at the cpu. | |
2491 | */ | |
ca64c47c MR |
2492 | if (!(v & (1 << (i & 0x1f)))) { |
2493 | atomic_inc(&irq_mis_count); | |
2494 | ||
dd5f15e5 | 2495 | eoi_ioapic_irq(irq, cfg); |
ca64c47c MR |
2496 | } |
2497 | ||
4da7072a | 2498 | ioapic_irqd_unmask(data, cfg, masked); |
3eb2cce8 | 2499 | } |
1d025192 | 2500 | |
f5b9ed7a | 2501 | static struct irq_chip ioapic_chip __read_mostly = { |
f7e909ea TG |
2502 | .name = "IO-APIC", |
2503 | .irq_startup = startup_ioapic_irq, | |
2504 | .irq_mask = mask_ioapic_irq, | |
2505 | .irq_unmask = unmask_ioapic_irq, | |
2506 | .irq_ack = ack_apic_edge, | |
2507 | .irq_eoi = ack_apic_level, | |
373dd7a2 | 2508 | .irq_set_affinity = native_ioapic_set_affinity, |
f7e909ea | 2509 | .irq_retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2510 | }; |
2511 | ||
1da177e4 LT |
2512 | static inline void init_IO_APIC_traps(void) |
2513 | { | |
da51a821 | 2514 | struct irq_cfg *cfg; |
ad9f4334 | 2515 | unsigned int irq; |
1da177e4 | 2516 | |
ad9f4334 | 2517 | for_each_active_irq(irq) { |
32f5ef5d | 2518 | cfg = irq_cfg(irq); |
0b8f1efa | 2519 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
1da177e4 LT |
2520 | /* |
2521 | * Hmm.. We don't have an entry for this, | |
2522 | * so default to an old-fashioned 8259 | |
2523 | * interrupt if we can.. | |
2524 | */ | |
b81bb373 JP |
2525 | if (irq < legacy_pic->nr_legacy_irqs) |
2526 | legacy_pic->make_irq(irq); | |
0b8f1efa | 2527 | else |
1da177e4 | 2528 | /* Strange. Oh, well.. */ |
2c778651 | 2529 | irq_set_chip(irq, &no_irq_chip); |
1da177e4 LT |
2530 | } |
2531 | } | |
2532 | } | |
2533 | ||
f5b9ed7a IM |
2534 | /* |
2535 | * The local APIC irq-chip implementation: | |
2536 | */ | |
1da177e4 | 2537 | |
90297c5f | 2538 | static void mask_lapic_irq(struct irq_data *data) |
1da177e4 LT |
2539 | { |
2540 | unsigned long v; | |
2541 | ||
2542 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2543 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2544 | } |
2545 | ||
90297c5f | 2546 | static void unmask_lapic_irq(struct irq_data *data) |
1da177e4 | 2547 | { |
f5b9ed7a | 2548 | unsigned long v; |
1da177e4 | 2549 | |
f5b9ed7a | 2550 | v = apic_read(APIC_LVT0); |
593f4a78 | 2551 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2552 | } |
1da177e4 | 2553 | |
90297c5f | 2554 | static void ack_lapic_irq(struct irq_data *data) |
1d025192 YL |
2555 | { |
2556 | ack_APIC_irq(); | |
2557 | } | |
2558 | ||
f5b9ed7a | 2559 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2560 | .name = "local-APIC", |
90297c5f TG |
2561 | .irq_mask = mask_lapic_irq, |
2562 | .irq_unmask = unmask_lapic_irq, | |
2563 | .irq_ack = ack_lapic_irq, | |
1da177e4 LT |
2564 | }; |
2565 | ||
60c69948 | 2566 | static void lapic_register_intr(int irq) |
c88ac1df | 2567 | { |
60c69948 | 2568 | irq_clear_status_flags(irq, IRQ_LEVEL); |
2c778651 | 2569 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
c88ac1df | 2570 | "edge"); |
c88ac1df MR |
2571 | } |
2572 | ||
1da177e4 LT |
2573 | /* |
2574 | * This looks a bit hackish but it's about the only one way of sending | |
2575 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2576 | * not support the ExtINT mode, unfortunately. We need to send these | |
2577 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2578 | * 8259A interrupt line asserted until INTA. --macro | |
2579 | */ | |
28acf285 | 2580 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2581 | { |
fcfd636a | 2582 | int apic, pin, i; |
1da177e4 LT |
2583 | struct IO_APIC_route_entry entry0, entry1; |
2584 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2585 | |
fcfd636a | 2586 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2587 | if (pin == -1) { |
2588 | WARN_ON_ONCE(1); | |
2589 | return; | |
2590 | } | |
fcfd636a | 2591 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2592 | if (apic == -1) { |
2593 | WARN_ON_ONCE(1); | |
1da177e4 | 2594 | return; |
956fb531 | 2595 | } |
1da177e4 | 2596 | |
cf4c6a2f | 2597 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2598 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2599 | |
2600 | memset(&entry1, 0, sizeof(entry1)); | |
2601 | ||
2602 | entry1.dest_mode = 0; /* physical delivery */ | |
2603 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2604 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2605 | entry1.delivery_mode = dest_ExtINT; |
2606 | entry1.polarity = entry0.polarity; | |
2607 | entry1.trigger = 0; | |
2608 | entry1.vector = 0; | |
2609 | ||
cf4c6a2f | 2610 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2611 | |
2612 | save_control = CMOS_READ(RTC_CONTROL); | |
2613 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2614 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2615 | RTC_FREQ_SELECT); | |
2616 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2617 | ||
2618 | i = 100; | |
2619 | while (i-- > 0) { | |
2620 | mdelay(10); | |
2621 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2622 | i -= 10; | |
2623 | } | |
2624 | ||
2625 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2626 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2627 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2628 | |
cf4c6a2f | 2629 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2630 | } |
2631 | ||
efa2559f | 2632 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2633 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2634 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2635 | { |
2636 | disable_timer_pin_1 = 1; | |
2637 | return 0; | |
2638 | } | |
54168ed7 | 2639 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f | 2640 | |
1da177e4 LT |
2641 | /* |
2642 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2643 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2644 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2645 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2646 | * |
2647 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2648 | */ |
8542b200 | 2649 | static inline void __init check_timer(void) |
1da177e4 | 2650 | { |
32f5ef5d | 2651 | struct irq_cfg *cfg = irq_cfg(0); |
f6e9456c | 2652 | int node = cpu_to_node(0); |
fcfd636a | 2653 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2654 | unsigned long flags; |
047c8fdb | 2655 | int no_pin1 = 0; |
4aae0702 IM |
2656 | |
2657 | local_irq_save(flags); | |
d4d25dec | 2658 | |
1da177e4 LT |
2659 | /* |
2660 | * get/set the timer IRQ vector: | |
2661 | */ | |
4305df94 | 2662 | legacy_pic->mask(0); |
fe402e1f | 2663 | assign_irq_vector(0, cfg, apic->target_cpus()); |
1da177e4 LT |
2664 | |
2665 | /* | |
d11d5794 MR |
2666 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2667 | * wire has to be disabled in the local APIC. Also | |
2668 | * timer interrupts need to be acknowledged manually in | |
2669 | * the 8259A for the i82489DX when using the NMI | |
2670 | * watchdog as that APIC treats NMIs as level-triggered. | |
2671 | * The AEOI mode will finish them in the 8259A | |
2672 | * automatically. | |
1da177e4 | 2673 | */ |
593f4a78 | 2674 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
b81bb373 | 2675 | legacy_pic->init(1); |
1da177e4 | 2676 | |
fcfd636a EB |
2677 | pin1 = find_isa_irq_pin(0, mp_INT); |
2678 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2679 | pin2 = ioapic_i8259.pin; | |
2680 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2681 | |
49a66a0b MR |
2682 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2683 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2684 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2685 | |
691874fa MR |
2686 | /* |
2687 | * Some BIOS writers are clueless and report the ExtINTA | |
2688 | * I/O APIC input from the cascaded 8259A as the timer | |
2689 | * interrupt input. So just in case, if only one pin | |
2690 | * was found above, try it both directly and through the | |
2691 | * 8259A. | |
2692 | */ | |
2693 | if (pin1 == -1) { | |
6a9f5de2 | 2694 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
691874fa MR |
2695 | pin1 = pin2; |
2696 | apic1 = apic2; | |
2697 | no_pin1 = 1; | |
2698 | } else if (pin2 == -1) { | |
2699 | pin2 = pin1; | |
2700 | apic2 = apic1; | |
2701 | } | |
2702 | ||
1da177e4 LT |
2703 | if (pin1 != -1) { |
2704 | /* | |
2705 | * Ok, does IRQ0 through the IOAPIC work? | |
2706 | */ | |
691874fa | 2707 | if (no_pin1) { |
85ac16d0 | 2708 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
497c9a19 | 2709 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
f72dccac | 2710 | } else { |
60c69948 | 2711 | /* for edge trigger, setup_ioapic_irq already |
f72dccac YL |
2712 | * leave it unmasked. |
2713 | * so only need to unmask if it is level-trigger | |
2714 | * do we really have level trigger timer? | |
2715 | */ | |
2716 | int idx; | |
2717 | idx = find_irq_entry(apic1, pin1, mp_INT); | |
2718 | if (idx != -1 && irq_trigger(idx)) | |
dd5f15e5 | 2719 | unmask_ioapic(cfg); |
691874fa | 2720 | } |
1da177e4 | 2721 | if (timer_irq_works()) { |
66759a01 CE |
2722 | if (disable_timer_pin_1 > 0) |
2723 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2724 | goto out; |
1da177e4 | 2725 | } |
6a9f5de2 | 2726 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
f72dccac | 2727 | local_irq_disable(); |
fcfd636a | 2728 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2729 | if (!no_pin1) |
49a66a0b MR |
2730 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2731 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2732 | |
49a66a0b MR |
2733 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2734 | "(IRQ0) through the 8259A ...\n"); | |
2735 | apic_printk(APIC_QUIET, KERN_INFO | |
2736 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2737 | /* |
2738 | * legacy devices should be connected to IO APIC #0 | |
2739 | */ | |
85ac16d0 | 2740 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
497c9a19 | 2741 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
4305df94 | 2742 | legacy_pic->unmask(0); |
1da177e4 | 2743 | if (timer_irq_works()) { |
49a66a0b | 2744 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
4aae0702 | 2745 | goto out; |
1da177e4 LT |
2746 | } |
2747 | /* | |
2748 | * Cleanup, just in case ... | |
2749 | */ | |
f72dccac | 2750 | local_irq_disable(); |
4305df94 | 2751 | legacy_pic->mask(0); |
fcfd636a | 2752 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2753 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2754 | } |
1da177e4 | 2755 | |
49a66a0b MR |
2756 | apic_printk(APIC_QUIET, KERN_INFO |
2757 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2758 | |
60c69948 | 2759 | lapic_register_intr(0); |
497c9a19 | 2760 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
4305df94 | 2761 | legacy_pic->unmask(0); |
1da177e4 LT |
2762 | |
2763 | if (timer_irq_works()) { | |
49a66a0b | 2764 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2765 | goto out; |
1da177e4 | 2766 | } |
f72dccac | 2767 | local_irq_disable(); |
4305df94 | 2768 | legacy_pic->mask(0); |
497c9a19 | 2769 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2770 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2771 | |
49a66a0b MR |
2772 | apic_printk(APIC_QUIET, KERN_INFO |
2773 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2774 | |
b81bb373 JP |
2775 | legacy_pic->init(0); |
2776 | legacy_pic->make_irq(0); | |
593f4a78 | 2777 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2778 | |
2779 | unlock_ExtINT_logic(); | |
2780 | ||
2781 | if (timer_irq_works()) { | |
49a66a0b | 2782 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2783 | goto out; |
1da177e4 | 2784 | } |
f72dccac | 2785 | local_irq_disable(); |
49a66a0b | 2786 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
fb209bd8 YL |
2787 | if (x2apic_preenabled) |
2788 | apic_printk(APIC_QUIET, KERN_INFO | |
2789 | "Perhaps problem with the pre-enabled x2apic mode\n" | |
2790 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); | |
1da177e4 | 2791 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2792 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2793 | out: |
2794 | local_irq_restore(flags); | |
1da177e4 LT |
2795 | } |
2796 | ||
2797 | /* | |
af174783 MR |
2798 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2799 | * to devices. However there may be an I/O APIC pin available for | |
2800 | * this interrupt regardless. The pin may be left unconnected, but | |
2801 | * typically it will be reused as an ExtINT cascade interrupt for | |
2802 | * the master 8259A. In the MPS case such a pin will normally be | |
2803 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2804 | * there is no provision for ExtINT interrupts, and in the absence | |
2805 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2806 | * interrupt, that is edge-triggered and unmasked by default. We | |
2807 | * used to do this, but it caused problems on some systems because | |
2808 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2809 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2810 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2811 | * the I/O APIC in all cases now. No actual device should request | |
2812 | * it anyway. --macro | |
1da177e4 | 2813 | */ |
bc07844a | 2814 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
1da177e4 LT |
2815 | |
2816 | void __init setup_IO_APIC(void) | |
2817 | { | |
54168ed7 | 2818 | |
54168ed7 IM |
2819 | /* |
2820 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2821 | */ | |
b81bb373 | 2822 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
1da177e4 | 2823 | |
54168ed7 | 2824 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2825 | /* |
54168ed7 IM |
2826 | * Set up IO-APIC IRQ routing. |
2827 | */ | |
de934103 TG |
2828 | x86_init.mpparse.setup_ioapic_ids(); |
2829 | ||
1da177e4 LT |
2830 | sync_Arb_IDs(); |
2831 | setup_IO_APIC_irqs(); | |
2832 | init_IO_APIC_traps(); | |
b81bb373 | 2833 | if (legacy_pic->nr_legacy_irqs) |
bc07844a | 2834 | check_timer(); |
1da177e4 LT |
2835 | } |
2836 | ||
2837 | /* | |
0d2eb44f | 2838 | * Called after all the initialization is done. If we didn't find any |
54168ed7 | 2839 | * APIC bugs then we can allow the modify fast path |
1da177e4 | 2840 | */ |
36062448 | 2841 | |
1da177e4 LT |
2842 | static int __init io_apic_bug_finalize(void) |
2843 | { | |
d6c88a50 TG |
2844 | if (sis_apic_bug == -1) |
2845 | sis_apic_bug = 0; | |
2846 | return 0; | |
1da177e4 LT |
2847 | } |
2848 | ||
2849 | late_initcall(io_apic_bug_finalize); | |
2850 | ||
6f50d45f | 2851 | static void resume_ioapic_id(int ioapic_idx) |
1da177e4 | 2852 | { |
1da177e4 LT |
2853 | unsigned long flags; |
2854 | union IO_APIC_reg_00 reg_00; | |
36062448 | 2855 | |
dade7716 | 2856 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
6f50d45f YL |
2857 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2858 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { | |
2859 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); | |
2860 | io_apic_write(ioapic_idx, 0, reg_00.raw); | |
1da177e4 | 2861 | } |
dade7716 | 2862 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
f3c6ea1b | 2863 | } |
1da177e4 | 2864 | |
f3c6ea1b RW |
2865 | static void ioapic_resume(void) |
2866 | { | |
6f50d45f | 2867 | int ioapic_idx; |
f3c6ea1b | 2868 | |
f44d1692 | 2869 | for_each_ioapic_reverse(ioapic_idx) |
6f50d45f | 2870 | resume_ioapic_id(ioapic_idx); |
15bac20b SS |
2871 | |
2872 | restore_ioapic_entries(); | |
1da177e4 LT |
2873 | } |
2874 | ||
f3c6ea1b | 2875 | static struct syscore_ops ioapic_syscore_ops = { |
15bac20b | 2876 | .suspend = save_ioapic_entries, |
1da177e4 LT |
2877 | .resume = ioapic_resume, |
2878 | }; | |
2879 | ||
f3c6ea1b | 2880 | static int __init ioapic_init_ops(void) |
1da177e4 | 2881 | { |
f3c6ea1b RW |
2882 | register_syscore_ops(&ioapic_syscore_ops); |
2883 | ||
1da177e4 LT |
2884 | return 0; |
2885 | } | |
2886 | ||
f3c6ea1b | 2887 | device_initcall(ioapic_init_ops); |
1da177e4 | 2888 | |
3fc471ed | 2889 | /* |
54859f59 | 2890 | * Dynamic irq allocate and deallocation. Should be replaced by irq domains! |
3fc471ed | 2891 | */ |
b1ee5441 TG |
2892 | int arch_setup_hwirq(unsigned int irq, int node) |
2893 | { | |
2894 | struct irq_cfg *cfg; | |
2895 | unsigned long flags; | |
2896 | int ret; | |
2897 | ||
2898 | cfg = alloc_irq_cfg(irq, node); | |
2899 | if (!cfg) | |
2900 | return -ENOMEM; | |
2901 | ||
2902 | raw_spin_lock_irqsave(&vector_lock, flags); | |
2903 | ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); | |
2904 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
2905 | ||
2906 | if (!ret) | |
2907 | irq_set_chip_data(irq, cfg); | |
2908 | else | |
2909 | free_irq_cfg(irq, cfg); | |
2910 | return ret; | |
2911 | } | |
2912 | ||
2913 | void arch_teardown_hwirq(unsigned int irq) | |
2914 | { | |
32f5ef5d | 2915 | struct irq_cfg *cfg = irq_cfg(irq); |
b1ee5441 TG |
2916 | unsigned long flags; |
2917 | ||
2918 | free_remapped_irq(irq); | |
2919 | raw_spin_lock_irqsave(&vector_lock, flags); | |
2920 | __clear_irq_vector(irq, cfg); | |
2921 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
2922 | free_irq_cfg(irq, cfg); | |
2923 | } | |
2924 | ||
2d3fcc1c | 2925 | /* |
27b46d76 | 2926 | * MSI message composition |
2d3fcc1c | 2927 | */ |
7601384f JR |
2928 | void native_compose_msi_msg(struct pci_dev *pdev, |
2929 | unsigned int irq, unsigned int dest, | |
2930 | struct msi_msg *msg, u8 hpet_id) | |
2d3fcc1c | 2931 | { |
7601384f | 2932 | struct irq_cfg *cfg = irq_cfg(irq); |
2d3fcc1c | 2933 | |
7601384f | 2934 | msg->address_hi = MSI_ADDR_BASE_HI; |
54168ed7 | 2935 | |
5e2b930b | 2936 | if (x2apic_enabled()) |
7601384f | 2937 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); |
f007e99c | 2938 | |
5e2b930b JR |
2939 | msg->address_lo = |
2940 | MSI_ADDR_BASE_LO | | |
2941 | ((apic->irq_dest_mode == 0) ? | |
2942 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2943 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2944 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
2945 | MSI_ADDR_REDIRECTION_CPU: | |
2946 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2947 | MSI_ADDR_DEST_ID(dest); | |
2948 | ||
2949 | msg->data = | |
2950 | MSI_DATA_TRIGGER_EDGE | | |
2951 | MSI_DATA_LEVEL_ASSERT | | |
2952 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
2953 | MSI_DATA_DELIVERY_FIXED: | |
2954 | MSI_DATA_DELIVERY_LOWPRI) | | |
2955 | MSI_DATA_VECTOR(cfg->vector); | |
7601384f JR |
2956 | } |
2957 | ||
2958 | #ifdef CONFIG_PCI_MSI | |
2959 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |
2960 | struct msi_msg *msg, u8 hpet_id) | |
2961 | { | |
2962 | struct irq_cfg *cfg; | |
2963 | int err; | |
2964 | unsigned dest; | |
2965 | ||
2966 | if (disable_apic) | |
2967 | return -ENXIO; | |
2968 | ||
2969 | cfg = irq_cfg(irq); | |
2970 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | |
2971 | if (err) | |
2972 | return err; | |
2973 | ||
2974 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | |
2975 | apic->target_cpus(), &dest); | |
2976 | if (err) | |
2977 | return err; | |
2978 | ||
2979 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); | |
54168ed7 | 2980 | |
51906e77 | 2981 | return 0; |
2d3fcc1c EB |
2982 | } |
2983 | ||
5346b2a7 TG |
2984 | static int |
2985 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
2d3fcc1c | 2986 | { |
5346b2a7 | 2987 | struct irq_cfg *cfg = data->chip_data; |
3b7d1921 EB |
2988 | struct msi_msg msg; |
2989 | unsigned int dest; | |
fb24da80 | 2990 | int ret; |
3b7d1921 | 2991 | |
fb24da80 PB |
2992 | ret = __ioapic_set_affinity(data, mask, &dest); |
2993 | if (ret) | |
2994 | return ret; | |
2d3fcc1c | 2995 | |
5346b2a7 | 2996 | __get_cached_msi_msg(data->msi_desc, &msg); |
3b7d1921 EB |
2997 | |
2998 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 2999 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3000 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3001 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3002 | ||
5346b2a7 | 3003 | __write_msi_msg(data->msi_desc, &msg); |
d5dedd45 | 3004 | |
f841d792 | 3005 | return IRQ_SET_MASK_OK_NOCOPY; |
2d3fcc1c EB |
3006 | } |
3007 | ||
3b7d1921 EB |
3008 | /* |
3009 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3010 | * which implement the MSI or MSI-X Capability Structure. | |
3011 | */ | |
3012 | static struct irq_chip msi_chip = { | |
5346b2a7 TG |
3013 | .name = "PCI-MSI", |
3014 | .irq_unmask = unmask_msi_irq, | |
3015 | .irq_mask = mask_msi_irq, | |
3016 | .irq_ack = ack_apic_edge, | |
5346b2a7 | 3017 | .irq_set_affinity = msi_set_affinity, |
5346b2a7 | 3018 | .irq_retrigger = ioapic_retrigger_irq, |
2d3fcc1c EB |
3019 | }; |
3020 | ||
5afba62c JR |
3021 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
3022 | unsigned int irq_base, unsigned int irq_offset) | |
1d025192 | 3023 | { |
c60eaf25 | 3024 | struct irq_chip *chip = &msi_chip; |
1d025192 | 3025 | struct msi_msg msg; |
51906e77 | 3026 | unsigned int irq = irq_base + irq_offset; |
60c69948 | 3027 | int ret; |
1d025192 | 3028 | |
c8bc6f3c | 3029 | ret = msi_compose_msg(dev, irq, &msg, -1); |
1d025192 YL |
3030 | if (ret < 0) |
3031 | return ret; | |
3032 | ||
51906e77 AG |
3033 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); |
3034 | ||
3035 | /* | |
3036 | * MSI-X message is written per-IRQ, the offset is always 0. | |
3037 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. | |
3038 | */ | |
3039 | if (!irq_offset) | |
3040 | write_msi_msg(irq, &msg); | |
1d025192 | 3041 | |
32f5ef5d | 3042 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c60eaf25 TG |
3043 | |
3044 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); | |
1d025192 | 3045 | |
c81bba49 YL |
3046 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3047 | ||
1d025192 YL |
3048 | return 0; |
3049 | } | |
3050 | ||
5afba62c | 3051 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
047c8fdb | 3052 | { |
0b8f1efa | 3053 | struct msi_desc *msidesc; |
be47be6c | 3054 | unsigned int irq; |
5afba62c JR |
3055 | int node, ret; |
3056 | ||
3057 | /* Multiple MSI vectors only supported with interrupt remapping */ | |
3058 | if (type == PCI_CAP_ID_MSI && nvec > 1) | |
3059 | return 1; | |
54168ed7 | 3060 | |
d047f53a | 3061 | node = dev_to_node(&dev->dev); |
be47be6c | 3062 | |
0b8f1efa | 3063 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
be47be6c TG |
3064 | irq = irq_alloc_hwirq(node); |
3065 | if (!irq) | |
51906e77 | 3066 | return -ENOSPC; |
5afba62c | 3067 | |
51906e77 | 3068 | ret = setup_msi_irq(dev, msidesc, irq, 0); |
be47be6c TG |
3069 | if (ret < 0) { |
3070 | irq_free_hwirq(irq); | |
3071 | return ret; | |
3072 | } | |
3073 | ||
54168ed7 IM |
3074 | } |
3075 | return 0; | |
047c8fdb YL |
3076 | } |
3077 | ||
294ee6f8 | 3078 | void native_teardown_msi_irq(unsigned int irq) |
3b7d1921 | 3079 | { |
be47be6c | 3080 | irq_free_hwirq(irq); |
3b7d1921 EB |
3081 | } |
3082 | ||
d3f13810 | 3083 | #ifdef CONFIG_DMAR_TABLE |
fe52b2d2 TG |
3084 | static int |
3085 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3086 | bool force) | |
54168ed7 | 3087 | { |
fe52b2d2 TG |
3088 | struct irq_cfg *cfg = data->chip_data; |
3089 | unsigned int dest, irq = data->irq; | |
54168ed7 | 3090 | struct msi_msg msg; |
fb24da80 | 3091 | int ret; |
54168ed7 | 3092 | |
fb24da80 PB |
3093 | ret = __ioapic_set_affinity(data, mask, &dest); |
3094 | if (ret) | |
3095 | return ret; | |
54168ed7 | 3096 | |
54168ed7 IM |
3097 | dmar_msi_read(irq, &msg); |
3098 | ||
3099 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3100 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3101 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3102 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
086e8ced | 3103 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
54168ed7 IM |
3104 | |
3105 | dmar_msi_write(irq, &msg); | |
d5dedd45 | 3106 | |
f841d792 | 3107 | return IRQ_SET_MASK_OK_NOCOPY; |
54168ed7 | 3108 | } |
3145e941 | 3109 | |
8f7007aa | 3110 | static struct irq_chip dmar_msi_type = { |
fe52b2d2 TG |
3111 | .name = "DMAR_MSI", |
3112 | .irq_unmask = dmar_msi_unmask, | |
3113 | .irq_mask = dmar_msi_mask, | |
3114 | .irq_ack = ack_apic_edge, | |
fe52b2d2 | 3115 | .irq_set_affinity = dmar_msi_set_affinity, |
fe52b2d2 | 3116 | .irq_retrigger = ioapic_retrigger_irq, |
54168ed7 IM |
3117 | }; |
3118 | ||
3119 | int arch_setup_dmar_msi(unsigned int irq) | |
3120 | { | |
3121 | int ret; | |
3122 | struct msi_msg msg; | |
2d3fcc1c | 3123 | |
c8bc6f3c | 3124 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
54168ed7 IM |
3125 | if (ret < 0) |
3126 | return ret; | |
3127 | dmar_msi_write(irq, &msg); | |
2c778651 TG |
3128 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
3129 | "edge"); | |
54168ed7 IM |
3130 | return 0; |
3131 | } | |
3132 | #endif | |
3133 | ||
58ac1e76 | 3134 | #ifdef CONFIG_HPET_TIMER |
3135 | ||
d0fbca8f TG |
3136 | static int hpet_msi_set_affinity(struct irq_data *data, |
3137 | const struct cpumask *mask, bool force) | |
58ac1e76 | 3138 | { |
d0fbca8f | 3139 | struct irq_cfg *cfg = data->chip_data; |
58ac1e76 | 3140 | struct msi_msg msg; |
3141 | unsigned int dest; | |
fb24da80 | 3142 | int ret; |
58ac1e76 | 3143 | |
fb24da80 PB |
3144 | ret = __ioapic_set_affinity(data, mask, &dest); |
3145 | if (ret) | |
3146 | return ret; | |
58ac1e76 | 3147 | |
d0fbca8f | 3148 | hpet_msi_read(data->handler_data, &msg); |
58ac1e76 | 3149 | |
3150 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3151 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3152 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3153 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3154 | ||
d0fbca8f | 3155 | hpet_msi_write(data->handler_data, &msg); |
d5dedd45 | 3156 | |
f841d792 | 3157 | return IRQ_SET_MASK_OK_NOCOPY; |
58ac1e76 | 3158 | } |
3145e941 | 3159 | |
1cc18521 | 3160 | static struct irq_chip hpet_msi_type = { |
58ac1e76 | 3161 | .name = "HPET_MSI", |
d0fbca8f TG |
3162 | .irq_unmask = hpet_msi_unmask, |
3163 | .irq_mask = hpet_msi_mask, | |
90297c5f | 3164 | .irq_ack = ack_apic_edge, |
d0fbca8f | 3165 | .irq_set_affinity = hpet_msi_set_affinity, |
90297c5f | 3166 | .irq_retrigger = ioapic_retrigger_irq, |
58ac1e76 | 3167 | }; |
3168 | ||
71054d88 | 3169 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) |
58ac1e76 | 3170 | { |
c60eaf25 | 3171 | struct irq_chip *chip = &hpet_msi_type; |
58ac1e76 | 3172 | struct msi_msg msg; |
d0fbca8f | 3173 | int ret; |
58ac1e76 | 3174 | |
c8bc6f3c | 3175 | ret = msi_compose_msg(NULL, irq, &msg, id); |
58ac1e76 | 3176 | if (ret < 0) |
3177 | return ret; | |
3178 | ||
2c778651 | 3179 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
60c69948 | 3180 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
32f5ef5d | 3181 | setup_remapped_irq(irq, irq_cfg(irq), chip); |
c81bba49 | 3182 | |
c60eaf25 | 3183 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
58ac1e76 | 3184 | return 0; |
3185 | } | |
3186 | #endif | |
3187 | ||
54168ed7 | 3188 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3189 | /* |
3190 | * Hypertransport interrupt support | |
3191 | */ | |
3192 | #ifdef CONFIG_HT_IRQ | |
3193 | ||
497c9a19 | 3194 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3195 | { |
ec68307c EB |
3196 | struct ht_irq_msg msg; |
3197 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3198 | |
497c9a19 | 3199 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3200 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3201 | |
497c9a19 | 3202 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3203 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3204 | |
ec68307c | 3205 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3206 | } |
3207 | ||
be5b7bf7 TG |
3208 | static int |
3209 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |
8b955b0d | 3210 | { |
be5b7bf7 | 3211 | struct irq_cfg *cfg = data->chip_data; |
8b955b0d | 3212 | unsigned int dest; |
fb24da80 | 3213 | int ret; |
8b955b0d | 3214 | |
fb24da80 PB |
3215 | ret = __ioapic_set_affinity(data, mask, &dest); |
3216 | if (ret) | |
3217 | return ret; | |
8b955b0d | 3218 | |
be5b7bf7 | 3219 | target_ht_irq(data->irq, dest, cfg->vector); |
f841d792 | 3220 | return IRQ_SET_MASK_OK_NOCOPY; |
8b955b0d | 3221 | } |
3145e941 | 3222 | |
c37e108d | 3223 | static struct irq_chip ht_irq_chip = { |
be5b7bf7 TG |
3224 | .name = "PCI-HT", |
3225 | .irq_mask = mask_ht_irq, | |
3226 | .irq_unmask = unmask_ht_irq, | |
3227 | .irq_ack = ack_apic_edge, | |
be5b7bf7 | 3228 | .irq_set_affinity = ht_set_affinity, |
be5b7bf7 | 3229 | .irq_retrigger = ioapic_retrigger_irq, |
8b955b0d EB |
3230 | }; |
3231 | ||
3232 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3233 | { | |
497c9a19 | 3234 | struct irq_cfg *cfg; |
ff164324 AG |
3235 | struct ht_irq_msg msg; |
3236 | unsigned dest; | |
497c9a19 | 3237 | int err; |
8b955b0d | 3238 | |
f1182638 JB |
3239 | if (disable_apic) |
3240 | return -ENXIO; | |
3241 | ||
3145e941 | 3242 | cfg = irq_cfg(irq); |
fe402e1f | 3243 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
ff164324 AG |
3244 | if (err) |
3245 | return err; | |
8b955b0d | 3246 | |
ff164324 AG |
3247 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3248 | apic->target_cpus(), &dest); | |
3249 | if (err) | |
3250 | return err; | |
8b955b0d | 3251 | |
ff164324 | 3252 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3253 | |
ff164324 AG |
3254 | msg.address_lo = |
3255 | HT_IRQ_LOW_BASE | | |
3256 | HT_IRQ_LOW_DEST_ID(dest) | | |
3257 | HT_IRQ_LOW_VECTOR(cfg->vector) | | |
3258 | ((apic->irq_dest_mode == 0) ? | |
3259 | HT_IRQ_LOW_DM_PHYSICAL : | |
3260 | HT_IRQ_LOW_DM_LOGICAL) | | |
3261 | HT_IRQ_LOW_RQEOI_EDGE | | |
3262 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | |
3263 | HT_IRQ_LOW_MT_FIXED : | |
3264 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3265 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3266 | |
ff164324 | 3267 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3268 | |
ff164324 AG |
3269 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3270 | handle_edge_irq, "edge"); | |
8b955b0d | 3271 | |
ff164324 | 3272 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
c81bba49 | 3273 | |
ff164324 | 3274 | return 0; |
8b955b0d EB |
3275 | } |
3276 | #endif /* CONFIG_HT_IRQ */ | |
3277 | ||
20443598 | 3278 | static int |
ff973d04 TG |
3279 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
3280 | { | |
3281 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); | |
3282 | int ret; | |
3283 | ||
3284 | if (!cfg) | |
3285 | return -EINVAL; | |
3286 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); | |
3287 | if (!ret) | |
e4aff811 | 3288 | setup_ioapic_irq(irq, cfg, attr); |
ff973d04 TG |
3289 | return ret; |
3290 | } | |
3291 | ||
20443598 SAS |
3292 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
3293 | struct io_apic_irq_attr *attr) | |
710dcda6 | 3294 | { |
6f50d45f | 3295 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
710dcda6 | 3296 | int ret; |
25aa2957 | 3297 | struct IO_APIC_route_entry orig_entry; |
710dcda6 TG |
3298 | |
3299 | /* Avoid redundant programming */ | |
6f50d45f | 3300 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
25aa2957 LPF |
3301 | pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin); |
3302 | orig_entry = ioapic_read_entry(attr->ioapic, pin); | |
3303 | if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity) | |
3304 | return 0; | |
3305 | return -EBUSY; | |
710dcda6 TG |
3306 | } |
3307 | ret = io_apic_setup_irq_pin(irq, node, attr); | |
3308 | if (!ret) | |
6f50d45f | 3309 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
710dcda6 TG |
3310 | return ret; |
3311 | } | |
3312 | ||
41098ffe | 3313 | static int __init io_apic_get_redir_entries(int ioapic) |
9d6a4d08 YL |
3314 | { |
3315 | union IO_APIC_reg_01 reg_01; | |
3316 | unsigned long flags; | |
3317 | ||
dade7716 | 3318 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
9d6a4d08 | 3319 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3320 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
9d6a4d08 | 3321 | |
4b6b19a1 EB |
3322 | /* The register returns the maximum index redir index |
3323 | * supported, which is one less than the total number of redir | |
3324 | * entries. | |
3325 | */ | |
3326 | return reg_01.bits.entries + 1; | |
9d6a4d08 YL |
3327 | } |
3328 | ||
62a08ae2 TG |
3329 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
3330 | { | |
518b2c63 JL |
3331 | unsigned int min = gsi_top + NR_IRQS_LEGACY; |
3332 | ||
3333 | return from < min ? min : from; | |
62a08ae2 TG |
3334 | } |
3335 | ||
4a046d17 YL |
3336 | int __init arch_probe_nr_irqs(void) |
3337 | { | |
3338 | int nr; | |
3339 | ||
f1ee5548 YL |
3340 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
3341 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
4a046d17 | 3342 | |
518b2c63 | 3343 | nr = (gsi_top + NR_IRQS_LEGACY) + 8 * nr_cpu_ids; |
f1ee5548 YL |
3344 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) |
3345 | /* | |
3346 | * for MSI and HT dyn irq | |
3347 | */ | |
518b2c63 | 3348 | nr += (gsi_top + NR_IRQS_LEGACY) * 16; |
f1ee5548 YL |
3349 | #endif |
3350 | if (nr < nr_irqs) | |
4a046d17 YL |
3351 | nr_irqs = nr; |
3352 | ||
b683de2b | 3353 | return NR_IRQS_LEGACY; |
4a046d17 | 3354 | } |
4a046d17 | 3355 | |
710dcda6 TG |
3356 | int io_apic_set_pci_routing(struct device *dev, int irq, |
3357 | struct io_apic_irq_attr *irq_attr) | |
5ef21837 | 3358 | { |
5ef21837 YL |
3359 | int node; |
3360 | ||
3361 | if (!IO_APIC_IRQ(irq)) { | |
3362 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
e0799c04 | 3363 | irq_attr->ioapic); |
5ef21837 YL |
3364 | return -EINVAL; |
3365 | } | |
3366 | ||
e0799c04 | 3367 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
e5198075 | 3368 | |
710dcda6 | 3369 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
5ef21837 YL |
3370 | } |
3371 | ||
54168ed7 | 3372 | #ifdef CONFIG_X86_32 |
41098ffe | 3373 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3374 | { |
3375 | union IO_APIC_reg_00 reg_00; | |
3376 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3377 | physid_mask_t tmp; | |
3378 | unsigned long flags; | |
3379 | int i = 0; | |
3380 | ||
3381 | /* | |
36062448 PC |
3382 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3383 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3384 | * supports up to 16 on one shared APIC bus. |
36062448 | 3385 | * |
1da177e4 LT |
3386 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3387 | * advantage of new APIC bus architecture. | |
3388 | */ | |
3389 | ||
3390 | if (physids_empty(apic_id_map)) | |
7abc0753 | 3391 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
1da177e4 | 3392 | |
dade7716 | 3393 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3394 | reg_00.raw = io_apic_read(ioapic, 0); |
dade7716 | 3395 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3396 | |
3397 | if (apic_id >= get_physical_broadcast()) { | |
3398 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3399 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3400 | apic_id = reg_00.bits.ID; | |
3401 | } | |
3402 | ||
3403 | /* | |
36062448 | 3404 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3405 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3406 | */ | |
7abc0753 | 3407 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
1da177e4 LT |
3408 | |
3409 | for (i = 0; i < get_physical_broadcast(); i++) { | |
7abc0753 | 3410 | if (!apic->check_apicid_used(&apic_id_map, i)) |
1da177e4 LT |
3411 | break; |
3412 | } | |
3413 | ||
3414 | if (i == get_physical_broadcast()) | |
3415 | panic("Max apic_id exceeded!\n"); | |
3416 | ||
3417 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3418 | "trying %d\n", ioapic, apic_id, i); | |
3419 | ||
3420 | apic_id = i; | |
36062448 | 3421 | } |
1da177e4 | 3422 | |
7abc0753 | 3423 | apic->apicid_to_cpu_present(apic_id, &tmp); |
1da177e4 LT |
3424 | physids_or(apic_id_map, apic_id_map, tmp); |
3425 | ||
3426 | if (reg_00.bits.ID != apic_id) { | |
3427 | reg_00.bits.ID = apic_id; | |
3428 | ||
dade7716 | 3429 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
3430 | io_apic_write(ioapic, 0, reg_00.raw); |
3431 | reg_00.raw = io_apic_read(ioapic, 0); | |
dade7716 | 3432 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3433 | |
3434 | /* Sanity check */ | |
6070f9ec | 3435 | if (reg_00.bits.ID != apic_id) { |
c767a54b JP |
3436 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3437 | ioapic); | |
6070f9ec AD |
3438 | return -1; |
3439 | } | |
1da177e4 LT |
3440 | } |
3441 | ||
3442 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3443 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3444 | ||
3445 | return apic_id; | |
3446 | } | |
41098ffe TG |
3447 | |
3448 | static u8 __init io_apic_unique_id(u8 id) | |
3449 | { | |
3450 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
3451 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
3452 | return io_apic_get_unique_id(nr_ioapics, id); | |
3453 | else | |
3454 | return id; | |
3455 | } | |
3456 | #else | |
3457 | static u8 __init io_apic_unique_id(u8 id) | |
3458 | { | |
3459 | int i; | |
3460 | DECLARE_BITMAP(used, 256); | |
3461 | ||
3462 | bitmap_zero(used, 256); | |
f44d1692 | 3463 | for_each_ioapic(i) |
d5371430 | 3464 | __set_bit(mpc_ioapic_id(i), used); |
41098ffe TG |
3465 | if (!test_bit(id, used)) |
3466 | return id; | |
3467 | return find_first_zero_bit(used, 256); | |
3468 | } | |
58f892e0 | 3469 | #endif |
1da177e4 | 3470 | |
41098ffe | 3471 | static int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3472 | { |
3473 | union IO_APIC_reg_01 reg_01; | |
3474 | unsigned long flags; | |
3475 | ||
dade7716 | 3476 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 | 3477 | reg_01.raw = io_apic_read(ioapic, 1); |
dade7716 | 3478 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
3479 | |
3480 | return reg_01.bits.version; | |
3481 | } | |
3482 | ||
9a0a91bb | 3483 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
61fd47e0 | 3484 | { |
9a0a91bb | 3485 | int ioapic, pin, idx; |
61fd47e0 SL |
3486 | |
3487 | if (skip_ioapic_setup) | |
3488 | return -1; | |
3489 | ||
9a0a91bb EB |
3490 | ioapic = mp_find_ioapic(gsi); |
3491 | if (ioapic < 0) | |
61fd47e0 SL |
3492 | return -1; |
3493 | ||
9a0a91bb EB |
3494 | pin = mp_find_ioapic_pin(ioapic, gsi); |
3495 | if (pin < 0) | |
3496 | return -1; | |
3497 | ||
3498 | idx = find_irq_entry(ioapic, pin, mp_INT); | |
3499 | if (idx < 0) | |
61fd47e0 SL |
3500 | return -1; |
3501 | ||
9a0a91bb EB |
3502 | *trigger = irq_trigger(idx); |
3503 | *polarity = irq_polarity(idx); | |
61fd47e0 SL |
3504 | return 0; |
3505 | } | |
3506 | ||
497c9a19 YL |
3507 | /* |
3508 | * This function currently is only a helper for the i386 smp boot process where | |
3509 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
fe402e1f | 3510 | * so mask in all cases should simply be apic->target_cpus() |
497c9a19 YL |
3511 | */ |
3512 | #ifdef CONFIG_SMP | |
3513 | void __init setup_ioapic_dest(void) | |
3514 | { | |
fad53995 | 3515 | int pin, ioapic, irq, irq_entry; |
22f65d31 | 3516 | const struct cpumask *mask; |
5451ddc5 | 3517 | struct irq_data *idata; |
497c9a19 YL |
3518 | |
3519 | if (skip_ioapic_setup == 1) | |
3520 | return; | |
3521 | ||
f44d1692 | 3522 | for_each_ioapic_pin(ioapic, pin) { |
b9c61b70 YL |
3523 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
3524 | if (irq_entry == -1) | |
3525 | continue; | |
3526 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
6c2e9403 | 3527 | |
3eb2be5f | 3528 | if ((ioapic > 0) && (irq > NR_IRQS_LEGACY)) |
fad53995 EB |
3529 | continue; |
3530 | ||
5451ddc5 | 3531 | idata = irq_get_irq_data(irq); |
6c2e9403 | 3532 | |
b9c61b70 YL |
3533 | /* |
3534 | * Honour affinities which have been set in early boot | |
3535 | */ | |
5451ddc5 TG |
3536 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
3537 | mask = idata->affinity; | |
b9c61b70 YL |
3538 | else |
3539 | mask = apic->target_cpus(); | |
497c9a19 | 3540 | |
373dd7a2 | 3541 | x86_io_apic_ops.set_affinity(idata, mask, false); |
497c9a19 | 3542 | } |
b9c61b70 | 3543 | |
497c9a19 YL |
3544 | } |
3545 | #endif | |
3546 | ||
54168ed7 IM |
3547 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3548 | ||
3549 | static struct resource *ioapic_resources; | |
3550 | ||
f44d1692 | 3551 | static struct resource * __init ioapic_setup_resources(void) |
54168ed7 IM |
3552 | { |
3553 | unsigned long n; | |
3554 | struct resource *res; | |
3555 | char *mem; | |
f44d1692 | 3556 | int i, num = 0; |
54168ed7 | 3557 | |
f44d1692 JL |
3558 | for_each_ioapic(i) |
3559 | num++; | |
3560 | if (num == 0) | |
54168ed7 IM |
3561 | return NULL; |
3562 | ||
3563 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
f44d1692 | 3564 | n *= num; |
54168ed7 IM |
3565 | |
3566 | mem = alloc_bootmem(n); | |
3567 | res = (void *)mem; | |
3568 | ||
f44d1692 | 3569 | mem += sizeof(struct resource) * num; |
54168ed7 | 3570 | |
f44d1692 JL |
3571 | num = 0; |
3572 | for_each_ioapic(i) { | |
3573 | res[num].name = mem; | |
3574 | res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4343fe10 | 3575 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
ffc43836 | 3576 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
f44d1692 | 3577 | num++; |
54168ed7 IM |
3578 | } |
3579 | ||
3580 | ioapic_resources = res; | |
3581 | ||
3582 | return res; | |
3583 | } | |
54168ed7 | 3584 | |
4a8e2a31 | 3585 | void __init native_io_apic_init_mappings(void) |
f3294a33 YL |
3586 | { |
3587 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3588 | struct resource *ioapic_res; |
d6c88a50 | 3589 | int i; |
f3294a33 | 3590 | |
f44d1692 JL |
3591 | ioapic_res = ioapic_setup_resources(); |
3592 | for_each_ioapic(i) { | |
f3294a33 | 3593 | if (smp_found_config) { |
d5371430 | 3594 | ioapic_phys = mpc_ioapic_addr(i); |
54168ed7 | 3595 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3596 | if (!ioapic_phys) { |
3597 | printk(KERN_ERR | |
3598 | "WARNING: bogus zero IO-APIC " | |
3599 | "address found in MPTABLE, " | |
3600 | "disabling IO/APIC support!\n"); | |
3601 | smp_found_config = 0; | |
3602 | skip_ioapic_setup = 1; | |
3603 | goto fake_ioapic_page; | |
3604 | } | |
54168ed7 | 3605 | #endif |
f3294a33 | 3606 | } else { |
54168ed7 | 3607 | #ifdef CONFIG_X86_32 |
f3294a33 | 3608 | fake_ioapic_page: |
54168ed7 | 3609 | #endif |
e79c65a9 | 3610 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3611 | ioapic_phys = __pa(ioapic_phys); |
3612 | } | |
3613 | set_fixmap_nocache(idx, ioapic_phys); | |
e79c65a9 CG |
3614 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
3615 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), | |
3616 | ioapic_phys); | |
f3294a33 | 3617 | idx++; |
54168ed7 | 3618 | |
ffc43836 | 3619 | ioapic_res->start = ioapic_phys; |
e79c65a9 | 3620 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
ffc43836 | 3621 | ioapic_res++; |
f3294a33 YL |
3622 | } |
3623 | } | |
3624 | ||
857fdc53 | 3625 | void __init ioapic_insert_resources(void) |
54168ed7 IM |
3626 | { |
3627 | int i; | |
3628 | struct resource *r = ioapic_resources; | |
3629 | ||
3630 | if (!r) { | |
857fdc53 | 3631 | if (nr_ioapics > 0) |
04c93ce4 BZ |
3632 | printk(KERN_ERR |
3633 | "IO APIC resources couldn't be allocated.\n"); | |
857fdc53 | 3634 | return; |
54168ed7 IM |
3635 | } |
3636 | ||
f44d1692 | 3637 | for_each_ioapic(i) { |
54168ed7 IM |
3638 | insert_resource(&iomem_resource, r); |
3639 | r++; | |
3640 | } | |
54168ed7 | 3641 | } |
2a4ab640 | 3642 | |
eddb0c55 | 3643 | int mp_find_ioapic(u32 gsi) |
2a4ab640 | 3644 | { |
f44d1692 | 3645 | int i; |
2a4ab640 | 3646 | |
678301ec PB |
3647 | if (nr_ioapics == 0) |
3648 | return -1; | |
3649 | ||
2a4ab640 | 3650 | /* Find the IOAPIC that manages this GSI. */ |
f44d1692 | 3651 | for_each_ioapic(i) { |
c040aaeb | 3652 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
f44d1692 | 3653 | if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) |
2a4ab640 FT |
3654 | return i; |
3655 | } | |
54168ed7 | 3656 | |
2a4ab640 FT |
3657 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
3658 | return -1; | |
3659 | } | |
3660 | ||
eddb0c55 | 3661 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
2a4ab640 | 3662 | { |
c040aaeb SS |
3663 | struct mp_ioapic_gsi *gsi_cfg; |
3664 | ||
f44d1692 | 3665 | if (WARN_ON(ioapic < 0)) |
2a4ab640 | 3666 | return -1; |
c040aaeb SS |
3667 | |
3668 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); | |
3669 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) | |
2a4ab640 FT |
3670 | return -1; |
3671 | ||
c040aaeb | 3672 | return gsi - gsi_cfg->gsi_base; |
2a4ab640 FT |
3673 | } |
3674 | ||
41098ffe | 3675 | static __init int bad_ioapic(unsigned long address) |
2a4ab640 FT |
3676 | { |
3677 | if (nr_ioapics >= MAX_IO_APICS) { | |
73d63d03 SS |
3678 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
3679 | MAX_IO_APICS, nr_ioapics); | |
2a4ab640 FT |
3680 | return 1; |
3681 | } | |
3682 | if (!address) { | |
73d63d03 | 3683 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
2a4ab640 FT |
3684 | return 1; |
3685 | } | |
54168ed7 IM |
3686 | return 0; |
3687 | } | |
3688 | ||
73d63d03 SS |
3689 | static __init int bad_ioapic_register(int idx) |
3690 | { | |
3691 | union IO_APIC_reg_00 reg_00; | |
3692 | union IO_APIC_reg_01 reg_01; | |
3693 | union IO_APIC_reg_02 reg_02; | |
3694 | ||
3695 | reg_00.raw = io_apic_read(idx, 0); | |
3696 | reg_01.raw = io_apic_read(idx, 1); | |
3697 | reg_02.raw = io_apic_read(idx, 2); | |
3698 | ||
3699 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { | |
3700 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", | |
3701 | mpc_ioapic_addr(idx)); | |
3702 | return 1; | |
3703 | } | |
3704 | ||
3705 | return 0; | |
3706 | } | |
3707 | ||
2a4ab640 FT |
3708 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
3709 | { | |
3710 | int idx = 0; | |
7716a5c4 | 3711 | int entries; |
c040aaeb | 3712 | struct mp_ioapic_gsi *gsi_cfg; |
2a4ab640 FT |
3713 | |
3714 | if (bad_ioapic(address)) | |
3715 | return; | |
3716 | ||
3717 | idx = nr_ioapics; | |
3718 | ||
d5371430 SS |
3719 | ioapics[idx].mp_config.type = MP_IOAPIC; |
3720 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; | |
3721 | ioapics[idx].mp_config.apicaddr = address; | |
2a4ab640 FT |
3722 | |
3723 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
73d63d03 SS |
3724 | |
3725 | if (bad_ioapic_register(idx)) { | |
3726 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); | |
3727 | return; | |
3728 | } | |
3729 | ||
d5371430 SS |
3730 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
3731 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); | |
2a4ab640 FT |
3732 | |
3733 | /* | |
3734 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups | |
3735 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
3736 | */ | |
7716a5c4 | 3737 | entries = io_apic_get_redir_entries(idx); |
c040aaeb SS |
3738 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
3739 | gsi_cfg->gsi_base = gsi_base; | |
3740 | gsi_cfg->gsi_end = gsi_base + entries - 1; | |
7716a5c4 EB |
3741 | |
3742 | /* | |
3743 | * The number of IO-APIC IRQ registers (== #pins): | |
3744 | */ | |
b69c6c3b | 3745 | ioapics[idx].nr_registers = entries; |
2a4ab640 | 3746 | |
c040aaeb SS |
3747 | if (gsi_cfg->gsi_end >= gsi_top) |
3748 | gsi_top = gsi_cfg->gsi_end + 1; | |
2a4ab640 | 3749 | |
73d63d03 SS |
3750 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
3751 | idx, mpc_ioapic_id(idx), | |
3752 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), | |
3753 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); | |
2a4ab640 FT |
3754 | |
3755 | nr_ioapics++; | |
3756 | } | |
05ddafb1 JP |
3757 | |
3758 | /* Enable IOAPIC early just for system timer */ | |
3759 | void __init pre_init_apic_IRQ0(void) | |
3760 | { | |
f880ec78 | 3761 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
05ddafb1 JP |
3762 | |
3763 | printk(KERN_INFO "Early APIC setup for system timer0\n"); | |
3764 | #ifndef CONFIG_SMP | |
cb2ded37 YL |
3765 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
3766 | &phys_cpu_present_map); | |
05ddafb1 | 3767 | #endif |
05ddafb1 JP |
3768 | setup_local_APIC(); |
3769 | ||
f880ec78 | 3770 | io_apic_setup_irq_pin(0, 0, &attr); |
2c778651 TG |
3771 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
3772 | "edge"); | |
05ddafb1 | 3773 | } |